ĐIỆN tử VIỄN THÔNG 14b lab5 comparator v9 khotailieu

Comparator Lab Comparator Lab www.xilinx.com 1-877-XLX-CLAS 14b-2 Comparator Lab (Part of the Calculator Project) Introduction In this lab, you will write two separate descriptions for the entity COMP (Comparator) The first will be behavioral in nature, using a combination of VHDL assert and conditional signal assignment statements The second will utilize purely RTL code, using if/else statements Objectives After completing this lab, you will be able to:  Use the VHDL assert statement  Use a basic VHDL if/else construct  Create behavioral and RTL versions of a given module  Verify the logic functionality Procedure Examine the circuit below (Figure 14b-1) In this lab, you will write two separate descriptions for the submodule COMP The first description is behavioral, using assert and conditional signal assignment statements The second description is RTL, using if/else statements The choice of which description to use is dependent on whether you are simulating or synthesizing the design Figure 14b-1 Schematic for a Simple Calculator Circuit Comparator Lab www.xilinx.com 1-877-XLX-CLAS 14b-3 NOTE: Toolwire is the default platform for running labs Use R:\ for all directory references This lab comprises three primary steps: You will create a behavioral version of COMP; create an RTL version of COMP; and, finally, create a testbench to verify that the behavioral model functions correctly For each procedure within a primary step, there are general instructions (indicated by the symbol) These general instructions only provide a broad outline for performing the procedure Below these general instructions, you will find accompanying step-by-step directions and illustrated figures that provide more detail for performing the procedure If you feel confident about completing a procedure, you can skip the step-by-step directions and move on to the next general instruction Note: If you are not using Toolwire to perform this lab, all software programs, files, and projects will be located on the C:\ drive instead of R:\ Note: If you are unable to complete the lab at this time, you can download the lab files for this module from the Xilinx FTP site at ftp://ftp.xilinx.com/pub/documentation/education/lang11000-9-rev1-xlnx_lab_files.zip Creating a Behavioral Version of Comparator Step For each procedure within a primary step, there are general instructions (indicated by the symbol) These general instructions only provide a broad outline for performing the procedure Below these general instructions, you will find accompanying step-by-step directions and illustrated figures that provide more detail for performing the procedure If you feel confident about completing a procedure, you can skip the step-by-step directions and move on to the next general instruction General Flow for this Lab: Step 1: Creating a Behavioral Version of Comparator Step 2: Creating an RTL Version of Comparator Step 3: Creating a Testbench and Verifying Functionality Open the existing My_Class_Labs project within the ISE™ software, located in the R:\training\vhdl\labs directory  Select Start  Programs  Xilinx ISE 9.1i  Project Navigator to launch the Project Navigator By default, the ISE software should start with the last open project as the current project  If not, select File  Open Project  My_Class_Labs Comparator Lab www.xilinx.com 1-877-XLX-CLAS 14b-4 ! ! Important: Unless otherwise noted, you must label your project and HDL source files as instructed, or simulation may not work properly Create a behavioral version of COMP  Select Project  New Source  In the New Source dialog box, select VHDL Module, enter COMP_BEH in the File name field, and click Next to open the table-based entity wizard  Enter the port data for the intended module with the information in Table 14b-1, which details the inputs and output for the COMP_BEH submodule Port Label COMP_EN CLK EXPECTED ALU_OUT RESULT Length bit bit bit bit bit Description Enable signal, generated from FSM Clock input Expected output, loaded from ROM Actual output, from ALU Result of comparison Table 14b-1 Ports for COMP_BEH  When you are finished, click Next and click Finish The tool automatically creates the entity declaration based on the data entered in the table  Leave the architecture label as the default Behavioral Note: After you exit the wizard, you must make all subsequent edits in the HDL editor, including changes to items that were originally specified in the wizard The file shows the entity declaration This data is based on what was entered in the wizard The label is COMP_BEH with the ports as specified After finishing the entity, complete the architecture shell This description is the behavioral version and intended for simulation Use a VHDL assert statement, complete with report and severity level to compare the two inputs and use a conditional signal assignment to the output signal RESULT Assign if the inputs are equal, if not  Create a report statement that concisely describes the simulation mismatch  Set the severity_level to warning  Within the same clocked process, assign the output signal RESULT based on whether ALU_OUT = EXP_OUT Assign logic if equal, else After finishing, your source code for the COMP_BEH submodule should be complete Comparator Lab www.xilinx.com 1-877-XLX-CLAS 14b-5 Perform a syntax check  In the Sources for window, select COMP_BEH.vhd In the Processes window, expand Synthesize and double-click Check Syntax  Double-click View RTL Schematic to verify that the synthesis compiler interprets your code as a synchronous comparator  Correct any errors Ask for help from the instructor if needed ! ! Note: Depending on the nature and type of VHDL behavioral constructs used, performing a syntax check with a synthesis-based tool is often not possible In this example, you were able to use the XST tool to verify the syntax of the behavioral source code; however, it could not be used to verify a common testbench This would require an HDL verification tool, such as ISE Simulator, or another VHDL simulator Creating an RTL Version of Comparator Step General Flow for this Lab: Step 1: Creating a Behavioral Version of Comparator Step 2: Creating an RTL Version of Comparator Step 3: Creating a Testbench and Verifying Functionality Create an RTL version of COMP  Select Project  New Source In the New Source dialog box, select VHDL Module, enter COMP_RTL in the File name field, and click Next to open the table-based entity wizard  Enter the file label as COMP_RTL and click Next  Label the architecture as RTL  Describe the same functionality as before However, use only an if/else statement within a clocked process Comparator Lab www.xilinx.com 1-877-XLX-CLAS 14b-6 Creating a Testbench and Verifying Functionality Step General Flow for this Lab: Step 1: Creating a Behavioral Version of Comparator Step 2: Creating an RTL Version of Comparator Step 3: Creating a Testbench and Verifying Functionality Build a simple testbench and verify that the behavioral model functions correctly Label the testbench as COMP_BEH_TB Take particular note that your report statement displays to the console window whenever the inputs are not equal to each other Run the ISE Simulator to perform simulation and debug your source code as needed Conclusion In this exercise, you created two versions of a given module The first was written in a behavioral style and would be used for simulation It included a VHDL assert statement with a report clause that would aid your debugging efforts The second version used a conventional if/else statement and was intended for RTL utilization In the final lab exercise, you will use a VHDL generate statement to choose between the two versions of the COMP submodule Comparator Lab www.xilinx.com 1-877-XLX-CLAS 14b-7 A Answers library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity COMP_BEH is port ( CLK : in std_logic ; EXPECTED : in std_logic_vector(3 downto 0); ALU_OUT : in std_logic_vector(3 downto 0); COMP_EN : in std_logic ; RESULT : out std_logic ); end COMP_BEH; architecture Behavioral of COMP_BEH is begin process ( CLK ) begin if rising_edge ( CLK) then if ( COMP_EN = '1' ) then if ( EXPECTED = ALU_OUT )then RESULT ALU_OUT, RESULT => RESULT, COMP_EN => COMP_EN, CLK => CLK ); CLK