ĐIỆN tử VIỄN THÔNG 12b lab4 counter v9 khotailieu

n­Bit Binary Counter and RTL  Verification Lab n-Bit Binary Counter and RTL Verification Lab www.xilinx.com 1-877-XLX-CLAS 12b-2 n-Bit Binary Counter and RTL Verification Lab Introduction In this lab, you will write a complete RTL description for the entity MY_CNTR by using generics to specify the bit width This is an n-bit binary, up/down loadable counter, with active low asynchronous reset You will then build a VHDL testbench to verify the functionality of the RTL code as well as the hardware it models Objectives After completing this lab, you will be able to:  Create, simulate, and verify RTL code for an n-bit binary counter  Use the language templates in the ISE™ software  Use VHDL generics Procedure Examine the circuit below (Figure 12b-1) In this lab, you will write a complete RTL description for the entity MY_CNTR by using generics to specify the bit width The circuit is an n-bit binary, up/down loadable counter, with active low asynchronous reset D_IN Q_OUT MY_CNTR CE LOAD UpDn CLK RST Figure 12b-1 Schematic for a Generic (n-bit) Wide Binary Counter NOTE: Toolwire is the default platform for running labs Use R:\ for all directory references n-Bit Binary Counter and RTL Verification Lab www.xilinx.com 1-877-XLX-CLAS 12b-3 This lab comprises two primary steps: You will declare a generic, using it to create an n-bit binary counter and create a testbench to verify the design For each procedure within a primary step, there are general instructions (indicated by the symbol) These general instructions only provide a broad outline for performing the procedure Below these general instructions, you will find accompanying step-by-step directions and illustrated figures that provide more detail for performing the procedure If you feel confident about completing a procedure, you can skip the step-by-step directions and move on to the next general instruction Note: When using Toolwire to perform this lab, all software programs, files and projects will be located on the R:\ drive instead of C:\ Note: If you are unable to complete the lab at this time, you can download the lab files for this module from the Xilinx FTP site at ftp://ftp.xilinx.com/pub/documentation/education/lang11000-9-rev1-xlnx_lab_files.zip Creating n-Bit Counter with Generics Step For each procedure within a primary step, there are general instructions (indicated by the symbol) These general instructions only provide a broad outline for performing the procedure Below these general instructions, you will find accompanying step-by-step directions and illustrated figures that provide more detail for performing the procedure If you feel confident about completing a procedure, you can skip the step-by-step directions and move on to the next general instruction General Flow for this Lab: Step 1: Creating an n-Bit Counter with Generics Step 2: Creating a Testbench and Verifying Functionality Open the existing My_Class_Labs project within the ISE™ software, located in the R:\training\vhdl\labs directory  Select Start  Programs  Xilinx ISE 9.1i  Project Navigator to launch the Project Navigator By default, the ISE software should start with the last open project as the current project  If not, select File  Open Project  My_Class_Labs n-Bit Binary Counter and RTL Verification Lab www.xilinx.com 1-877-XLX-CLAS 12b-4 ! ! Important: Unless otherwise noted, you must label your project and HDL source files as instructed, or simulation may not work properly in the Toolwire environment  Select Project  New Source  In the New Source dialog box, select VHDL Module and enter MY_CNTR in the File name field  Click Next to open the table-based entity wizard  Use this table to enter the port data for the intended module Refer to the counter schematic in Figure 12b-1 Note that you cannot enter the generic at this point  When you are finished, click Next and click Finish The tool automatically creates the entity declaration based on the data entered in the table Note: After you exit the wizard, all subsequent edits are made in the HDL editor itself, including changes to items that were originally specified in the wizard Again, you cannot specify the generic by using the wizard You will simply specify the generic within the HDL text editor Also, in this particular model, you will need to reference the subprograms that allow arithmetic operations on arrays in VHDL The wizard in the ISE™ software includes some of these packages by default, and they are declared at the top of the file  Add the IEEE.numeric_std.all package to the file, as shown below: library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.numeric_std.all; These are so-called arithmetic packages and they are fully explained later in this course The text editor opens and the file shows the entity declaration This data is based on what was entered in the wizard The label is MY_CNTR with the ports as specified Specify the generics  Declare a VHDL generic to specify the port width for the input and output data bus Specify the generic as an integer with a default value of  Label the generic as you wish For examples on using generics, refer to the “Language Concepts” module or the quick reference card located near the front of this workbook n-Bit Binary Counter and RTL Verification Lab www.xilinx.com 1-877-XLX-CLAS 12b-5 After finishing the entity, complete the architecture shell Recall that this is a dependent (secondary) design unit to the entity To write the functional code for the binary counter, you will use a combination of nested if/else statements that accurately describe the counter operation In doing so, you must determine the priority of the if/else statements, which directly infer logic and functional priority For example, what is the priority of the control inputs, LOAD, RST, CE, and UPDN? Again, the nesting of if/else statements directly controls signal precedence ! ! You can find an example of a similar binary counter in the language templates of the ISE™ software Click either the Light Bulb button in the toolbar or select Edit  Language Templates You can copy and paste the HDL source code examples directly into the HDL editor  Using the generic, declare an 8-bit wide signal within the architecture with the name COUNT This signal will be updated and assigned within the clocked process  Outside the process, assign the value of the internal signal COUNT to the module’s output port Q_OUT; that is, Q_OUT LOAD_SIG, ce => CE_SIG, q_out => Q_OUT_SIG ); CLK_SIG