ĐIỆN tử VIỄN THÔNG 13 controlled operation v9 khotailieu

Controlled Operation Statements Objectives After completing this module, you will be able to: • • • Write if/else and if/elsif conditional statements Write a case conditional statement Write for loop statements for repetitive operations Controlled Operation Statements - 13 - â 2007 Xilinx, Inc All Rights Reserved Outline • • • • Controlled Operation Statements - 13 - If/Else Statements Case Statements Concurrent Form of If/Else and Case Statements Loop Statements Summary © 2007 Xilinx, Inc All Rights Reserved If/Else Statements • The if/else statement allows operations to be performed based on certain conditions It has three basic forms process begin if (boolean expression) then sequential statements; end if ; process begin if (boolean expression) then sequential statements ; else sequential statements ; end if ; Controlled Operation Statements - 13 - process begin if (boolean expression 1) then sequential statements ; elsif (boolean expression 2) then sequential statements ; elsif (boolean expression 3) then sequential statements ; else sequential statements ; end if ; © 2007 Xilinx, Inc All Rights Reserved If/Elsif Example and Rules • • • The first condition found to be true will be executed Conditions can overlap A B The first condition of an if/elsif has priority process (A, B, C, D, SEL ) begin if (SEL = “00”) then Z sequential statements ; when others => sequential statements ; end case ; end process ; © 2007 Xilinx, Inc All Rights Reserved Case Examples and Rules • • • • All possible values of the selector expression must be specified No conditions can overlap All range specifications must be of a discrete type Case statements are preferable for process (A, B, C, D, SEL) begin LUT-based architectures – Synthesis tools will produce a multiplexer A B Z C D Z Z Z Z end case ; end process ; © 2007 Xilinx, Inc All Rights Reserved Default Assignments • • Any conditional expression, if/else or case, should have the default explicitly stated to avoid compiler ambiguity and inferred latches However, there are two equally important considerations for the default – – Simulation: Visibility; should not obscure or mask problems Synthesis: Optimization, no additional logic, decreased performance process ( A, B, C, D, SEL ) begin process ( A, B, C, D, SEL ) begin if ( SEL = “00” ) elsif ( SEL = “01” ) elsif ( SEL = “10” ) elsif ( SEL = “11” ) end if ; then then then then end process ; – Z end case ; Z Z Z Z