ĐIỆN tử VIỄN THÔNG 08 signal datatypes v9 khotailieu

Signals and Data Types Objectives After completing this module, you will be able to: • Declare ports and signals by using appropriate data types • List possible values for each data type • Declare scalar and composite data types (array and record) • Declare one-dimensional and two-dimensional arrays • Declare and use VHDL subtypes Signals and Data Types - - © 2007 Xilinx, Inc All Rights Reserved Outline • • • • • Signals and Data Types - - Overview Scalar Types Composite Types 2-D Arrays Summary © 2007 Xilinx, Inc All Rights Reserved Data Types • The wide range of available data types provides flexibility in hardware modeling and builtin error checking to ensure signal compatibility in large, complex models – • Data types are very important in VHDL – – • Type checking rules must be obeyed in behavioral and gate-level models A given data type allows only values within its range to be applied Each object (signal, variable, constant, or port) must have its type defined when declared VHDL is a strongly typed language – Connected signals must be of the same type Signals and Data Types - - © 2007 Xilinx, Inc All Rights Reserved Signals and Ports • Data type and width must match on signal and port assignments entity REG_4 is port ( D_IN1 CNTRL CLK, RST Q end entity REG_4; signal signal signal signal : in std_logic_vector (3 downto 0); : in std_logic_vector (1 downto 0); : in std_logic; : out std_logic_vector (3 downto 0)); A : integer ; B : bit ; C : integer ; D : std_logic ; Signals and Data Types - - A