VHDL Simulation and RTL Verification Lab VHDL Simulation and RTL Verification Lab www.xilinx.com 1-877-XLX-CLAS 7b-2 VHDL Simulation and RTL Verification Lab Introduction In this lab, you will write a VHDL testbench for the AND_OR module completed in the previous exercise As part of the testbench, you will create a simple input stimulus by using both concurrent and sequential statements Objectives After completing this lab, you will be able to: Create a VHDL testbench to verify the AND_OR hierarchical structure created in the previous lab exercise Use the testbench wizard in the ISE™ software Create basic input stimulus Run a simulation Procedure Examine the circuit below (Figure 7b-1) In this lab, you will write a complete VHDL testbench description for the entity AND_OR VHDL Simulation and RTL Verification Lab www.xilinx.com 1-877-XLX-CLAS 7b-3 Figure 7b-1 Schematic for Upper-level Testbench with AND_OR as the UUT NOTE: Toolwire is the default platform for running labs Use R:\ for all directory references This lab comprises three primary steps: You will create a testbench with the VHDL testbench generation wizard in the ISE™ software; create concurrent and sequential input stimulus statements; and, finally, verify the logic structure by running a simulation, examining the waveforms, and verifying the intended functionality For each procedure within a primary step, there are general instructions (indicated by the symbol) These general instructions only provide a broad outline for performing the procedure Below these general instructions, you will find accompanying step-by-step directions and illustrated figures that provide more detail for performing the procedure If you feel confident about completing a procedure, you can skip the step-by-step directions and move on to the next general instruction Note: When using Toolwire to perform this lab, all software programs, files and projects will be located on the R:\ drive instead of C:\ Note: If you are unable to complete the lab at this time, you can download the lab files for this module from the Xilinx FTP site at ftp://ftp.xilinx.com/pub/documentation/education/lang11000-9-rev1-xlnx_lab_files.zip Creating a Testbench Step For each procedure within a primary step, there are general instructions (indicated by the symbol) These general instructions only provide a broad outline for performing the procedure Below these general instructions, you will find accompanying step-by-step directions and illustrated figures that provide more detail for performing the procedure If you feel confident about completing a procedure, you can skip the step-by-step directions and move on to the next general instruction General Flow for this Lab: Step 1: Creating a Testbench Step 2: Creating Simple Input Stimulus Step 3: Verifying Logic Functionality Open the existing My_Class_Labs project within the ISE software, located in the R:\training\vhdl\labs directory Select Start Programs Xilinx ISE 9.1i Project Navigator to launch the Project Navigator By default, the ISE software should start with the last open project as the current project VHDL Simulation and RTL Verification Lab www.xilinx.com 1-877-XLX-CLAS 7b-4 If not, select File Open Project My_Class_Labs ! ! Important: Unless otherwise noted, you must label your project and HDL source files as instructed, or simulation may not work properly in the Toolwire environment Select Project New Source In the New Source dialog box, select VHDL Test Bench and enter AND_OR_TB in the File name field The file type is implied; therefore, NOT type vhd (Figure 7b-2) Figure 7b-2 New Source Dialog Box Click Next The next dialog box prompts you for which module to associate with the testbench file This association is part of the automated design management capabilities within ISE™ software Select the top-level AND_OR module Click Next and click Finish in the Summary dialog box At this point, you have created a top-level testbench shell using a template within the ISE software that automates the structural portion of the testbench If you examine the file, you will see that the template contains the following: Component declaration: Based on the Unit Under Test (UUT) that you designated Signal declarations at top level: Using the same names as the ports on the UUT module VHDL Simulation and RTL Verification Lab Instantiation and port map: Connected the declared component and signals www.xilinx.com 1-877-XLX-CLAS 7b-5 Process shell for input stimulus: Convenient starting place for sequential stimulus VHDL Simulation and RTL Verification Lab www.xilinx.com 1-877-XLX-CLAS 7b-6 Creating Simple Input Stimulus Step General Flow for this Lab: Step 1: Creating a Testbench Step 2: Creating Simple Input Stimulus Step 3: Verifying Logic Functionality Create the actual input stimulus You will use both concurrent and sequential statements for input stimulus Specifically, you will treat the INP ( downto 0) bus as two separate portions by using the VHDL notation for a slice You will assign stimulus by using concurrent statements to one portion of the bus and sequential statements to the other Within the architecture, assign to the following slices INP ( downto ) use concurrent statements INP ( downto ) use sequential statements Create separate stimulus statements for INP ( downto 2) and INP ( downto 0) For examples on creating concurrent and sequential assignments, refer to page 6-24 in the “Introduction to Testbenches” module ! ! Note that when assigning to bus, std_logic_vector, for example, values are contained within double quotes For example: INP( downto ) INP, OUT1 => OUT1 ); INP(3 downto 2)