Thuật caching trong quản trị mạng lưu trữ

TRN TH VN NGA B GIO DC V O TO TRNG I HC BCH KHOA H NI - TRN TH VN NGA K THUT IN T TIN HC THUT CACHING TRONG QUN TR MNG LU TR LUN VN THC S KHOA HC K THUT IN T TIN HC KHO 2009 H Ni Nm 2012 B GIO DC V O TO TRNG I HC BCH KHOA H NI - H v tờn tỏc gi lun TRN TH VN NGA TấN TI LUN VN THUT CACHING TRONG QUN TR MNG LU TR Chuyờn ngnh: K thut in t tin hc LUN VN THC S KHOA HC K THUT IN T TIN HC NGI HNG DN KHOA HC TS NGUYN VIT NGUYấN H Ni - Nm 2012 MC LC DANH MC CC HèNH V, TH DANH MC CC BNG DANH MC CC Kí HIU, CC CH VIT TT LI CAM OAN LI NểI U PHN M U CHNG 1: TNG QUAN V CACHING 11 1.1 Lch s i 11 1.2 Khỏi nim 11 1.3 Nguyờn tc b nh cache 14 1.3.1 B nh cache 14 1.3.2 Tng quan v hot ng ca b nh cache 14 1.3.3 Cỏc yu t ca thit k cache 16 1.4 Mụ hỡnh cache c bn 26 1.4.1 Cache Hits 26 1.4.2 Cache Miss 27 1.4.3 Cache Consistency 28 1.5 Kin trỳc cache 28 1.5.1 Kin trỳc c 29 1.5.2 Chớnh sỏch vit 31 1.6 Cỏc thnh phn cache 34 1.6.1 SRAM 34 1.6.2 Tag RAM 34 1.6.3 B iu khin cache 34 1.7 Cache Organization 35 1.7.1 Fully-Associative (kt hp y ) 36 1.7.2 Direct Map 37 1.7.3 Set Associative 38 CHNG 2: THUT TON CACHING 39 2.1 Tng quan v mt s thut toỏn cache 39 2.1.1 Least Frequently Used (LFU) 39 2.1.2 Least Recently Used (LRU) 39 2.1.3 Least Recently Used (LRU2) 40 2.1.4 Adaptive Replacement Cache (ARC) 40 2.1.5 Most Recently Used (MRU) 40 2.1.6 First in First out (FIFO) 41 2.1.7 Simple time-based 42 2.1.8 Extended time-based expiration 42 2.1.9 Sliding time-based expiration 42 2.2 Mt s thut toỏn caching ni ting 43 2.2.1 Thut toỏn Cache Random (b nh cache ngu nhiờn) 43 2.2.2 Thut toỏn cache FIFO 46 2.2.3 Thut toỏn cache LFU 49 2.2.4 Thut toỏn cache LRU 52 CHNG 3: THUT TON CACHING TRONG H THNG LU TR TP TIN 58 3.1 Gii thiu 58 3.2 Cỏc thut toỏn thay th cache ca a cng 59 3.2.1 Thut toỏn LRU 59 3.2.2 Thut toỏn LFU 59 3.2.3 Thut toỏn FBR 61 3.2.4 Thut toỏn MIN 62 3.2.5 Thut toỏn RAND 62 CHNG 4: NH GI HIU SUT CA D LIU CACHING 64 4.1 Tng quan 64 4.2 Cu hỡnh chy mụ phng cache 67 4.3 Thit lp mụ phng 68 4.3.1 To file chy mụ phng 68 4.3.2 Phn mm TraceAnalyzer- phõn tớch tin vt 70 4.4 Phõn tớch v ỏnh giỏ kt qu mụ phng 72 4.4.1 ỏnh giỏ hiu sut ca cache ph thuc vo block size 72 4.4.2 ỏnh giỏ hiu sut ca cache ph thuc vo associative 73 KT LUN V HNG PHT TRIN 75 TI LIU THAM KHO 77 PH LC 80 Ph lc 1: tin mụ phng (*.c) 80 Ph lc 1: vớ d v trace file (*.tr) 81 Ph lc 3: Hng dn ci t simplescalar 84 DANH MC CC HèNH V, TH Hỡnh 1.1: T chc b nh mỏy tớnh 12 Hỡnh 1.2: V trớ ca b nh cache 14 Hỡnh 1.3: Cu to ca b nh cache v Main memory 15 Hỡnh 1.4: T chc b nh cache in hỡnh 15 Hỡnh 1.5: T chc ỏnh x trc tip 18 Hỡnh 1.6: Minh ỏnh x trc tip 19 Hỡnh 1.7: T chc Cache ỏnh x kt hp 20 Hỡnh 1.8: Minh ỏnh x kt hp 21 Hỡnh 1.9: T chc cache liờn kt K chiu 23 Hỡnh 1.10: Minh ỏnh x liờn kt 24 Hỡnh 1.11: Mụ hỡnh cache c bn 26 Hỡnh 1.12: Look Aside Cache 29 Hỡnh 1.13: Look Through Cache 30 Hỡnh 1.14: Write - back 32 Hỡnh 1.15: Write-through 33 Hỡnh 1.16: Cache page 35 Hỡnh 1.17: Fully-Associative Cache 36 Hỡnh 1.18: Direct Mapped 37 Hỡnh 1.19: 2-Way Set Associative 38 Hỡnh 3.1: Ba phn ca cache FBR 62 Hỡnh 4.1: B cụng c ca SimpleScalar 65 Hỡnh 4.2: Cu trỳc ca b mụ phng simplescalar 66 Hỡnh 4.3: Vớ d v on script chy mụ phng 69 Hỡnh 4.4: Thc hin mụ phng 70 Hỡnh 4.5: Phn mm phõn tớch tin vt (trace file) 71 Hỡnh 4.6: S ph thuc ca missrate vo block size 72 Hỡnh 4.7: S ph thuc ca missrate vo associative 74 DANH MC CC BNG Bng 1.1: Ba trng ca a ch b nh chớnh 17 Bng 1.2: Cache ỏnh x trc tip 17 Bng 2.1: Minh quỏ trỡnh thc hin cache ngu nhiờn 46 Bng 2.2: Minh quỏ trỡnh thc hin cache FIFO 48 Bng 3.1: m tham chiu ó thay i 61 Bng 4.1: Bng giỏ tr Miss_rate thay i block size 72 Bng 4.2: Bng giỏ tr Miss_rate thay i associative 73 DANH MC CC Kí HIU, CC CH VIT TT STT TấN VIT TT TấN Y PHIấN M DRAM Dynamic random-access memory Truy cp b nh ngu nhiờn ng SRAM Static random-access memory Truy cp b nh ngu nhiờn tnh TRAM Tag random-access memory Truy cp b nh ngu nhiờn theo th LFU Least Frequently Used t s dng thng xuyờn nht LRU Least Recently Used Gn õy s dng ớt nht LRU2 Least Recently Used Gn õy s dng ớt nht phiờn bn ARC Adaptive Replacement Cache B nh cache thay th thớch nghi MRU Most Recently Used Gn õy s dng nhiu nht FIFO First in First out 10 FBR Frequency Based Replacement Thay th da vo tn s 11 MIN Optimal strategy Chin lc thay th ti u 12 RAND Random replacement S thay th ngu nhiờn LI CAM OAN Li cam oan ca hc viờn: Tờn tụi l Trn Th Võn Nga, cam kt lun tt nghip l cụng trỡnh nghiờn cu ca bn thõn tụi di s hng dn ca TS Nguyn Vit Nguyờn ging viờn Vin in t Vin thụng trng i Hc Bỏch Khoa H Ni Cỏc kt qu nờu lun l trung thc, khụng phi l chộp ton ca bt k cụng trỡnh no khỏc H Ni, ngy 25 thỏng 03 nm 2012 Hc viờn Trn Th Võn Nga LI NểI U Trc ht, em xin c chõn thnh gi li cm n ti cỏc thy cụ giỏo trng i hc Bỏch Khoa H Ni ó tn tỡnh ging dy, truyn t cho em nhng kin thc, nhng kinh nghim quý bỏu thi gian hc v rốn luyn ti trng i hc Bỏch Khoa H Ni hon thnh ỏn ny em xin chõn thnh cm n thy giỏo TS Nguyn Vit Nguyờn, ging viờn Vin in t vin thụng - i hc Bỏch Khoa H Ni ó ch bo tn tỡnh v giỳp em sut quỏ trỡnh lm ỏn Trong quỏ trỡnh lm iu kin thi gian v trỡnh cú hn khụng th trỏnh nhng sai sút Vỡ vy em rt mong nhn c nhng ý kin ch bo quý bỏu ca cỏc thy cụ, cỏc ý kin úng gúp ca bn bố em cú th kp thi b sung, sa cha nhng thiu sút ca mỡnh Em xin chõn thnh cm n! H Ni, ngy 25 thỏng 03 nm 2012 Hc viờn: Trn Th Võn Nga Lp: Cao hc in t Tin hc 2009 PHN M U Lý chn ti Ngy cỏc b vi x lý ngy cng phỏt trin v tc v phc B nh cache l mt phn khụng th thiu cỏc b vi x lý B nh cache khụng phi l cụng ngh mi Trong thc t, u tiờn nú c trin khai cho mỏy ln hng chc nm trc õy Nu núi mt cỏch n gin thỡ cache giỳp cho vic truy xut d liu nhiu ln mt quỏ trỡnh x lý tr nờn nhanh hn Ngy nay, gn nh tt c cỏc thit b cú kh nng lu tr hay truy xut d liu u cú b nh cache Trong HDD cng cú, DVD cng cú Nhng tu theo cụng ngh v kh nng x lý m nú quyt nh cht lng, chi phớ v mc ớch s dng ca nú Mi loi cache u ci thin tc truy xut v x lý d liu Vic s dng b nh cache hiu qu giỳp hiu sut x lý ca h thng tng cao Vi s phỏt trin nhanh v mt cụng ngh cng nh yờu cu v x lý d liu vi lng ln, yờu cu x lý nhanh nh ngy thỡ vic s dng b nh cache nh th no hiu qu s l mt bi toỏn cn gii quyt Cỏc thut toỏn cache cn cú thi gian x lý nhanh, xung t d liu hay t l li d liu thp (miss_rate) s l yờu cu tiờn quyt Cng nhiu d liu c trao i vi vựng m thỡ chng trỡnh phi quyt nh cng nhiu cỏch thc s dng tt nht khụng gian nh cho phộp V cng s dng n vựng m thỡ cng chng t hiu qu ca cache Vi cỏc lý nờu trờn tỏc gi ó chn lun ca mỡnh l Thut caching qun tr mng lu tr v nghiờn cu sõu v ỏnh giỏ hiu nng ca d liu caching Mc ớch nghiờn cu ca lun Tỡm hiu lý thuyt cache Nghiờn cu mt s thut toỏn cache Nghiờn cu vic ng dng thut toỏn cache h thng lu tr TraceAnalyzer (phn mm phõn tớch tin du vt) t ng húa khõu to tin mụ phng vi vic thay i cỏc tham s t ng v t ng húa khõu phõn tớch tin du vt lm tng hiu qu v nng sut thc hin mụ phng cng nh phõn tớch v ỏnh giỏ kt qu Hng phỏt trin ca ti Trong khuụn kh thi gian cú hn nờn lun mi ch trung nghiờn cu mt s thut toỏn cache v ỏnh giỏ hiu nng ca d liu cache thay i mt s thụng s Trong thi gian ti tỏc gi s tip tc nghiờn cu sõu hn v cỏc thut toỏn cache khỏc Thờm vo ú cũn mt s khỏc ca cache cn c nghiờn cu sõu hn nh: ng dng cache h c s d liu Cache i vi web site Cht lng dch v hon thnh ỏn ny em xin chõn thnh cm n thy giỏo TS Nguyn Vit Nguyờn ging viờn Vin in t vin thụng - i hc Bỏch Khoa H Ni ó ch bo tn tỡnh v giỳp em sut quỏ trỡnh lm ỏn Em rt mong nhn c nhng ý kin ch bo quý bỏu ca cỏc thy cụ, cỏc ý kin úng gúp ca bn bố em cú th kp thi b sung, sa cha nhng thiu sút ca mỡnh Em xin chõn thnh cm n! 76 TI LIU THAM KHO Bach, M J., The Design of the UNIX Operating System, Prentice-Hall, 1986 Baker, M G., Hartman, J H., Kupfer, M D., Shirriff, K W., and Ousterhout, J K., "Measurements of a Distributed File System," Proceedings of the 13th ACM Symposium on Operating System Principles, October 1991, pp 198-212 Korner, K., "Intelligent Caching for Remote File Service," ICDCS, May 1990, pp 220-226 Leffler, S J., McKusick, M K., Karels, M J., and Quarterman, J S., The Design and Implementation of the Jf BSD UNIX Operating System, Addison Wesley, 1989 Makaroff, D J., and Eager, D L., "Disk Cache Performance for Distributed Systems," ICDCS, May 1990, pp 212-219 Muller, K and Pasquale, J., "A High Performance Multi-Structured File System Design," Proceedings of the 13th ACM Symposium on Operating System Principles, October 1991, pp 56-67 Ousterhout, J K., Da Costa, H., Harrison, D., Kunze, J A., Kupfer, M and Thompson, J G., "A Trace-Driven Analysis of the UNIX 4.2 BSD File System," Proceedings of the 10th ACM Symposium on Operating System Principles, December 1985, pp 15-24 Robinson, J T., and Devarakonda, M V., "Data Cache Management Using Frequency-Based Replacement," Proceedings of the ACM SIGMETRICS Conference on Measurement and Modeling of Computer Systems, May 1990, pp 134-142 77 Rosenblum, M., and Ousterhout, J., K., "The Design and Implementation of a Log-Structured File System," Proceedings of the 13th ACM Symposium on Operating System Principles, October 1991, pp 115 10 Venkat Rangan, P., and Harrick, M Vin, "Designing File Systems for Digital Video and Audio," Proceedings of the 13th ACM Symposium on Operating System Principles, October 1991, pp 81-94 11 U Hahn, W Dilling, and D Kaletta Adaptive replacement algorithm for disk caches in hsm systems In 16 Intl Symp on Mass Storage Syst., pages 128 140, San Diego, California, Mar 15-18 1999 12 E J ONeil, P E ONeil, and G Weikum The LRU-K page replacement algorithm for database buffering In Proc ACM SIGMOD93: Intl Conf on Mgmnt of Data, pages 297 306, Washington, DC, May 1993 13 Ari, M Gottwals, and D Henze SANBoost: Automated SAN-level caching in storage area networks In Proceedings of the 1st International Conference on Autonomic Computing (ICAC 04), pages 164171, 2004 14 E J ONeil, P E ONeil, and G Weikum The LRU-K page replacement algorithm for database disk buffering In Proceedings of the 1993 ACM SIGMOD International Conference on Management of Data, pages 297 306, 1993 15 Sibel Adali, K Selỗuk Candan, Yannis Papakonstantinou, and V S Subrahmanian Query Caching and Optimization in Distributed Mediator Systems Proc ACM SIGMOD International Conference on Management of Data, Montreal, Quebec, Canada, June 1996 78 16 Shaul Dar, Michael J Franklin, Bjửrn ịúr Júnsson, and Divesh Srivastava, Michael Tan Data Caching and Replacement Proc Very Large Data Bases Conference, Bombay, India, 1996 17 C Mohan Caching Technologies for Web Applications Tutorial at Very Large Data Bases Conference, Roma, Italy, 2001 http://www.almaden.ibm.com/u/mohan/Caching_VLDB2001.pdf 18 SimpleScalar SimpleSclar home page [Online] [Cited: March 26, 2008.] http://www.simplescalar.com 19 Al-Issa, Khalid A Simplescalar Installation guide [Online] [Cited: den 26 March 2008.] http://www.studiokhalid.com/simplescalar/simplescalar.htm 79 PH LC Ph lc 1: tin mụ phng (*.c) #define TAB_SIZE #define CACHE_SIZE 1048576 16384 /* MB */ /* 16 kB */ int main(void) { int int int A[TAB_SIZE]; sum; i, j; /* * Initialization */ sum = 0; for (i = 0; i < TAB_SIZE; i++) { A[i] = 1; } /* * Data referencing */ for (i = 0; i < TAB_SIZE - CACHE_SIZE; i++) { for (j = 0; j < 5; j++) { sum += A[i]; sum += A[i+CACHE_SIZE]; } } printf("Sum = %d\n", sum); return 0; } 80 Ph lc 1: vớ d v trace file (*.tr) sim-cache: SimpleScalar/PISA Tool Set version 3.0 of August, 2003 Copyright (c) 1994-2003 by Todd M Austin, Ph.D and SimpleScalar, LLC All Rights Reserved This version of SimpleScalar is licensed for academic non-commercial use No portion of this work may be used by any commercial entity, or for any commercial purpose, without the prior written permission of SimpleScalar, LLC (info@simplescalar.com) sim: command line: /home/ubuntu/simplescalar/simplesim-3.0/sim-cache cache:il1 il1:16:32:2:l -cache:il2 none -cache:dl1 dl1:16:32:2:l cache:dl2 none -tlb:itlb none test1 sim: simulation started @ Mon Mar 26 11:49:26 2012, options follow: sim-cache: This simulator implements a functional cache simulator Cache statistics are generated for a user-selected cache and TLB configuration, which may include up to two levels of instruction and data cache (with any levels unified), and one level of instruction and data TLBs No timing information is generated # -config # load configuration from a file # -dumpconfig # dump configuration to a file # -h false # print help message # -v false # verbose operation # -d false # enable debug message # -i false # start in Dlite debugger -seed # random number generator seed (0 for timer seed) # -q false # initialize and terminate immediately # -chkpt # restore EIO trace execution from # -redir:sim # redirect simulator output to file (non-interactive only) # -redir:prog # redirect simulated program output to file -nice # simulator scheduling priority -max:inst # maximum number of inst's to execute -cache:dl1 dl1:16:32:2:l # l1 data cache config, i.e., {|none} -cache:dl2 none # l2 data cache config, i.e., {|none} -cache:il1 il1:16:32:2:l # l1 inst cache config, i.e., {|dl1|dl2|none} -cache:il2 none # l2 instruction cache config, i.e., {|dl2|none} -tlb:itlb none # instruction TLB config, i.e., {|none} -tlb:dtlb dtlb:32:4096:4:l # data TLB config, i.e., {|none} -flush false # flush caches on system calls -cache:icompress false # convert 64-bit inst addresses to 32bit inst equivalents 81 # -pcstat (mult uses ok) # profile stat(s) against text addr's The cache config parameter has the following format: :::: random - Examples: name of the cache being defined number of sets in the cache block size of the cache associativity of the cache block replacement strategy, 'l'-LRU, 'f'-FIFO, 'r'-cache:dl1 dl1:4096:32:1:l -dtlb dtlb:128:4096:32:r Cache levels can be unified by pointing a level of the instruction cache hierarchy at the data cache hiearchy using the "dl1" and "dl2" cache configuration arguments Most sensible combinations are supported, e.g., A unified l2 cache (il2 is pointed at dl2): -cache:il1 il1:128:64:1:l -cache:il2 dl2 -cache:dl1 dl1:256:32:1:l -cache:dl2 ul2:1024:64:2:l Or, a fully unified cache hierarchy (il1 pointed at dl1): -cache:il1 dl1 -cache:dl1 ul1:256:32:1:l -cache:dl2 ul2:1024:64:2:l sim: ** starting functional simulation w/ caches ** Sum = 10321920 sim: ** simulation statistics ** sim_num_insn 493920285 # total number of instructions executed sim_num_refs 87822277 # total number of loads and stores executed sim_elapsed_time 49 # total simulation time in seconds sim_inst_rate 10080005.8163 # simulation speed (in insts/sec) il1.accesses 493920285 # total number of accesses il1.hits 493919274 # total number of hits il1.misses 1011 # total number of misses il1.replacements 979 # total number of replacements il1.writebacks # total number of writebacks il1.invalidations # total number of invalidations il1.miss_rate 0.0000 # miss rate (i.e., misses/ref) il1.repl_rate 0.0000 # replacement rate (i.e., repls/ref) il1.wb_rate 0.0000 # writeback rate (i.e., wrbks/ref) il1.inv_rate 0.0000 # invalidation rate (i.e., invs/ref) dl1.accesses 87822372 # total number of accesses dl1.hits 87432769 # total number of hits dl1.misses 389603 # total number of misses dl1.replacements 389571 # total number of replacements dl1.writebacks 131497 # total number of writebacks dl1.invalidations # total number of invalidations 82 dl1.miss_rate 0.0044 dl1.repl_rate 0.0044 repls/ref) dl1.wb_rate 0.0015 dl1.inv_rate 0.0000 invs/ref) dtlb.accesses 87822372 dtlb.hits 87819321 dtlb.misses 3051 dtlb.replacements 2923 dtlb.writebacks 1025 dtlb.invalidations dtlb.miss_rate 0.0000 dtlb.repl_rate 0.0000 repls/ref) dtlb.wb_rate 0.0000 dtlb.inv_rate 0.0000 invs/ref) ld_text_base 0x00400000 ld_text_size 73568 bytes ld_data_base 0x10000000 base ld_data_size 8304 uninit'ed `.bss' size in bytes ld_stack_base 0x7fffc000 (highest address in stack) ld_stack_size 16384 ld_prog_entry 0x00400140 ld_environ_base 0x7fff8000 address ld_target_big_endian non-zero if big endian mem.page_count 1050 mem.page_mem 4200k allocated mem.ptab_misses 1050 misses mem.ptab_accesses 2151784292 mem.ptab_miss_rate 0.0000 # miss rate (i.e., misses/ref) # replacement rate (i.e., # writeback rate (i.e., wrbks/ref) # invalidation rate (i.e., # # # # # # # # total number of accesses total number of hits total number of misses total number of replacements total number of writebacks total number of invalidations miss rate (i.e., misses/ref) replacement rate (i.e., # writeback rate (i.e., wrbks/ref) # invalidation rate (i.e., # program text (code) segment base # program text (code) size in # program initialized data segment # program init'ed `.data' and # program stack segment base # program initial stack size # program entry point (initial PC) # program environment base address # target executable endian-ness, # total number of pages allocated # total size of memory pages # total first level page table # total page table accesses # first level page table miss rate 83 Ph lc 3: Hng dn ci t simplescalar Phn mm simplescalar cú th ci t phn mm simplescalar trờn h iu hnh Linux v windows Trong phn ny tỏc gi gii thiu ci t trờn Ubuntu Trc ht cn download cỏc gúi source code nh sau ti a ch www.simplescalar.com tin hnh ci t: - simplesim-3v0d.tgz - simpleutils-990811.tar.gz - gcc-2.7.2.3.ss.tar.gz - simpletools-2v0.tgz Bc 1: Thit lp cỏc bin mụi trng To mt th mc simplescalar Th mc ny s l th mc gc ci t cha ton b cụng c SimpleScalar Th mc nờn c t /home//simplescalar M ca s terminal v ỏnh: uname -a bit c phiờn bn ca h iu hnh ó ci t (i386/i686) Tựy thuc vo giỏ tr nhn c trờn s s dng HOST=i686-pc-linux hoc HOST=i386-pc-linux $ export HOST= bờn trờn $ export IDIR=/home/YOUR_USER_NAME/simplescalar $ export TARGET=sslittle-na-sstrix m bo rng ó ci y cỏc gúi tin sau: flex bison build-essential 84 Nu cha ci s dng dũng lnh sau ci sudo apt-get install Bc 2: Tin hnh ci t Copy tt c cỏc gúi source code c download trờn vo th mc gc simplescalar v ng ti th mc gc ny Ci t simple tools: Gii nộn file simpletools-2v0.tgz v xúa th mc gcc $ cd $IDIR $ tar xzvf simpletools-2v0.tgz $ rm -rf gcc-2.6.3 Ci t SimpleUtils Gii nộn file simpleutils-990811.tar.gz: $ tar xzvf simpleutils-990811.tar.gz $ cd simpleutils-990811 Trc build, cn phi sa mt s li nh sau: Trong th mc ld m file ldlex.l v thay th yy_current_buffer bng YY_CURRENT_BUFFER Cú th thc hin bng cỏc cõu lnh sau: $ find -type f -print0 | xargs -0 sed -i -e s,yy_current_buffer,YY_CURRENT_BUFFER,g $ /configure host=$HOST target=$TARGET with-gnuas with-gnu-ld prefix=$IDIR $ make 85 $ make install Ci t Simulator Gii nộn gúi tin simplesim-3v0d.tgz thc hin cỏc lnh bờn di: $ cd $IDIR $ tar xzvf simplesim-3v0d.tgz $ cd simplesim-3.0 $ make config-pisa $ make Sau ci t thnh cụng cú th th bng cõu lnh: $ /sim-safe tests/bin.little/test-math Ci t GCC Cross-Compiler cho kin trỳc SimpleScalar õy l bc rt quan trng phi thc hin tht chớnh xỏc Tin hnh ci t theo cỏc bc nh sau: $ cd $IDIR $ tar xzvf gcc-2.7.2.3.ss.tar.gz $ cd gcc-2.7.2.3 $ export PATH=$PATH:/home/YOUR_USER_NAME/simplescalar/sslittlena-sstrix/bin $ /configure host=$HOST target=$TARGET with-gnuas with-gnu-ld prefix=$IDIR Trc thc hin tit cn phi sa mt s li: 86 M file Makefile ti dũng 130 thay th I/usr/include vo cui dũng thc hin chy dũng ln sau $ gedit Makefile M file protoize.c ti dũng 60, thay th #include bng #include thc hin s dng cõu lnh sau: $ chmod +w protoize.c $ gedit protoize.c M file obstack.h ti dũng s 341 Thay th *((void **) o->next_free)++=((void *)datum); Bng *((void **) o->next_free++)=((void *)datum); thc hin s dng cõu lờnh $ chmod +w obstack.h $ gedit obstack.h Copy patched file th mc patched a vo v trớ tng ng bờn di thc hin theo cỏc cõu lnh: 87 $ cp /patched/sys/cdefs.h /sslittle-nasstrix/include/sys/cdefs.h $ cp /sslittle-na-sstrix/lib/libc.a /lib/ $ cp /sslittle-na-sstrix/lib/crt0.o /lib/ Download file (http://www.igoy.in/wp-content/uploads/2009/09/arranlib.tar.gz), gii nộn v a vo th mc $IDIR/sslittle-na-sstrix/bin ng thi phi m bo rng tt c cỏc file th mc ny cú cỏc quyn execution & write permission kim tra dựng cõu lnh: $ cd $IDIR/sslittle-na-sstrix/bin ls -al (nu file no m cha cú quyn thỡ s dng cõu lnh sau thay:chmod +w , chmod +x ) Sau kim tra xong, thc hin cõu lnh: $ make Tip tc nhn c mt s li Sa li nh sau: M file insn-output.c, b du \ ti cui cỏc dũng 675, 750 v 823 m file s dng cõu lnh: $ gedit insn-output.c $ make M file objc/sendmsg.c, ti dũng 35 thờm on code #define STRUCT_VALUE Cỏch thc hin nh sau: 88 $ cd $IDIR/gcc-2.7.2.3/objc $ chmod +w sendmsg.c $ gedit sendmsg.c $ cd $ make LANGUAGES="c c++" CFLAGS="-O" CC="gcc" Li cui cựng cn phi sa, m file cxxmain.c, xúa b dũng ti v trớ 29782979, ni dung dũng ú l: char * malloc (); char * realloc (); thc hin s dng cõu lnh: $ chmod +w cxxmain.c $ gedit cxxmain.c Tip tc thc hin cỏc cõu lnh $ make LANGUAGES="c c++" CFLAGS="-O" CC="gcc" $ make install LANGUAGES="c c++" CFLAGS="-O" CC="gcc" Kim tra kim tra, to mt file vi tờn hello.c cú ni dung nh sau: #include main (void) { printf(Kiem tra mo phong); } Thc hin cõu lnh: 89 $ $IDIR/bin/sslittle-na-sstrix-gcc -o hello hello.c $ $IDIR/simplesim-3.0/sim-safe hello V kt qu s tr v nh bờn di: sim: ** starting functional simulation ** My name is Tran Thi Van Nga sim: ** simulation statistics ** sim_num_insn 9242 # total number of instructions executed sim_num_refs 4328 # total number of loads and stores executed sim_elapsed_time # total simulation time in seconds sim_inst_rate 9242.0000 # simulation speed (in insts/sec) ld_text_base 0ì00400000 # program text (code) segment base ld_text_size 71968 # program text (code) size in bytes ld_data_base 0ì10000000 # program initialized data segment base ld_data_size 8528 # program inited `.data and uninited `.bss size in bytes ld_stack_base 0ì7fffc000 # program stack segment base (highest address in stack) ld_stack_size 16384 # program initial stack size ld_prog_entry 0ì00400140 # program entry point (initial PC) ld_environ_base 0ì7fff8000 # program environment base address address ld_target_big_endian # target executable endian-ness, non-zero if big endian mem.page_count mem.page_mem 26 # total number of pages allocated 104k # total size of memory pages allocated mem.ptab_misses 26 # total first level page table misses mem.ptab_accesses 495046 # total page table accesses mem.ptab_miss_rate 0.0001 # first level page table miss rate 90 ... văn TRẦN THỊ VÂN NGA TÊN ĐỀ TÀI LUẬN VĂN THUẬT CACHING TRONG QUẢN TRỊ MẠNG LƯU TRỮ Chuyên ngành: Kỹ thuật điện tử tin học LUẬN VĂN THẠC SĨ KHOA HỌC KỸ THUẬT ĐIỆN TỬ TIN HỌC NGƯỜI HƯỚNG DẪN KHOA... tác giả chọn luận văn Thuật caching quản trị mạng lưu trữ nghiên cứu sâu đánh giá hiệu liệu caching Mục đích nghiên cứu luận văn • Tìm hiểu lý thuyết cache • Nghiên cứu số thuật toán cache • Nghiên... CHƯƠNG 3: THUẬT TOÁN CACHING TRONG HỆ THỐNG LƯU TRỮ TẬP TIN 58  3.1 Giới thiệu 58  3.2 Các thuật toán thay cache đĩa cứng 59  3.2.1 Thuật toán LRU 59  3.2.2 Thuật