Sơ đồ khối Mainboard G41 MD

route the lines in parallel 10 mils width 7 mils spacing to low speed signals14mils spacing to high speed signalsmax.. 1200mils placed near pin D23, within 500 mils 4 mils width, 10 mils

Trang 2

Serial & Parallel

VGA Connector

Yorkfield Wolfdale LGA775 Processor

Trang 3

SLP_S3#

LGA775 processor

ATX Power

RSMRST circuit

PWRGD_3V

ACZ_RST#

Translation Circuitry

PCIe LAN

RST#

TPM

Trang 4

PCI Express/DMI 100 MHz Diff Pair

DOT 96 MHz Diff Pair

PCI Express x16 Gfx

USB/SIO 48 MHz PCI Express/DMI 100 MHz Diff Pair PCI Express 100 MHz Diff Pair

ICH 33 MHz MCH 200/266/333 MHz Diff Pair

REF 14 MHz

SATA 100 MHz Diff Pair

G41

CPU 200/266/333 MHz Diff Pair

PCI Express 100 Mhz Diff Pair

PCI Slot 1 PCI 33 MHz

SPI

SPI Clock

Trang 5

4.345A(S0,S1) 22mA(S3)

5VSB

Linear 1.25V

to 1.05V V_1P05V_ICH 2A

-12V Icc(Max)=0.1A -12V

3.3VSB Icc(Max)=0.375A(wake) Icc(Max)=0.02A(no wake)

+5V DUAL=5A(S0, S1) +5V DUAL=20mA(S3)

3.3V

LDO 12V

to 5V

HDA Codec

FSB_Vtt 1.2V FSB Vtt Icc(Max)=1.3A

Single Phase Switch 5V to 1.8V Ivdd(Max)=TBD LDO

1.8V to 0.9V Ivterm(Max)=1.2A

3.3V Icc(Max)=50mA

*1.25V (DMI&PCIe) VCCA_EXP 2.5A

3.3SBV Icc(Max)=50mA(S0)

1.5V VCCGLAN1_5 74mA

DDR2 Channel A

5V

CK505

Vccp (CPU Vcore) Voltage=1.15~1.5V Icc(Max)=125A 3-Phases Swithing

5V_STBY to 3.3SB 1.5A

VRD 11 Switching Three Phase

Linear 1.8V

to 1.2V 6A

1.2V FSB Vtt=5.3A

3.3V VccCL3_3 12mA 3.3V VccSUS3_3 141mA 3.3V VccLAN (10/100) 12mA 3.3V VccSUSHDA 4mA 3.3V VCC3_3 310mA 3.3V VccGLAN3_3 1mA 3.3V VccHDA 4mA

RTC=5uA RTC

3.3SBV Icc(Max)=38mA(S3)

FWH

3.3V=107mA(S0, S1)

PCI Per Slot (X2)

12V Icc(Max)=0.5A

5V Icc(Max)=5A 3.3V Icc(Max)=7.6A

PCI Express X16 slot (1)

+12V=5.5A

+3.3V=3A 3.3V VCCA_DAC 70mA

3.3V VCC3_3 15.8mA

PS2

+5V DUAL=345mA(S0, S1) +5V DUAL=2mA(S3)

PCI Express X1 Per slot (1)

+12V=0.5A

+3.3V=3A

3.3V STBY

IO LED 15.5nA 1.8V ANALOG 418.2mA

Nineveh GbE Lan

1.0V Internal 1.8

to 1.0 VR core 277.2mA

BJT

1.25V VCCDMI 40mA

Linear 1.8V

to 1.5V V_1P5V_ICH 2.2A

Vdd (Core)=1.8V

Ivdd(Max)=TBD(per channel)

12V

Trang 6

VIDPWRGD +3D3V_DUAL

+5V_SYS

PS_ONJ

VTT_VR

Vcc_PWRGD VTT_VR

VIDPWRGD

+5V_SYS

VRM_OUTEN VTT_DDR

VIDPWRGD

S0->S5

+3D3V_SYS +12V_SYS

VRM_OUTEN

PS_ONJ VTT_VR

1ms to 10ms

+1D8V_STR +1D8V_STR

Trang 7

CK_48M_SIOCK_48M_ICH

3D3V_CLK

CK_33M_SIOCK_33M_ICHCK_33M_PCI1

CK_33M_SIOCK_33M_PCI2

CK_33M_ICHCK_33M_PCI1

ICS_FSBSEL0CK_48M_ICH

X1X2X1

PE_100M_N_GMCHPE_100M_N_ICHPE_100M_P_ICH

3D3V_SYS

FSB_VTT3D3V_CLK

3D3V_SYS

3D3V_CLK

3D3V_CLK3D3V_CLK

3D3V_CLK

FSBSEL0 12,14FSBSEL1 12,14FSBSEL2 12,14VRMPWRGD 9,22

CK_14M_ICH22

CK_33M_SIO30CK_33M_PCI236

CK_33M_ICH24

CK_33M_PCI136

CK_48M_ICH22CK_48M_SIO30

CK_96M_P_GMCH14CK_96M_N_GMCH14

CK_SATA_100M_N_ICH23

CK_SATA_100M_P_ICH23

CK_PE_100M_P_LAN28

CK_PE_100M_N_LAN28

DPL_REFSSCLKIN_P14

DPL_REFSSCLKIN_N14

CK_PE_100M_P_16PORT20

CK_PE_100M_N_16PORT20

SMB_CLK_MAIN18,19,20,22,27,31,36SMB_DATA_MAIN 18,19,20,22,27,31,36

CK_200M_N_CPU12CK_200M_P_CPU12

CK_200M_N_GMCH14CK_200M_P_GMCH14ICH_SYS_RSTJ 8,12,22

CK_PE_100M_N_GMCH 14CK_PE_100M_P_GMCH14CK_PE_100M_P_ICH 22CK_PE_100M_N_ICH 22CK_PE_100M_N_1PORT27CK_PE_100M_P_1PORT 27

266MHz(1066) 0

0 1

0 1 0

133MHz(533) 200MHz(800)

FS_AFS_BFS_C

+/-5%

R11133

+/-5%

* R1204.7K

CP2X_COPPERCP2

50V, NPO, +/-5%

Dummy

*C146

Dummy

CP7X_COPPER

Dummy

X3

XTAL-14.318MHzX3

XTAL-14.318MHz12

*C127

*R1278.2K

+/-5%

*R1278.2K

**DOC_02

**DOC_13GND44PCICLK0_2X5

**SEL_STOP/PCICLK1_2X6

PCICLK2_2X7FSLC/PCICLK3_2X8

FSLB/PCICLK4_2X9

VDDPCI10PCICLK5_2X11PCICLK6_2X12VDD4813FSLA/USB_4814

*SEL24_48#/24_48Mhz15

GND1616DOT96T_LR/PCIeT_LR017

DOT96C_LR/PCIeC_LR018

GND1919SATACLKT_LR20SATACLKC_LR21VDDSATA22GND2323Vtt_PwrGd#/WOL_STOP#

24PCIeT_LR025PCIeC_LR026GND2727VDD28

+/-5%

*RN15470

+/-5%

1584

+/-5%*C116

Dummy

CP3X_COPPER

+/-5%*C117

Trang 8

3D3V_SYS 3D3V_SYS 3D3V_SYS

12V_SYS 5V_SYS

5V_SYS

SPKR 22

PS_ONJ 30

ICH_SYS_RSTJ 7,12,22

SIO_BEEP 30

PBTNJ_SIO 30

PWRG_ATX 11,30

HDD_LEDJ 23

Front Panel Switch/LED

HD_LED- 3 4 Power LED(Green)

Change to 5% or not

place at power connecter

Q49 MMBT3904-7-F Q49

, + *

C472 0.1uF

Dummy

*

C471 220pF

Dummy

*

C465 0.1uF

* R387 10K +/-5%

*

C454 10nF

Dummy

*

C492 220pF 50V, NPO, +/-5%

Dummy

R390 330 +-5%

*

C463 0.1uF 16V, Y5V, +80%/-20%

Dummy

*

C463 0.1uF 16V, Y5V, +80%/-20%

* R374 4.7K +/-5%

*

C462 0.1uF

R391 330 +-5%

*

C487 220pF

Dummy

*

C487 220pF

Dummy

*

C240 0.1uF

* R358 4.7K +/-5%

*

C464 0.1uF

* R375 4.7K +/-5%

*

C350 0.1uF

, + Dummy

* C473 0.1uF

Dummy

*

C490 220pF 50V, NPO, +/-5%

Dummy

*

C466 0.1uF 16V, Y5V, +80%/-20%

*

C466 0.1uF 16V, Y5V, +80%/-20%

* RN45

100 Ohm +/-5%

* RN45

100 Ohm +/-5%

1 5 8 4

BUZZER

BUZ

Buzzer Dummy

BUZZER

BUZ

Buzzer Dummy

+

-SPEAKER

Header_1X4_K2 SPEAKER

Header_1X4_K2

1 1

3 3 4 4

Q47

BAT54C Q47

BAT54C

2

1 3

*

C347 0.1uF

* R378 4.7K +/-5%

*

C476 0.1uF

Header_2X5_K10 X FP1

Header_2x12

+3.3V1 1 +3.3V2 2 +5V1 4 GND1 3

+5V2 6 GND2 5

+12V_1 10 +5V_AUX 9 PWR0K 8 GND3 7

+3.3V3 13 -12V 14 GND4 15 PSON 16 GND5 17 GND6 18 GND7 19 RSVD 20 +5V3 21 +5V4 22 +12V_2 11 +3.3V4 12 +5V5

23 GND8 24

* C481 0.1uF

, + *

C455 0.1uF

* R393 10K +/-5%

Q46 MMBT3904-7-F Q46 MMBT3904-7-F

B

* C488 0.1uF

Trang 9

LG1

ISP1

Phase1FBRTN

12V_VRM

12V_VINVCCP

VID112

VID212

VID312

VID412

VID512

VID612

VID_SELECT:VR10.1 connect GND; VR11 connect VTT

R1442.2

+/-5%

R1442.2

+/-5%

*R10710K

+/-1%

R1981K

+/-1%

*C368

1nF

/- *C368

+/-5%

R1000

+/-5%

R822.2

+/-5%

Q20

AOD472Q20

AOD472G

VIDSEL1VID 040VID 139VID 238VID 337VID 436VID 535VID 634

PWRGD31

AOD472G

*C124

0.1uF

*C124

0.1uF

*C176

4.7uF

25V, Y5V, +80%/-20%

*C176

+/-1%

DummyR2091K

+/-1%

Dummy

*C92

0.1uF

*C92

+/-5%

*R11310K

+/-1%

*R1839.1K

+/-1%

R18722K

PWM2

NC3

VCC4

G

*C247

1uF

+/-10%

*C247

1uF

+/-10%

*C258

0.1uF

25V, X7R, +/-10%

*C258

0.1uF

25V, X7R, +/-10%

D25LS4148-FD25LS4148-F

+/-1%

DummyT *R17810K

0.1uFDummy

*C102

0.1uFDummy

*C179

4.7uF

25V, Y5V, +80%/-20%

*C179

AOD472G

R1052.2

+/-5%

R1052.2

+/-1%

*R1921.6K

+/-1%

R1770+/-5%*R1770+/-5%

* R1860

+/-5%

Dummy

* R1860

25V, X7R, +/-10%

Dummy

*C281

+/-5%

*R18239K

+/-5%

*C363

1nF

/- *C363

1uF

+/-10%

*C264

1uF

+/-10%

*C257

0.1uF

16V, X7R, +/-10%

Dummy

*C257

+/-5%

*

R176620

+/-5%

*R10110K

1nF

/- *C165

0.1uF

25V, X7R, +/-10%

*C248

0.1uF

25V, X7R, +/-10%

*C271

0.1uF

25V, X7R, +/-10%

*C241

0.1uF

25V, X7R, +/-10%

*C245

0.1uF

25V, X7R, +/-10%

Dummy

*C245

0.1uF

25V, X7R, +/-10%

Dummy

R1502.2

+/-5%

R1502.2

0.1uF

*C105

0.1uF

Trang 10

Pull FB trace out after Cout

R638,R658 must less than 1k

Can change to 0402 or not

Need to change to RUBYCON16MBZ470MEFC8X11.5

*R355470

+/-5%

*R355470

+/-5%

Q382N7002Q382N7002

P3055LDGG

0.1uF

25V, X7R, +/-10%

*C316

0.1uF

16V, Y5V, +80%/-20%

*C273

APW7120KE-TRL

COMP/OCSET7

FB6

AOD472ALG

Q41

P3055LDGQ41

P3055LDGG

*R29124K

+/-1%

*R29124K

U18D

LM324DR2G

Reserved

+-

U18D

LM324DR2G

Reserved

121314

*C447

0.1uF

16V, Y5V, +80%/-20%

*C447

0.1uF

16V, Y5V, +80%/-20%

*R3601.5KOhm

+/-1%

*R3601.5KOhm

1uF

10V, Y5V, +80%/-20%

*C432

+/-5%

R2272.2

+/-5%

+-

U18CLM324DR2G

+-

U18CLM324DR2G10

98

+/-1%

*R37021KOhm

+/-1%

R2572.2

+/-5%

R2572.2

+/-5%

*C451

1uF

10V, Y5V, +80%/-20%

*C451

1uF

10V, Y5V, +80%/-20%

*C158

0.1uF

16V, Y5V, +80%/-20%

*C158

+/-1%

R3661.02KOhm

U18A

LM324DR2G

+-

U18A

LM324DR2G3

21

U18B

LM324DR2G

+-

U18B

LM324DR2G5

67

*C441

0.1uF

16V, Y5V, +80%/-20%

Dummy

*C441

P3055LDGG

+/-5%

*R22510K

+/-5%

*R3611K

+/-5%

*R36912KOhm

+/-1%

*R36912KOhm

+/-1%

Q25

AOD452ALQ25

AOD452ALG

*R3591.8KOhm

+/-1%

*R3591.8KOhm

+/-1%

*R3652.2KOhm

+/-1%

*R3652.2KOhm

0.1uF

16V, Y5V, +80%/-20%

*C155

0.1uF

16V, Y5V, +80%/-20%

D13

LS4148-FD13

LS4148-FCA

Trang 11

5V_DUAL

1D5V_STR

3D3V_SB5V_SB

5V_DUAL5V_SB

1D5V_STR

VTT_DDR3D3V_SYS

1D8V_GPIO14221D8V_GPIO1022

ICH_RIJ_PU 22

SLP_S4J

15,22

PWRG_ATX8,30

NRIB32

Pull FB trace out after Cout

R638,R658 must less than 1k

Iadj=50uA Vref=1.25V

915 series failure issue

Ring

Need to Check Change to Dummy

U17

RT9173U17

RT9173

VIN1

REFEN3

+/-5%

R3622.2

Q39

2N7002DWS11G12D16

D17LS4148-FD17LS4148-F

AOD452ALG

*R34410K

+/-5%

*R34410K

Q48

2N7002DWS11G12D16

Q51AP3310HQ51AP3310H

G

*R38121KOhm

+/-1%

*R38121KOhm

0.1uF

16V, Y5V, +80%/-20%

*C426

R3372.2

+/-5%

R3372.2

+/-5%

*R386210Ohm

+/-1%

*R386210Ohm

+/-1%

*R357100KOhm

+/-1%

R377226Ohm

+/-1%

Q40

AOD452ALQ40

AOD452ALG

D20

BAT54CD20

BAT54C213

+/-1%

*R379301

+/-1%

D18

BAT54CD18

BAT54C213

Q43

AOD472ALQ43

AOD472ALG

+/-1%

*R356100KOhm

APW7120KE-TRL

COMP/OCSET7

FB6

+/-1%

*R380499

+/-1%

R3721.02KOhm

2.2nF

50V, X7R, +/-10%

*C453

Trang 12

HAJ31

HAJ11

HAJ15

HAJ27HAJ21

HAJ22

HAJ10HAJ4

TP_APJ0

HBR0JTESTHI_8TESTHI_10

HREQJ0HREQJ2HREQJ4HDJ[63 0]

HDBIJ0

HDBIJ1 HDBIJ3

HDBIJ2

HCPURSTJHCOMP2

HCOMP3HCOMP0

HCOMP1

HBR0J

TESTHI_8TESTHI_10

HBPM4JHTRSTJ

FSBSEL0HBPM2J

HTDOHTDI

VID5VID2VID0

HCOMP0VID1

TESTHI_2_7

VID6

HCOMP2VCC_PLL

CPU_BOOT

TESTHI_2_7TESTHI_0

MS_ID0HGTLREF_1_2

HIERRJ

HCOMP4DPRSTP#

HCOMP4

TESTHI_1DPSLP#

HDJ56HDJ14

HDJ13

HDJ48

HDJ54

HDJ63HDJ19

HDJ35

HDJ24

HDJ49HDJ44

HDJ0

HDJ34HDJ32

HDJ29

VTT_OUT_LEFTTESTHI_1

PROCHOTJ

VID_SELECT

HAJ34HAJ32

PROCHOTJ

H_TEST

FORCEPHJTESTHI_12

HGTLREF_1_2

HGTLREF_0_3

TP_CPU_G1

HBPM0JHBPM4J

HTDIHTMSHBPM3J

DPSLP#

CPU_SLPJHVCCPLL

HVCCAHVSSA

VRM_ENVTT_PWRGDVTT_PWRGD

VTT_OUT_RIGHTVTT_OUT_LEFT

HADSJ 14HBNRJ 14HITJ 14

INITJ 23

HBPRIJ 14HDBSYJ 14HDRDYJ 14HITMJ 14

HLOCKJ 14HTRDYJ 14HDEFERJ 14

HBR0J 14HADSTBJ0

14

HADSTBJ114

HREQJ[4 0]

14

SMIJ23

STPCLKJ23

A20MJ23INTR23NMI23FERRJ23

IGNNEJ23

VID09VID19VID29VID39VID49VID59

CK_200M_P_CPU7CK_200M_N_CPU7

THERMDA30THERMDC30

THERMTRIPJ 23CPU_PWRG 22HDJ[63 0] 14

HDSTBNJ2 14HDSTBPJ2 14HDBIJ2 14

ICH_SYS_RSTJ7,8,22

FSBSEL07,14FSBSEL17,14FSBSEL27,14

VCC_SENSE9VSS_SENSE9

VID69VID79

ICH_THRM_UP 22,30TP_CPU_G1 13

PECI30

GTL_GPIO1322GTL_GPIO2622

HVCCA13HVSSA13HVCCPLL13

VRM_EN 9

VID_SELECT9

7 mils spacing to low speed signals

14mils spacing to high speed signals

max 1200mils

Place at CPU end of route

Place BPM termination near CPU

MSID0: NC = 2005 Mainstream / Value, 2006 65W FMB

Vss = 2005 Performance FMB

MSID1: Vss = 2005 Performance,2005 Mainstream/Value,2006 65W FMB

THERMDA/THERMDC

1 width=10 mils, spacing=10 mils

2 route the lines in parallel

10 mils width

7 mils spacing to low speed signals14mils spacing to high speed signalsmax 1200mils

placed near pin D23, within 500 mils

4 mils width, 10 mils spacing

Stuff to enable Thermal event

reserve for Kentsfield CPU support

In Design Guide is NC

GTLREF voltage should be 0.63*VTT

12 mils width, 15 mils spacingdivider should be within 1.5" of the GTLREF pin0.22nF caps should be placed near CPU pin

O.635*VTT

O.667*VTT meet the 0.63Vtt value before

BIOS GPIO setting This is a Intel spec.

GPIO26: Default low GPIO13: Default input

*C307

R281 130+/-1%

*R2831K

+/-5%

*R2831K

*R236

51 Ohm

*R236

+/-1%

*R24249.9

+/-1%

*C295

220pF

50V, NPO, +/-5%

*C295

K3FERR#/PBE#

R3LINT0K1LINT1L1IGNNE#

N2STPCLK#

M3VCCAA23VSSAB23RSVD5D23VCCIOPLLC23

VID0AM2VID1AL5VID2AM3VID3AL6VID4AK4VID5AL4FC11AM5

BCLK0F28BCLK1G28SKTOCC#

AE8

THERMDAAL1THERMDCAK1VCCSENSEAN3VSSSENSEAN4VCC_MB_REGAN5VSS_MB_REGAN6

RSVD9F29

*R2884.12K

R238 62

+/-5% *R238 62

C5D02#

A4D03#

C6D04#

A5D05#

B6D06#

B7D07#

A7D08#

A10D09#

A11D10#

B10D11#

C11D12#

D8D13#

B12D14#

C12D15#

D11DBI0#

A8DSTBN0#

C8DSTBP0#

B9D16#

G9D17#

F8D18#

F9D19#

E9D20#

D7D21#

E10D22#

D10D23#

F11D24#

F12D25#

D13D26#

E13D27#

G13D28#

F14D29#

G14D30#

F15D31#

G15DBI1#

G11DSTBN1#

G12DSTBP1#

0.1uF

16V, Y5V, +80%/-20%

Dummy

*C297

0.1uF

16V, Y5V, +80%/-20%

Dummy

*C302

+/-1%

*R25657.6 Ohm

+/-1%

*R29520K

+/-1%

R2611.3KOhm

+/-1%

R2611.3KOhm

+/-1%

R250 62

+/-5% * DummyR250 62

+/-5% Dummy

*C310

1uF

10V, Y5V, +80%/-20%

*C310

#REFDE10COPPER

25V, X7R, +/-10%

Dummy

*C399

10V, Y5V, +80%/-20%Dummy*C398

AG1

BPM0#

AJ2BPM1#

AJ1BPM2#

AD2BPM3#

AG2BPM4#

AF2BPM5#

AG3DBR#

AC2ITPCLKOUT0AK3ITPCLKOUT1AJ3BSEL0G29BSEL1H30BSEL2G30

+/-1%

*R26349.9

Socket-IntelPrescottCPU

A03#

L5A04#

P6A05#

M5A06#

L4A07#

M4A08#

R4A09#

T5A10#

U6A11#

T4A12#

U5A13#

U4A14#

V5A15#

V4A16#

W5RSVD2

N4REQ0#

K4REQ1#

J5REQ2#

M6REQ3#

K6REQ4#

J6ADSTB0#

R6PCREQ#

G5A17#

AB6A18#

W6A19#

Y6A20#

Y4A21#

AA4A22#

AD6A23#

AA5A24#

AB5A25#

AC5A26#

AB4A27#

AF5A28#

AF4A29#

AG6A30#

AG4A31#

AG5A32#

AH4A33#

AH5A34#

AJ5A35#

AJ6RSVD3AC4RSVD4AE4ADSTB1#

Trang 13

HVSSA 12

HVCCPLL 12

LGA775-2

10 mils width

7 mils spacing to low speed signals 14mils spacing to high speed signals max 1200mils

15 mils width

7 mils spacing to low speed signals 14mils spacing to high speed signals max 1200mils

VRDSEL

PLL Supply Filter

Notes:

1 Cap should be within 1.5" mils of the VCCA and VSSA pins

2 VCCA route should be parallel and next to VSSA route to minimize loop area

3 VCCIOPLL route should be parallel and next to VSSA route to minimize loop area

3 Min 12 mils trace from the filter to the processor pins

4 The inductors should be close to the cap.

can be NC for supporting only Core2 Duo, Core2 Extreme, Wolfdale and Yorkfield family processors (have on-die filter)

TP3

* C156 10uF 10V, Y5V, +80%/-20%

R130 1K +/-5%

Dummy

R130 1K +/-5%

Dummy

* R159 24.9 +/-1%

5 OF 7 U11E

VCCP1 AG22 VCCP2 K29 VCCP3 AM26 VCCP4 AL8 VCCP5 AE12 VCCP6 AE11 VCCP7 W23 VCCP8 W24 VCCP9 W25 VCCP10 T25 VCCP11 Y28 VCCP12 AL18 VCCP13 AC25 VCCP14 W30 VCCP15 Y30 VCCP16 AN14 VCCP17 AD28 VCCP18 Y26 VCCP19 AC29 VCCP20 M29 VCCP21 U24 VCCP22 J23 VCCP23 AC27 VCCP24 AM18 VCCP25 AM19 VCCP26 AB8 VCCP27 AC26 VCCP28 J8 VCCP29 J28 VCCP30 T30 VCCP31 AM9 VCCP32 AF15 VCCP33 AC8 VCCP34 AE14 VCCP35 N23 VCCP36 W29 VCCP37 U29 VCCP38 AC24 VCCP39 AC23 VCCP40 Y23 VCCP41 AN26 VCCP42 AN25 VCCP43 AN11 VCCP44 AN18 VCCP45 Y27 VCCP46 Y25 VCCP47 AD24 VCCP48 AE23 VCCP49 AE22 VCCP50 AN19 VCCP51 V8 VCCP52 K8 VCCP53 AE21 VCCP54 AM30 VCCP55 AE19 VCCP56 AC30 VCCP57 AE15 VCCP58 M30 VCCP59 K27 VCCP60 M24 VCCP61 AN21 VCCP62 T8 VCCP63 AC28 VCCP64 N25 VCCP65 AE18 VCCP66 W26 VCCP67 AD25 VCCP68 M8 VCCP69 N30 VCCP70 AD26 VCCP71 AJ26 VCCP72 AM29 VCCP73 M25 VCCP74 M26 VCCP75 L8 VCCP76 U25 VCCP77 Y8 VCCP78 AJ12 VCCP79 AD27 VCCP80 U23 VCCP81 M23 VCCP82 AG29 VCCP83 N27 VCCP84 AM22 VCCP85 U28 VCCP86 K28 VCCP87 U8 VCCP88 AK18 VCCP89 AD8 VCCP90 K24 VCCP91 AH28 VCCP92 AH21

VCCP93 AK12 VCCP94 AH22 VCCP95 T29 VCCP96 AM14 VCCP97 AM25 VCCP98 AE9 VCCP99 Y29 VCCP100 AK25 VCCP101 AK19 VCCP102 AG15 VCCP103 J22 VCCP104 T24 VCCP105 AG21 VCCP106 AM21 VCCP107 J25 VCCP108 U30 VCCP109 AL21 VCCP110 AG25 VCCP111 AJ18 VCCP112 J19 VCCP113 AH30 VCCP114 J15 VCCP115 AG12 VCCP116 AJ22 VCCP117 J20 VCCP118 AH18 VCCP119 AH26 VCCP120 W27 VCCP121 AL25 VCCP122 AN8 VCCP123 AH14 VCCP124 U27 VCCP125 T23 VCCP126 R8 VCCP127 AK22 VCCP128 AN29 VCCP129 AG11 VCCP130 AK26 VCCP131 J10 VCCP132 AJ15 VCCP133 AG26 VCCP134 AN9 VCCP135 AH15 VCCP136 AF18 VCCP137 AL15 VCCP138 J26 VCCP139 J18 VCCP140 J21 VCCP141 AG27 VCCP142 AK15 VCCP143 AF11 VCCP144 AD23 VCCP145 AM15 VCCP146 AF8 VCCP147 AK21 VCCP148 AG30 VCCP149 AJ21 VCCP150 AM11 VCCP151 AL11 VCCP152 AJ11 VCCP153 K30 VCCP154 AL14 VCCP155 AN30 VCCP156 AH25 VCCP157 AL12 VCCP158 AJ9 VCCP159 AK11 VCCP160 AG14 VCCP161 N29 VCCP162 AL30 VCCP163 AJ25 VCCP164 AH9 VCCP165 J29 VCCP166 J11 VCCP167 K25 VCCP168 P8 VCCP169 K23 VCCP170 AL19 VCCP171 AM8 VCCP172 T26 VCCP173 N28 VCCP174 AH12 VCCP175 AL22 VCCP176 AN15 VCCP177 AJ8 VCCP178 U26 VCCP179 AJ19 VCCP180 T27 VCCP181 AK8 VCCP182 AN12 VCCP183 AG9 VCCP184 N26

TP2

* R262

51 Ohm +/-5%

* R262

51 Ohm +/-5%

6 OF 7 U11F

VCCP185 AF9 VCCP186 AF22 VCCP187 AH11 VCCP188 AJ14 VCCP189 AH19 VCCP190 AH29 VCCP191 AH27 VCCP192 AG28 VCCP193 AL26 VCCP194 AM12 VCCP195 J24 VCCP196 J13 VCCP197 T28 VCCP198 W28 VCCP199 J12 VCCP200 J27 VCCP201 AG19 VCCP202 AL9 VCCP203 AD30 VCCP204 AF21 VCCP205 Y24 VCCP206 AK14 VCCP207 J9 VCCP208 M27 VCCP209 AF14 VCCP210 J30 VCCP211 AG18 VCCP212 AA8 VCCP213 AG8 VCCP214 AL29 VCCP215 AD29 VCCP216 W8 VCCP217 AH8 VCCP218 N24 VCCP219 AN22 VCCP220 J14 VCCP221 K26 VCCP222 AF19 VCCP223 N8 VCCP224 AF12 VCCP225 M28 VCCP226 AK9

VSS1 C10 VSS2 D12

VSS4 C24 VSS5 K2 VSS6 C22 VSS7 AN1 VSS8 B14 VSS9 K7 VSS10 AE16 VSS11 B11 VSS12 AL10 VSS13 AK23 VSS14 H12 VSS15 AF7 VSS16 AK7 VSS17 H7 VSS18 E14 VSS19 L28 VSS20 Y5 VSS21 E11 VSS22 AL16 VSS23 AL24 VSS24 AK13 VSS25 AL3 VSS26 D21 VSS27 AL20 VSS28 D18 VSS29 AN2 VSS30 AK16 VSS31 AK20 VSS32 AM27 VSS33 AM1 VSS34 AL13 VSS35 AL17 VSS36 C19 VSS37 E28 VSS38 AH7 VSS39 AK30 VSS40 D24

VSS41 AL23 VSS42 A12 VSS43 L25 VSS44 J7 VSS45 AE28 VSS46 AE29 VSS47 K5 VSS48 J4 VSS49 AE30 VSS50 AN20 VSS51 AF10 VSS52 AE24 VSS53 AM24 VSS54 AN23 VSS55 H9 VSS56 H8 VSS57 H13 VSS58 AC6 VSS59 AC7 VSS60 AH6 VSS61 C16 VSS62 AM16 VSS63 AE25 VSS64 AE27 VSS65 AJ28 VSS66 AJ7 VSS67 F19 VSS68 AH13 VSS69 AD7 VSS70 AH16 VSS71 AK17 VSS72 E17 VSS73 AH17 VSS74 AH20 VSS75 AE5 VSS76 AH23 VSS77 AE7 VSS78 AM13 VSS79 AH24 VSS80 AJ30 VSS81 AJ10 VSS82 AF3 VSS83 AK5 VSS84 AJ16 VSS85 AF6 VSS86 AK29 VSS87 AJ17 VSS88 F22 VSS89 AH3 VSS90 AK10 VSS91 AM10 VSS92 F16 VSS93 AJ23 VSS94 F13 VSS95 AG7 VSS96 F10 VSS97 L26 VSS98 AD4 VSS99 H11 VSS100 L24 VSS101 L23 VSS102 AM23 VSS103 A15 VSS104 AH10 VSS105 H29 VSS106 B24 VSS107 L3 VSS108 H27 VSS109 A21 VSS110 AE2 VSS111 AJ29 VSS112 A24 VSS113 AK27 VSS114 AK28 VSS115 B20 VSS116 AM20 VSS117 H26 VSS118 B17 VSS119 H25 VSS120 H24 VSS121 AA3 VSS122 AA7 VSS123 H23 VSS124 AA6 VSS125 H10

7 OF 7 U11G

VSS126 H22 VSS127 H21 VSS128 H20 VSS129 H19 VSS130 H18 VSS131 AB7 VSS132 H17 VSS133 AJ24 VSS134 AM17 VSS135 AC3 VSS136 H14 VSS137 P28 VSS138 V6 VSS139 AK2 VSS140 P27 VSS141 P26 VSS142 AM28 VSS143 AJ13 VSS144 W4 VSS145 P25 VSS146 AJ20 VSS147 W7 VSS148 P23

VSS152 C7 VSS153 Y2 VSS154 L30 VSS155 L29 VSS156 D15 VSS157 AL27 VSS158 Y7 VSS159 L27 VSS160 AA29 VSS161 N6 VSS162 N7 VSS163 AA28 VSS164 AN13 VSS165 AA27 VSS166 AA26 VSS167 P4 VSS168 AA25 VSS169 AA24 VSS170 P7 VSS171 E26 VSS172 V30 VSS173 R2 VSS174 V29 VSS175 V28 VSS176 R5 VSS177 V27 VSS178 R7 VSS179 E20 VSS180 AN10 VSS181 V25 VSS182 T3 VSS183 V24 VSS184 V23 VSS185 T6 VSS186 AL7 VSS187 E25 VSS188 U1 VSS189 R29 VSS190 R28 VSS191 R27 VSS192 R26 VSS193 R25 VSS194 U7 VSS195 R24 VSS196 R23 VSS197 P30 VSS198 V3 VSS199 P29 VSS200 AF16 VSS201 AE10 VSS202 AF13 VSS203 H6 VSS204 A18 VSS205 A2 VSS206 E2 VSS207 D9 VSS208 C4 VSS209 A6 VSS210 D6

VSS211 D5 VSS212 A9 VSS213 D3 VSS214 B1 VSS215 B5 VSS216 B8 VSS217 AJ4 VSS218 AE26 VSS219 AH1 VSS220 E29 VSS221 V7 VSS222 C13 VSS223 AK24 VSS224 AB30 VSS225 L6 VSS226 L7 VSS227 AB29 VSS228 M1 VSS229 AB28

VSS232 AN17 VSS233 AB27 VSS234 AB26 VSS235 AN16 VSS236 M7 VSS237 AB25 VSS238 AB24 VSS239 AB23 VSS240 N3 VSS241 AA30 VSS242 F4 VSS243 AG10 VSS244 AE13 VSS245 AF30 VSS246 H28 VSS247 F7 VSS248 AF29 VSS249 AF28 VSS250 G1 VSS251 AF27 VSS252 AF26 VSS253 AF25 VSS254 AN28 VSS255 AN27 VSS256 AF24 VSS257 AF23 VSS258 AG24 VSS259 AF17 VSS260 AN24 VSS261 H3 VSS263 P24 VSS264 AE20 VSS265 AE17 VSS266 E27 VSS267 T7 VSS268 R30 VSS269 AJ27 VSS270 AB1 VSS271 AM4 VSS272 V26 VSS273 AA23 VSS274 AL28 VSS275 AF20 VSS276 AG23

RSVD26 F6 RSVD28 Y3 RSVD29 AE3

RSVD31 E7 RSVD32 B13 RSVD33 D14 RSVD34 E6 RSVD35 D1 RSVD36 E5

VSS149 AG13 VSS150 AG16 VSS151 AG17

VSS230 E8 VSS231 AG20

L17 L0805 10uH L17 L0805 10uH

Trang 14

GMCH_EXP_RBIASDMI_RXP0

TP_XORTEST

HSWINGTP_MCH_N25

DMI_RXN0DMI_RXP1DMI_RXN1DMI_RXP2DMI_RXN2EXP_RXP0

DMI_RXP3DMI_RXN3

EXP_RXN0EXP_RXP1EXP_RXN1EXP_RXP2EXP_RXN2EXP_RXP3EXP_RXN3EXP_RXP4

TP_MCH_AB13EXP_RXN4

TP_MCH_AD13

TP_MCH_J15

TP_MCH_J20

EXP_RXP5EXP_RXN5EXP_RXP6EXP_RXN6

TP_MCH_J15TP_MCH_G20

MCH_GTLREF

HSWINGHRCOMP

EXP_SM

DMI_TXN3

TP_MCH_M17

EXP_TXP0EXP_TXP1EXP_TXP2

HAJ24

DAC_REFSETEXP_TXN2

HAJ3HAJ5HAJ7

EXP_TXP4

ICH_SYNCJ

HAJ10HAJ9

PWRGD_3V

HAJ13HAJ11

HAJ14

HAJ18HAJ16

TP_MCH_L13

DMI_TXP0DMI_TXP1DMI_TXP2DMI_TXP3

EXP_TXN8EXP_TXN9EXP_TXP10EXP_TXP11HDJ0

EXP_TXN11

HDJ2HDJ4HDJ6HDJ8HDJ10HDJ9HDJ11HDJ13

HDJ16

HDJ20HDJ18

HDJ22

EXP_TXP12

HDJ23HDJ25

HDJ28HDJ26

HDJ30HDJ32HDJ34

HDJ37HDJ39

HDJ42HDJ40

HDJ43

HDJ46

HDJ50HDJ48

HDJ52

EXP_TXP13

HDJ54

HDJ58HDJ56

HDJ60

HDJ63HDJ61

HDJ[63 0]

EXP_TXN13

TP_MCH_F20TP_MCH_J20

EXP_TXP14EXP_TXP15

HSYNC_P

CL_RST

PLTRSTJ CL_RST

DDPC_CTRLCLKDDPC_CTRLDATA

TP_MCH_L13

H_FSBSEL2H_FSBSEL0

DPL_REFSSCLKIN_N

HDA_SDIHDA_SDOHDA_BCLK

HDA_SYNCHDA_RSTB

H_FSBSEL2H_FSBSEL2_NB

H_FSBSEL0H_FSBSEL0_NB

DMI_RXP222DMI_RXN022

DMI_RXN222DMI_RXP122

DMI_RXN322

EXP_RXN520EXP_RXP620

EXP_RXP920

EXP_RXP520

EXP_RXN1120

EXP_RXN220

EXP_RXN620

EXP_RXN420

EXP_RXP1420

EXP_RXP720

EXP_RXN120

EXP_RXP820

EXP_RXN320

EXP_RXP120

EXP_RXN720

EXP_RXP020

EXP_RXP1020

EXP_RXP1520

EXP_RXN1020

EXP_RXN1420EXP_RXP1320

EXP_RXN920EXP_RXN820

EXP_RXP1220EXP_RXN1220EXP_RXP1120

EXP_RXN1320

EXP_RXP320

EXP_RXN020

EXP_RXN1520

EXP_RXP420

EXP_RXP220

EXP_TXN9 20EXP_TXP9 20

EXP_TXN11 20

EXP_TXP6 20EXP_TXP4 20

EXP_TXN5 20

EXP_TXP12 20

EXP_TXN0 20

EXP_TXP10 20EXP_TXN10 20

EXP_TXP5 20

EXP_TXP7 20

EXP_TXP3 20EXP_TXN2 20EXP_TXN3 20EXP_TXP2 20

EXP_TXN6 20EXP_TXN4 20EXP_TXN1 20

EXP_TXN8 20EXP_TXN7 20

EXP_TXP14 20EXP_TXN13 20

EXP_TXP15 20EXP_TXN14 20EXP_TXP13 20

EXP_TXN15 20EXP_TXN12 20

CK_96M_N_GMCH7CK_96M_P_GMCH 7

GMCH_EXP_EN_HDR20

CK_200M_P_GMCH7CK_200M_N_GMCH7

SDVO_CTRLCLK20SDVO_CTRLDATA20

PLTRSTJ 20,22,27,30ICH_SYNCJ 22PWRGD_3V 22,30

GREEN 21BLUE 21RED 21

CK_PE_100M_N_GMCH7

CK_PE_100M_P_GMCH7

FSBSEL07,12FSBSEL17,12FSBSEL27,12

HSYNC 21

PLTRSTJ20,22,27,30

DPL_REFSSCLKIN_P 7DPL_REFSSCLKIN_N 7

DMI_TXP1 22DMI_TXP2 22

DMI_TXN3 22DMI_TXN2 22

DMI_TXP0 22

DMI_TXN1 22

DMI_TXP3 22DMI_TXN0 22

For platforms that do not support IntelAMT,no action is needed

update: Ref spec update 1.01011808

Placed close toGMCH within

250 mils

0.35V

min 4 mils width

10 mils spacing

5 mils min for max of 300 mils in breakout

Concurrent SDVO and PCI Express:

0 = Only SDVO or PCI Express is operational

1 = Both SDVO and PCI Express are operating

Enable TLS

placed close to GMCH within 500 mils

4 mils width

6 mils spacing to static signals

12 mils spacing to toppling signals

Check DG1.2useR2=464ohm?????

PCI Express* Static Lane Reversal:

0 = GMCH PCI Express lane numbers are reversed (BTX)

1 = Normal operation (ATX)

HSWING voltage should be 0.25*FSB_VTT

10 mils width, 10 mils spacingmax 3 inches long

10 mils width, 7 mils spacing

max 500 mils

5 on 5 mils in breakout, max 250 mils

GTLREF voltage should be 0.67*VTT = 0.75V

12 mils width, 15 mils spacingdivider should be within 1.5" of the GTLREF pin220pF caps should be placed near MCH pinplace series resistor as close to divider

+/-1%

R40349.9

+/-1%

R18849.9

*R1402.2Kdummy

*R222464

+/-1%

*R222464

+/-1%

*R1491K

+/-5%

*R1491K

+/ -1%

*R168150

Jumper_2P_Blu

*R1412.2Kdummy

0.1uF

16V, Y5V, +80%/-20%

*C287

0.1uF

16V, Y5V, +80%/-20%

*R13810K

+/-5%

Dummy*R13810K

+/-5%

Dummy

TP33

*R14357.6 Ohm

+/-1%

*R14357.6 Ohm

+/-1%

TP32

MEM_OC_1333:2-3

Jumper_2P_BluMEM_OC_1333:2-3

Jumper_2P_Blu

CPU_533

Header_1X3CPU_533

Header_1X3112233

Header_1X313

FSB_REQB_0G38FSB_REQB_1K35FSB_REQB_2J39FSB_REQB_3C43FSB_REQB_4G39FSB_ADSTBB_0J40FSB_ADSTBB_1T39FSB_DSTBPB_0C39FSB_DSTBNB_0B39FSB_DINVB_0B40FSB_DSTBPB_1K31FSB_DSTBNB_1J31FSB_DINVB_1F33FSB_DSTBPB_2J25FSB_DSTBNB_2K25FSB_DINVB_2F26FSB_DSTBPB_3C32FSB_DSTBNB_3D32FSB_DINVB_3D30FSB_ADSBJ42FSB_TRDYBL40FSB_DRDYBJ43FSB_DEFERBG44FSB_HITMBK44FSB_HITBH45FSB_LOCKBH40FSB_BREQ0BL42FSB_BNRBJ44FSB_BPRIBH37FSB_DBSYBH42FSB_RSB_0G43FSB_RSB_1L44FSB_RSB_2G42FSB_CPURSTBD27RSVD_3N25

*R21710K

TP30

*R2211K

+/-1%

*R2211K

+/ -1%

*R170150

RSVD_8M17CENJ17BSCANTESTG20RSVD_10J16RSVD_11M16RSVD_12J15RSVD_13J20DUALX8_ENABLEF20

CL_DATAAY4CL_CLKAY2CL_VREFAN13CL_RSTBAW2CL_PWROKAN8

JTAG_TDIAR7JTAG_TDOAN10JTAG_TCKAN11JTAG_TMSAN9

RSVD_14R31RSVD_15R32RSVD_16U30RSVD_17U31RSVD_18R15RSVD_19R14RSVD_20T15RSVD_21T14RSVD_22AB15RSVD_23A45RSVD_24B2RSVD_25BE1RSVD_26BE45RSVD_27L13RSVD_28L11

+/ -1%

*R165150

EXP_CLKPD9EXP_CLKNE9SDVO_CTRLDATAJ13

SDVO_CTRLCLKG13RSVD_1AB13RSVD_2AD13

Trang 15

M_DQM_A0

M_DATA_A1M_DATA_A3

M_DATA_A6M_DATA_A0

M_DQS_AJ3

M_MAA_A4

M_MAA_A7M_MAA_A3

M_MAA_A6M_MAA_A1

M_MAA_A8

M_MAA_A13M_MAA_A10M_MAA_A5

M_MAA_A12

MCH_DDR_RPD

MCH_DDR_SPU

M_DATA_A13M_DATA_A10

M_DATA_A14M_DATA_A11M_DATA_A9M_DQM_A1M_DQS_A1

M_DQS_AJ4M_BS_A0

MCH_DDR_SPUM_DATA_A36

M_DATA_A60

M_DATA_A61

M_DATA_A33

M_DATA_A57

M_DQM_A2

M_DQM_A5M_DQM_A4

M_DQM_A7M_DQM_A6M_DATA_A39

M_DATA_A20

M_DATA_A40

M_DATA_A49

M_DATA_A17

M_DATA_A22

M_DATA_A47

M_DATA_A51

M_SCKE_A0

M_DQS_A2M_BS_A1

M_MAA_A11

M_BS_A2

M_ODT_A1

MCH_DDR_RPUM_DQS_AJ5

MCH_DDR_SPD

M_DQS_A3M_DQM_A3

M_DQS_AJ7

M_DATA_A25

M_DATA_A28M_DATA_A30M_DATA_A26M_DATA_A24

M_DQS_AJ0

DDR3_DRAM_PWROK

M_SCKE_B0M_MAA_B13

M_ODT_B0

M_MAA_B0

M_MAA_B4M_MAA_B2

M_MAA_B7

M_MAA_B11M_MAA_B9

M_BS_B0M_MAA_B14

M_BS_B1

M_DATA_B17M_DATA_B19M_DATA_B16

M_DQM_B7

M_DQS_B3M_DQM_B3

M_DQS_B4M_DQM_B4

M_DQS_B5

M_DQS_B6

M_DATA_B9M_DATA_B11

M_DATA_B31

M_DATA_B38

M_DATA_B30

M_DATA_B32M_DATA_B29

M_DATA_B43M_DATA_B40M_DATA_B42M_DQM_B5

M_DATA_B49M_DATA_B0

M_DATA_B50

M_DATA_B54M_DATA_B51M_DATA_B53M_DATA_B55M_DATA_B52

M_DQM_B6M_DATA_B48

M_DATA_B57

M_DATA_B60

M_DATA_B2

M_DATA_B8

M_DATA_B4M_DATA_B6

M_DQS_B7

M_DQS_B0M_DQM_B0M_DQS_BJ0

M_DQS_BJ1

M_DQS_BJ2

M_DQS_BJ3

M_DQS_BJ4M_DQS_B1

M_DQS_BJ5M_DQM_B1

M_DQS_BJ6

M_DQS_BJ7M_DQS_B2

1D5V_STR

5V_SB

M_CAS_AJ19M_RAS_AJ19

CK_M_200M_P_DDR0_A19

CK_M_200M_N_DDR0_A19

CK_M_200M_P_DDR2_A19

M_DATA_A[63 0] 19

M_DQM_A[7 0] 19M_DQS_A[7 0] 19

M_DQM_A[7 0] 19M_DATA_A[63 0] 19

M_DQS_A[7 0] 19M_DATA_A[63 0] 19

M_DATA_A[63 0] 19

M_DQS_AJ[7 0] 19M_DQS_A[7 0] 19M_DQM_A[7 0] 19

M_DQS_AJ[7 0] 19M_DQM_A[7 0] 19

M_DQM_A[7 0] 19

M_DQS_A[7 0] 19

M_DATA_A[63 0] 19

M_DQM_A[7 0] 19M_DQS_AJ[7 0] 19M_DQS_AJ[7 0] 19M_DQS_AJ[7 0] 19

M_DQS_A[7 0] 19

M_DQS_A[7 0] 19M_DQM_A[7 0] 19M_DATA_A[63 0] 19M_DQS_AJ[7 0] 19

M_DQS_AJ[7 0] 19M_DQM_A[7 0] 19M_DQS_A[7 0] 19

M_DATA_A[63 0] 19

M_DQS_A[7 0] 19M_DQS_AJ[7 0] 19

M_SCS_B1J18

M_CAS_BJ18M_RAS_BJ18

M_ODT_B[1 0]

18

M_SCS_B0J18

M_WE_BJ18

CK_M_200M_N_DDR0_B18

M_SCKE_B[1 0]

18

CK_M_200M_N_DDR2_B18

CK_M_200M_P_DDR0_B18

M_MAA_B[14 0]

18

CK_M_200M_P_DDR2_B18

M_DQS_BJ[7 0] 18M_DQM_B[7 0] 18

M_DQS_BJ[7 0] 18

M_DQS_B[7 0] 18

M_DQS_BJ[7 0] 18

M_DQS_B[7 0] 18M_DQS_BJ[7 0] 18M_DQM_B[7 0] 18

M_DQS_B[7 0] 18

M_DATA_B[63 0]18

M_DQS_BJ[7 0] 18

M_DQM_B[7 0] 18M_DQM_B[7 0] 18M_DATA_B[63 0]18

M_DATA_B[63 0]18M_DQM_B[7 0] 18

M_DQS_BJ[7 0] 18

M_DQM_B[7 0] 18M_DATA_B[63 0]18

M_SCS_A1J_DDR319M_MAA_A0_DDR319M_WE_AJ_DDR319

DDR3_DRAMRST_N18,19

M_SCS_A0J19

For a single DIMM per channel implementation,

the following second DIMM specific system memory

signals should be tested pointed

CK/CKB[5:3] - DDR2 Clock Pairs

CK/CKB[3 and 5] - Channel A DDR3 Clock Pairs

CSB[3:2]

ODT[3:2]

DDRII Compensation Group Signals

width 10 mils, spacing 10 mils

5 mils width/spacing minimum for max of 300 mils

in GMCH break-out area Placed close to GMCH pin

DDR_A

3 OF 10

U33C

Eaglelake-QDDR_A

4 OF 10

U33D

Eaglelake-Q

DDR_B_MA_0BD24DDR_B_MA_1BB23DDR_B_MA_2BB24DDR_B_MA_3BD23DDR_B_MA_4BB22DDR_B_MA_5BD22DDR_B_MA_6BC22DDR_B_MA_7BC20DDR_B_MA_8BB20DDR_B_MA_9BD20DDR_B_MA_10BC26DDR_B_MA_11BD19DDR_B_MA_12BB19DDR_B_MA_13BE38DDR_B_MA_14BA19DDR_B_WEBBD36DDR_B_CASBBC37DDR_B_RASBBD35DDR_B_BS_0BD26DDR_B_BS_1BB26DDR_B_BS_2BD18DDR_B_CSB_0BB35DDR_B_CSB_1BD39DDR_B_CSB_2BB37DDR_B_CSB_3BD40DDR_B_CKE_0BC18DDR_B_CKE_1AY20DDR_B_CKE_2BE17DDR_B_CKE_3BB18DDR_B_ODT_0BD37DDR_B_ODT_1BC39DDR_B_ODT_2BB38DDR_B_ODT_3BD42DDR_B_CK_0AY33DDR_B_CKB_0AW33DDR_B_CK_1AV31DDR_B_CKB_1AW31DDR_B_CK_2AW35DDR_B_CKB_2AY35DDR_B_CK_3AT31DDR_B_CKB_3AU31DDR_B_CK_4AP31DDR_B_CKB_4AP30DDR_B_CK_5AW37DDR_B_CKB_5AV35

DDR3_A_CSB1AR43DDR3_A_MA0BB40DDR3_A_WEBAT44DDR3_A_ODT3AV40DDR3_A_DRAM_PWROKAR6

DDR3_DRAMRSTBBC24

RSVD_4AN29RSVD_5AN30RSVD_6AJ33RSVD_7AK33

DDR_VREFBB44

DDR_RPDAY42DDR_RPUBA43DDR_SPDBC43DDR_SPUBC44

+/-1%

*R2311K

+/-1%

*R2281K

Q52

2N7002DWS11G12D16

Trang 16

VCCDQ_CRT

VCCA_HPLL

VCCA_EXPVCCA_MPLLVCCA_EXP

VCCA_GPLLVCCA_HPLL

VCCDQ_CRT

VCCAVRAM_EXP

VCCA_DAC

VCCCML_DDRVCCD_HPLL

1D1V_PCIEXPRESS

1D1V_MCH3D3V_SYS

refer to EL update summary052208

BACK

(mA)(mVpp)MinVoutVCCAPLL_EXP 50 20 1.045V/VCCDPLL_EXP

Place these parts close to VCC_CKDDR ballout in MCH backside

BACK

(mA)MinVoutVCCA_DAC 70 2.97V

BACK

(mA)MinVoutVCCA_EXP 4 1.425V

(mA)(mVpp)MinVoutVCCA_MPLL >102 70 1.045V

BACK

INT VRM DISABLE: VCCAVRM_EXP ->1.1VINT VRM ENABLE: VCCAVRM_EXP ->1.5Vfor better PCIe Gen2 performance???

BACK

(mA)(mVpp)MinVoutVCCA_DPLLA/B>102 50 1.045V

BACK

VCCDQ_CRT is very sensitive tolow frequency noise (noise below 1MHz)

1250mA

BACK

Place these caps close to 1D1V_MCH plane in MCH backside

(mA)(mVpp)MinVoutVCCAPLL_EXP 50 20 1.045V/VCCDPLL_EXP

Place in 1D1V_MCH_CL plane(less than 100 mils from the package)

Place in FSB_VTT plane as close to the GMCH as possible(less than 100 mils from the package)

Connect ground sides of caps with traces to GND balls(less than 100 mils from the package)

BACK

(mA)MinVoutVCC_SMCLK 450 1.7V (mA)MinVout

Near E19 Pin

0.1uF

16V, Y5V, +80%/-20%

*C438

R163 1R163 1

VCCA_HPLLB22VCCA_MPLLA21VCCA_DPLLAD20VCCA_DPLLBC20

VCC_HDAAR2VCC3_3E19

VCCA_DAC_1B19VCCA_DAC_2D19VCC_EXPA17

VCCDQ_CRTB20VSSB17

L41L0805 1uH+/-10%

R157 1R157 1

Trang 18

M_MAA_B5

M_MAA_B9

M_MAA_B12M_MAA_B4M_BS_B1

M_MAA_B11M_MAA_B1

SMVREF_B_DDR3

M_ODT_B0

M_DQS_B1

M_DQS_BJ6M_DQS_BJ5

M_DQS_B7M_DQS_BJ4M_DQS_B0

M_DQS_BJ7M_DQS_B5

M_DQS_B2M_DQS_BJ0

M_DQS_B6

M_DQS_BJ1

M_DQS_B3M_DQS_BJ2

M_DQS_BJ3M_DQS_B4

M_DQM_B6

M_DQM_B3

M_DQM_B4

M_DQM_B7M_DQM_B5

M_DQM_B0

M_DQM_B2M_DQM_B1

M_DATA_B61

M_DATA_B46M_DATA_B41M_DATA_B26M_DATA_B8

M_DATA_B17

M_DATA_B32

M_DATA_B19

M_DATA_B29

M_DATA_B55

M_DATA_B35

M_DATA_B47

M_DATA_B52

M_DATA_B10M_DATA_B4

M_BS_B[2 0]

15

M_CAS_BJ15

CK_M_200M_P_DDR0_B

15

M_SCS_B1J15

CK_M_200M_P_DDR2_B

15

M_SCS_B0J15

M_SCKE_B[1 0]

15

M_WE_BJ15

M_BS_B[2 0]

15

M_ODT_B[1 0] 15

M_DQS_B[7 0] 15M_DQS_BJ[7 0] 15

4.7uF

6.3V, X5R, +/-10%

*C394

0.1uF

16V, Y5V, +80%/-20%

*C431

0.1uF

16V, Y5V, +80%/-20%

*C443

VREFDQ1SCL118SDA238SA1237SA0117

BA0

71 BA1190

CKE0

50 CKE1169

185CK0184A0188A1181A261A3180A459A558A6178A756A9175A10/AP70A1155A12174A13196A14172A15171

A8177

CAS*

74RAS*

192WE*

VREFCA67

VTT

120 VTT240

FREE1198FREE2187FREE349FREE448

Định dạng
Số trang	36
Dung lượng	0,91 MB