Thiết kế mạch logic bằng Verilog - HDL potx

7KLୱW Nୱ P୓FK logic EୣQJ HDLVerilog-ĈһQJ Bá .KҳF 7ULӅX *LҧQJ viên Khoa CNTT 7UѭӡQJ ĈҥL KӑF Bách khoa Ĉj 1ҹQJ 1... Yêu FҫX FӫD khóa KӑF Giáo viên FKӍ KѭӟQJ GүQ QKӳQJ gì Fѫ EҧQ QKҩW, sinh

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7KLୱW Nୱ P୓FK logic EୣQJ HDL

Verilog-ĈһQJ Bá KҳF 7ULӅX

*LҧQJ viên Khoa CNTT 7UѭӡQJ ĈҥL KӑF Bách khoa Ĉj 1ҹQJ

1

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Yêu FҫX FӫD khóa KӑF

Giáo viên FKӍ KѭӟQJ GүQ QKӳQJ gì Fѫ EҧQ

QKҩW, sinh viên SKҧL Wӵ tìm KLӇX thêm

Trang web FӫD khóa KӑF:

http://dangtrieu.wiki.zoho.com/LapTrinhVeri log2009.html

http://dangtrieu.wiki.zoho.com/LapTrinhVerilog

2009-Feedback.html

ĈӏD FKӍ email: dangtrieu@gmail.com

Không có câu KӓL QJӟ QJҭQ, hãy PҥQK GҥQ

trao ÿәL ý NLӃQ YӟL giáo viên và EҥQ bè

Sinh viên ÿ{QJ nên WUѭӟF KӃW hãy trao ÿәL YӟL

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2009 ĈɴQJBá KɬF 7ULɾX, GV khoa CNTT, WUɉ͝QJ Ĉ+%.Ĉ1

Phân 4 sv PӝW nhóm, theo WKӭ Wӵ Wӯ trên

[XӕQJ FӫD danh sánh OӟS

%ҧQ báo cáo YLӃW EҵQJ Word, JӱL theo

email và in ra PӝW EҧQ QӝS WUӵF WLӃS

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*LӟL WKLӋX Verilog-HDL và cách

ĈһQJ Bá KҳF 7ULӅX

*LҧQJ viên Khoa CNTT 7UѭӡQJ ĈҥL KӑF Bách khoa Ĉj 1ҹQJ

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/୽FK Vட SK£W WUL୵Q

Ò୙X WL¬Q, WKLୱW Nୱ P୓FK KTS G»QJ vacuum tubes Y¢

transistors

7LୱS theo O¢ Ó୩W WU¬Q P஋W single chip, J୿L O¢ IC (integrated

circuit) Y஍L qui P¶ SSI (Small Scale Integration)

Sau Óµ ÓୱQ qui P¶ MSI (Medium Scale Integration), Y஍L

Y¢L WUÅP FஇQJ logic

7LୱS theo O¢ LSI (Large Scale Integration), Y஍L Y¢L QJK®Q

FஇQJ logic

0஛F Ó஋ SK஛F W୓S WÅQJ O¬Q -> Electronic Design Automation

(EDA).

0୓FK Yଢ଼Q ÓŲகF test WU¬Q breadboard, Y¢ layout ÓŲகF O¢P

EୣQJ tay WU¬Q JLୗ\ KR୩F P£\ W¯QK

9஍L VLSI (Very Large Scale Integration), qui P¶ WU¬Q

100,000 transistors

K¶QJ WK୵ NL୵P tra WU¬Q breadboard

&୙Q SK୕L WKLୱW Nୱ Y¢ WKணF KL୹Q NL୵P tra logic WU¬Q P£\ W¯QK UஅL

P஍L in O¬Q chip.

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3KҫQ PӅP và tài OLӋX

Ta FҫQ cài ÿһW:

ISE WebPACK 10.1: SK୙Q P୳P W୓R project

ModelSim Xilinx Edition-III 6.3c: SKҫQ PӅP

E- ERRN³Verilog HDL A Guide to Digital Design

DQG6\QWKHVLV6HFRQG(GLWLRQ´

7

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http://www.xilinx.com/support/download/ind

ex.htm

ISE WebPACK

A FREE, easy-to-use software solution for your

Xilinx C CPLD or medium-density F FPGA design

Current:10.1 - March 2008 Requirements: OS |

Memory Product Info: Free ISE WebPACK

Download: Download ISE WebPACK

&£F video tham NK୕R:

http://www.xilinx.com/products/design_resources/

&£FK download, F¢L Ó୩W ISE WebPACK 10.1

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9

Sign in KRһF ÿăQJ ký PӝW account PӟL QӃX FKѭD có

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Operating System Support

Microsoft Windows® XP Professional

(32-bit and 64-(32-bit)

Microsoft Windows® Vista Business (32-bit

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Microsoft Windows XP Professional

Cài trên Vista FǊQJ ÿѭӧF

Download, F¢L Ó୩W ModelSim Xilinx Edition-III

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2009 ĈɴQJBá KɬF 7ULɾX, GV khoa CNTT, WUɉ͝QJ Ĉ+%.Ĉ1 13

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Sau khi finish FҫQ ÿăQJ ký licence Licence

VӁ ÿѭӧF JӱL vào email ÿăQJ ký.

To license the ModelSim XE product,

please follow these steps:

1) Save the attached file to your hard drive, noting its

location.

2) Run the "Licensing Wizard" program from within the

ModelSim XE program group.

3) Using the Licensing Wizard, specify the location of

the saved license file.

4) Optionally, allow the Licensing Wizard to Modify

your FlexLM environment variable and reboot your

machine to complete the license installation process.

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7ҥR Project

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7ҥR Project

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7ҥR Project

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7ҥR Project

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7ҥR Project

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9LӃW FKѭѫQJ trình

&KӑQ Verilog Module; ÿһW tên file

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ĈһW ÿҫX ra vào (không FҫQ WKLӃW)

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Summary YӅ file YӯD WҥR

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7ҥR file simulation

&KӑQ Test Bench Waveform và ÿһW tên file

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7ҥR file simulation

&KӑQ file WѭѫQJ ӭQJ PXӕQ simulation

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Summary

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7KLӃW OұS các tham Vӕ simulation

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7KLӃW OұS ÿҫX vào (a, b)

*Lҧ Vӱ ta WKLӃW OұS QKѭ hình GѭӟL

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.KӣL ÿӝQJ SKҫQ PӅP ModelSim

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Xem NӃW TXҧ simulation

&KӍ khi a, b cùng EҵQJ 1 thì c PӟL EҵQJ 1

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Phép toán trên bit

Bitwise Operators

~ ~m Invert each bit of m

& m & n AND each bit of m with each bit of n

| m | n OR each bit of m with each bit of n

^ m ^ n Exclusive OR each bit of m with n

~^ m ~^ n

Exclusive NOR each bit of m with n

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1-bit full adder

sum = (a XOR b XOR c_in)

c_out = (a AND b) OR (c_in AND (a XOR b))

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output sum, c_out;

assign sum = (a ^ b) ^ c_in;

assign c_out = (a & b) + (c_in & (a ^ b));

endmodule

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0ҥFK logic ÿѭӧF WҥR ra

Ĉk\ là WәQJ WKӇ FӫD module

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0ҥFK logic ÿѭӧF WҥR ra

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7ҥR input

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.ӃW TXҧ simulation

&KѭѫQJ trình cho NӃW TXҧ ÿ~QJ

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4-bit full adder

Làm WKӃ nào?

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Có cách nào ÿѫQ JLҧQ KѫQ không?

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9LӃW OҥL 1-bit full adder ÿѫQ JLҧQ

{m, n} : Concatenate m to n, creating larger

`timescale 1ns / 1ps

module OBFASimple(c_in, a, b, sum, c_out);

input c_in, a, b;

output sum, c_out;

assign {c_out, sum} = a + b + c_in;

endmodule

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&KѭѫQJ trình 4-bit full adder

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Xem GѭӟL GҥQJ Vӕ WKұS OөF phân

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Xem GѭӟL GҥQJ WKұS phân, không GҩX

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