Models in Hardware Testing- P1 pptx

[...]... hours spent together discussing, eating, tasting wine, talking of culture, sharing everyday problems of our private lives, telling us your experiences in fishing and hunting, have been invaluable It will be very hard for all of us attending next scientific and technical events without your friendliness We will look for you until we realize that, instead of attending yet another boring panel session, you will... shown in Fig 1.3, where the interconnect line is driving an inverter The floating line voltage VFL / is determined by (a) the surrounding circuitry, (b) the transistor capacitances of the driven gates, and (c) the initial trapped charge (Konuk 1997; Champac and Zenteno 2000; Arum´ et al 2005), as reviewed ı next a Neighboring interconnect lines routed close to the floating line add parasitic coupling capacitances... neighboring lines with different coupling lengths Experimental results showed that when both neighbors had the same logic value, they determined the logic interpretation of the floating line, even for floating lines of a few tens of m in length Therefore, in the presence of an interconnect full open defect, its detectability when carrying out a logic test can be improved in the following manner: Testing... leakage currents flowing between the floating node and the output node of the inverter With the knowledge of the gate leakage currents in uencing the downstream gate, the steady state voltage of the floating line can be predicted Assuming a floating line driving an inverter for a 90 nm technology, Fig 1.6a illustrates the total gate current IFN / at the input floating node related to the input and output voltages... currents on the floating line VFN / and the response of the inverter VOUT / for two initial voltages at the input node (VFN0 equals 0 and 1 Open Defects in Nanometer Technologies 7 Fig 1.4 Transient response of the inverter with its input floating for the 90 nm PTM technology (Arum´ et al 2008b) (a) Inverter input and (b) inverter output VFN0 is the initial input voltage ı I1 N1 N3 CN1 IN CN3 Cgb(p) Nm... neighboring capacitances When the floating line length LFL / is short, transistor capacitances generally dominate and set the floating line to an intermediate value Nevertheless, for long LFL , neighboring capacitances dominate and the floating line may achieve a wider range of values The exact location of the open is also important since only parasitic capacitances located after the open in uence the floating... coupled with neighboring lines As traditionally considered, tunneling currents are assumed negligible Next, thin open defects are described, and finally interconnect full open defects with gate leakage are modeled Full Open Defect Modeling in the Interconnect Paths An interconnect line with a full open is disconnected from its driver and becomes electrically floating This line may, in turn, drive one (or... replacement of aluminum with copper in metal interconnections (Stamper et al 1998) Figure 1.1 illustrates the photographs of two real opens in a copper interconnect technology During the last decades, an intensive research effort has been dedicated to CMOS Integrated Circuits (ICs) in the presence of open defects Scaling trends of CMOS in the nanometer range require new models and analysis methods In this context,... interconnect line (Xue et al 1994) For this reason, special attention is paid to interconnect opens A review of interconnect open defects is provided next, following the classification according to defect resistance, i.e full and resistive opens 4 J Figueras et al 1.2.1.1 Full Open Defects in Interconnect Lines In this subsection, we first review the classical model for full opens in interconnect lines... the floating line The last factor is the test pattern applied because it sets a certain state on the neighboring lines Champac and Zenteno (2000) presented simulation results showing the in uence of these factors Furthermore, experimental evidence was provided in the work by Arum´ et al (2008a), where a set of open defects was ı intentionally injected into a test circuit Every floating line was routed . spent together discussing, eating, tasting wine, talking of culture, sharing everyday problems of our private lives, telling us your experiences in fishing and hunting, have been invaluable. It will. becomes electrically floating. This line may, in turn, drive one (or more) transistor pair(s). An illustrative example is shown in Fig. 1.3, where the interconnect line is driving an inverter. The floating line voltage. Electronic Engineering Dpt. ETSEIB, Diagonal 647, 08028 Barcelona, Spain e-mail: figueras@eel.upc.edu H J. Wunderlich (ed.), Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian