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5 Generalized Fault Modeling for Logic Diagnosis 141 Fig. 5.4 Example of aliasing in diagnosis. The response to a test set in (a) is explained by a single stuck-at fault. The defective behavior is actually more complex because the additional test in (b) produces a 0 at the output a Test set detects all single stuck-at faults: x c b d a1 0 1 1 0 1 0 1 1 0 1 0 1 1 0 1 & & =1 Possible explanation x 1 1 1 1 a d c b d a 1 0 1 1 0 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 & & =1 Possible explanation x 1 1 1 1 0 b Improved test set: The first part of the condition is true, if there is an event on line a, and the second part is true, if the final value of a is different from the current value of line b. At the first glance, the explanations for observed responses with the minimum number of CLFs are the most reasonable ones, however, there is the risk of alias- ing as demonstrated in Fig. 5.4. Thus, not only the number of CLFs, but also the complexity of their conditions should be considered. In most cases, the goal for production test generation is to achieve high stuck- at fault coverage. It is likely, that standard ATPG would generate the four patterns shown in case (a). This test set provides complete single stuck-at fault coverage and leads to two fails. The most reasonable explanation of this behavior is a stuck-at 1 at the output x. However, if one additional pattern is added to the test set like in case (b), the circuit produces a 0. This response cannot be explained anymore by a stuck-at fault at the output. In fact, there exists no single stuck-at fault, which would produce such a response. One possible explanation involves two stuck-at faults at lines a and d. 142 H J. Wunderlich and S. Holst 5.3.1.1 Other General Fault Models The idea of generalizing fault modeling to describe complex defects is not new. However, the main motivation of the previous works was more related to test gen- eration than to diagnosis. For efficient test generation, the initial values of internal signals, the preconditions and the fault effects have to be given explicitly in a formal way. Therefore, these notations are more restrictive in their formulation of condi- tions than CLFs. We will take a quick look at three modeling approaches and discuss their relation to the CLF calculus. Pattern faults (Keller 1996) distinguish between static and dynamic faults. Static faults have a condition in the form of a set of required signal values. If the condition is met, the fault is active and its impact is described as a set of value changes on internal signals. The following example shows the description of a static OR-bridge: STATIC f REQ f net a 1 g PROP f net b 0/1 g g Signal b changes from 0 to 1 if the aggressor signal a is 1. Two conditions have to be met in order to detect this fault. Signal a has to be 1, and signal b has to be 0. In CLF notation, this fault is equivalent to b ˚ Œa N b. In general, a pattern fault may require multiple signals to carry a specific value. This corresponds to a conjunction of these signals in the condition of a CLF. If the condition of CLF is a Boolean formula with only one minterm, the fault can be expressed in the pattern fault model. The fault a ˚ Œb Nc for instance can be ex- pressed as: STATIC f REQ f net b 1 net c 0 g PROP f net a 0/1 net a 1/0 g g In contrast to the CLF calculus, the propagation description has two terms. 5 Generalized Fault Modeling for Logic Diagnosis 143 Dynamic pattern faults contain an additional block describing an initial condition for a set of signals. This initial condition has to be met first, and then the signals must change to match the values given in the REQ section. The signal values given in the initial condition correspond to the indexed (x 1 / values in CLF notation. A dynamic pattern fault corresponds to a CLF with one minterm in the condition. In addition, the minterm may contain both current and indexed previous signal values. An example of a dynamic pattern fault is described below where a transition on signal a causes a faulty value on signal c: DYNAMIC f INIT f net a 0 net b 0 g REQ f net a 1 net b 0 g PROP f net c 1/0 g g In CLF, this fault corresponds to c ˚ ŒNa 1 N b 1  a N b  c. The previous values of the signals a and b have to be 0, the current value of signal a has to be 1, signal b must stay at 0 and signal c must be 1. If the condition of a CLF is not Boolean, it has no representation in the pattern fault notation. A similar notation is used in Kundu et al. (2006) which also targets test genera- tion. The fault effect can be described as slow-to-rise or slow-to-fall signal with a certain delay. This way, ATPG can be advised to sensitize a path of sufficient length from the fault site to an observation point to observe the fault effect. This explicit definition of the temporal behavior of the fault impact has no direct representation in CLF as it cannot be directly observed in logic diagnosis. Another very general fault modeling technique with a wide application field uses fault tuples (Blanton et al. 2006). A single fault tuple covers either a condition in the form of a required signal value or a fault impact in the form of a new value for a victim signal. For example, the condition fault tuple .a;0;i/ c requires the signal a to carry the value 0 at time i, and the excitation fault tuple .b;0;i/ e describes a stuck-at 0 on line b at time i. The product of fault tuples combines conditions and excitations, so that the described fault impact is only present, if all condition fault tuples are satisfied. For instance, the product of the two tuples above models a bridge, where signal a AND-dominates signal b. Multiple products can be combined with the OR-operation to model more complex faults. 144 H J. Wunderlich and S. Holst This modeling technique is very similar to pattern faults or the notation in Kundu et al. (2006). Again, any CLF with a Boolean function can be noted with fault tuples, more complex conditions cannot be expressed. 5.3.1.2 A Taxonomy of Static Bridging Faults As already described in the second chapter, bridges are an important fault class. They usually involve two signal lines which interact in a certain manner. Depending on the type of bridge and the current values of the signal lines, one or both signals may change their logic value. The types of bridges are described by two CLFs at most. Static bridges provide a good example of how the CLF calculus can be used to express a class of fault models. There are many different fault models available for static bridges (e.g. wired-logic, dominant-driver). Roussetetal.(2007)presentsa taxonomy for the most common models. Common to all these fault models is the fact that they do not model timing related behavior. The conditions can therefore be expressed using Boolean functions which depend on the current values of the involved signals. Another basic property of static bridge fault models is the fact that errors only occur, if the two involved signal lines carry different values. This necessary precon- dition is described by an XOR-term in the conditions. If this precondition is true, the actual behavior of the two signals is determined by two Boolean functions f a and f b . The function f a depends only on signal b, because the value of signal a is already determined by the precondition. Similarly, function f b depends only on signal a. This leads to the following generalized CLF formulation of an arbitrary bridge between two signal lines a and b: a ˚ Œf a .b/  .a ˚ b/; b ˚ Œf b .a/  .a ˚ b/ There are exactly four basic expressions for f a and f b , respectively. An expression may be constant 0, constant 1 or may use the positive or the inverted value of the other signal in the bridge: f a .b/ 2f0; 1; N b; bg;f b .a/ 2f0; 1; Na; ag Any more complex Boolean formula can be simplified by using the precondition and Boolean identities. The formulas given above therefore model every possible static bridge configuration. There are 4 2 = 16 possible configurations that are derived by choosing one of the four possible expressions for f a and f b . From these 16 config- urations, there are six, that are actually derived from other bridges by interchanging the roles of the signals a and b. This leads to ten unique bridge types including the fault free case (Table 5.1). 5 Generalized Fault Modeling for Logic Diagnosis 145 Table 5.1 The ten possible static bridge types f a .b/ f b .a/ Bridge type 00Fault free 01adominates b 0 NaaAND-dominates b 0aa OR-dominates b 11aand b swap values (4-way bridge) 1 Nabdominates a & a AND-dominates b 1abdominates a & a OR-dominates b N b Na wired-AND N babAND-dominates a & a OR-dominates b bawired-OR All common bridge fault models are present in this table. There are also three more exotic bridges described which are not widely used. These are combinations of different dominations from a to b and from b to a. 5.4 Logic Diagnosis In this section, we apply the CLF calculus to logic diagnosis. The method presented below identifies possible faulty regions in a combinational circuit based on its in- put/output behavior and independent of a fault model. The approach combines a flexible and powerful effect-cause pattern analysis algorithm with high-resolution ATPG . 5.4.1 Effect Cause and Cause Effect The classic diagnosis algorithms follow two different paradigms: Effect-cause anal- ysis looks at the failing outputs and starts reasoning using the logic structure of the circuits (Abramovici and Breuer 1980; Waicukauski and Lindbloom 1989). One example of effect-cause analysis is the ‘Single Location At a Time’ (SLAT) tech- nique introduced in Bartenstein et al. (2001). A diagnostic test pattern has the SLAT property, if there is at least one observable stuck-at fault which produces a response on that pattern identical with the response of the device under diagnosis (DUD). In SLAT diagnosis, the explaining stuck-at faults for all available SLAT patterns are combined to form possible explanations for the erroneous behavior of the DUD as a whole. Cause-effect analysis is based on a fault model. For each fault of the model, fault simulation is performed, and the behavior is matched with the outcome of the DUD. Standard debug and diagnosis algorithms usually work in two passes. First, a fast effect-cause analysis is performed to constrain the circuits region where possible 146 H J. Wunderlich and S. Holst culprits may be located. Second, for each of the possible fault sites, a cause-effect simulation is performed for identifying those faults, which match the real observed behavior (Desineni et al. 2006; Amyeen et al. 2006). The resolution of a test set cor- responds to the number of faults which cannot be distinguished any further (Ve ner is et al. 2004; Bartenstein 2000; Bhatti and Blanton 2006). The main drawback of the cause-effect paradigms is the dependency on a fault model. 5.4.2 Fault Dictionaries vs. Adaptive Diagnosis Cause-effect diagnosis can be speeded up, if for each fault and each failing pattern the erroneous output is determined by simulation and then stored in a dictionary (Pomeranz and Reddy 1992). Even after an effect-cause pass, the size of such a dictionary may explode, and significant research effort has been spent for reducing the size of fault dictionaries (Boppana et al. 1996; Chess and Larrabee 1999; Liu et al. 2008). During debug and during diagnosis of first silicon, there exists an ef- ficient alternative to precomputed fault dictionaries in so-called adaptive diagnosis (Gong and Chakravarty 1995). Here, we use faulty and fault free responses of the device under diagnosis (DUD) in order to guide the automatic generation of new patterns for increasing the reso- lution. A pattern analysis step extracts information from responses of the DUD and accumulates them in a knowledge base. This knowledge in turn guides an automatic test pattern generator (ATPG) to generate relevant patterns for achieving high di- agnostic resolution. Such a diagnostic ATPG does not rely on a precomputed fault dictionary, and significant memory savings are obtained. The loop ends, when an acceptable diagnostic resolution is reached (Fig. 5.5). The definition of the exact abort criterion depends on the number and confidence levels of fault candidates. In the subsequent sections we present the ‘Partially Overlapping Impact couNTER’ (POINTER) approach (Holst and Wunderlich 2009). 5.4.3 Pattern Analysis In this section, we present a method to analyze the behavior of the DUD for a given test set and a measure to quantify how well it is reflected by a certain CLF. The SLAT paradigm will be just the special case of a perfect match for one pattern. Let FM(f) be a fault machine, i.e. the circuit with stuck-at fault f injected. For each test pattern t 2 T , we define the evidence e.f; t/ D . t ;à t ; t / as tuple of natural numbers  t ;à t ; t 2 N (see Fig. 5.6)where: 5 Generalized Fault Modeling for Logic Diagnosis 147 knowledge resolution acceptable? pattern analysis pattern generation no yes done Fig. 5.5 Adaptive diagnosis flow t t DUD FM f ΔT t Δσ t Δι t Fig. 5.6 Definition of evidence  t is the number of failing outputs where both the DUD and the fault machine FM match. It can be interpreted as the number of predictions by assuming fault f as the culprit. à t is the number of outputs which fail in FM but are correct in DUD. This is the number of mispredictions by assuming fault f .  t is the number of outputs which fail in DUD but are correct in FM. These are error outputs which cannot be explained by fault f . 148 H J. Wunderlich and S. Holst For a SLAT test pattern t, the evidence will provide maximum  t and à t D  t D 0 as this fault explains all the errors and there is no single stuck-at fault with a higher number of predictions. The evidence of a fault f and a test set T is e.f; T / D . T ;à T ; T /; with  T D X t2T  t ; à T D X t2T à t ; and  T D X t2T  t Again, if the real culprit is indeed the stuck-at fault f ,wegetà T D  T D 0 and  T will be maximum. While processing pattern after pattern, t 1 ;:::;t i , the knowledge base is con- structed by the evidences e.f; T i /; T i Dft 1 ;:::;t i g for all the stuck-at faults f . If a fault is not observable under a certain pattern, no value change takes place and this fault is not considered within this iteration. If the DUD gives the correct output under a pattern t, only à T is increased for faults which are observable under this pat- tern and hence lead to a misprediction. In this way, candidates can be excluded using passing patterns, too. The maximum achievable diagnostic resolution is bounded by the size of the equivalence classes of the faults in the knowledge base. If the fault in the DUD is not always active due to nondeterministic behav- ior or some unknown activation mechanism, the measure still provides consistent evidences. For instance, let f 0 be a slow to rise transition fault. For some patterns t, fault f 0 will appear as a stuck-at 0 fault, for others it is not observable. In this case, e.f; t/ D . t ;à t ; t / provides  t  Q t for all the other evidences e. Q f;t/D . Q t ;Qà t ;Q t /. As a consequence, we have  T Q T for all evidences e. Q f;T/and the evidence e.f; T / still contributes information for locating the fault. However, the value à T will not be zero anymore and can be used for ranking fault candidates. Now we define  t D minf t ;à t g and  T D P t2T  t . Under the single fault assumption, let f be a stuck-at fault which models at least a part of the DUD behavior for some patterns under some conditions. If the condi- tions are satisfied for a pattern t 2 T , the set of failing outputs of FM(f) corresponds to the fails of the DUD and there is no misprediction (à t D 0/.Otherwise,the failing outputs of FM(f) and DUD are disjoint ( t D 0/. Hence, all  t and also  T are zero for fault f . If there is a pattern t with  t >0like in Fig. 5.6,the corresponding conditional stuck-at is not a single fault candidate. When assuming multiple faults, we observe that mutual fault masking is rather rare, and ranking the stuck-at fault according to the size of  T provides a good heuristic. 5 Generalized Fault Modeling for Logic Diagnosis 149 Table 5.2 Fault models and evidence forms Classic model à T  T  T Single stuck-at 0 0 0 Stuck-at, more fault sites present 0 >0 0 Single conditional stuck-at >0 00 Cond. stuck-at, more fault sites present >0 >0 0 Delay fault, i.e. long paths fail >0 0 >0 This fault model independent pattern analysis approach is able to identify circuit parts containing arbitrary faulty behavior. However, if the behavior of the DUD can be explained using some classic fault models, certain evidence forms are observed. Table 5.2 shows suspect evidences for some classic models. If à T ,  T and  T are all zero, a single stuck-at fault explains the DUD behavior completely. If  T and  T are zero, a faulty value on a single signal line under some patterns T 0  T provides complete explanation. With à T D  T D 0, such a stuck-at fault explains a subset of all fails, but some other faulty behavior is present in the DUD. These other fault sites are independent from the stuck-at fault at hand, i.e. for each pattern an output is either influenced by the stuck-at fault only or by some other fault sites. With only  T D 0, a faulty value on the corresponding single signal line explains a part of DUD behavior and more fault sites are present again. If only  T is zero, the suspect fails are a superset of DUD fails. If all suspects show positive values in all components à T ,  T ,  T , the responses were caused by multiple interacting fault sites, and all simplistic fault models would fail to explain the DUD behavior. For further analysis, the evidences in the knowledge base are ordered to create a ranking with the most suspicious fault sites at the beginning (lowest rank). Firstly, evidences are sorted by increasing  T ,i.e.  a T > b T ) rank.e.f a ;T// >rank.e.f b ;T// moving single conditional stuck-at faults in front. Evidences with identical  T are sorted by decreasing  T moving candidates in front, which explain most failures:  a T > b T ) rank.e.f a ;T//< rank.e.f b ; T //: Finally evidences with identical  T and  T are ordered by increasing à T values: à a T >à b T ) rank.e.f a ;T// >rank.e.f b ; T //: For a brief example of the pattern analysis approach, consider the circuit in Fig. 5.7. It contains two gates and four exemplary stuck-at faults for fault simulation. The exhaustive test set and the response from the DUD are shown in the first two columns of Table 5.3. The erroneous bits are shown in bold, the DUD has failed on output x in the third pattern. 150 H J. Wunderlich and S. Holst Fig. 5.7 Circuit model for fault simulation 1 & b a x y f 4 f 3 f 2 f 1 Table 5.3 Syndrome and result from stuck-at fault simulation Pattern Syndrome f 1 f 2 f 3 f 4 ab xy xy xy xy xy 00 10 00101010 01 10 01 10 10 10 10 10001001 00 11 01 01 10 01 00 Table 5.4 Evidences and rank of the four faults Fault  T à T  T  T Rank f 1 03104 f 2 12001 f 3 01102or3 f 4 01103or2 Now, the four faults are simulated for the given pattern set and their signatures are shown in the remaining columns in Table 5.3. The fault f 1 is observable in three response bits, but it fails to explain the erroneous bit in the syndrome. This leads for this fault to an evidence of e.f 1 ;T/D . T ;à T ; T ; T / D .0;3;1;0/. The evidence is derived for the other stuck-at faults as well; Table 5.4 shows the result. All evidences show  T D 0, so the ranking procedure continues with  T .Only f 2 has positive  T , so this fault is ranked above all other faults. The other faults are ranked by increasing à T . The top-ranked evidence f 2 shows positive  T and positive à T . Therefore, none of the simulated faults can explain the syndrome completely,but f 2 explains a subset of all fails. This leads to a CLF of the form a ˚ Œa  cond with some arbitrary condition. 5.4.4 Volume Diagnosis and Pattern Generation If the resolution provided by the evidences of a test pattern set T is not sufficient dur- ing adaptive diagnosis or design debug, we have the option to use the evidences for guiding further diagnostic ATPG. In volume diagnosis, the pattern set is fixed, and we have to extract as much diagnostic information as possible from rather limited information. Usually, only the first i failing patterns are recorded, and in addition, all the passing patterns up to this point can be used for diagnosis. [...]... the stuck-at 1 fault at line a and a ˚ Œcond0  As a consequence, assuming faults at line a will explain all the errors, and there is no line where assumed unconditional faults could explain more errors However, there may be several of those lines explaining all the errors, and the ranking explained in the section above prefers those with a minimum number of mispredictions In ? (?) the calculus described... fully entering the Very Deep Sub Micron era This chapter provides an overview of models and notations currently used in memory testing practice highlighting challenging problems waiting for solutions Keywords Memory testing Memory modeling Fault models March test 6.1 Introduction Since 1945 when the ENIAC, the first computer system with its memory of mercury and nickel wire delay lines went into service,... Di Carlo ( ) and P Prinetto Politecnico di Torino, Control and Computer Engineering Department, Corso duca degli Abruzzi 24, 10129, Torino, Italy e-mail: stefano.dicarlo@polito.it H.-J Wunderlich (ed.), Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault, Frontiers in Electronic Testing 43, DOI 10.1007/978-90-481-3282-9 6, c Springer Science+Business Media B.V 2010... currently used in the memory testing practice, and concludes by highlighting challenging and still open problems 6 Models in Memory Testing 159 6.2 Models for Memory Testing: A Multidimensional Space Tens of models have been proposed in the literature to support the different aspects and phases of the memory life-cycle From design to validation and verification, from manufacturing to testing, and from... classified into different classes based on the characteristic of the related SOS In particular, let jf j be the number of f-cells involved in the SOS, and m (Eq 6.2) the number of operations composing SOS Depending on jf j, FPs can be categorized into single-cell FPs when jf j D 1, and n-coupling FPs when jf j D n In case of n-coupling FPs, the set of f-cells is split into victims (v) and aggressors (a) In. .. representation domains are included Based on this model, in the sequel of this section we shall analyze the matrix proposed in Fig 6.5, outlining 162 S Di Carlo and P Prinetto Fig 6.4 Different memory modeling levels proposed by Van de Goor Fig 6.5 Abstraction level vs representation domain modeling sub-space a set of well established models used to represent memory structures, behaviors, and architectures In particular... dimension include: behavioral domain, structural domain, physical domain, and geometrical domain The behavioral domain focuses on the behavior of the system, only, without any reference to its internal organization The structural domain focuses on the structure (i.e., the topology) of the system, in terms of connection of blocks Such a description is usually technology independent The physical domain introduces... (2000) Fault distinguishing pattern generation In Proceedings 31st IEEE international test conference (ITC) 2000, pp 820–828, doi:10.1109/ TEST.2000.894285 Bartenstein T, Heaberlin D, Huisman LM, Sliwinski D (2001) Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm In Proceedings 32nd IEEE international test conference (ITC) 2001, pp 287–296, doi:10.1109/TEST.2001.966644... arbitrary faults In Proceedings 37th IEEE international test conference (ITC) 2006, pp 19.2, doi:10.1109/TEST.2006.297647 Blanton RD, Dwarakanath KN, Desineni R (2006) Defect modeling using fault tuples IEEE Trans CAD Integrat Circuits Sys 25(11):2450–2464, doi:10.1109/TCAD.2006.870836 Boppana V, Hartanto I, Fuchs WK (1996) Full fault dictionary storage based on labeled tree encoding In Proceedings 14th IEEE... focus on those models usually used in memory testing The system level is the highest representation level and is usually very close to the specifications When dealing with memories, behavioral descriptions at system level describe the memory behavior in terms of Input/Output (I/O) relationships Timing diagrams can be used to graphically represent the minimum and maximum timing constraints and the I/O . overview of models and notations currently used in the memory testing practice, and concludes by highlighting challenging and still open problems. 6 Models in Memory Testing 159 6.2 Models for. there may be several of those lines explaining all the errors, and the ranking explained in the section above prefers those with a minimum number of mispredictions. In ? (?) the calculus described. generation. In Proceedings 31st IEEE interna- tional test conference (ITC) 2000, pp 820–828, doi:10.1109/ TEST.2000.894285 Bartenstein T, Heaberlin D, Huisman LM, Sliwinski D (2001) Diagnosing combinational