Models in Hardware Testing- P7 ppt

172 S. Di Carlo and P. Prinetto 6.4.3.2 2-Coupling Static Faults 2-coupling static FFMs are faults described by FPs involving two f-cells ( j f j D 2) and sensitized by the application of at most a single memory operation (m Ä 1). In this condition, one of the two f-cells (usually denoted by the generic address v)isthe victim cell where the effect of the faulty behavior manifests, while the second cell (usually denoted by the generic address a) is the aggressor cell, responsible with the victim for producing the faulty behavior. With this distinction three classes of SOSs can be generated: 1. No cell accessed: the state of the cells sensitizes the fault. 2. Only the aggressor cell is accessed. 3. Only the victim cell is accessed: the aggressor contributes to the fault simply with its initial state. Starting with this classification it is possible to enumerate the space of 2-coupling FPs of Table 6.2 composed of 36 different FPs. Only those combinations of opera- tions that actually represent a faulty behavior have been considered. As for the single-cell static FFMs, this set of FPs can be grouped to define a set of seven well established and characterized FFMs: 1. State Coupling Fault (CFst): the victim cell is forced into a given logic state when the aggressor cell is in a given state, without performing any operation. As for the state fault, this FFM is special, as no operation is required to sensi- tize the fault. Four types of state coupling faults exist, defined as CF st.xy/ D f <x a y v = Ny v = > g ,wherex;y 2 f 0; 1 g . This covers FP 1 ,FP 2 ,FP 3 ,andFP 4 . Table 6.2 2-coupling FP space #FP #FP 1 <0 a 0 v =1 v = > 19 <0 a 0 v ; w v 1 =0 v = > 2 <0 a 1 v =0 v = > 20 <1 a 0 v ; w v 1 =0 v = > 3 <1 a 0 v =1 v = > 21 <0 a 1 v ; w v 0 =1 v = > 4 <1 a 1 v =0 v = > 22 <1 a 1 v ; w v 0 =1 v = > 5 <0 a 0 v ; w a 0 =1 v = > 23 <0 a 1 v ; w v 1 =0 v = > 6 <0 a 1 v ; w a 0 =0 v = > 24 <1 a 1 v ; w v 1 =0 v = > 7 <0 a 0 v ; w a 1 =1 v = > 25 <0 a 0 v ;r v 0 =0 v =1 v > 8 <0 a 1 v ; w a 1 =0 v = > 26 <1 a 0 v ;r v 0 =0 v =1 v > 9 <1 a 0 v ; w a 0 =1 v = > 27 <0 a 0 v ;r v 0 =1 v =0 v > 10 <1 a 1 v ; w a 0 =0 v = > 28 <1 a 0 v ;r v 0 =1 v =0 v > 11 <1 a 0 v ; w a 1 =1 v = > 29 <0 a 0 v ;r v 0 =1 v =1 v > 12 <1 a 1 v ; w a 1 =0 v = > 30 <1 a 0 v ;r v 0 =1 v =1 v > 13 <0 a 0 v ;r a 0 =1 v = > 31 <0 a 1 v ;r v 1 =0 v =0 v > 14 <0 a 1 v ;r a 0 =0 v = > 32 <1 a 1 v ;r v 1 =0 v =0 v > 15 <1 a 0 v ;r a 1 =1 v = > 33 <0 a 1 v ;r v 1 =0 v =1 v > 16 <1 a 1 v ;r a 1 =0 v = > 34 <1 a 1 v ;r v 1 =0 v =1 v > 17 <0 a 0 v ; w v 0 =1 v = > 35 <0 a 1 v ;r v 1 =1 v =0 v > 18 <1 a 0 v ; w v 0 =1 v = > 36 <1 a 1 v ;r v 1 =1 v =0 v > 6 Models in Memory Testing 173 2. Disturb coupling fault (CF ds ): an operation (write or read) performed on the aggressor cell forces the victim cell into a given logic state. Any oper- ation performed on the aggressor is accepted as sensitizing operation (a read, a transition write, or a non-transition write). Twelve types of disturb coupling faults exist, defined as CF ds.xz;w y / D ˚ <x a z v ; w a y =Nz v = > « ,and CF ds.xz;r y / D f <x a y v ;r a x = Ny v = > g where x; y; z 2 f 0; 1 g . This covers FP 5 , FP 6 ,FP 7 ,FP 8 ,FP 9 ,FP 10 ,FP 11 ,FP 12 ,FP 13 ,FP 14 ,FP 15 ,andFP 16 . 3. Transition coupling fault (CF tr ): the state of the aggressor cell causes the fail- ure of a transition write operation performed on the victim cell. This fault is sensitized by a write operation on the victim cell, while the aggressor is in a given state. Four types of transition coupling faults exist, defined as CF tr.x0/ D ˚ <x a 0; w v 1 =0 v = > « ,andCF tr.x1/ D ˚ <x a 1; w v 0 =1 v = > « where x 2 f 0; 1 g . This covers FP 19 ,FP 20 ,FP 21 ,FP 22 . 4. Write destructive coupling fault (CF wd ): a non-transition write operation per- formed on the victim cell while the aggressor cell is in a given state results in a transition of the cell itself. Four types of write destructive coupling faults exist, defined as CF wd.xy/ D ˚ <x a y v ; w v y = Ny v = > « ,wherex;y 2 f 0; 1 g . This covers FP 17 ,FP 18 ,FP 23 ,FP 24 . 5. Read destructive coupling fault (CF rd ): a read operation performed on the vic- tim cell, while the aggressor cell is in a given state, destroys the data stored in the victim. Four types of read destructive coupling faults exist, defined as CF rd.xy/ D ˚ <x a y v ;r v y = Ny v = Ny v > « ,wherex; y 2 f 0; 1 g . This covers FP 29 ,FP 30 , FP 31 ,FP 32 . 6. Incorrect read coupling fault (CFir): a read operation performed on the vic- tim cell returns the incorrect logic value, while the aggressor is in a given state. Four types of incorrect read coupling faults exist, defined as CF ir.xy/ D ˚ <x a y v ;r v y =y v = Ny v > « ,wherex; y 2 f 0; 1 g . This covers FP 25 ,FP 35 ,FP 26 , FP 36 . 7. Deceptive read destructive coupling fault (CFdr): a read operation performed on the victim cell returns the correct logic value and changes the contents of the victim while the aggressor is in a given logic state. Four types of deceptive read destructive coupling faults exist, defined as CF dr.xy/ D ˚ <x a y v ;r v y = Ny v =y v > « , where x;y 2 f 0; 1 g .ThiscoversFP 27 ,FP 33 ,FP 28 ,FP 34 . The presented set of FFMs allows covering all FPs proposed in Table 6.2,andany test covering these FFMs is therefore able to cover all possible 2-coupling static faults. Other sets of fault models have been presented in the literature, such as:  Idempotent coupling fault (CF id ): a transition write operation on the aggressor cell forces the victim in a given state: CF id.xy;w Nx / D ˚ <x a y v ; w a Nx = Ny v = > « , where x;y 2 f 0; 1 g .  Inversion coupling fault (CF in ): a transition write operation on the aggressor cell flips the content of the victim cell: CF in.x;w Nx / D ˚ <x a 0 v ; w a Nx =1 v = >, <x a 1 v ; w a Nx =0 v = > « ,wherex 2 f 0; 1 g . 174 S. Di Carlo and P. Prinetto  Non-transition coupling fault (CF nt ): a non-transition write operation performed on the aggressor cell forces the victim cell in a given state: CF nt.xy;w x / D f <x a y v ; w a x = Ny v = > g ,wherex;y 2 f 0; 1 g . Nevertheless, all these FFMs are either subsets of the seven FFMs presented before or can be expressed as a combination of these basic FFMs. 6.4.4 Dynamic Fault Models As operations are added to the SOS we enter into the dynamic fault space that re- sults in a theoretically infinite number of potential FFMs. Equation 6.7 describes a relation between the number of possible FPs and the number m of operations in SOS for single-cell dynamic faults (Al-Ars 2005): #FP singlecell D ( 2mD 0 10  3 m1 m  1 (6.7) The equation clearly shows an exponential relation between the number of FPs and the number of operations in SOS. This actually reduces the ability of exploring this huge space of faults for defining FFMs, due to limited availability of simulation time and computation power. In order to cope with this problem, experiments on an extensive set of memory devices showed that the probability of dynamic fault decreases when m increases (Al-Ars et al. 2002). Based on this assumption, two-operations dynamic faults have been the most studied in the literature and will be considered in this chapter. As for static fault models, two-operations dynamic faults can be additionally clustered according to the number of f-cells . j f j / involved in the fault. We shall focus on: (i) single-cell two-operations dynamic faults . j f j D 1; m D 2/, and (ii) 2-coupling two-operations dynamic faults . j f j D 2; m D 2/. This leads to a space of 30 single- cell FPs, plus 192 2-coupling FPs. This space is in some way already too huge to be explored. For this reason in Van de Goor et al. (2000), a limited set of these FPs has been simulated on realistic defective memory devices and the following established FFMs have been defined: 1. Dynamic Read Disturb Fault (dRDF): a write operation immediately followed by a read operation on the same cell changes the logical value stored in the faulty memory cell and returns an incorrect output. Four types of dRDFs exist, defined as dRDF .xy/ D ˚ <x;w y r y = Ny= Ny> « ,wherex;y 2 f 0; 1 g . 2. Dynamic Deceptive Read Disturb Fault (dDRDF): a write operation immediately followed by a read operation on the same cell changes the logical value stored in the faulty memory cell, but returns the expected output. Four types of dDRDFs exist, defined as dDRDF .xy/ D ˚ <x;w y r y = Ny=y > « ,wherex;y 2 f 0; 1 g . 3. Dynamic Incorrect Read Disturb Fault (dIRF): a write operation immediately followed by a read operation on the same cell does not change the logical value 6 Models in Memory Testing 175 stored in the faulty memory cell, but returns an incorrect output. Four types of dIRFs exist, defined as IRF .xy/ D ˚ <x;w y r y =y= Ny> « ,wherex;y 2 f 0; 1 g . 4. Dynamic Disturb Coupling Fault (dCFds): a write operation followed im- mediately by a read operation performed on the aggressor cell causes the victim cell to flip. Eight types of dCFdss exist, defined as dCFds .xyz/ D ˚ <x a y v ; w a z r a z = Ny v = > « ,wherex;y; z 2 f 0; 1 g . 5. Dynamic Read Disturb Coupling Fault (dCFrd): a write operation immediately followed by a read operation on the victim cell when the aggressor cell is in a given state changes the logical value stored in the victim, and returns an in- correct output. Eight types of dynamic dCFrds exist, defined as dCFrd .xyz/ D ˚ <x a y v ; w v z r v z =Nz=Nz > « ,wherex;y; z 2 f 0; 1 g . 6. Dynamic Deceptive Read Disturb Coupling Fault (dCFdr): a write operation immediately followed by a read operation on the victim cell when the ag- gressor cell is in a given state changes the logical value stored in the victim cell, but returns the expected output. Eight types of dCFdrs exist, defined as dCFdr .xyz/ D ˚ <x a y v ; w v z r v z =Nz=z > « ,wherex;y;z 2 f 0; 1 g . 7. Dynamic Incorrect Read Disturb Coupling Fault (dCFir): a write operation im- mediately followed by a read operation on the victim cell when the aggressor cell is in a given state does not affect the logical value stored in the victim but returns an incorrect output. Eight types of dCFirs, defined as dCFir .xyz/ D ˚ <x a y v ; w v z r v z =z=Nz > « ,wherex;y; z 2 f 0; 1 g . It is clear that the set of FFMs defined here addresses a very restricted numberof FPs with respect to the complete fault space. This makes dealing with dynamic faults a very complex task that can be solved only moving from higher abstraction levels to lower ones where the knowledge of the physical memory layout and structure, and of the set of realistic defects can be used to restrict the fault space (see Section 6.6) 6.4.5 n-Coupling Fault Models In-coupling faults represent fault models where n different memory cells are in- volved in the fault mechanism (f -cells D n). They are usually referred to as pattern sensitive faults. In general the content of a cell i (or the ability of i to change its state) is influenced by the contents of all other memory cells, or by the opera- tions performed on them. A pattern sensitive fault is the most general definition of n-coupling fault in which n is equal to the size of the memory. In a more realistic situation, the so called neighborhood pattern sensitive faults (NPSFs) are usually considered, in which a reduced set of cells spatially located in adjacent positions are responsible for the fault mechanism. The neighborhood is the total number of cells in this set. Traditionally the victim cell is called in this context base cell, while the aggressor cells are called the deleted neighborhood. In the PSF the neighborhood can be anywhere in the memory while in the NPSF the neighborhood must be in a single position surrounding the base cell. These type 176 S. Di Carlo and P. Prinetto Fig. 6.12 Type-1 and Type-2 NPSF of fault models are particularly indicated when dealing with high density DRAMs, due to the reduced memory cell capacitance. In general two types of neighborhood patterns are considered: Type-1 including four deleted neighborhood cells, and Type-2 including eight deleted neighborhood cells (Suk et al. 1979). The type-2 model is more complex and allows to model diagonal coupling effects in the memory matrix. Figure 6.12 shows the two types of neighborhood. Three types of NPSF have been considered in the literature: 1. Active NPSF (ANPSF) (Suk et al. 1980), also called dynamic NPSF (Saluja et al. 1985) where the base cell changes its value based on a change in the pattern of the deleted neighborhood. In particular, a cell of the deleted neighborhood has a transition while the rest of the neighborhood including the base cell has a given pattern. For example <x d0 1 x d1 2 x d2 3 x d3 4 x B 5 ; w d0 Nx 1 = Nx B 5 = >,wherex i 2 f 0; 1 g , denotes a generic FP belonging to the ANPSF FFM. 2. Passive NPSF (Suk et al. 1980): a certain neighborhood pattern prevents the base cell to change. 3. Static NPSF (Saluja et al. 1985): the base cell is forced into a particular state when the deleted neighborhood contains a particular pattern. This differs from the ANPSF as no transition is required to excite the fault. 6.4.6 Multiple Faults It may happen that the effects of two FFMs link together. If the faults share the same aggressor cell and/or the same victim cell, the FFMs are said to be linked. As an example let’s consider the CF ds denoted by the following two FPs: FP 1 D < 0 a 0 v ; w a 1 =1 v = >,andFP 2 D <0 a 1 v ; w a 1 =0 v = >. 6 Models in Memory Testing 177 Fig. 6.13 Example of linked fault Figure 6.13 shows a memory with n cells affected by FP 1 and FP 2 having different aggressor cells with addresses a 1 and a 2 , the same victim cell with ad- dress v,anda 1 <a 2 < v. According to FP 1 , starting with a 1 equal to 0 and by performing w a 1 1 , the victim cell v flips from 0 to 1; then, starting with a 2 equal to 0 and performing w a 2 1 , according to FP 2 the victim cell v changes its value again, from 1 to 0. The global result is that the fault effect is masked by the application of FP 2 ,sinceFP 2 has a faulty behavior opposite to FP 1 . Basedonthisexample,twoFPs,FP 1 D <SOS 1 =FB 1 >,andFP 2 D <SOS 2 =FB 2 > are linked, and denoted by FP 1 ! FP 2 , if both of the follow- ing conditions are satisfied:  FP 1 masks FP 2 , i.e., FB 2 ! FB 1 .  SOS 2 is applied after SOS 1 , on either the aggressor cell or the victim cell of FP 1 . To detect linked faults (LFs), it is necessary to detect in isolation at least one of the FPs that compose the fault (i.e., preventing the other FP to mask the fault) (Hamdioui et al. 2004). Among the extended space of possible linked FFMs, based on several simulations on defective memory devices, the following established realistic linked FFMs have been defined (Hamdioui et al. 2004):  Single cell linked faults: involve a single memory location where all FPs are sequentially applied. Table 6.3 reports the list of realistic single-cell linked faults.  2-coupling linked faults: 2-coupling linked faults involve two distinct memory cells: one aggressor cell a, and one victim cell v. Two different situations may happen: (i) a<v, and (ii) v <a. Based on this distinction realistic 2-coupling linked faults can be clustered in three different classes: (i) linked faults based on a combination of 2-coupling FPs that share both the aggressor and the victim cell .LF2 aa /, (ii) linked faults where FP 1 is a 2-coupling FP and FP 2 is a single-cell FP .LF2 av /, and (iii) linked faults where FP 1 is a single-cell FP and FP 2 is a 178 S. Di Carlo and P. Prinetto Table 6.3 Single-cell linked faults FFM FPs TF Nx ! WDF x <x;w Nx =x= >!<x;w x = Nx= >; x 2f0; 1g WDF x ! WDF Nx <x;w x = Nx= >!< Nx;w Nx =x= >x2f0; 1g DRDF x ! WDF Nx <x;r x = Nx=x >!< Nx; w Nx =x= >; x 2f0; 1g TF Nx ! RDF x <x;w Nx =x= >!<x;r x = Nx=Nx>;x2f0; 1g WDF x ! RDF Nx <x;w x = Nx= >!< Nx;r Nx =x=x >; x 2f0; 1g DRDF x ! RDF Nx <x;r x = Nx=x >!< Nx; r Nx =x=x >; x 2f0; 1g 2-coupling FP .LF2 va /.Table6.4 reports the list of realistic 2-coupling linked faults where the following notation is used: op 2fr; wg, x 2 D y 1 , x i D y i if op i D r.  3-coupling linked faults: 3-coupling linked faults are composed of FPs sharing the same victim cell but having different aggressor cells (a 1 and a 2 ). Considering the possible mutual positions of a 1; a 2 ,andv, realistic fault models proposed in [Hamdioui et al. 2004] belong to the following two situations: (i) a 1 < v <a 2 , and (ii) a 2 < v <a 1 . Realistic 3-coupling linked faults can be represented by the same FPs used to represent 2-coupling linked faults. 6.4.7 Fault Models for Specific Technologies and Architectures The space of fault models defined in the previous sections is far from representing a complete taxonomy of possible memory faults. It actually focuses on a set of very high level, technology independent faults that can be easily applied to any type of memory. As we start exploring all the dimensions of the multidimensional space intro- duced in Section 6.2, several specific functional fault models can be defined, as for example:  Fault models for multi-port memories (Hamdioui et al. 2001)  Fault models for cache memories (Al-Ars et al. 2008)  Fault models for DRAMs (Al-Ars 2005) A detailed analysis of all these fault models is out of the scope of this chapter, and, if interested, the reader should refer to specific publications. 6.5 From Fault Models to Memory Testing In order to inspect memory devices for possible faulty behaviors, all memory com- ponents are usually tested at the end of production and sometimes in the field. As already stated in Section 6.1, common practice for memory testing is to apply func- tional test patterns that try to cover FFMs. 6 Models in Memory Testing 179 Table 6.4 2-coupling linked faults 2-coupling linked faults L aa CF ds . x 1 0;op1 y1 / ! CF ds . x 2 1;op2 y2 / CF wd . x0 / ! CF wd . x1 / CF ds . x 1 1;op1 y 1 / ! CF ds . x 2 0;op2 y2 / CF wd.x1/ ! CF wd.x0/ CF tr.x0/ ! CF ds . x1;op y / CF dr . x0 / ! CF wd . x1 / CF tr . x1 / ! CF ds . x0;op y / CF dr . x1 / ! CF wd . x0 / CF wd . x0 / ! CF ds . x1;op y / CF ds . x0;op y / ! CF wd . y1 / CF wd . x1 / ! CF ds . x0;op y / CF ds . x1;op y / ! CF wd . y0 / CF dr . x0 / ! CF ds . x1;op y / CF tr . x0 / ! CF rd.x1/ CF dr . x1 / ! CF ds . x0;op y / CF tr . x1 / ! CF rd.x0/ CF ds . x0;op y / ! CF wd . y1 / CF wd . x0 / ! CF rd . x1 / CF ds . x1;op y / ! CF wd . y0 / CF wd . x1 / ! CF rd.x0/ CF tr . x0 / ! CF wd . x1 / CF dr . x0 / ! CF rd . x1 / CF tr . x1 / ! CF wd . x0 / CF dr . x1 / ! CF rd . x0 / 2-coupling linked faults L av CF ds . x0;op y / ! WDF 1 CF ds . x0;op y / ! RDF 1 CF ds . x1;op y / ! WDF 0 CF ds . x1;op y / ! RDF 0 CF tr . x0 / ! WDF 1 CF tr . x0 / ! RDF 1 CF tr . x1 / ! WDF 0 CF tr . x1 / ! RDF 0 CF wd . x0 / ! WDF 1 CF wd . x0 / ! RDF 1 CF wd . x1 / ! WDF 0 CF wd . x1 / ! RDF 0 CF dr . x0 / ! WDF 1 CF dr . x0 / ! RDF 1 CF dr . x1 / ! WDF 0 CF dr . x1 / ! RDF 0 2-coupling linked faults L va TF 0 ! CF ds . x1;op y / DRDF 0 ! CF ds . x1;op y / TTF 1 ! CF ds . x0;op y / DRDF 1 ! CF ds . x0;op y / TF 0 ! CF wd . x1 / DRDF 0 ! CF wd . x1 / TF 1 ! CF wd . x0 / DRDF 1 ! CF wd . x0 / TF 0 ! CF rd . x1 / DRDF 0 ! CF rd . x1 / TF 1 ! CF rd . x0 / DRDF 1 ! CF rd . x0 / WDF 0 ! CF ds . x1;op y / WDF 1 ! CF ds . x0;op y / WDF 0 ! CF wd . x1 / WDF 1 ! CF wd . x0 / WDF 0 ! CF rd . x1 / WDF 1 ! CF rd . x0 / Memories are among of the most complex digital circuits. They involve many analog parts and the resulting circuitry is denser than any other type of digital device. No single pattern is therefore sufficient to test a memory for all types of real defects. Actually a suite of patterns is required to detect the real defects that may happen in the manufacturing environment (Dean et al. 1993). 180 S. Di Carlo and P. Prinetto Several testing approaches have been proposed in the literature to build functional memory test algorithms. One of the first proposed algorithms was the GALPAT (Van de Goor 1991). It is composed of the following steps: 1. Initialize all memory cells with ‘0’ 2. For each cell i do: a) Complement the cell content b) For each cell j ¤ i read the content of j and the content of i c) Complement the content of i 3. Repeat step 2 starting with the memory initialized with ‘1’ The main drawback of this approach is that its complexity is O.4n 2 / where n is the number of memory cells. Several improvements of this algorithm have been proposed:  Galloping Diagonal Test: similar to GALPAT (Van de Goor 1991), but it moves diagonally checking both column and row decoders simultaneously. Its complex- ity is O.n 3 2 /.  Walking Pattern: similar to GALPAT except that the test cell is read once and then all other cells are read. Its complexity is O.2n 2 /. All these tests have two commondrawbacks: (i) the complexity is in generaltoo high as it is not linear with the number of memory cells, and (ii) the fault coverage is in general low as they to not systematically try to address specific fault models. For these two reasons these tests have been abandoned and nowadays common practice is to resort to a well-known category of test algorithms known as march tests. The idea of march tests is to construct a number of operation sequences and to perform each sequence on all memory cells, one after the other, before performing the next sequence in the test. A march test is therefore defined as a sequence of march elements, where a march element is a sequence of memory operations per- formed sequentially on all memory cells. In a march element, the way one proceeds from one cell to the next is specified by the address order, which can be increas- ing (denoted by *) or decreasing (denoted by +). The * address order has to be the exactly opposite of the + address order. For some march elements, the address order can be chosen arbitrarily as increasing or decreasing and denoted by the m symbol. In a march element, it is possible to perform a write 0 (w 0 ), write 1 (w 1 ), read 0 (r 0 ), and read 1 (r 1 ) operation. The 0 and 1 after the read operations represent the expected values of the read. By arranging a number of march elements one after the other, a march test is constructed. Among all published march tests, a very interesting march algorithm able to cover all static, dynamic, and linked FFMs proposed in the pervious sections of this chapter is the March AB (Bosio et al. 2008) reported in Eq.6.8. m .w 1 / + .r 1 w 0 r 0 w 0 r 0 / + .r 0 w 1 r 1 w 1 r 1 / (6.8) 6 Models in Memory Testing 181 * .r 1 w 0 r 0 w 0 r 0 / * .r 0 w 1 r 1 w 1 r 1 / m .r 0 / March tests are a preferred method for RAM testing either by means of external testers or through built in self test (BIST) solutions. Their linear complexity, regu- larity, and symmetry are the reason for this preference. However, tests for NPSFs (see Section 6.4.5) cannot be performed by march tests (Mazumder et al. 1996), since the base cell needs to be addressed differently from the cells in the deleted neighbor, thus requiring test algorithms with higher complexity difficult to imple- ment in embedded test environments. 6.5.1 Generation of March Tests The generation of a march test begins with the analysis of a set of target FPs used to identify so-called detection conditions providing the minimum requirements a march test has to achieve in order to detect the target faulty behaviors. Detection conditions can be then combined together to provide a complete march test. As an example, starting with the following FP <0;w 1 =0= > modeling a TF 1 transition fault, it is easy to derive that any march test containing the following conditions: m .:::w 0 :::/ m .:::w 1 :::/ m .:::r 1 :::/, is able to detect the target faulty behavior. Multiple detection conditions needed to detect a number of different FPs have to be combined together to generate a single march test to fully test the memory for all targeted faulty behaviors. The automatic generation of march test is a deeply studied and analyzed problem and several generation algorithms are available in the literature: Smit et al. (1994), Zarrineh et al. (1998), Wu et al. (2000), Zarrineh et al. (2001), Cheng et al. (2002), Benso et al. (2002), Al-Harabi et al. (2003), Niggemeyer et al. (2004), Benso et al. (2005, 2006a,b, 2008). 6.6 From Fault-Based to Defect-Based Memory Testing: Trends and Challenges Functional tests and functional fault models proved to be very helpful in generating functional test algorithms independentof the target technology and able to guarantee high fault coverage and therefore high quality in memory products. Unfortunately, as technology continuously scales down, and we fully enter the VDSM era, the sensitivity of memories to physical defects is strongly increasing. This turns into the continuous identification and definition of new dynamic faulty behaviors (see Section 6.4.4) to model the effect of new memory defects. [...]... significant reduction in test power can be obtained However, power-driven stitching of the scan cells may result in longer interconnections between the scan cells and congestion issues during scan routing To solve these problems, physical design constraints can be included in the reordering algorithm (Bonhomme et al 2003) 7.5.1.3 Logic Insertion in Scan Chain This technique consists in inserting logic elements... so as to minimize the occurrence of transitions in the scan chains (and hence in the combinational logic) during shift operations Adding logic elements in the scan chains transforms the logic values that need to be shifted in By doing this intelligently, it is possible to transform the scan vectors so that they contain fewer transitions Although efficient to reduce shift power (in both combinational... found in Girard et al (2007) 7.5.1.1 Gated Scan Cells The combinational logic toggling that happens during scan shifting can be eliminated (or reduced) by incorporating a blocking circuitry at all (or some) outputs of the scan flip-flops Although there exists various ways of implementing the blocking logic (muxes, transmission gates, etc.), a typical solution consists in adding a NOR gate as a blocking... Institut f¨ r Technische Informatik, Universit¨ t Stuttgart, Pfaffenwaldring 47, u a D-70569 Stuttgart, Germany H.-J Wunderlich (ed.), Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault, Frontiers in Electronic Testing 43, DOI 10.1007/978-90-481-3282-9 7, c Springer Science+Business Media B.V 2010 187 188 P Girard and H.-J Wunderlich The power issues are severe in. .. Keywords Low power test Design for test 7.1 Introduction Before 2005, the trend stopped to exponentially increase system frequency while scaling down the geometrical dimensions Instead, scaling is now mainly used for implementing highly parallel systems and increasing performance not by frequency but by parallelism The main reason of this development is found in the increased power consumption which reaches... the flip-flop also serving as blocking enable signal (Gerstend¨ rfer and Wunderlich 1999) During scan o shifting, the NOR gate can hence prevent data in the scan cells from propagating 202 P Girard and H.-J Wunderlich to the combinational logic Obviously, this technique is very effective in reducing shift power However, it induces design overheads (area and functional timing) and timing closure issues... following the system clock rising or falling edge Consequently, the instantaneous power dissipated in the circuit after the application of a test vector Vk can be expressed by: Pinst Vk / D EV k =tsmall (7.6) The peak power corresponds to the highest value of instantaneous power measured during test It can be expressed in terms of the highest energy consumed during a small instant of time during the... 1999) The main objective of these solutions is to reduce heat dissipation during testing, which is achieved by reducing switching activity without increasing test time Energy is another important dissipation parameter and represents the total switching activity generated during application of the complete test sequence Beside issues as those described in Section 7.3, an energy increased during BIST has... Trans Comput C-29(6):419–429 6 Models in Memory Testing 185 Thatte SM, Abraham JA (Jun 1977) Testing of semiconductor random access memories In Proceedings of the international fault-tolerant computing symposium, pp 81–87 van de Goor AJ, Verruijt CA (Mar 1990) An overview of deterministic functional RAM chip testing ACM Comput Surv 22(1): 5–33 van de Goor AJ (1991) Testing semiconductor memories, theory... circuit’s behaviour and result in yield loss The classical workaround in industry consists in partitioning and scheduling the test (Zorian 1993), reducing the test frequency or even both These measures will increase test time and incur additional costs, and the reduced test speed makes it difficult to detect delay faults as described in the previous chapters Power considerations during test are motivated by . involve a single memory location where all FPs are sequentially applied. Table 6.3 reports the list of realistic single-cell linked faults.  2-coupling linked faults: 2-coupling linked faults involve. while scaling down the geometrical dimensions. Instead, scaling is now mainly used for implementing highly parallel systems and increasing performance not by fre- quency but by parallelism. The main. Pfaffenwaldring 47, D-70569 Stuttgart, Germany H J. Wunderlich (ed.), Models in Hardware Testing: Lecture Notes of the Forum in Honor of Christian Landrault, Frontiers in Electronic Testing 43, DOI