electronics Article The Three-Carrier Quasi Switched Boost Inverter Control Technique Article The Three-Carrier Quasi Switched Boost Inverter Thanh-Hai Quach , Xuan-Vinh Le and Viet-Anh Truong 1, * Control Technique Thanh-Hai Quach , Faculty of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology and Education, Ho Chi Minh City 71300, Vietnam; haiqt@hcmute.edu.vn Xuan-Vinh Le and Viet-Anh Truong 1,* Faculty of Technology, Dong Nai Technology University, Bien Hoa 76000, Vietnam; lexuanvinh@dntu.edu.vn * Correspondence: anhtv@hcmute.edu.vn; Tel.: +84-09-1311-7659 Citation: Quach, T.-H.; Le, X.-V.; Truong, V.-A The Three-Carrier Citation: Quach, T.-H.; Le, X.-V.; Quasi Switched Boost Inverter Trương, V.-A The Three-Carrier Control Technique Electronics 2021, Quasi Switched Boost Inverter 10, 2019 https://doi.org/10.3390/ Control Technique Electronics 2021, electronics10162019 10, x https://doi.org/10.3390/xxxxx Academic Editor: Enrique Academic Editor: Enrique RomeroRomero-Cadaval Cadaval Received: 12 June 2021 Received: 12 June 2021 Accepted: 17 August 2021 Accepted: 17 August 2021 Published: 20 August 2021 Published: 20 August 2021 Faculty of Electrical and Electronics Engineering, Ho Chi Minh City University of Technology and Education, Ho Chi Minh City 71300,modulation Vietnam; haiqt@hcmute.edu.vn This paper presents a carrier technique to control the three-phase, two-level Abstract: Faculty of Technology, Dong Nai Technology University, Dong Nai 76000, Vietnam; quasi switched boost inverter This PWM algorithm uses three carrier waves, the first of which is for lexuanvinh@dntu.edu.vn the inverter while the others are for the booster The boost factor depends on the short circuit interval * Correspondence: anhtv@hcmute.edu.vn; Tel.: +84-09-1311-7659 on the DC/DC booster and the inverter When the short circuit interval on the DC boost is twice that on the inverter, the modulation be enlarged The new analyzed, calculated, Abstract: This paper presents aindex carriercan modulation technique toalgorithm control theisthree-phase, two-level simulated, and tested The analysis and calculation results show that the proposed technique canis quasi switched boost inverter This PWM algorithm uses three carrier waves, the first of which reduce the voltage on the DC link capacitor compared to a conventional approach It can reach 22.16% for the inverter while the others are for the booster The boost factor depends on the short circuit when theon ratio the DC sourceand voltage to the effective reference voltage is 0.5.onThe interval the of DC/DC booster the inverter When the short circuit interval themodulation DC boost is index can extend to 29% under these conditions and the current ripple in the boost inductor can be twice that on the inverter, the modulation index can be enlarged The new algorithm is analyzed, reduced by 4.8% The simulation and experimental results also show similarities, thereby confirming calculated, simulated, and tested The analysis and calculation results show that the proposed techthe analysis and calculation nique can reduce the voltage on the DC link capacitor compared to a conventional approach It can reach 22.16% when the ratio of the DC source voltage to the effective reference voltage is 0.5 The Keywords: DC/DC boost; carrier PWM; direct boost inverter; three-carrier; QSBI modulation index can extend to 29% under these conditions and the current ripple in the boost inductor can be reduced by 4.8% The simulation and experimental results also show similarities, thereby confirming the analysis and calculation Introduction Keywords: DC/DC boost; carrier PWM; direct boost inverter; three-carrier; QSBI Single-stage direct boost inverters are widely used in electrical systems such as wind power, solar cells (PV), UPS, and electric vehicles [1–4] There are two types of single-stage direct boost inverters: the Z source inverter (ZSI) [5,6] (Figure 1) and the quasi switched boost inverter (QSBI) [7,8] (Figure 2) Introduction Both inverter configurations overcome the problem of short circuit on the switches [9] Single-stage inverters are widely in electrical systems suchand as wind In addition, QSBIsdirect have boost advantages over ZSIs due used to their reduced size, weight, low power, solar cells (PV), UPS, and electric vehicles [1–4] There are two types of singlepower losses [10] Because the QSBI adds a controllable switch for DC/DC boost, the stageuses direct boost inverters: source inverter (ZSI) of [5,6] andgives the more quasi QSBI more IGBT than ZSIthe [11].Z However, the addition the(Figure S switch1)also switched boost inverter (QSBI) [7,8] (Figure 2) control solutions Publisher’s Note: MDPI stays neutral Publisher’s Note: MDPI stays neuwith regard to jurisdictional claims in tral with regard to jurisdictional published maps and institutional affilclaims in published maps and instituiations tional affiliations Load Copyright: 2021byby authors Copyright: © 2021 thethe authors LiLicensee MDPI, Basel, Basel, Switzerland Switzerland censee MDPI, This Thisarticle article isis an an open open access access article distributed under the the terms and distributed under terms and conconditions of the Creative Commons ditions of the Creative Commons AtAttribution (CC BY) license (https:// tribution (CC BY) license (http://creacreativecommons.org/licenses/by/ tivecommons.org/licenses/by/4.0/) Figure1.1.Schematic Schematicof ofZSI ZSI Figure 4.0/) Electronics 2021, 10, 2019 https://doi.org/10.3390/electronics10162019 https://www.mdpi.com/journal/electronics Electronics 2021, 10, 2019 Electronics 2021, 10, x FOR PEER REVIEW of 15 of 16 a a b c b c Figure2.2.Schematic SchematicofofQSBI QSBI Figure The papers [12–15] presentedovercome PWM control to short enhance the continuous input Both inverter configurations the strategies problem of circuit on the switches current for QSBIs In [12], a PWM technique QBSI was employed [9] In addition, QSBIs have advantages overapplying ZSIs dueintosingle-phase their reduced size, weight, and to obtain a higher modulation index The PWM method in [13] controls the input inductor low power losses [10] Because the QSBI adds a controllable switch for DC/DC boost, the current ripple turning additional switch at a different of the shoot-through QSBI uses moreby IGBT thanon ZSIthe [11] However, the addition of thetime S switch also gives more state so that a low inductor current ripple and a high modulation index are achieved control solutions for aThe QSBI A maximum boost PWM control technique is used in [14]the with an improved papers [12–15] presented PWM control strategies to enhance continuous involtage gain of QSBI by modifying the shoot-through (ST) control signal A PWM with put current for QSBIs In [12], a PWM technique applying in single-phase QBSI was em-a low modulation index and a large ST duty cycle operation in the buck mode was shown ployed to obtain a higher modulation index The PWM method in [13] controls the input in [15] As a result of using a low modulation index at a high boost factor for the buck inductor current ripple by turning on the additional switch at a different time of the shootmode operation, the QSBI has a lower efficiency and a higher current distortion The through state so that a low inductor current ripple and a high modulation index are disadvantage of QSBIs are the low modulation index (m), the high voltage on the DC link achieved for a QSBI A maximum boost PWM control technique is used in [14] with an capacitor, and the high input current ripple [15] Therefore, it is necessary to propose an improved voltage gain of QSBI by modifying the shoot-through (ST) control signal A improved PWM technique to increase the modulation index (m), reduce the voltage across PWM with a low modulation index and a large ST duty cycle operation in the buck mode the capacitor, and reduce the current ripple The content of this paper will consist of four was shown in [15] As a result of using a low modulation index at a high boost factor for main parts: an analysis of QSBI in Section 2; the QSBI control technique will be analyzed the buck mode operation, the QSBI has a lower efficiency and a higher current distortion to propose a control algorithm to reduce current ripple and reduce the voltage of the DC The disadvantage of QSBIs are the low modulation index (m), the high voltage on the DC link in Section 3; Section presents the simulation and experimental results; and Part will link capacitor, and the high input current ripple [15] Therefore, it is necessary to propose generalize the conclusions and discussions an improved PWM PWM technique to increase theon modulation (m),carriers reduce for thereducing voltage The improved technique is based using moreindex than two across the capacitor, and reduce the current ripple The content of this paper will consist the current ripple through the booster inductor and the stress voltage on the DC link of four main parts: an analysis of QSBI in Section 2; the QSBI control technique will be analyzed to propose a control algorithm to reduce current ripple and reduce the voltage Three-Phase, Two-Level QSBI of theThe DC link in Sectiontwo-level 3; Sectionquasi presents the simulation and experimental results; and three-phase, switched boost inverter (3P2LQSBI) consists of a Part will generalize the conclusions and discussions booster circuit combined with a voltage source inverter (VSI) in Figure The 3P2LQSBI The improved PWM technique is based on using more than reducing components include VS source, an inductor (L), a capacitor (C),two twocarriers diodes for (D1, D2), six the current ripple through the booster inductor and the stress voltage on the DC inverter IGBT switches (denoted SxP, SxN where x is a, b, c), and an IGBT switchlink S in the boost DC–DC circuit The output load phase voltage is ua , ub , and uc Three-Phase, −−→ Two-Level QSBI Let Vre f = (v a , vb , vc ) be a desired voltage vector in the dq coordinate, with angle α, The three-phase, two-level quasi switched boost inverter (3P2LQSBI) consists of a −−→ booster combined through with a voltage source as inverter in Figure The 3P2LQSBI then Vrecircuit state vectors shown(VSI) in Figure and2.calculated using f is represented components Formula (1) include VS source, an inductor (L), a capacitor (C), two diodes (D1, D2), six → → an IGBT switch S in the −−→ SxP,→SxN where inverter IGBT switches (denoted x is → a, b, c), and Vre f = T0 V + T1 V + T2 V + T7 V (1) boost DC–DC circuit The output load phase voltage is ua, ub, and uc → → beVa desired voltage vector in the dq coordinate, with angle α, , Let In Table=1, the, vectors and V that are located at the center of the space vector → as shown → then is represented through state vectors in Figure and calculated using hexagon are zero vectors In the vector state V or V , the outputs a, b, and c are connected Formula (1) through N or P [8,9] Therefore, the VPN voltage does not affect the load at this time, so it is possible to short-circuit P–N L There are three (1) = Tto store V + Tthe V energy + T Vin+the T inductor V main operation modes in the 3P2LQSBI circuit: short-circuit for the booster (SB), non-short Electronics 2021, 10, x FOR PEER REVIEW of 16 Electronics 2021, 10, 2019 of 15 Electronics 2021, 10, x FOR PEER REVIEW of 16 circuit (NST), and short-circuit on the inverter side (ST) Figure shows the operation modes of 3P2LQSBI Figure Space Vector for three-phase, two-level inverter In Table 1, the vectors V and V that are located at the center of the space vector hexagon are zero vectors In the vector state V or V , the outputs a, b, and c are connected through N or P [8,9] Therefore, the VPN voltage does not affect the load at this time, so it is possible to short-circuit P–N to store the energy in the inductor L There are three main operation modes in for thethree-phase, 3P2LQSBI circuit: short-circuit for the booster (SB), non-short cirFigure Figure 3 Space SpaceVector Vector for three-phase, two-level inverter cuit (NST), and short-circuit on the inverter side (ST) Figure shows the operation modes of 3P2LQSBI Table State of1,space vector V and V that are located at the center of the space vector In1 Table the vectors hexagon are zero vectors In the vector state V or V , the outputs a, b, and c are connected Value Switch On Note Table 1.Vector State of space vector through N→or P [8,9] Therefore, the VPN voltage does not affect the load at this time, so it 1.0.0 , Switch SbNinductor , ScN On L There Active vectormain Note is possibleVto1Vector short-circuit P–N to storeValue the energy SinaPthe are three → 1.1.0 S , S , S Active vector operation modes non-short Active vector cir1.0.0short-circuit aP S for cN, Sbooster (SB), V V in the 3P2LQSBI circuit: bP, Sthe → cuit (NST),VandVshort-circuit on the inverter side (ST) Figure shows the operation modes , S , S S Active vector 1.1.0 0.1.0 S , S , S Active vector aN bP cN → of 3P2LQSBI , S , S S Active vector 0.1.0 0.1.1 SaN , SbP , ScP Active vector V4 V → S , S , S 0.1.1 Active vector V 0.0.1 SaN , SbN , ScP Active vector V space vector Table State → of V S , S , S 0.0.1 Active vector 1.0.1 SaP , SbN , ScP Active vector V6 S , S , S 1.0.1 Active vector →Vector V Note 1.1.1 Value SaPSwitch , SbP , ScPOn Zero vector V7 1.1.1 Zero vector → VV SS , S, S , ,SS Active vector 1.0.0 0.0.0 SaN , SbN , ScN Zero vector V0 , S , S S Zero vector 0.0.0 V S ,S ,S Active vector 1.1.0 V + + - V V V V V V - 0.1.0 - 0.1.1+ 0.0.1 1.0.1 1.1.1 0.0.0 - + S S S S S S ,S ,S ,S ,S ,S ,S ,S ,S ,S ,S ,S ,S + + Active vector Active vector Active vector Active vector Zero vector Zero vector - Figure Figure4.4.The Theoperation operationmodes modesof of3P2LQSBI: 3P2LQSBI:(a) (a) short short circuit circuit for for booster booster mode, mode, (b) (b) non-short non-short circuit mode,and and(c) (c)short shortcircuit circuitinininverter invertermode mode(shoot-through (shoot-throughmode) mode) mode, 2.1 2.1.Short ShortCircuit Circuitfor forBooster BoosterMode Mode Figure 4a shows the short mode, the switch S Figure 4a shows the shortcircuit circuiton onthe thebooster boostermode mode(SB) (SB).InInthis this mode, the switch turns on, charging the inductor L The voltage across the inductor is: S turns on, charging the inductor L The voltage across the inductor is: Figure The operation modes of 3P2LQSBI: VL (a) = short L didtL circuit = VS for booster mode, (b) non-short circuit (2) mode, and (c) short circuit in inverter mode (shoot-through mode) S=1 2.1 Short Circuit for Booster Mode Figure 4a shows the short circuit on the booster mode (SB) In this mode, the switch S turns on, charging the inductor L The voltage across the inductor is: Electronics 2021, 10, 2019 of 15 Diode D2 turns on, so the VSI operates with a voltage supply to the capacitor C The state of the six switches on the inverter side is like in a normal VSI, so that: VC = VPN (3) SxN = − SxP m.VPN = 2uˆ where m is the modulation index of the inverter and uˆ is the peak amplitude of the phase voltage fundamental 2.2 None Short Circuit Mode (NST) In this mode (Figure 4), the switch S is off and two diodes (D1 , D2 ) are turned on The energy from the source (VS ) and inductor (L) charges capacitor C and supplies the power to the VSI VC = VS + VL = VPN (4) S=0 SxN = − SxP where phase voltage is as Equation (3) 2.3 Short Circuit in Inverter Mode (ST) → → This mode corresponds to the moment when zero vectors V orc V are active At this time, all six switches of the VSI are on so that P to N is short-circuited and the energy from the source is charged into the inductor di VL = L dtL = VS SxN = SxP = S=0 (5) Combine Equations (3)–(6) to get: ( S VC = T −T.V tS −tST m.VC = 2uˆ (6) where T is the carrier period, tS is the ON time of switch S, and tST is the short circuit time on the VSI 2.4 The Two Carrier Technique for QSBI A QSBI controlled by two carrier techniques is presented in [16,17] This technique uses two triangle carriers, one for the inverter and the other for the booster They are 90◦ phase shift triangle carriers Because the tS and tST are the same as shown in Figure 5, the duty cycle on the DC–DC boost and the inverter are the same too, and if the offset function is the third harmonic component, they have the same values as in Formula (7): √ ! tS tST 2dS = = = 2dST = − m (7) T T So that stress across the DC link is given by: VPN = VC = VS 1−4 − √ m (8) Electronics 2021, 10, 2019 of 15 Then, the ripple of input current is calculated as: √ ! − m T V t V ∆i L = S ST = S L L Electronics 2021, 10, x FOR PEER REVIEW of (9) 16 Under this technique, the VSI’s switches have to switch more because, besides the inverter function, they also undertake the boost 1function √3 The duty cycle for the inverter (9) = short-circuit − boost is large It equals half of∆ the=required ratio, so the modulation index leads to a larger DC link voltage Figure Figure5.5.The Theprinciple principleof ofthe thetwo twocarrier carriertechnique technique The Proposed Algorithms Under this technique, the VSI’s switches have to switch more because, besides the Setfunction, the duty they cyclealso of the signal control for the switchThe (S) turn as dfor shootinverter undertake the boost function dutyon cycle thefor inverter s and through in theItVSI as dST proposed technique reduces theso inverter (dST ) dutyindex cycle boost is large equals halfThe of the required short-circuit ratio, the modulation and increases the modulation index, lowering the voltage of the DC-link capacitor (V leads to a larger DC link voltage C ) In one cycle, there are two S turn-ons and four short-circuits in the VSI Per carrier period, two S turn-ons and four short-circuits in the VSI This is the same as when using 3.there Theare Proposed Algorithms threeSet triangle carriers, two forsignal the VSI and one for the booster, where each phase the duty cycle of the control for the switch (S) turn on as ds waver and forisshootshifted by α angle where α = π/3 The inverter carrier is CrI, while the booster carriers are through in the VSI as dST The proposed technique reduces the inverter (dST) duty cycle and CrB1 and CrB2 increases the modulation index, lowering the voltage of the DC-link capacitor (VC) In one Figure shows that when minimizing the ripple of the input current, the charging cycle, there are two S turn-ons and four short-circuits in the VSI Per carrier period, there time with the S switch closed (tS /4) and charging time with the inverter switches closed are two S turn-ons and four short-circuits in the VSI This is the same as when using three (tST /2) should be the same, so that: triangle carriers, two for the VSI and one for the booster, where each waver is phase ts = 2tst (10) shifted by α angle where α = π/3 The inverter carrier is CrI, while the booster carriers are CrB1 So andwhen CrB2.the inverter control voltages are v av , vbv , and vcv : Figure shows that when minimizing the ripple of the input current, the charging v = v av a + votime f f set with the inverter switches closed time with the S switch closed (tS/4) and charging v = v + v (11) b o f f set (tST/2) should be the same, so that: bv vcv = vc + vo f f set (10) =2 Additionally, the offset function is the third harmonic component as in (12) [16]: So when the inverter control voltages are , , and : vo f f set = 0.5 − max(v= a , vb ,+vc ) + min( v a , vb , vc ) = + = + (12) (11) Additionally, the offset function is the third harmonic component as in (12) [16]: = 0.5 − where x = a, b, c and: max , , + , , (12) Electronics 2021, 10, x FOR PEER REVIEW Electronics 2021, 10, 2019 of 16 of 15 = + 12 m2 v a = sin(ωt) + 2 11 vb == m2 sin ωt −−2π ++ 2 v = m sin ωt − 4π + c 34 21 = − + The principle of the improved technique is shown in Figure where x = a, b, c and: (13) (13) Figure Figure6 6.The Theprinciple principleof ofthe theimproved improvedtechnique technique Figure shows thatimproved in every technique carrier cycle there are four instances of charging the The principle of the is shown in Figure inductance switch S and carrier two instances of charging switches Figure 6through shows that in every cycle there are four through instancesthe of VSI charging the Therefore: inductance through switch S and two instances of charging through the VSI switches tS = 4(t2 − t1 ) = 4dST T Therefore: (14) tST = 2(t4 − t3 ) = 2dST T =4 =4 − (14) Additionally, (6) becomes: =2 =2 − ( VS VS Additionally, (6) becomes: VC = 1−4dS −2dST = 1−6dST (15) mVC = 2uˆ = = (15) 1−4 −2 1−6 √ With uˆ = 2urms being the amplitude-phase = voltage So the DC link voltage is: = √2 being the amplitude-phaseVvoltage So the DC link voltage is: S VPN = VC = (16) − 6.dST = = (16) − at Figure gives: Applying the offset function in (12) and looking With √ gives: Applying the offset function in (12) and looking at Figure m = dST (17) (v av )min = (vbv )min = (vcv )min = 1− √3 (17) = = = − = We then combine (15)–(17) with (18) to get: We then combine (15)–(17) with (18) to get: VS 2uˆ √ = (18) (18) 1.5m − = m 1.5 √3 − Therefore, the modulation index will change change according according to to the the supply supply voltage and Therefore, the modulation index will voltage V VSS and reference RMS voltage (u ) as in (19): rms reference RMS voltage (urms ) as in (19): √ m= √ 6− VS urms (19) Electronics 2021, 10, x FOR PEER REVIEW of 16 Electronics 2021, 10, 2019 = 4√2 3√6 − of 15 (19) S Setk kasasthe theratio ratioofofDC DCsources sources(V (VS)S )and andreference referenceRMS RMSoutput outputvoltage, voltage, k== uVrms Set Compared with conventional techniques [16], the modulation index of the proposed Compared conventional techniques [16], algorithm with increases the ∆m value, calculated as:the modulation index of the proposed algorithm increases the Δm value, calculated as: √ √ 4√2 22√22 − ∆m = (m)3−carrier − (m)2−carrier = √ (20) ∆ = − = − k − 2√6 − k (20) 3√6 − 2√6 − The Thepercentage percentageofofthe themodulation modulationindex indexincreases increasesΔm% ∆m%asasinin(21): (21): ∆ 2√6 √ − − (21) 100% = ∆ % = (m) − k 100% ∆m 3−carrier − ( m )2−carrier 2√2 √ ∆m% = 100% = 100% (21) (m) carrier 2 Figure shows the ability to2−increase the modulation index (m) with the ratio (k) FigureFigure shows that thethe effect of increasing modulation index decreases theratio k ratio shows ability to increasethe the modulation index (m) withasthe (k) increases The efficiency increase in the modulation index of the technique corresponds to Figure shows that the effect of increasing the modulation index decreases as the k ratio 2.2 For example, with power supply VS =technique 55 V, referent output the ratio 0.5The efficiency = increases increase in the modulation index of the corresponds VS to the ratio < V, k =meaning with power supply are VS =used 55 V,and referent k = For 0.5 example, if the proposed algorithms the voltage urms =0.5110 urms < 2.2 output voltage urms 110reduced V, meaning k = 0.5 if the proposed are used and modulation index can= be by 29% compared with thealgorithms method used in [16] the modulation index can be reduced by 29% compared with the method used in [16] Compared to the two carrier technique, the voltage across the capacitor (C) will decrease Compared with ∆ : to the two carrier technique, the voltage across the capacitor (C) will decrease with ∆Vc: ∆ ∆m ∆ = = (VC )2−carrier − − (VC )3−carrier = (22) (22) ∆Vc = 22uˆ +∆m ∆ ) m (m + Figure Figure7.7.The Therelationship relationshipbetween betweenΔm% ∆m%and andk.k The Thecharacteristic characteristicofofreducing reducingthe thestress stressvoltage voltagepercentage, percentage,asasseen seeninin(23), (23),isisshown shown ininFigure Figure8:8: ∆ ∆ − ∆Vc % = (VC )2−carrier − (VC )3−carrier 100% = ∆m 100% %= 100% = 100% Vc +∆∆m) (VC )2−carrier (m + (23) (23) ΔVC% 25 Electronics 2021, 2019 PEER REVIEW Electronics 2021, 10,10, x FOR 20 of8 of 16 15 15 ΔVC% 25 10 20 15 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 k 10 Figure The relationship between ΔVC% and k Figure shows that the reducing effect (of the voltage on the DC link) decreases in the k range from 0.5 to 2.2 When applying the proposed algorithm at k = 0.5, the DC link k 1.1 compared 1.3 1.5 to 1.7 conventional 1.9 2.1 2.3 techniques With (19) and f = 1/T, the voltage is0.5 less0.7 than0.922% ripple of the input current can be calculated using Formula (24): Figure The relationship between % and Figure 8 The relationship between ΔV∆V C%Cand k k √3 √3 4√2 ∆that =the − = (of −voltage (24) Figure shows reducing effect the the DC link) decreases Figure shows that the reducing effect (of the onon the DC link) decreases inin 4 3√6 2voltage − at k = 0.5, the DC link the k range from 0.5 to 2.2 When applying the proposed algorithm the k range from 0.5 to 2.2 When applying the proposed algorithm at k = 0.5, the DC link voltage less than compared to conventional techniques With (19) and 1/T, the From Figure 6,22% it22% is compared easy to seetothat the input current frequency with thef proposed voltage is is less than conventional techniques With (19) and =f = 1/T, the ripple of the input current can be calculated using Formula (24): technique is 1.5 times higher than its frequency with the application of conventional techripple of the input current can be calculated using Formula (24): nology Therefore, for the same input current frequency, the of the two! √ frequency √ √ carrier 1 4√2 √3 √3 carrier technique must∆be = 1.5 proposed method −higher in the In thiscase, the current V times S 1− =V (24) √− m T= −4 3√6 ∆IL = S 2− (24) ripple of the three-carrier technology technology by L 44 is smallerf than L 22 that 4of conventional 6−k the value ∆ The ∆ to %see is calculated usingcurrent Formula (25) and with represented by the FromofFigure 6, itvalue is easy that the input frequency the proposed graph in Figure From Figure 6,higher it is easy toits seefrequency that the input current frequency with the proposed technique is 1.5 times than with the application of conventional techtechnique is 1.5 for times than current its frequency withthe thecarrier application nology Therefore, the higher same input frequency, frequency of the two3√6 √6 of conventional − − technology Therefore, for the same input current frequency, the carrier frequency of the carrier technique must be 1.5 times higher in the proposed method In this case, the current 3√6 − 2√6 − ∆ − ∆ ∆ of % the = three-carrier 100% =than (25) two-carrier technique must be 1.5 times higher in the proposed method.technology In100% this case, the ripple technology is smaller that of conventional by ∆ √6 thevalue three-carrier smaller than conventional technology − that thecurrent value ripple of ∆ ofThe ∆ % istechnology calculatedisusing Formula (25)ofand represented by the 2√6 − by the graph in value Figureof9.∆IL The value ∆IL % is calculated using Formula (25) and represented by theFigure graph in Figurethe reduction characteristic of the input current ripple at the same shows 3√6 √6 √ frequency when applying the conventional and proposed√technique − − 3√6 −√ 2√6√−6 ∆ − ∆ − − When the reference voltage is 110 Vrms, the DC source voltage (V ) kis) 100% 55 V, 110(25) V, ∆ %= 100% = (∆IL )2−carrier − (∆IL )3−carrier (3 6− k ) (2 6S− ∆ √ 100%of=the voltage√6 = 100% (25) L %respectively and 165∆IV, The calculation results across the capacitor, the −1 − √ (∆IL )2−carrier 2√6 − − k percentage reduction in the capacitor voltage, and the current ripple compared with the ( ) conventional technique are presented in Table Figure shows the reduction characteristic of the input current ripple at the same frequency when applying the conventional and proposed technique ΔILWhen % 25 the reference voltage is 110 Vrms, the DC source voltage (VS) is 55 V, 110 V, and 165 V, respectively The calculation results of the voltage across the capacitor, the 20 reduction in the capacitor voltage, and the current ripple compared with the percentage conventional technique are presented in Table 15 ΔIL% 25 10 20 15 10 k 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 Figure 9 The relationship between ΔI∆I L% and k Figure The relationship between L % and k Figure shows the reduction characteristic of the input current ripple at the same frequency technique k when applying the conventional and proposed 0.5 the 0.7 reference 0.9 1.1 voltage 1.3 1.5 is1.7 2.1 the 2.3DC source voltage (VS ) is 55 V, 110 V, When 110 1.9 Vrms, and 165 V, respectively The calculation results of the voltage across the capacitor, the Figure The relationship between ΔIL% and k Electronics 2021, 10, 2019 of 15 percentage reduction in the capacitor voltage, and the current ripple compared with the of 16 technique are presented in Table Electronics 2021, 10, x FOR PEER REVIEW conventional Table The calculation results of the voltage across the capacitor, the percentage reduction in the capacitor voltage, and the current ripple Table The calculation results of the voltage across the capacitor, the percentage reduction in the capacitor voltage, and the current ripple VS urms VS 55 110 55 165 110 165 110 110 110 urms 110 110 110 ∆VC ΔVC 107 79 107 79 52 52 ∆VC % ΔVC% 22.16 22.16 18.59 18.59 13.97 13.97 ∆IL % ΔIL% 3.65 3.65 7.88 7.8812.82 12.82 It is easy to see that when the output voltage is greater than the DC supply voltage, It is easy to see that when the output voltage is greater than the DC supply voltage, the capacitor voltage reduction effect is higher and can reach 22.16% On the contrary, the capacitor voltage reduction effect is higher and can reach 22.16% On the contrary, the the reducing effect of the current ripple is more effective when the ratio of the DC source reducing effect of the current ripple is more effective when the ratio of the DC source voltage the reference referencevoltage voltageisislarge large voltage and and the The proposed algorithm uses the flowchart in Figure The proposed algorithm uses the flowchart in Figure 10 10 Begin CrBi,CrI,VS,urms v = v v v = v +v = v +v = v +v 1−d or d CrBi CrBi N Si=0 Y Si=1 1−d or d CrI CrI Y N ST=0 ST=1 v CrI N Y Sx=1 S=Si, SxP=Sx|ST SxN=(1−Sa)|ST End Figure 10 Proposed algorithm flowchart Figure 10 Proposed algorithm flowchart Sx=0 Electronics 2021, 10, 2019 10 of 15 Simulation and Experimental Results The algorithm is simulated in PSIM software with parameters as shown in Table To verify the proposed technique, a simulation was performed with DC power voltages of 55 V, 110 V, and 165 V The desired output voltage is 110 Vrms and 50 Hz with a carrier frequency of 5.1 kHz with two carriers and 3.4 kHz with the proposed technique Table Component parameters No Devices Parameter Note LS -CS Load L C D1 , D2 IGBT 2.3 mH–1.2 µF 363 Ω–1 mH 4.21 mH 50 µF RHR15120 FGA25N120 Filter Three Phase Load Boost Boost Diode Figure 11 shows the simulation results with VS = 55 V From the top to the bottom of Figure 11, the first graph (Figure 11a) is the voltage of the capacitor, the second is the current in the boost inductor (Figure 11b), and the third is the inverter output voltage (Figure 11c) Red lines are with two carriers, and the blues are with the proposed algorithm It is easy to see that the capacitor voltage reduces from 483 V down to 376 V ∆VC is 107 V, a 22.15% reduction, and the input current ripple reduces from 0.569 A down to 0.550 A, a Electronics 2021, 10, x FOR PEER REVIEW 11 of 16 3.5% reduction Moreover, the average input current also decreased from 4.99 A to 3.87 A, equivalent to a 22.4% reduction These values are presented in Table Figure11 11.The The simulation results with Figure simulation results with Vs =Vs 55 =V.55 V VC(V) 500 Electronics 2021, 10, 2019 11 of 15 The same can be seen in Figures 12 and 13, with Vs being 110 V and 165 V, respectively When VS is 110 V, the voltage of the capacitor reduces to 348 V with ∆VC being 81 V (an 18.9% reduction) (Figure 12a) and the input current ripple reduces from 0.963 A down to Figure The simulation results(Figure with Vs12b) = 55 V 0.891 11 A (a 7.47% reduction) VC(V) 500 375 250 3.0 348V 429V 125 0.02s/div iL(A) t (a) on capacitor (a) The voltage 2.5 0.963A 2.0 0.891A 1.5 2.280 1.926A 1.0 50us/div (b)in boost inductor (b) The current Electronics 2021, 10, x FOR PEER REVIEW t 12 of 16 Figure12 12.The Thesimulation simulationresults resultswith withVsVs= =110 110VV Figure VC 400 300 200 321V 373V 100 2.0 1.5 0.02s/div t (a) (a) The voltage on capacitor iL 1.09A 0.949A 1.0 0.5 1.2A 1.4A (b) 50us/div t (b) The current in boost inductor Figure 13 The simulation results with Vs = 165 V Figure 13 The simulation results with Vs = 165 V With VS = 165 V, the ∆VC is 52 V (a 13% reduction) and the input current ripple reduces from 1.09 A down to 0.949 A (a 12.9% reduction) (Figure 13a,b) The FFT of the phase voltage is shown in Figure 14, with the red graph being the two-carrier and the blue graph being the proposed algorithm It is easy to see that at a frequency of 2fc , the amplitude of the harmonics with the two-carrier technique is higher than it is in the proposed algorithm This is not a problem because the proposed method has a higher modulation index 0.5 1.2A 1.4A (b) 50us/div t (b) The current in boost inductor Electronics 2021, 10, 2019 12 of 15 Figure 13 The simulation results with Vs = 165 V Figure 14 14 FFT FFTof of phase phase voltage voltage with with Vs Vs==165 165V V Figure The experiment applied the same model as the simulation conditions for easy comparison The devices used were a TMS320 F28335, a GWINSTEK GDS 1072A-U, and a GDS 1104B oscilloscope with an inductance (L) of 4.2 mH, variable 55 V, 110 V, and 165 V DC Electronics 2021, 10, x FOR PEER REVIEW 13 of power supplies, and a filter with LS = 2.3 mH and CS = 11.2 µF (Figure 15) Figure 15 Experimental devices Figure 15 Experimental devices 16 Electronics 2021, 10, 2019 13 of 15 Figure 16 shows the experimental results with a DC supply of 55 V with the proposed algorithm The top to bottom graphs are phase voltage, load current, capacitor voltage, and the current in the boost inductor, respectively The experimental results are the same as the simulation (Figure 11), once again confirming the validity of the proposed technique Figure 15 Experimental devices Figure 16 The experiment results with VS = 55 V Figure 16 The experiment results with VS = 55 V The experimental results with a DC supply of 165 V, including the phase voltage, load 14 of 16 currents, capacitor voltage, and the boost inductor (Figure 17) show a similar trend Electronics 2021, 10, x FOR PEER REVIEW Figure 17 The experimental results with VS = 165 V Figure 17 The experimental results with VS = 165 V Conclusions This paper presents a carrier modulation technique with three carriers to control the three-phase, two-level quasi switched boost inverter The three-carrier QSBI control technique has been analyzed, calculated, simulated, Electronics 2021, 10, 2019 14 of 15 Conclusions This paper presents a carrier modulation technique with three carriers to control the three-phase, two-level quasi switched boost inverter The three-carrier QSBI control technique has been analyzed, calculated, simulated, and tested The results show that the analysis and new technical recommendations are appropriate In addition, the calculation, simulation, and experimental results show that the technique is especially effective when a large voltage boost ratio is required Specifically, at the ratio of the DC source (VS ) and reference RMS output voltage (k) is equal to 0.5 Compared with the two-carrier technique, the proposed method reduces the voltage on the capacitor by 22.16%, but at k = 1.5 this figure is only 13.97% Compared with the two-carrier technique, the proposed technique helps to extend the modulation index so that it is possible to reduce the capacitor voltage For example, it shows that when the reference voltage is double the DC supply voltage, the modulation index (m) can be expanded by 29%, thus reducing the voltage of the DC link by 22.16% if we apply the three-carrier PWM technique It also shows the ability to reduce the current ripple in the boost inductor with the same switching frequency Experimentally, the reduced current ripple effect will increase if the boost coefficient reduces For example, with a 165VDC supply and 110 V reference phase voltage, compared with the two-carrier technique, the current ripple with the proposed method can be reduced by 12.9% However, it is only 3.65% at a DC supply voltage of 55 V Besides, this technique also has other advantages that needs to be studied, e.g., reducing the amplitude at the first harmonic of the carrier frequency The simulation and experiment results also show that the proposed technique can help increase the performance of QSBI (because the average input current also decreased from 4.99 A to 3.87 A, a reduction of 22.4%) Future research in this area is encouraged Author Contributions: Conceptualization, T.-H.Q.; Data curation, X.-V.L.; Resources, V.-A.T.; Writing— original draft, T.-H.Q.; Writing—review & editing, V.-A.T All authors have read and agreed to the published version of the manuscript Funding: This study was carried out by the support of laboratories C201 and C406 of Ho Chi Minh City University of Technology and Education Conflicts of Interest: The authors declare no conflict of interest Nomenclature VS VL IL ∆IL VPN uˆ urms m tS tST dS dST DC power supply Voltage on the inductor Current in the inductor Ripple of the current in the inductor DC link voltage Amplitude of the phase voltage fundamental RMS value of the phase voltage fundamental Modulation index Short circuit time on the DC–DC boost side Short circuit time on the VSI side Duty cycle when switch S is turned on Duty cycle when the VSI is shot through (V) (V) (A) (A) (V) (V) (V) (s) (s) References Sreekanth, T.; Lakshminarasamma, N.; Mishra, M.K A Single-Stage Grid-Connected High Gain Buck–Boost Inverter with Maximum Power Point Tracking IEEE Trans Energy Convers 2016, 32, 330–339 [CrossRef] Pal, A.; Basu, K A Unidirectional Single-Stage Three-Phase Soft-Switched Isolated DC–AC Converter IEEE Trans Power Electron 2018, 34, 1142–1158 [CrossRef] Serrano, D.; Ramos, R.; Alou, P.; Oliver, J.A.; Cobos, J.A Multimode Modulation with ZVS for a Single-Phase Sin-gle-Stage Inverter IEEE Trans Power Electron 2020, 35, 5319–5330 [CrossRef] Electronics 2021, 10, 2019 10 11 12 13 14 15 16 17 15 of 15 Sriramalakshmi, P.; Sreedevi, V.T Design and Implementation of a Dual DC Source-based Quasi-Switched Boost Inverter for Renewable Energy Applications IETE J Res 2020 [CrossRef] Ahmad, A.; Bussa, V.K.; Singh, R.K.; Mahanty, R Switched-Boost-Modified Z-Source Inverter Topologies With Improved Voltage Gain Capability IEEE J Emerg Sel Top Power Electron 2018, 6, 2227–2244 [CrossRef] Noroozi, N.; Zolghadri, M.R Three-Phase Quasi-Z-Source Inverter with Constant Common-Mode Voltage for Photo-voltaic Application IEEE Trans Ind Electron 2018, 65, 4790–4798 [CrossRef] Nandi, P.; Adda, R Reduction of Capacitance in Four-Switch quasi-Switched Boost Inverter using Low-frequency Ripple Damping Scheme In Proceedings of the 2020 IEEE Energy Conversion Congress and Exposition (ECCE), Detroit, MI, USA, 11–15 October 2020; pp 6285–6292 Barath, J.G.N.; Soundarrajan, A.; Stepenko, S.; Prystupa, A.; Bondarenko, O.; Padmanaban, S Interleaved Single-Phase QuasiSwitched Boost and Active Quasi-Z-Source Inverter In Proceedings of the 2020 IEEE 40th International Conference on Electronics and Nanotechnology (ELNANO), Kyiv, Ukraine, 22–24 April 2020; Institute of Electrical and Electronics Engineers (IEEE): Piscataway, NJ, USA, 2020; pp 874–878 Kumar, A.; Bao, D.; Beig, A.R Comparative Analysis of Extended SC-qSBI with EB-QZSI and EB/ASN-QZSI IEEE Access 2021, 9, 61539–61547 [CrossRef] Nguyen, M.-K.; Le, T.-V.; Park, S.-J.; Lim, Y.C A Class of Quasi-Switched Boost Inverters IEEE Trans Ind Electron 2015, 62, 1526–1536 [CrossRef] Nguyen, M.-K.; Choi, Y.-O PWM Control Scheme for Quasi-Switched-Boost Inverter to Improve Modulation Index IEEE Trans Power Electron 2018, 33, 4037–4044 [CrossRef] Gambhir, A.; Mishra, S.K.; Joshi, A A modified PWM scheme to improve performance of a single-phase ac-tive-front-end impedance source inverter IEEE Trans Ind Appl 2019, 55, 928–942 [CrossRef] Nguyen, M.-K.; Tran, T.-T.; Lim, Y.-C A family of PWM control strategies for single-phase quasi-switched-boost in-verter IEEE Trans Power Electron 2019, 34, 1458–1469 [CrossRef] Nguyen, M.-K.; Choi, Y.-O Maximum Boost Control Method for Single-Phase Quasi-Switched-Boost and Quasi-Z-Source Inverters Energies 2017, 10, 553 [CrossRef] Nag, S.S.; Mishra, S Current-Fed Switched Inverter IEEE Trans Ind Electron 2014, 61, 4680–4690 [CrossRef] Le, X.-V.; Nguyen, D.-M.; Truong, V.-A.; Quach, T.-H Algorithm to control output voltage and reduce the ripple of input current in quasi switched boost inverter Sci Technol Dev J Eng Technol 2021, 4, 999–1008 [CrossRef] Do, D.-T.; Nguyen, M.-K.; Quach, T.-H.; Tran, V.-T.; Blaabjerg, F.; Vilathgamuwa, D.M A PWM Scheme for a Fault-Tolerant Three-Level Quasi-Switched Boost T-Type Inverter IEEE J Emerg Sel Top Power Electron 2019, 8, 3029–3040 [CrossRef] ... This paper presents a carrier modulation technique with three carriers to control the three- phase, two-level quasi switched boost inverter The three- carrier QSBI control technique has been analyzed,... carriers, one for the inverter and the other for the booster They are 90◦ phase shift triangle carriers Because the tS and tST are the same as shown in Figure 5, the duty cycle on the DC–DC boost. .. one for the booster, where each waver is phase ts = 2tst (10) shifted by α angle where α = π /3 The inverter carrier is CrI, while the booster carriers are CrB1 So andwhen CrB2 .the inverter control