(Luận văn thạc sĩ hcmute) nghiên cứu bộ tăng áp dc dc tỉ số cao trong hệ thống pin mặt trời công suất vừa và nhỏ

BỘ GIÁO DỤC VÀ ĐÀO TẠO TRƯỜNG ĐẠI HỌC SƯ PHẠM KỸ THUẬT THÀNH PHỐ HỒ CHÍ MINH LUẬN VĂN THẠC SĨ LƯƠNG XUÂN TRƯỜNG NGHIÊN CỨU BỘ TĂNG ÁP DC – DC TỈ SỐ CAO TRONG HỆ THỐNG PIN MẶT TRỜI CÔNG SUẤT VỪA VÀ NHỎ NGÀNH: KỸ THUẬT ĐIỆN - 1880616 SKC 0 Tp Hồ Chí Minh, 2020 Luan van BỘ GIÁO DỤC VÀ ĐÀO TẠO TRƯỜNG ĐẠI HỌC SƯ PHẠM KỸ THUẬT THÀNH PHỐ HỒ CHÍ MINH LUẬN VĂN THẠC SĨ LƯƠNG XUÂN TRƯỜNG NGHIÊN CỨU BỘ TĂNG ÁP DC – DC TỈ SỐ CAO TRONG HỆ THỐNG PIN MẶT TRỜI CÔNG SUẤT VỪA VÀ NHỎ NGÀNH: KỸ THUẬT ĐIỆN - 1880616 (dịng 25) bảo vệ) Tp Hồ Chí Minh, tháng …/… (chữ thường, cỡ 13; ghi tháng năm Luan van BỘ GIÁO DỤC VÀ ĐÀO TẠO TRƯỜNG ĐẠI HỌC SƯ PHẠM KỸ THUẬT THÀNH PHỐ HỒ CHÍ MINH LUẬN VĂN THẠC SĨ LƯƠNG XUÂN TRƯỜNG NGHIÊN CỨU BỘ TĂNG ÁP DC – DC TỈ SỐ CAO TRONG HỆ THỐNG PIN MẶT TRỜI CÔNG SUẤT VỪA VÀ NHỎ NGÀNH: KỸ THUẬT ĐIỆN - 1880616 Hướng dẫn khoa học: PGS.TS TRƯƠNG VIỆT ANH Luan van Luan van Luan van Luan van Luan van Luan van Luan van LÝ LỊCH KHOA HỌC I LÝ LỊCH SƠ LƯỢC: Họ & tên: Lương Xuân Trường Giới tính: Nam Ngày, tháng, năm sinh: 31/10/1996 Nơi sinh: TP HCM Quê quán: Nam Định Dân tộc: Kinh Chỗ riêng địa liên lạc: 86 Lê Thị Út, Tân Đông Hiệp, Dĩ An, Bình Dương Điện thoại quan: Điện thoại nhà riêng: Fax: E-mail: xuantruongpdl@gmail.com II QUÁ TRÌNH ĐÀO TẠO: Trung học chuyên nghiệp: Hệ đào tạo: Thời gian đào tạo từ ……/…… đến ……/ Nơi học (trường, thành phố): Ngành học: Đại học: Hệ đào tạo: Chính quy Thời gian đào tạo từ 10/2014 đến 08/2018 Nơi học (trường, thành phố): Đại học Sư phạm Kĩ thuật TP HCM, TP HCM Ngành học: CNKT Điện – Điện tử Tên đồ án, luận án môn thi tốt nghiệp: Cải tiến giải thuật P&O dò điểm công suất cực đại cho pin mặt trời Ngày & nơi bảo vệ đồ án, luận án thi tốt nghiệp: 06/2018 trường Đại học Sư phạm Kĩ thuật TP HCM Người hướng dẫn: PGS TS Trương Việt Anh III Q TRÌNH CƠNG TÁC CHUN MƠN KỂ TỪ KHI TỐT NGHIỆP ĐẠI HỌC: i Luan van Table Active switches involved in the modes of the converter Mode PWM signals Turn off switch S1, S2, S3, S4 None S1, S2, S3 S4 S1, S2 S3 to S4 Figure Proposed converter (a), the operating states: (b), (c) and (d) 63 Luan van S1 S2 to S4 Figure The waveform of the gate voltages (a), the voltage and current on switches (c–f), inductors (b), and capacitors (g) This section analyzes the first mode with full activity levels Figure shows the established waveforms in the switching cycle of the converter in the first mode In this case, all of the levels operate together The control cycle of S1 is the same as S3 and the phase shifts by 180° between S2 and S4 In the first mode, there are three operating states, which are shown in Table Table The operation states of the circuit when all of the levels are active Stage Switch on Switch off Time S1, S2, S3, S4 D1, D2, D3, D4 t1 - t2 S2, S4, D1, D3 S1, S3, D2, D4 t2 - t3 S1, S3, D2, D4 S2, S4, D1, D3 t3 - t4 Result All inductors store energy Capacitor C4 discharges to the load Capacitors C1 and C3 charged, capacitor C2 discharged Capacitor C4 discharges to the load Capacitors C2 and C4 charged, capacitors C1 and C3 discharged In stage 1, from t1 to t2, the MOSFETs turn on, the diodes turn off and four inductors are magnetized by the input source (Figure 3b) Therefore, the current that is charged into the inductor linearly increases and can be calculated using the following formula (3, 4) The output capacitor (C4) supplies energy to the load 𝑖𝐿1 (𝑡) = 𝐼𝐿1 (𝑡0 ) + 𝑉𝑖𝑛 (𝑡 − 𝑡0 ) 𝐿1 and 𝑖𝐿3 (𝑡) = 𝐼𝐿3 (𝑡0 ) + 𝑉𝑖𝑛 (𝑡 − 𝑡0 ) 𝐿3 (3) 𝑖𝐿2 (𝑡) = 𝐼𝐿2 (𝑡0 ) + 𝑉𝑖𝑛 (𝑡 − 𝑡0 ) 𝐿2 and 𝑖𝐿4 (𝑡) = 𝐼𝐿4 (𝑡0 ) + 𝑉𝑖𝑛 (𝑡 − 𝑡0 ) 𝐿4 (4) State [t2 - t3]: the two switches S1 and S3 turn off while the remaining switches (S2, S4) still turn on (Figure 3c) The capacitor C1 is charged by the energy stored in L1 and the power source, similar to the C3 in level The inductor in levels and still magnetizes so that the current that passes through S2 and S4 is the sum of the inductor’s magnetized current and the capacitor’s charging current The output capacitor (C4) supplies energy to the load: 64 Luan van 𝑉𝐶1 = 𝑉𝑆1 = 𝑉𝑆3 = 𝑉𝐶3 = 𝑉𝐶2 + 𝑉𝑖𝑛 1−𝐷 𝑉𝑖𝑛 𝑉𝑖𝑛 =3 1−𝐷 1−𝐷 (5) (6) State [t3 - t1]: this state is the same as state with the status of switches and capacitors on the reverse Both capacitors C1 and C3 transfer energy to capacitors C2 and C4, respectively The output capacitor C4 still supplies the load In this state, the S1 current is only the L1’s magnetized current 𝑉𝑆2 = 𝑉𝑆4 = 𝑉𝐶2 = 𝑉𝐶4 = 𝑉𝐶3 + 𝑉𝑖𝑛 1−𝐷 (7) 𝑉𝑖𝑛 1−𝐷 (8) 𝑉𝑖𝑛 𝑉𝑖𝑛 =4 1−𝐷 1−𝐷 (9) Consequently, the voltage boost factor depends on the activity levels (N) The ideal voltage boost ratio B* can be determined by the formula (10), 𝐵∗ = 𝑉𝐶𝑜 𝑁 𝐼𝑖𝑛 = = 𝑤ℎ𝑒𝑟𝑒 𝑁 = 1, 2, 𝑁𝑚𝑎𝑥 𝑉𝑖𝑛 − 𝐷 𝐼𝑜 (10) The switch voltage stress (at the current level) is: 𝑉𝑆1 = 𝑉𝑆2 = 𝑉𝑆3 = 𝑉𝑆4 = 𝑉𝑖𝑛 1−𝐷 (11) The voltage across on the diode can be calculated based on the analysis of stage and stage 3: 𝑉𝐷1 = 𝑉𝑖𝑛 1−𝐷 𝑖𝑉𝑖𝑛 𝑘ℎ𝑖 𝑖 < 𝑁 1−𝐷 𝑉𝐷𝑖 = 𝑘ℎ𝑖 𝑖 > 𝑁 𝑉𝐷𝑖 = (12) 2.2 Power Loss Analysis The resistors RD, RL, RS can be described as the resistance of the turn-on diode, the inductor and the turned-on switch 2.2.1 Power Loss in Diode: All diodes are turned on in the (1 − 𝐷)𝑇 period with the current the same as the level current at the corresponding stage Therefore, the conductive losses on the diode can be calculated by: ∆𝑃𝐷 = 𝑁(1 − 𝐷)𝑅𝐷 𝐼𝐷2 = 𝑁𝑅𝐷 𝐼𝑜2 1−𝐷 (13) where N is the number of the activity levels and io is the load current 2.2.2 Power Loss in Inductor: The power losses in the inductors consist of two main losses: copper and core losses The sum of the two losses can be represented by a resistor The currents that pass through the inductor in all stages can be presented as the mean current on the level Therefore, the losses in the N inductors can be calculated as: ∆𝑃𝐿 = 𝑁𝑅𝐿 𝐼𝐿2 = 𝑁𝑅𝐿 𝐼𝑜2 (1 − 𝐷)2 65 Luan van (14) 2.2.3 Power Loss in the Switch: The power loss in switch S1 can be calculated similarly to the traditional boost circuit using the formula (15) ∆𝑃𝑆1 = 𝐷𝑅𝑆 𝐼𝑆1 = 𝐷𝑅𝑆 𝐼𝑜2 (1 − 𝐷)2 (15) At levels to 4, the current on the turned-on switch is also the current on the inductor in stage Consequently, ∆𝑃𝑆𝑖(𝑆1) = (2𝐷 − 1)𝑅𝑆 𝐼𝑆(𝑆1) = (2𝐷 − 1)𝑅𝑆 𝐼𝑜2 , 𝑖 = .4 (1 − 𝐷)2 (16) However, in stages and 3, during (1 − 𝐷)𝑇, the switch current is the magnetization and charge of the front level capacitor (Figure 4) Therefore, the power losses in the switches in these stages can be calculated, respectively, as: ∆𝑃𝑆𝑖(𝑆2_3) = (1 − 𝐷)𝑅𝑆 𝐼𝑆(𝑆2) = (1 − 𝐷)𝑅𝑆 4𝐼𝑜2 4𝐼𝑜2 = 𝑅𝑆 , 𝑖 = .4 (1 − 𝐷) (1 − 𝐷) (17) Consequently, the total loss in a switch (S2, S3 or S4) in a cycle is: ∆𝑃𝑆𝑖 = (3 − 2𝐷)𝑅𝑆 𝐼𝑜2 (1 − 𝐷)2 (18) 2.2.4 Power Loss in the Output Capacitor The output capacitor (C4) serves not only to store energy but also to supply it to the load The output capacitor current has two components, namely the charge and discharge currents The C4 discharge current is the load current, and the charge current is the difference between the last level and the output current Therefore, this can be calculated as (19): ∆𝑃𝐶4 = 𝐷𝑅𝐶 𝐼𝑜2 1−𝐷 (19) 2.2.5 Losses in the Level Capacitor: The level capacitors (C1 to C3) operate in stages and only Both the charge and discharge currents of them are involved in the inductor current sequence Thus, the power losses to the level capacitor can be calculated as (20) ∆𝑃𝐶𝑖 = 2𝑅𝐶 𝐼𝑜2 1−𝐷 (20) According to [19], conductive losses are low when switching frequencies below 100 kHz, which can lead to the switching losses being ignored Consequently, the total power loss in the proposed circuit can be calculated by the following: ∆𝑃 = ∆𝑃𝐿 + ∆𝑃𝑆 + ∆𝑃𝐷 + ∆𝑃𝐶 = 𝑁𝑅𝐿 𝐷 + (𝑁 − 1)(3 − 2𝐷)𝑅𝑆 𝑁𝑚𝑎𝑥 𝑅𝐷 𝐷 + 2(𝑁 − 1)𝑅𝐶 𝐼𝑜2 + 𝐼𝑜 + 𝐼 + 𝐼𝑜 (1 − 𝐷) (1 − 𝐷)2 1−𝐷 𝑜 1−𝐷 (21) 2.3 Control Technology to Minimize Power Loss In order to maximize the conversion efficiency, it is necessary to determine the correct values of N and D for minimizing the power losses defined by the formula (21) on the conditions in (22) 66 Luan van ≤ 𝑁 ≤ 𝑁𝑚𝑎𝑥 (𝑁𝜖ℕ) 0.1 ≤ 𝐷 ≤ 0.8 𝑖𝑓 𝑁 = 0.5 ≤ 𝐷 ≤ 0.8 𝑖𝑓 𝑁 > ((22) The formula (21) is rewritten as below ∆𝑃 = 𝐼𝑜2 𝑁𝑅𝐿 𝐷 + (𝑁 − 1)(3 − 2𝐷)𝑅𝑆 𝑁𝑚𝑎𝑥 𝑅𝐷 𝐷 + 2(𝑁 − 1)𝑅𝐶 + + + (1 − 𝐷) (1 − 𝐷)2 1−𝐷 1−𝐷 ((23) If set up internal resistance: 𝑟𝑜 = 𝑁𝑅𝐿 𝐷 + (𝑁 − 1)(3 − 2𝐷)𝑅𝑆 𝑁𝑚𝑎𝑥 𝑅𝐷 𝐷 + 2(𝑁 − 1)𝑅𝐶 + + + (1 − 𝐷) (1 − 𝐷)2 1−𝐷 1−𝐷 ((24) Thus: ∆𝑃 = 𝐼𝑜2 𝑟𝑜 (25) 𝑃𝑜 𝑉𝑜 ∆𝑃 = 𝐼𝑜2 𝑟𝑜 = ( ) 𝑟𝑜 = ( ) 𝑟𝑜 𝑉𝑜 𝑅𝐿𝑜𝑎𝑑 (26) Alternatively: Therefore, with the required output power Po and output voltage Vo (respectively Io and RLoad), the choice of working levels N and duty cycle D to minimize power losses is, in fact, essentially minimum internal resistance ro The efficiency of the circuit can be calculated according to equation (27) B* is the ideal voltage boost ratio in (10), and the internal resistance (ro) is zero The efficiency can be calculated by 𝜂= The real voltage boost 𝐵 = 𝑉𝑜 𝑉 𝑖𝑛 𝑃𝑜 𝑉𝑜 𝐼𝑜 𝑉𝑜 𝐼𝑜 𝑉𝑜 = = = 𝑃𝑖𝑛 𝑉𝑖𝑛 𝐼𝑖𝑛 𝑉𝑖𝑛 𝐼𝑜 𝐵 ∗ 𝑉𝑖𝑛 𝐵 ∗ (27) is set up, then 𝐵= 𝑉𝑜 𝑉 𝑖𝑛 = 𝜂𝐵 ∗ (28) The input power Pin and output voltage Vo are also calculated as follows: 𝑃𝑖𝑛 = 𝑃0 + ∆𝑃 (29) 𝑉𝑜 = 𝑉𝑖𝑛 𝐵 ∗ (𝑁, 𝐷) − 𝐼𝑜 𝑟𝑜 (30) This paper proposes using a graph method to determine N and D for minimum ΔP (or minimum internal resistance ro) The value of r0 as calculated in formula (24) with the parameters RL, RS, RD, RC is given in Table The values D and N satisfy the constraint (22) The real voltage boost B can be calculated by formula (28) for each value of N, D, and ro The load resistor RLoad can be calculated from the required output voltage and power of the DCDC converter in equation (31) We select RLoad = 250 Ohm, which is suitable for Vo from 400 V to 600 V and Po from 250 W to 1000 W 𝑅𝐿𝑜𝑎𝑑 = 𝑉𝑜2 𝑃𝑜 (31) The efficiency and boost ratio graphs according to the activity levels N and duty cycle D are indicated by the flowchart in Figure 5, and Figure shows the results of this 67 Luan van Begin Input 𝑉𝑜 𝑃𝑜 Calculate 𝑅𝐿𝑜 𝑑 (31) N=1 D = 0.1 Calculate: Equivalent resistance ro (24) Power input Pin (29) Efficiency  (27) Boost factor B (28) D = D + ΔD No D > 0.8 Yes Graph η = (N, D) B = (N, D) D = 0.5 N=N+1 N