Tuyen tap bao cao khoa hgc Hdi nghi Khoa hgc ky thuat Do ludng toan qud'c lan thfl IV Hd Ngi, 11 - 2005 ^ LJTNG DUNG THIET Bj MANG CONG KHA TRINH FPGA CUA XILINX TREN CO s d Str DUNG CdNG CU ISE FOUNDATION Phan Qud'c Thdng, Phgm Tudn Hdi, Le Trgng Nghia Hgc vien KyTfnidt Qudn Su Tdm tdt: Bdi hdo gidi t/deu mgt so cdng nghe cff bdn FPGA (Field Programmable Gate Arrays) cua Xilinx phucfng phdp trien khai thuc te'khi thiic hien bdi todn dieu khien, ndi ghep vdi mdy tinh xdy dUng chuang trinh, xdy dipig giao diin thUc tevd trien khai ifng dung hdi todn diiu khien dgng ca budc cung mgt sdket qud dgt dugc Trong bdi sit dung bo mgch Spartan3 Starter Kit de dieu khien ddng ca budc vdi md ta dugc chgn Id 7.5" budc, dien dp cdp cho dgng ca la 5V I DAT VAN DE Da cd mdt sd kfi't qua nghifin cflu vific tridn khai flng dung cdng nghfi CPLD (Complex Programmable Logic Device) thuc tifin Tuy nhifin, dd'i vdi cac flng dung phflc tap hon, cdng nghfi CPLD ddi gap phai mdt sd ban chd nhd't dinh Chi'nh vi vdy vific ldm chu cdng nghfi FPGA cQa Xilinx Id didu cdn thidt, giup cho cac nha thifi't kfi' cd them cdc giai phap tdi uu giai quydt cac bai toan flng dung phflc lap Xud'l phdt tfl thflc te dd, bai bdo mud'n di sdu nghifin cflu vd cdng nghfi FPGA cua Xilinx, lim hidu mdi trudng thiet kd ISE Foudation cung nhu vific tridn khai flng dung thuc tfi' n CONG NGHE FPGA CUA XILINX Tfl nam 1985, bang Xilinx da dd xud't mOt y tudng mdi dd la kfi't hop gifla kha nang thifi't kd cua ngudi dung cdc chip cd mdt dd tfch hgp cao, gia ma trdn cdng va rut ngdn thdi gian dua san phdm PLD {Programmable Logic Device) thi trudng Ddy la nhflng CO sd ddu tifin ddi cac thifi't bi FPGA Cho dfi'n Xilinx vdn la nha phdn phdi sd trfin todn thd gidi vd hg thifi't bi Cd'u true FPGA bao gdm cac cdng logic (Logic Cell) va cac khd'i module va cac dudng nd'i (hlnh 1) Cac dudng nd'i ddu dugc ngudi dung kidm soat, cd nghTa ngudi dung cd thd thidt kfi', lap trinh va thay ddi mach mdi cdn thie't Vdi hg FPGA kha nang lich hgp da vugt qua gidi ban 10 trifiu cdng (Hg Xilinx Virtex™- II va Virtex™- FPGA hifin dang giu ky luc) Cd hai loai FPGA co ban: Loai SRAM (Static Random Access Memory) cd thd Idp trinh lai nhidu ldn va loai OTP (One - Time Programmable) ldp trinh mdt ldn Hai loai khac d chd thuc hifin cua cdc logic cell vd ky thudt tao kfi't ndi gifla chflng thifi't bi Loai hay dflgc dung hon ca la loai SRAM, vi cd thd lap trinh duoc nhidu ldn Thuc id thi FPGA SRAM dugc nap cd^u hinh Iai mdi bat ngudn, bdi vi FPGA loai ndy thuc chd't la mdt chip nhd 779 III CONG CU ISE FOUNDATION fl»»»«^!«^-C^A CUA XILINX ISE Foudation cua Xilinx cai thifin dang ke thdi gian dua san ph^m thi trudng nhd rut ngdn dugc thdi gian thie't kfi' ISE Foudation bao gdm phdn mdm thifi't ke va cdc phan mdm bd sung khac Vific thuc hifin thifi't ke bdng cdng cu ISE Foundation gdm cdc budc nhu sau: » -» -» m " " • " " ! " * " I ' 1J^'.4-tir" m w m » » ' ~m-~.'.' » » * , •• * _»_ • • r : - - - i » - - - : _ > _ : : - _i» ;• *;;• :fc|.ii:-i:;:]:l::::l:::: -5-4 -»-{•• g - i - - - S •• -S • Nhap thidt ke Cac cfing cu hd trg dd tao mdt thifi't kd bao gdm: Nhdp ihifi't kfi' bdng so 66 hoac bang ngfin ngfl HDL, bang viec tfch hgp cac Idi IP Hinh Cau true cua FPGA Cdc cdng cu thie't kfi' bao gdm; Schematic Editor, HDL Editor State Diagram Editor, Core Generator System, PACE (Pinout and Area Constraint Editor), Architecture Wizard (DCM - Digital Clock Management MGT - Multi-Gigabit Transceiver), Xilinx System Generator for DSP Tdng hgp thidt ke Sau giai doan nhdp thifi't kd se la budc tdng hgp thifi't kd Dua trfin bd tdng hgp mdi, ISE cho phep td'i uu hod qua trinh tdng hgp thie't ke cac PLD Bd tdng hgp cd kha ndng ldi flu boa cao mdt thidt kd mdt thdi gian ngdn ISE tfch hgp cac bd tdng hop nhfl sau: Mentor Graphics Leonardo Spectrum, Exempla, Synopsys vd Synplicity SynplifylPro ABEL, AST (Xlinx Synthesis Technology) Thuc thi va nap cau hinh Vific thuc hifin thifi't kd logic kha trinh la gdn cdc chfle ndng logic dflgc tao qud trinh nhdp thifi't kd va tdng hgp chung vao tai nguyfin vdt ly cu thd Thudt ngfl "Sdp ddt vd dinh tuyen " dugc sfl dung dd md la qua trinh thuc hifin cho FPGA, cdn "Ldp dat " dugc sfl dung cho CPLD Thuc thi chi'nh la qua trinh nap cd'u hinh cho thifi't bj De thuc hifin ndi dung cd cdc cdng cu hd trg sau: FloorPlanner, Constraints Editor, Timing Driven Place & Route, Modular Design, Timing Improvent Wizard Tich hgp mflc Board Phdn mdm ISE hd trg ngudi dung Ihuc hifin thifi't kd logic lap trinh lam vific hfi thd'ng vdi mdt loat kha nang nhu bd tri, sap dat board mach kd ca board mach phflc tap, tong hgp tfn hifiu, giao tiep bus td'c dd cao, xac dinh dd rdng dai thdng vao ra, nhidu difin tfl D6 cd thd dfi dang thuc hifin cdc budc Xilinx da sfl dung nhidu cdng nghfi mdi tren FPGA nhu: - XCITE Trd khang didu khidn sd - DCM Bd quan Iy ddng hd sd thdi gian hfi thdng - EMI Bd quan Iy nhidu difin tfl trflfiing - Thdng tin ddng gdi lich hgp d mflc Board - Kifi'm tra mflc Board ISE Cac cdng nghe trfin dugc thuc hifin nhd cac gdi phdn mdm sau; - IBIS Models - STAMP Models - LMG Models - ChipScope ILA 780 Kiem tra thiet ke Phdn mdm ISE cho phep thuc hien kifim tra d tat ca cdc giai doan cua thie't kfi' bat ddu Ifl khau nhap thie't kd cho de'n tieh hgp board * Kiem tru tuili: Cdng cu kidm tra tmh cho phep ngudi thie't kc kidm tra thiet ke ngoai yfiu cau Viec kidm tra cd thd thuc hifin d mgi khia canh hoac kidm tra theo su chon lira, cho phep tim ldi qua trinh thuc thi Cdng cu kiem tra tinh cung cho phep thuc hien go rdi va phan tfch Cac cdng cu kifim Ira tinb gdm: - Constraint Editor - Delay Calculator - Trace - Timing Analyzer - Prime Time - X Power - Formality - Conformal " LEC -DRC - Chip Viewer * Kidm tra ddng: Bao gdm cac cdng cu sau - H D L Bencher'" - ModelSim XE - State Bench - HDL Siinulalion Libraries * Kiem tra mflc Board; Vific sfl dung cdng cu kidm tra mflc board nhdm dam bao viec thifi't ke dugc thuc bien diing theo du dinh va dugc tfch hgp vdi phdn cdn Iai ciia he Ihdng Cac cdng cu bao gdm: - IBIS Models - Tau - BLAST - Stamp Models - Impact IV T H U t HIEN NHIEM VU DIEU KHIEN DUNG CONG NGHE FPGA XILINX Phdn bai hao trinh bay viec flng dung cdng nghfi FPGA va phdn mdm ISE Foundation dd didu khifin ddng co budc cd ghep ndi vdi may tfnh Vific ghep nd'i vdi may tfnh ddi hdi chuong trinh phai dugc thie't ke mdt bd UART dd nhdn dfl lieu tfl may ti'nh PC Thdng Ihudng thifi't kfi' phan cflng, can sfl dung vi mach chuydn ddi mflc Max232, Max3232 UART 1640 hoac 1650 Chuong trinh dieu khien Nhiem vu dat la can thiet ke' bd UART kfi't hgp vdi module didu khie'n ddng co budc nhu da nfiu d tren Chuong trinh sfl dung ngdn ngfl Visual Basic Chiing ta cd thfi l;"iy du lieu tfl mach phan hdi ciia ddng co dd xfl ly mdy tfnh Trfin form chuong trinh, sau kfch chugt vao mil nhan thi chuong trinh se truydn cac Byte du lieu qua cdng COM vdi khudn mdu truyen ddt sdn la "9600.N,8,1" [Chifong trinh ndy dd diffft thd nghiem ghep nd'i vdi bd vi M} ly 89C51 vd FPGA Spartan3 XC3S200 5FT256) Mdi ldn kfch chugt la chuong irinh truyen mdt Byte dfl lifiu, vi thd bd UART dugc vifi't trfin bo mach Spartan-3 se cd tdc Baudrate la 9600 vdi khudn mdu truyfin nhan nhu trfin Chuong trinh difiu khidn dugc vifi't dudi dang mdt Form dan vdi sau mil nhd'n nhu sau: - Start: Khdi ddng Motor - Left, Right: Dung dd dao chidu ddng co Niit Slow/Fast; Dung dd tang giam td'c dd ddng CO WBI!ilHW^"l^^^*^^i^^ll^ h4ok>r dk/nto/ ji SLOW LEFT -FAST RIGHT St^ Motor fDontroH&r Ciestgnedt^ Fiwm Tuan Na/-MasterC>?iffse 16 MMa/y Tschn/ca!.Acadsn}/ START ^ ^ H Hinh Giao dien khdi dieu khien Motor va so ghep noi Modul XC3s200 pm-rs232-td Led Starl/Slop piii-rs232-rd Mudul UART Cnt-Dir Sec [3:0] Modul Step-Motor Inc/Dee Led] Hinh So dd noi ghep Modul dieu khien vdi may tfnh Thiet ke bd UART: De thie't ke' Modul UART, nhdm tac gia thifi't kd mdt Modul chi'nh va hai modul vdi cdc tfin file nhu sau - Modul UART.vhd: Modufi chi'nh chiia cac Module phdn - Modul Rx.vhd: Modue dung dfi lam bd thu dtt lifiu khdng ddng bd - Modul Tx.vhd; Module diing dd thuc hifin bd phat dfl lieu khdng ddng bd - Modul Counter.vhd: Dung de tao ddng hd Baudrate, thie't ldp td'c dd Baudrate vdi may tfnh PC - Modul Synchroniser.vhd dung de ddng bd Clock So dd khdi tdng quat cua bd didu khifi'n Motor bdng may tfnh se nhu sau: Modul UART chi thu du lifiu, sau dd xfl ly rdi dua cac dudng didu khidn nhu tren hinh sang khd'i Step-motor Cdng vific tifi'p theo la vifi't chuong trinh va md phdng cac bd Tx va Rx Qua trinh xfl ly cdc tin hifiu dieu khidn cdn cd thfim mfit Process modul I/O Chflong trinh dugc thuc hifin vdi ngdn ngfl VHDL, sau dd se dugc ghep vdi modul didu khidn motor Hinh Luu thuat toan cua bo dem thu TxD Sau chay chuong trinh md phdng ta thu dugc tfn hieu trfin dudng Tx nhu hinh dudi ddy Gia sfl ta nap sd 04 Hex dfi truyfin di, dd tren dudng Tx cd dang xung nhu bidu dd: i!jj|jjjj2^^ Hinh Bieu mo phdng bp dem phat Bo dem thu dOr lieu: Tuong tu, bo dem thu co luu thuSl toan nhu sau: \^ HKiEl = C.BilpntJCI J Hinh Luu thuat tuan bu dem thu dfl lieu Bifiu dd md phdng cua bd dfim thu sau kbi cho dau vao Rx so 06 Hex, chay chuong trinh ModelSim la thu duoc cdc tin hifiu d ddu Data[7:0] sd 06 Hex nhu bidu dd dudi day: Hinh Bie'u song dau ciia bd dem thu du lieu Rx Sau vidt mdt doan Process xfl ly cac Byte nhdn tfl mdy tfnh sang dd dua cac dudng difiu khidn nhu hinh Trong file lO.vhd khai bao thfim mdt sd tfn hieu ciia Module Top-Step Sau dd ldng hgp va thuc thi chuong trinh, nfi'u khdng cd ldi thi tifi'n hanh gan chdn chuong Irinh Xilinx PACE dung cho Board mach Starter Kit Board Spartan-3 vdi cac chdn dugc gan nhu sau: 784 E^i^S UmAl S«c Sec r»232_ld iiZ32_td Puihbtn Ledl Led CLK - Output {CS Output ee Output Input Input dulpul Output Output Input R13 T13 UA K12 'P14 LT2 its Hi G r o u p l I / O Diiactioni 4|Sec Output Lew I/O Std! |Vt