CMOS VLSI Design - Lecture 5: DC & Transient Response doc

Lecture 5: DC & Transient Response Outline       Pass Transistors DC Response Logic Levels and Noise Margins Transient Response RC Delay Models Delay Estimation 5: DC and Transient Response CMOS VLSI Design 4th Ed Pass Transistors  We have assumed source is grounded  What if source > 0? VDD – e.g pass transistor passing VDD VDD  Vg = VDD – If Vs > VDD-Vt, Vgs < Vt – Hence transistor would turn itself off  nMOS pass transistors pull no higher than VDD-Vtn – Called a degraded “1” – Approach degraded value slowly (low Ids)  pMOS pass transistors pull no lower than Vtp  Transmission gates are needed to pass both and 5: DC and Transient Response CMOS VLSI Design 4th Ed Pass Transistor Ckts VDD VDD VDD VDD VDD VDD Vs = VDD-Vtn VDD-Vtn VDD-Vtn VDD VDD-Vtn VDD-Vtn Vs = |Vtp| VDD VDD-2Vtn VSS 5: DC and Transient Response CMOS VLSI Design 4th Ed DC Response  DC Response: Vout vs Vin for a gate  Ex: Inverter – When Vin = -> Vout = VDD – When Vin = VDD -> Vout = VDD – In between, Vout depends on Idsp transistor size and current Vin Vout – By KCL, must settle such that Idsn Idsn = |Idsp| – We could solve equations – But graphical solution gives more insight 5: DC and Transient Response CMOS VLSI Design 4th Ed Transistor Operation  Current depends on region of transistor behavior  For what Vin and Vout are nMOS and pMOS in – Cutoff? – Linear? – Saturation? 5: DC and Transient Response CMOS VLSI Design 4th Ed nMOS Operation Cutoff Vgsn < Vtn Vin < Vtn Linear Vgsn > Vtn Vin > Vtn Vdsn < Vgsn – Vtn Vout < Vin - Vtn Saturated Vgsn > Vtn Vin > Vtn Vdsn > Vgsn – Vtn Vout > Vin - Vtn VDD Vgsn = Vin Vdsn = Vout 5: DC and Transient Response Vin Idsp Vout Idsn CMOS VLSI Design 4th Ed pMOS Operation Cutoff Vgsp > Vtp Vin > VDD + Vtp Linear Vgsp < Vtp Vin < VDD + Vtp Vdsp > Vgsp – Vtp Vout > Vin - Vtp Saturated Vgsp < Vtp Vin < VDD + Vtp Vdsp < Vgsp – Vtp Vout < Vin - Vtp VDD Vgsp = Vin - VDD Vdsp = Vout - VDD 5: DC and Transient Response Vtp < Vin Idsp Vout Idsn CMOS VLSI Design 4th Ed I-V Characteristics  Make pMOS is wider than nMOS such that βn = βp Vgsn5 Idsn Vgsn4 Vgsn3 Vgsn2 Vgsn1 -Vdsp Vgsp1 Vgsp2 -VDD VDD Vdsn Vgsp3 Vgsp4 -Idsp Vgsp5 5: DC and Transient Response CMOS VLSI Design 4th Ed Current vs Vout, Vin Vin0 Vin1 Vin4 Vin2 Vin3 Vin3 Vin4 Idsn, |Idsp| Vin5 Vin2 Vin1 Vout 5: DC and Transient Response CMOS VLSI Design 4th Ed VDD 10 Simulated Inverter Delay  Solving differential equations by hand is too hard  SPICE simulator solves the equations numerically – Uses more accurate I-V models too!  But simulations take time to write, may hide insight 2.0 1.5 1.0 (V) Vin tpdf = 66ps tpdr = 83ps Vout 0.5 0.0 0.0 200p 400p 600p 800p 1n t(s) 5: DC and Transient Response CMOS VLSI Design 4th Ed 22 Delay Estimation  We would like to be able to easily estimate delay – Not as accurate as simulation – But easier to ask “What if?”  The step response usually looks like a 1st order RC response with a decaying exponential  Use RC delay models to estimate delay – C = total capacitance on output node – Use effective resistance R – So that tpd = RC  Characterize transistors by finding their effective R – Depends on average current as gate switches 5: DC and Transient Response CMOS VLSI Design 4th Ed 23 Effective Resistance  Shockley models have limited value – Not accurate enough for modern transistors – Too complicated for much hand analysis  Simplification: treat transistor as resistor – Replace Ids(Vds, Vgs) with effective resistance R • Ids = Vds/R – R averaged across switching of digital gate  Too inaccurate to predict current at any given time – But good enough to predict RC delay 5: DC and Transient Response CMOS VLSI Design 4th Ed 24 RC Delay Model  Use equivalent circuits for MOS transistors – Ideal switch + capacitance and ON resistance – Unit nMOS has resistance R, capacitance C – Unit pMOS has resistance 2R, capacitance C  Capacitance proportional to width  Resistance inversely proportional to width d g d k s s kC R/k kC 2R/k g g kC kC d k s s 5: DC and Transient Response kC g kC d CMOS VLSI Design 4th Ed 25 RC Values  Capacitance – C = Cg = Cs = Cd = fF/µm of gate width in 0.6 µm – Gradually decline to fF/µm in nanometer techs  Resistance – R ≈ KΩ*µm in 0.6 µm process – Improves with shorter channel lengths  Unit transistors – May refer to minimum contacted device (4/2 λ) – Or maybe µm wide device – Doesn’t matter as long as you are consistent 5: DC and Transient Response CMOS VLSI Design 4th Ed 26 Inverter Delay Estimate  Estimate the delay of a fanout-of-1 inverter 2C R A Y 2C 2C 2C 2C Y R C R C C C C d = 6RC 5: DC and Transient Response CMOS VLSI Design 4th Ed 27 Delay Model Comparison 5: DC and Transient Response CMOS VLSI Design 4th Ed 28 Example: 3-input NAND  Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R) 2 3 5: DC and Transient Response CMOS VLSI Design 4th Ed 29 3-input NAND Caps  Annotate the 3-input NAND gate with gate and diffusion capacitance 2C 2C 2C 5C 2C 2C 2C 3C 5C 3C 5C 3C 5: DC and Transient Response 2C 2C 2C 3 CMOS VLSI Design 4th Ed 9C 3C 3C 3C 3C 30 Elmore Delay  ON transistors look like resistors  Pullup or pulldown network modeled as RC ladder  Elmore delay of RC ladder t pd ≈ ∑ Ri −to − sourceCi nodes i = R1C1 + ( R1 + R2 ) C2 + + ( R1 + R2 + + RN ) C N R1 R2 R3 C1 C2 5: DC and Transient Response RN C3 CMOS VLSI Design 4th Ed CN 31 Example: 3-input NAND  Estimate worst-case rising and falling delay of 3-input NAND driving h identical gates 2 Y 9C 5hC n2 3C n1 h copies t pdr = ( + 5h ) RC 5: DC and Transient Response = t pdf = 3C ( 3C ) ( R ) + ( 3C ) ( R + R ) + ( + 5h ) C  ( R + R + R ) 3   3 (11 + 5h ) RC CMOS VLSI Design 4th Ed 32 Delay Components  Delay has two parts – Parasitic delay • or 11 RC • Independent of load – Effort delay • 5h RC • Proportional to load capacitance 5: DC and Transient Response CMOS VLSI Design 4th Ed 33 Contamination Delay  Best-case (contamination) delay can be substantially less than propagation delay  Ex: If all three inputs fall simultaneously 2 Y 9C 5hC n2 3C n1 3C tcdr 5: DC and Transient Response  R  =) C    = RC ( + 5h  3+ h   3  CMOS VLSI Design 4th Ed 34 Diffusion Capacitance  We assumed contacted diffusion on every s / d  Good layout minimizes diffusion area  Ex: NAND3 layout shares one diffusion contact – Reduces output capacitance by 2C – Merged uncontacted diffusion might help too 2C 2C Shared Contacted Diffusion Isolated Contacted Diffusion Merged Uncontacted Diffusion 2 3 3C 3C 3C 5: DC and Transient Response CMOS VLSI Design 4th Ed 7C 3C 3C 35 Layout Comparison  Which layout is better? VDD A VDD B Y GND 5: DC and Transient Response A B Y GND CMOS VLSI Design 4th Ed 36 ... and 5: DC and Transient Response CMOS VLSI Design 4th Ed Pass Transistor Ckts VDD VDD VDD VDD VDD VDD Vs = VDD-Vtn VDD-Vtn VDD-Vtn VDD VDD-Vtn VDD-Vtn Vs = |Vtp| VDD VDD-2Vtn VSS 5: DC and Transient. .. 3C 3C 3C 5: DC and Transient Response CMOS VLSI Design 4th Ed 7C 3C 3C 35 Layout Comparison  Which layout is better? VDD A VDD B Y GND 5: DC and Transient Response A B Y GND CMOS VLSI Design 4th... 6RC 5: DC and Transient Response CMOS VLSI Design 4th Ed 27 Delay Model Comparison 5: DC and Transient Response CMOS VLSI Design 4th Ed 28 Example: 3-input NAND  Sketch a 3-input NAND with transistor