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Lecture4:
Nonideal
Transistor
Theory
CMOS VLSI DesignCMOS VLSIDesign
4th Ed.
4: NonidealTransistorTheory 2
Outline
NonidealTransistor Behavior
– High Field Effects
• Mobility Degradation
• Velocity Saturation
– Channel Length Modulation
– Threshold Voltage Effects
• Body Effect
• Drain-Induced Barrier Lowering
• Short Channel Effect
– Leakage
• Subthreshold Leakage
• Gate Leakage
• Junction Leakage
Process and Environmental Variations
CMOS VLSI DesignCMOS VLSIDesign
4th Ed.
4: NonidealTransistorTheory 3
Ideal Transistor I-V
Shockley long-channel transistor models
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
VV
V
I VV VVV
VV VV
β
β
<
= −− <
−>
CMOS VLSI DesignCMOS VLSIDesign
4th Ed.
4: NonidealTransistorTheory 4
Ideal vs. Simulated nMOS I-V Plot
65 nm IBM process, V
DD
= 1.0 V
0
0.2
0.4
0.6
0.8 1
0
200
400
600
800
1000
1200
V
ds
I
ds
(µA)
V
gs
= 1.0
V
gs
= 1.0
V
gs
= 0.8
V
gs
= 0.6
V
gs
= 0.4
V
gs
= 0.8
V
gs
= 0.6
Channel length modulation:
Saturation current increases
with V
ds
I
on
= 747 mA @
V
gs
= V
ds
= V
DD
Simulated
Ideal
Velocity saturation & Mobility degradation:
Saturation current increases less than
quadratically with V
gs
Velocity saturation & Mobility degradation:
I
on
lower than ideal model predicts
CMOS VLSI DesignCMOS VLSIDesign
4th Ed.
4: NonidealTransistorTheory 5
ON and OFF Current
I
on
= I
ds
@ V
gs
= V
ds
= V
DD
– Saturation
I
off
= I
ds
@ V
gs
= 0, V
ds
= V
DD
– Cutoff
0
0.2 0.4 0.6
0.8 1
0
200
400
600
800
1000
V
ds
I
ds
(µA)
V
gs
= 1.0
V
gs
= 0.4
V
gs
= 0.8
V
gs
= 0.6
I
on
= 747 mA @
V
gs
= V
ds
= V
DD
CMOS VLSI DesignCMOS VLSIDesign
4th Ed.
4: NonidealTransistorTheory 6
Electric Fields Effects
Vertical electric field: E
vert
= V
gs
/ t
ox
– Attracts carriers into channel
– Long channel: Q
channel
∝ E
vert
Lateral electric field: E
lat
= V
ds
/ L
– Accelerates carriers from drain to source
– Long channel: v = µE
lat
CMOS VLSI DesignCMOS VLSIDesign
4th Ed.
4: NonidealTransistorTheory 7
Coffee Cart Analogy
Tired student runs from VLSI lab to coffee cart
Freshmen are pouring out of the physics lecture hall
V
ds
is how long you have been up
– Your velocity = fatigue × mobility
V
gs
is a wind blowing you against the glass (SiO
2
) wall
At high V
gs
, you are buffeted against the wall
– Mobility degradation
At high V
ds
, you scatter off freshmen, fall down, get up
– Velocity saturation
• Don’t confuse this with the saturation region
CMOS VLSI DesignCMOS VLSIDesign
4th Ed.
4: NonidealTransistorTheory 8
Mobility Degradation
High E
vert
effectively reduces mobility
– Collisions with oxide interface
CMOS VLSI DesignCMOS VLSIDesign
4th Ed.
4: NonidealTransistorTheory 9
Velocity Saturation
At high E
lat
, carrier velocity rolls off
– Carriers scatter off atoms in silicon lattice
– Velocity reaches v
sat
• Electrons: 10
7
cm/s
• Holes: 8 x 10
6
cm/s
– Better model
CMOS VLSI DesignCMOS VLSIDesign
4th Ed.
4: NonidealTransistorTheory 10
Vel Sat I-V Effects
Ideal transistor ON current increases with V
DD
2
Velocity-saturated ON current increases with V
DD
Real transistors are partially velocity saturated
– Approximate with α-power law model
– I
ds
∝ V
DD
α
– 1 < α < 2 determined empirically (≈ 1.3 for 65 nm)
( )
( )
2
2
ox
22
gs t
ds gs t
VV
W
I C VV
L
β
µ
−
= = −
( )
ox maxds gs t
I CWV V v= −
[...]... (tox ≈ 10.5 Å) From [Song01] 4:NonidealTransistorTheoryCMOSVLSIDesign 4th Ed 22 Junction Leakage Reverse-biased p-n junctions have some leakage – Ordinary diode leakage – Band-to-band tunneling (BTBT) – Gate-induced drain leakage (GIDL) p+ n+ n+ p+ p+ n+ n well p substrate 4:NonidealTransistorTheoryCMOSVLSIDesign 4th Ed 23 Diode Leakage Reverse-biased p-n junctions have some leakage... coefficient γ = tox 2qε si N A = ε ox 4:NonidealTransistorTheory 2qε si N A Cox CMOSVLSIDesign 4th Ed 15 Body Effect Cont For small source-to-body voltage, treat as linear 4:NonidealTransistorTheoryCMOSVLSIDesign 4th Ed 16 DIBL Electric field from drain affects channel More pronounced in small transistors where the drain is closer to the channel Drain-Induced Barrier Lowering VVVη – Drain... temperature Vgs 4:NonidealTransistorTheoryCMOS VLSI Design 4th Ed 27 So What? So what if transistors are not ideal? – They still behave like switches But these effects matter for… – Supply voltage choice – Logical effort – Quiescent power consumption – Pass transistors – Temperature of operation 4:NonidealTransistorTheoryCMOS VLSI Design 4th Ed 28 Parameter Variation fast Transistors have... increases with Vds n n L + + L – Even in saturation p GND bulk Si DD DD d eff 4:NonidealTransistorTheoryCMOS VLSI Design 4th Ed 12 Chan Length Mod I-V I ds = β (V 2 gs − Vt ) (1 + λVds ) 2 λ = channel length modulation coefficient – not feature size – Empirically fit to I-V characteristics 4:NonidealTransistorTheoryCMOS VLSI Design 4th Ed 13 Threshold Voltage Effects Vt is Vgs for which the channel... Reverse-biased PN junction diode current 4:NonidealTransistorTheoryCMOS VLSI Design 4th Ed 20 Subthreshold Leakage Subthreshold leakage exponential with Vgs Vgs −Vt 0 +ηVds − kγ Vsb I ds I ds 0 e nvT −Vds 1 − e vT n is process dependent – typically 1. 3-1 .7 Rewrite relative to Ioff on log scale S ≈ 100 mV/decade @ room temperature 4:NonidealTransistorTheoryCMOSVLSI Design. .. Eg: bandgap voltage – A, B: tech constants 4:NonidealTransistorTheoryCMOSVLSIDesign 4th Ed 25 Gate-Induced Drain Leakage Occurs at overlap between gate and drain – Most pronounced when drain is at VDD, gate is at a negative voltage – Thwarts efforts to reduce subthreshold leakage using a negative gate voltage 4:NonidealTransistorTheoryCMOSVLSIDesign 4th Ed 26 Temperature Sensitivity ... pMOS FF pMOS SF TT slow slow 4:NonidealTransistorTheoryCMOSVLSIDesign 4th Ed FS SS fast 29 Environmental Variation VDD and T also vary in time and space Fast: – VDD: high – T: low Corner Voltage Temperature F 1.98 0C T 1.8 70 C S 1.62 125 C 4:NonidealTransistorTheoryCMOSVLSIDesign 4th Ed 30 Process Corners Process corners describe worst case variations – If a design works in all corners,... which Vt decreases with L 4:NonidealTransistorTheoryCMOSVLSIDesign 4th Ed 18 Leakage What about current in cutoff? Simulated results What differs? – Current doesn’t go to 0 in cutoff 4:NonidealTransistorTheoryCMOSVLSIDesign 4th Ed 19 Leakage Sources Subthreshold conduction – Transistors can’t abruptly turn ON or OFF – Dominant source in contemporary transistors Gate leakage – Tunneling... with four letters (T, F, S) – nMOS speed – pMOS speed – Voltage – Temperature 4:NonidealTransistorTheoryCMOSVLSIDesign 4th Ed 31 Important Corners Some critical simulation corners include Purpose nMOS pMOS VDD Temp Cycle time S S S S Power F F F F Subthreshold leakage F F F S 4:NonidealTransistorTheoryCMOSVLSIDesign 4th Ed 32 ... VD vT = I S e − 1 ID At any significant negative diode voltage, ID = -Is Is depends on doping levels – And area and perimeter of diffusion regions – Typically < 1 fA/µm2 (negligible) 4:NonidealTransistorTheoryCMOSVLSIDesign 4th Ed 24 Band-to-Band Tunneling Tunneling across heavily doped p-n junctions – Especially sidewall between drain & channel when halo doping is used to . Lecture 4:
Nonideal
Transistor
Theory
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 2
Outline
Nonideal Transistor. Environmental Variations
CMOS VLSI DesignCMOS VLSI Design
4th Ed.
4: Nonideal Transistor Theory 3
Ideal Transistor I-V
Shockley long-channel transistor models
(