CMOS VLSI Design - Lecture 3: CMOS Transistor Theory potx

Lecture 3: CMOS Transistor Theory Outline      Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V Characteristics Gate and Diffusion Capacitance 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed Introduction  So far, we have treated transistors as ideal switches  An ON transistor passes a finite amount of current – Depends on terminal voltages – Derive current-voltage (I-V) relationships  Transistor gate, source, drain all have capacitance – I = C (∆V/∆t) -> ∆t = (C/I) ∆V – Capacitance and current determine speed 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed MOS Capacitor  Gate and body form MOS capacitor V Vt g + s + d n+ n+ Vgs > Vgd > Vt Ids < Vds < Vgs-Vt p-type body b 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed nMOS Saturation     Channel pinches off Ids independent of Vds We say current saturates Similar to current source Vgs > Vt g + - + - Vgd < Vt d Ids s n+ n+ Vds > Vgs-Vt p-type body b 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed I-V Characteristics  In Linear region, Ids depends on – How much charge is in the channel? – How fast is the charge moving? 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed Channel Charge  MOS structure looks like parallel plate capacitor while operating in inversions – Gate – oxide – channel  Qchannel = CV Cox = εox / tox  C = Cg = εoxWL/tox = CoxWL  V = Vgc – Vt = (Vgs – Vds/2) – Vt gate Vg polysilicon gate W tox n+ L n+ SiO2 gate oxide (good insulator, εox = 3.9) + + Cg Vgd drain source Vgs Vs Vd channel + n+ n+ Vds p-type body p-type body 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed 10 Carrier velocity  Charge is carried by e Electrons are propelled by the lateral electric field between source and drain – E = Vds/L  Carrier velocity v proportional to lateral E-field – v = µE µ called mobility  Time for carrier to cross channel: – t=L/v 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed 11 nMOS Linear I-V  Now we know – How much charge Qchannel is in the channel – How much time t each carrier takes to cross Qchannel I ds = t W = µCox L V − V − Vds  gs t  V = β Vgs − Vt − ds Vds  2   3: CMOS Transistor Theory V  ds  CMOS VLSI Design 4th Ed W β = µCox L 12 nMOS Saturation I-V  If Vgd < Vt, channel pinches off near drain – When Vds > Vdsat = Vgs – Vt  Now drain voltage no longer increases current V I ds β Vgs − Vt − dsat =   = β (V gs − Vt ) 3: CMOS Transistor Theory V  dsat  CMOS VLSI Design 4th Ed 13 nMOS I-V Summary  Shockley 1st order transistor models      Vds I ds =  β Vgs − Vt −   β  (Vgs − Vt )   3: CMOS Transistor Theory Vgs < Vt V V < V  ds ds dsat  Vds > Vdsat CMOS VLSI Design 4th Ed cutoff linear saturation 14 Example  We will be using a 0.6 µm process for your project – From AMI Semiconductor – tox = 100 Å 2.5 V =5 2/V*s – µ = 350 cm – Vt = 0.7 V 1.5 V =4  Plot Ids vs Vds V =3 – Vgs = 0, 1, 2, 3, 4, 0.5 V =2 – Use W/L = 4/2 λ V =1 Ids (mA) gs gs gs gs W = µ Cox β = L  3.9 × 8.85 ⋅10−14   W  W ( 350 )  μA/V −8 = 120   L  100 ⋅10  L  3: CMOS Transistor Theory gs CMOS VLSI Design 4th Ed Vds 15 pMOS I-V  All dopings and voltages are inverted for pMOS – Source is the more positive terminal  Mobility µp is determined by holes – Typically 2-3x lower than that of electrons àn 120 cm2/Vãs in AMI 0.6 àm process  Thus pMOS must be wider to provide same current – In this class, assume µn / µp = Vgs = -1 Vgs = -2 -0.2 Ids (mA) Vgs = -3 -0.4 Vgs = -4 -0.6 -0.8 -5 Vgs = -5 -4 -3 -2 -1 Vds 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed 16 Capacitance  Any two conductors separated by an insulator have capacitance  Gate to channel capacitor is very important – Creates channel charge necessary for operation  Source and drain have capacitance to body – Across reverse-biased diodes – Called diffusion capacitance because it is associated with source/drain diffusion 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed 17 Gate Capacitance  Approximate channel as connected to source  Cgs = εoxWL/tox = CoxWL = CpermicronW  Cpermicron is typically about fF/µm polysilicon gate W tox n+ L n+ SiO2 gate oxide (good insulator, εox = 3.9ε0) p-type body 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed 18 Diffusion Capacitance  Csb, Cdb  Undesirable, called parasitic capacitance  Capacitance depends on area and perimeter – Use small diffusion nodes – Comparable to Cg for contacted diff – ½ Cg for uncontacted – Varies with process 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed 19 ... assume µn / µp = Vgs = -1 Vgs = -2 -0 .2 Ids (mA) Vgs = -3 -0 .4 Vgs = -4 -0 .6 -0 .8 -5 Vgs = -5 -4 -3 -2 -1 Vds 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed 16 Capacitance  Any two conductors... Linear – Saturation 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed nMOS Cutoff  No channel  Ids ≈ Vgs = g + - + - s d n+ Vgd n+ p-type body b 3: CMOS Transistor Theory CMOS VLSI Design 4th Ed... 3: CMOS Transistor Theory V  dsat  CMOS VLSI Design 4th Ed 13 nMOS I-V Summary  Shockley 1st order transistor models      Vds I ds =  β Vgs − Vt −   β  (Vgs − Vt )   3: CMOS Transistor