Advanced Computer Architecture - Lecture 9: Computer hardware design. This lecture will cover the following: multi cycle and pipeline - datapath and control design; features of multi cycle design; multi cycle control design; introduction to pipeline datapath; high level view of multiple cycle datapath;...
CS 704 Advanced Computer Architecture Lecture Computer Hardware Design (Multi Cycle and Pipeline - Datapath and Control Design) Prof Dr M Ashraf Chughtai Today’s Topics Recap: multi cycle datapath and control Features of Multi cycle design Multi Cycle Control Design Introduction to Pipeline datapath Summary MAC/VU-Advanced Computer Architecture Lecture – Computer Hardware Design (3) Recap: Lecture Information flow and Control signals for single cycles data path to execute: – Add/Subtract Instruction – Immediate Instruction – Load/Store Instructions – Control Instructions Analysis of single cycle data path How effectively are different sections used? … Next please MAC/VU-Advanced Computer Architecture Lecture – Computer Hardware Design (3) How effectively different sections are used? – Memory is used twice, at different times (i.e., Instruction Fetch and Load or Store) – Adders in IF section are used once for fraction of time (Fetch Phase) – ALU is used for the execution of R-type instructions and memory address calculation Conclusion: We can reduce H/W without hurting performance by using extra control MAC/VU-Advanced Computer Architecture Lecture – Computer Hardware Design (3) Multiple Cycle Approach Cycle Clk Clk I fetch ID/Reg Exec Mem Cycle 1 Cycle 2 Cycle 3 Cycle 4 Wr Cycle 5 Clk The single cycle operations are performed in five steps: Instruction Fetch Instruction Decode and Register Read Execute (R- I-type or address for Load/store/Branch) Memory (Read/write) Write (to register file) MAC/VU-Advanced Computer Architecture Lecture – Computer Hardware Design (3) Multiple Cycle Approach In the Single Cycle implementation, the cycle time is set to accommodate the longest instruction, the Load instruction In the Multiple Cycles implementation, the cycle time is set to accomplish longest step, the memory read/write Consequently, the cycle time for the Single Cycle implementation can be five times longer than the multiple cycle implementation As an example, if T = µ Sec for single cycle then T= µ Sec for multi cycle implementation MAC/VU-Advanced Computer Architecture Lecture – Computer Hardware Design (3) Single Cycle vs Multiple Cycle Single Cycle Implementation: Cycle 1 Cycle 2 Clk Load Store Waste Multiple Cycle Implementation: Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Clk Store Load I fetch ID/Reg MAC/VU-Advanced Computer Architecture Exec Mem Wr I fetch ID/Reg Lecture – Computer Hardware Design (3) Exec Rtype Mem Ifetch Single Cycle vs Multiple Cycle: Explanation For different classes of instructions, Multi Cycle implementation may take 3, or cycles to fetch and execute an instruction Now in order to compare the performance of single cycle and multi cycle implementations, let us consider a program segment comprising three instructions, given in the sequence: Load Store R-type (say Add) MAC/VU-Advanced Computer Architecture Lecture – Computer Hardware Design (3) Single Cycle vs Multiple Cycle: Explanation The execution time for these three instructions using single cycle implementation with cycle length equals µ Sec is: T exe = x µ Sec = 15 µsec Note that here the cycle time is long enough for the load instruction, but it is too long for the Store and R-type instruction So the last part of the cycle, in case of the store and 4th (memory) part in case of R-type instruction is wasted MAC/VU-Advanced Computer Architecture Lecture – Computer Hardware Design (3) Single Cycle vs Multiple Cycle: Explanation In Multi cycle implementation, Load is completed in Cycles, and store and R-type each takes cycles to complete Thus, these three instructions take 5+4+4 = 13 cycles, if the cycle length is µ Sec then the execution time for the three instructions is: T exe = 13 x µ Sec = 13 µsec Conclusion: The multi cycle is 15/13 = 1.24 times faster Next: High-view of multi cycle datapath MAC/VU-Advanced Computer Architecture Lecture – Computer Hardware Design (3) 10 Multiple Cycle Datapath Architecture Cycle - [Exe] The select inputs ALUSelA and ALUSelB to the MUX-3 and MUX-5, respectively for the instruction in hand; available at ALUop input to the ALU Control Unit - For R-type instructions: ALUSelA = and ALUSelB = 01 to connect bus A and bus B to ALU to perform the operation [Green Path] -MAC/VU-Advanced Computer Architecture Lecture – Computer Hardware Design (3) 16 Multiple Cycle Datapath Architecture - For I-type and Memory Instructions: ALUSelA = and ALUSelB = 11 to connect bus A and Sign Extended Imm16 to ALU to perform the operation on immediate data [Red Path] The ALU output is kept in ALU OUT Register as result of ALU OP execution in case of I-type operation and as Memory address in case of memory instructions Load/store MAC/VU-Advanced Computer Architecture Lecture – Computer Hardware Design (3) 17 Multiple Cycle Datapath Architecture - For J- type Instructions: 1: Condition Test: ALUSelA = and ALUSelB = 01; ALUop=SUB If ALU output Zero =1 then assert PCWrCond and 2: PC PC+4+[Sign Extend Imm16 and Shift left bits] ALUSelA = ; ALUSelB = 10 Assert BrWr ; and PCSrc of MUX-2 = to pass the target address to PC [Blue Path] MAC/VU-Advanced Computer Architecture Lecture – Computer Hardware Design (3) 18 Multiple Cycle Datapath Architecture Cycle - [Memory Instruction Load/Store] - Load instruction: IorD=1 to pass the ALUout Register as RAdr (Read Address) input to the memory to read data at the Dout [Dark Green Path] - Store instruction: MemWr is asserted; as the ALUout Register output is wired to WrAdr (Write address input) [Dark Green Path] and bus B of the register file is wired to Din (Data In) [Dark blue] of the memory MAC/VU-Advanced Computer Architecture Lecture – Computer Hardware Design (3) 19 Multiple Cycle Datapath Architecture Cycle - [Write Back] - R-type instruction: RegDest of MUX-4 = to select Rd as the destination address; MemToReg = to connect ALUout to Bus-W and RegWr is asserted memory - I-type instruction: RegDest of MUX-4 = to select Rt as the destination address; MemToReg = to connect ALUout to Bus-W and RegWr is asserted memory Load instruction next … MAC/VU-Advanced Computer Architecture Lecture – Computer Hardware Design (3) 20 Multiple Cycle Datapath Architecture Cycle - [Write Back] - Load instruction: RegDest of MUX-4 = to select Rt as the destination address; MemToReg = to connect Dout of the memory to Bus-W or the register file and RegWr is asserted MAC/VU-Advanced Computer Architecture Lecture – Computer Hardware Design (3) 21 Multi Cycle Control design Control may be designed in the following steps using the initial representation as: Finite State Machine Here, the sequence control is defined by explicit next state functions, logic is represented by logic equations and usually PLAs are used to implement the machine Micro-program -Here, micro-program counter and a dispatch ROM defines the sequence control, logic is represented by truth table and control is implemented using ROM MAC/VU-Advanced Computer Architecture Lecture – Computer Hardware Design (3) 22 Multi Cycle Controller FSM Specifications IR