Advanced Computer Architecture - Lecture 38: Input/Output systems

Advanced Computer Architecture - Lecture 38: Input/Output systems. This lecture will cover the following: storage and I/O systems; disk storage systems; interfacing storage devices; storage technology drivers; devices magnetic disks; I/O performance parameters; I/O performance measure;...

CS 704 Advanced Computer Architecture Lecture 38 Input Output Systems (Storage and I/O Systems) Prof Dr M Ashraf Chughtai Today’s Topics Recap: Disk Storage Systems Interfacing Storage Devices Conclusion MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) Recap: Multiprocessing In last four lectures we discussed how the computer performance can be improved by Parallel Architectures Parallel Architecture is a collection of processing elements that cooperate and communicate to solve larger problems fast Parallel architectures are implemented as: SIMD, MISD and MIMD machines, where the MIMD machines facilitate complete parallel processing MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) Recap: Multiprocessing The MIMD machines are classified as: – Centralized Shared Memory Architecture – Distributed Memory Architecture The centralized memory architecture, maintain a single centralized memory with uniform access time In contrast, the distributed Shared-Memory multiprocessors have non uniform memory architecture but offer greater scalability MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) Recap: Multiprocessing The sharing of caches for multi-processing introduces cache coherence problem In Centralized shared-memory architecture, the cache coherence problem is resolved by using write invalidation and write broadcasting schemes those implement Snooping algorithm In Distributed shared-memory architecture, the cache coherence problem is resolved by using Directory Based Protocols MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) Recap: outside processor Today the :  Processing Power doubles every 18 months  Memory Size doubles every 18 months; and  Disk positioning rate (Seek + Rotate) doubles every 10 Years Recall the 2nd lecture, where we discussed the quantitative principles to define the computer performance, we noticed that the execution time of CPU is not the only measure of computer performance MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) Introduction: outside the processor The overall performance of a computer is measured by its throughput, which is very much influenced by the systems external to the processor As we have already pointed out in 25th lecture that measuring the overall performance of a powerful Uni-processor or a parallel processing architecture without considering the I/O devices and their interconnection, is just like trying to determine the road performance of a car, which is fitted with powerful engine but is without wheels MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) Introduction: outside the processor The effect of neglecting the I/Os on the overall performance of a computer system can best be visualized by Amdahl's Law which identifies that: system speed-up limited by the slowest part! Let us consider computer whose response time is 10% longer than the CPU time If the CPU time is speeded up by a factor of 10 then neglecting the I/Os, the overall speed up as determined using the Amdahl's Law is 5; i.e., MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) Introduction: outside the processor Half of what we would have achieved if both the CPU time and I/O time were sped up 10 times In other words we can say 50% lose in the speedup Similarly, if the CPU time is speeded up 100 times and neglecting the I/Os, the overall speed up is 10; i.e., 10% of what we would have achieved if both the CPU time and I/O time were sped up 100 times In other words we can say that ignoring the I/Os there is 90% lose in the speed-up MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) Introduction: outside the processor Thus, I/O performance increasingly limits the system performance and efficiency After having detailed discussion on the performance enhancement of: – – – – – instruction Set Architecture computer hardware instruction level parallelism memory hierarchy systems and parallel processing architecture We are, now, going to focus our discussion on the study of the systems outside processor, i.e., I/O systems MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) 10 Response Time vs Productivity Example: Let us see what happens to transaction time as system response time shrinks from 1.0 sec to 0.3 sec? Assume: – with Keyboard the entry time is 4.0 sec and think time is 9.4 sec; and – With Graphics: 0.25 sec entry, 1.6 sec think time The upper part of graph showing the response time for conventional use (keyboard) depicts that: MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) 35 Response Time & Productivity conventional 0.3s conventional 1.0s graphics 0.3s entry graphics 1.0s 0.00 5.00 resp 10.00 think 15.00 Time 1.0 – 0.3 = 0.7sec off response saves 4.9 sec (34%) And, lower graphs for graphics saves 2.0 sec (70%) of total time per transaction; i.e., shrinkage in the response time results in greater productivity MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) 36 Processor Interface Issues Processor interface – – – Isolated I/O Memory mapped I/O Interrupts I/O Control Structures – – – – – Polling Interrupts DMA I/O Controllers I/O Processors Capacity, Access Time, Bandwidth Interconnections – Busses MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) 37 I/O - Processor Interface Isolated I/O Bus is implemented as: - Independent I/O bus - common memory & I/O bus It requires separate I/O instructions (in, out) MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) 38 Independent I/O Bus CPU Memory memory bus Interface Interface Peripheral Peripheral MAC/VU-Advanced Computer Architecture Separate I/O instructions (in, out) Lec 38 Input/Output System (1) 39 Common Memory & I/O Bus CPU Memory Interface Peripheral MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) Interface Peripheral 40 Memory Mapped I/O CPU Memory CPU Single Memory & I/O Bus No Separate I/O Instructions Interface Interface Peripheral Peripheral ROM RAM $ I/O L2 $ Memory Bus Memory MAC/VU-Advanced Computer Architecture I/O bus Bus Adaptor Lec 38 Input/Output System (1) 41 Programmed I/O (Polling) CPU Is the data ready? Memory IOC device no yes read data but checks for I/O completion can be dispersed among computationally intensive code store data done? busy wait loop not an efficient way to use the CPU unless the device is very fast! no yes MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) 42 Interrupt Driven Data Transfer CPU add sub and or nop (1) I/O interrupt Memory IOC (2) save PC device (3) interrupt service addr (4) read store rti user program interrupt service routine memory  User program progress only halted during actual transfer  1000 transfers at ms each: • 1000 interrupts @ àsec per interrupt ã 1000 interrupt service @ 98 µsec each = 0.1 CPU sec MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) 43 Direct Memory Access CPU sends a starting address, direction, and length count to DMAC Then issues "start" Memory Mapped I/O CPU Memory DMAC RAM Peripherals IOC device ROM n DMAC DMAC provides handshake signals for Peripheral Controller, and Memory Addresses and handshake signals for Memory MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) 44 Input / Output Processors CPU D1 IOP D2 main memory bus target device where cmnds are OP Device Address Mem Dn I/O bus I/O Processor looks in memory for commands MAC/VU-Advanced Computer Architecture OP Addr Cnt Other what to Lec 38 Input/Output System (1) special requests where to put data how much 45 Input / Output Processors CPU (1) (4) IOP (2) (3) memory CPU issues instruction to IOP 2-3 IOP steals memory cycles Device to/from memory transfers are controlled by the IOP directly MAC/VU-Advanced Architecture IOP interrupts when Computer 46 Lec 38CPU Input/Output System (1) done Summary Disk industry growing rapidly, improves: – bandwidth 40%/yr , – areal density 60%/year, $/MB faster? queue + controller + seek + rotate + transfer Advertised average seek time benchmark much greater than average seek time in practice Response time vs Bandwidth tradeoffs MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) 47 Summary Value of faster response time: – 0.7sec off response saves 4.9 sec and 2.0 sec (70%) total time per transaction => greater productivity – everyone gets more done with faster response, but novice with fast response = expert with slow Processor Interface: today peripheral processors, DMA, I/O bus, interrupts MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) 48 Thanks and Allah Hafiz MAC/VU-Advanced Computer Architecture Lec 38 Input/Output System (1) 49 ... DMA, I/O bus, interrupts MAC/VU -Advanced Computer Architecture Lec 38 Input/Output System (1) 48 Thanks and Allah Hafiz MAC/VU -Advanced Computer Architecture Lec 38 Input/Output System (1) 49 ... out) MAC/VU -Advanced Computer Architecture Lec 38 Input/Output System (1) 38 Independent I/O Bus CPU Memory memory bus Interface Interface Peripheral Peripheral MAC/VU -Advanced Computer Architecture. .. Storage Systems Interfacing Storage Devices Conclusion MAC/VU -Advanced Computer Architecture Lec 38 Input/Output System (1) Recap: Multiprocessing In last four lectures we discussed how the computer