Advanced Computer Architecture - Lecture 39: Input/Output systems. This lecture will cover the following: bus structures connecting I/O devices; I/O interconnect trends; I/O performance measurement; bus-based interconnect; bus standards; CPU–memory buses; bus transition protocols;...
CS 704 Advanced Computer Architecture Lecture 39 Input Output Systems (Bus Structures Connecting I/O Devices) Prof Dr M Ashraf Chughtai MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) Today’s Topics Recap: I/O interconnect Trends Bus-based Interconnect Bus Standards Conclusion MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) Recap: I/O System Last time we noticed that the overall performance of a computer is measured by its throughput, which is very much influenced by the systems external to the processor The effect of neglecting the I/Os on the overall performance of a computer system can best be visualized by Amdahl's Law which identifies that: system speed-up limited by the slowest part! – We noticed that an I/O system comprises storage I/Os and Communication I/Os MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) Recap: I/O Systems The Storage I/Os consist of Secondary and Tertiary Storage Devices; and The communication I/O consists of I/O Bus system which interconnect the microprocessor and memory with the I/O devices The development in processing effected the storage industry and motivated to develop: – the smaller, cheaper, more reliable and lower power embedded storages for ubiquitous computing; and … MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) Recap: I/O Systems – high capacity, hierarchically managed storages as data utilities We noticed that diversity, capacity, latency and bandwidth are the most important parameters of I/O performance measurement I/O system works on the principle of producerserver model, which comprises an area called queue, wherein the tasks accumulate while waiting to be serviced The metrics of disk I/O performance are: MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) Recap: I/O Systems – Response Time, which is the time to Queue + Device Service time; and – Throughput, which is the percent of the total bandwidth Example: Comparing the performance of different I/Os Assume the following parameters, and compare the time to read and write a 64Kbyte block to flash memory and disk MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) I/O Performance Measurement: Example ─ Flash memory takes: ─ 65 ns to read byte ─ 1.5 µsec to write byte and ─ msec to erase 4KB ─ Disk Storage has: ─ Average seek time = 4.0 msec ─ Average rotational delay = 8.3 msec ─ Transfer time = 4.2 MB/sec; ─ Controller overhead = 0.1 msec MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) I/O Performance Measurement: Example ─ Average read or write time for disk is same and is calculated as: = Average seek time + Average rotational delay + = Transfer time + Controller overhead 4.0 ms+ 8.3 ms + 64KB/4.2 MB/sec + 0.1 ms = 27.3 msec ─ Read time for flash is the ratio of the flash size to the read bandwidth: = 64KB/1B/65ns = 4.3 ms ─ Flash is about times faster than the disk for reading 64KB MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) I/O Performance Measurement: Example ─ Write time for flash is sum of the erase time and the ratio of the flash size to the write bandwidth: = (64KB/4KB/5ms) + (64KB/1B/1.5µs) = 178.3 ms The disk is about times faster than the flash for writing 64KB MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) Interconnect Trends The I/O interconnect is the glue that interfaces computer system components I/O interconnects are facilitated using High speed hardware interfaces and logical protocols Based on the desired communication distance, bandwidth, latency and reliability, interconnects are classified as used: Backplanes, channels, Networks MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) 10 Bus Arbitration Schemes Distributed Arbitration schemes are classified as: Distributed arbitration by self-selection Distributed arbitration by Collision Detection MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) 34 Bus Arbitration Schemes Distributed arbitration by self-selection This scheme also uses multiple request line The devices requesting the bus access determine who will be granted the access Here, each device wanting the access places a code indicating its identity on the bus By examining this code, the devices can determine the highest priority device that has made request MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) 35 Bus Arbitration Schemes Distributed arbitration by Collision detection In this scheme each device independently request the bus Multiple simultaneous requests result is collision A device is selected among the collided devices based on the priority MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) 36 Bus Options: Design Decisions Option High performance Low cost Bus width Separate address & data lines Multiplex address & data lines Data width Wider is faster (e.g., 32 bits) Narrower is cheaper (e.g., bits) Transfer size Multiple words has less bus overhead Single-word transfer is simpler Bus masters Multiple (requires arbitration) Single master (no arbitration) Split transaction? Yes—separate Request and Reply packets gets higher bandwidth No—continuous connection is cheaper and has lower latency (needs multiple masters) Clocking Synchronous Asynchronous MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) 37 Bus Design Decisions The decisions regarding design of a bus system depend on: Bus Bandwidth Data width Transfer size Based on the bus bandwidth; separate address and data buses are used for high performance while the multiplexed address and data line are used for low cost design MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) 38 Bus Design Decisions Based on the data width; wider (64-bit) data bus is recommended for high performance systems and narrow (8-bit) offers cheap solution Based on the transfer size, multiple word are transferred for high performance computing as it offers less overhead while single word transfer is used for low cost design as it is simples Split transition, Bus masters, and clocking are other important parameters in bus design decisions MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) 39 Bus Design Decisions Based on the bus masters, multiple master are used in high performance computing; and single master that involve no arbitration is used for low cost systems Split transition is used for high performance design where separate requests and reply packets get higher bandwidth; it involves multiple masters The synchronous multiple masters protocols are described hereafter MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) 40 Synchronous Bus Protocols- Multiple Masters Pipelined/Split transaction Bus Protocol Address addr addr addr Data data data data Wait wait OK Where as bus has multiple masters, the multiple processors or I/O devices can initiate bus transaction MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) 41 Synchronous Bus Protocols- Multiple Masters Here, the bus can offer higher bandwidth using packets as opposed to holding the bus for full transaction This technique is called a split transaction or pipelined bus Here, the bus events are divided into number of requests and replies; so the bus can be used in time between request and reply The split transaction makes the bus available for other masters while the memory reads the word from requested address MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) 42 Bus Standards SCSI: Small Computer System Interface Clock rate: MHz / 10 MHz (fast) / 20 MHz(ultra) Width: n = bits / 16 bits (wide); up to n – devices to communicate on a bus or “string” Devices can be slave (“target”) or master (“initiator”) SCSI protocol: a series of “phases”, during which specific actions are taken by the controller and the SCSI disks MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) 43 SCSI: Small Computer System Interface – Bus Free: No device is currently accessing the bus – Arbitration: When the SCSI bus goes free, multiple devices may request (arbitrate for) the bus; fixed priority by address – Selection: informs the target that it will participate (Reselection if disconnected) – Command: the initiator reads the SCSI command bytes from host memory and sends them to the target MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) 44 SCSI: Small Computer System Interface – Data Transfer: data in or out, initiator: target – Message Phase: message in or out, initiator: target (identify, save/restore data pointer, disconnect, command complete) – Status Phase: target, just before command complete MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) 45 1993 I/O Bus Survey (P&H, 2nd Ed) Bus Originator SBus Sun Clock Rate (MHz) 16-25 Addressing Virtual Data Sizes (bits) 8,16,32 Master Arbitration Multi Central 32 bit read (MB/s) 33 Peak (MB/s) 89 Max Power (W) 16 MAC/VU-Advanced Computer Architecture TurboChannel MicroChannel DEC IBM 12.5-25 async Physical 8,16,24,32 Physical 8,16,24,32,64 Single Central Multi Central 25 84 20 75 26 13 Lecture 39 Input / Output System (2) PCI Intel 33 Physical 8,16,24,32,64 Multi Central 33 111 (222) 25 46 1993 MP Server Memory Bus Survey Bus Summit Challenge XDBus Originator Clock Rate (MHz) HP 60 SGI 48 Sun 66 Split transaction? Yes Yes Yes? Address lines Data lines 48 128 40 256 ?? 144 (parity) Data Sizes (bits) Clocks/transfer 512 1024 512 4? Peak (MB/s) Master 960 Multi 1200 Multi 1056 Multi Arbitration Addressing Central Physical Central Physical Central Physical Slots Busses/system 16 10 Length 13 inches 12? inches 17 inches MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) 47 Thanks and Allah Hafiz MAC/VU-Advanced Computer Architecture Lecture 39 Input / Output System (2) 48 ... inches 12? inches 17 inches MAC/VU -Advanced Computer Architecture Lecture 39 Input / Output System (2) 47 Thanks and Allah Hafiz MAC/VU -Advanced Computer Architecture Lecture 39 Input / Output System... MAC/VU -Advanced Computer Architecture Lecture 39 Input / Output System (2) 22 Read Transaction Address Master Asserts Address Next Address Data Read Req Ack Cycle Handshake t0 MAC/VU -Advanced Computer. .. throughput – In server systems, where I/O is frequent, design a bus-system capable of meeting the demand of the processor is a real challenge MAC/VU -Advanced Computer Architecture Lecture 39 Input