Advanced Computer Architecture - Lecture 33: Memory hierarchy design. This lecture will cover the following: virtual memory system; virtual memory address translation; virtual memory performance; protection of multiple processes sharing memory; VM address translation concept; fast address translation;...
CS 704 Advanced Computer Architecture Lecture 33 Memory Hierarchy Design (Virtual Memory System) Prof Dr M Ashraf Chughtai Today’s Topics Recap: Main memory and Virtual memory Design Virtual Memory Address Translation Virtual Memory Performance Protection of multiple processes sharing memory Summary MAC/VU-Advanced Computer Architecture Lec 33 Memory Hierarchy Design (9) Recap: Memory Hierarchy Main memory organization Organized using banks of memory arrays Dual Inline Memory Modules - DIMMs Fast page mode Synchronous Double Data Rate DRAMs MAC/VU-Advanced Computer Architecture Lec 33 Memory Hierarchy Design (9) Recap: Main Memory Performance Fast page mode Synchronous DRAM (SDRAM) Double Data Rate (DDR) DRAM latency and bandwidth MAC/VU-Advanced Computer Architecture Lec 33 Memory Hierarchy Design (9) Recap: Main Memory Performance concern of caches bandwidth Inputs/outputs and multiprocessors Wider Main Memory Simple Interleaved Memory Independent Memory Banks MAC/VU-Advanced Computer Architecture Lec 33 Memory Hierarchy Design (9) Recap: Virtual Memory Multiple processes Dedicate a full address space Virtual Memory MAC/VU-Advanced Computer Architecture Lec 33 Memory Hierarchy Design (9) Recap: Virtual Memory … Cont’d MAC/VU-Advanced Computer Architecture Lec 33 Memory Hierarchy Design (9) Recap: Virtual Memory … Cont’d Fix-sized fragment Variable-sized fragment Contiguous pages in virtual memory Physically available on the main memory MAC/VU-Advanced Computer Architecture Lec 33 Memory Hierarchy Design (9) Recap: Virtual Memory Cont’d Protection and Relocation Protection Relocation MAC/VU-Advanced Computer Architecture Lec 33 Memory Hierarchy Design (9) Recap: Cache verses Virtual memory Page fault or address fault – CPU produces virtual address – Mapping of a virtual address – MAC/VU-Advanced Computer Architecture Lec 33 Memory Hierarchy Design (9) 10 Summary Cache memories: HW-management Separate instruction and data caches permits simultaneous instruction fetch and data access Four questions: – Block placement – Block identification – Block replacement – Write strategy MAC/VU-Advanced Computer Architecture Lec 33 Memory Hierarchy Design (9) 39 Summary Virtual memory: – Software-management – Very high miss penalty => miss rate must be very low Also supports: – program loading – memory protection – Multiprogramming MAC/VU-Advanced Computer Architecture Lec 33 Memory Hierarchy Design (9) 40 Summary Memory hierarchy organization Modules of DRAM and SRAM design and working of disk storages DRAM, SRAM and Disk MAC/VU-Advanced Computer Architecture Lec 25 – Memory Hierarchy Design (1) 41 Recap: Memory Hierarchy Principles Concept of Caching Principle of Locality MAC/VU-Advanced Computer Architecture Lecture 27 Memory Hierarchy (3) 42 Recap: Principle of Locality Data or instructions Processor access a relatively small portion of the address space Fastest memory closet to the processor MAC/VU-Advanced Computer Architecture Lecture 27 Memory Hierarchy (3) 43 Recap: Types of Locality Temporal locality Spatial locality MAC/VU-Advanced Computer Architecture Lecture 27 Memory Hierarchy (3) 44 Recap: Improving Cache Performance ─ ─ ─ The miss penalty The miss rate The miss Penalty or miss rate via Parallelism ─ The time to hit in the cache MAC/VU-Advanced Computer Architecture Lecture 30 Memory Hierarchy (6) 45 Recap: Reducing Miss Penalty – Multilevel Caches – Critical Word first and Early Restart – Priority to Read Misses Over writes – Merging Write Buffers – Victim Caches MAC/VU-Advanced Computer Architecture Lecture 30 Memory Hierarchy (6) 46 Recap: Reducing Miss Penalty ‘Multi level caches’ the more the merrier MAC/VU-Advanced Computer Architecture Lecture 30 Memory Hierarchy (6) 47 Recap: Reducing Miss Penalty “ Critical Word First and Early Restart’, MAC/VU-Advanced Computer Architecture Lecture 30 Memory Hierarchy (6) 48 Recap: Reducing Miss Penalty ‘priority to read miss over the write miss’, Favoritism MAC/VU-Advanced Computer Architecture Lecture 30 Memory Hierarchy (6) 49 Recap: Reducing Miss Penalty ‘merging write-buffer,’ acquaintance “victim cache’ salvage MAC/VU-Advanced Computer Architecture Lecture 30 Memory Hierarchy (6) 50 Recap: Reducing Miss Penalty Reducing miss penalty Reducing miss rate Cache-misses and methods to reduce the miss rate MAC/VU-Advanced Computer Architecture Lecture 30 Memory Hierarchy (6) 51 Summary – Cache Optimization – – – – methods to reduce the miss penalty ways to reduce 3Cs methods for reducing miss rate and miss penalty via parallelism; and techniques to reduce hit time The performance of these methods is summarized here MAC/VU-Advanced Computer Architecture Lecture 31 Memory Hierarchy (7) 52 Allah Hafiz MAC/VU-Advanced Computer Architecture Lecture 31 Memory Hierarchy (7) 53 ... MAC/VU -Advanced Computer Architecture Lec 33 Memory Hierarchy Design (9) Recap: Virtual Memory … Cont’d MAC/VU -Advanced Computer Architecture Lec 33 Memory Hierarchy Design (9) Recap: Virtual Memory. .. MAC/VU -Advanced Computer Architecture Lec 33 Memory Hierarchy Design (9) 17 VM Address Translation Concept page offset page number MAC/VU -Advanced Computer Architecture Lec 33 Memory Hierarchy Design. .. bytes MAC/VU -Advanced Computer Architecture Lec 33 Memory Hierarchy Design (9) 33 Address Translation Example VA – L2 MAC/VU -Advanced Computer Architecture Lec 33 Memory Hierarchy Design (9) 34