Advanced Computer Architecture - Lecture 8: Computer hardware design

Advanced Computer Architecture - Lecture 8: Computer hardware design. This lecture will cover the following: multi cycle datapath and control design; example of single cycle design; multi cycle design - datapath; hardware design principles; controller FSM spec; sequencer-based control unit;...

CS 704 Advanced Computer Architecture Lecture Computer Hardware Design (Multi Cycle Datapath and Control Design) Prof Dr M Ashraf Chughtai Today’s Topics Recap: Single cycle datapath and control Example of Single Cycle Design Multi Cycle Design - Datapath Summary MAC/VU-Advanced Computer Architecture Lecture – Computer H/W Design (2) Recap: Lecture Basic building blocks of a computer: CPU, Memory and I/O sub-systems and Buses CPU sub-system: Datapath and control Phases of instruction performing: Fetch and Execute Datapath Designs: Uni-, 2- and 3-bus structures Micro-operations of Fetch and execute phases: - Fetch: MBR  M[PC]; PC PC+4; IR MBR - Exe: ID, operand read; exe; mem; WB 3-bus based single cycles data path – MIPS datapath Control signals for single cycles data path – Add Instruction MAC/VU-Advanced Computer Architecture Lecture – Computer H/W Design (2) A critical review of single cycle datapath and control signals Fetch Circuit Instruction Memory Address  nPC_sel 00 Adder imm16 PC Mux Adder PC Ext MAC/VU-Advanced Computer Architecture Instruction Clk address alignment at  the boundary of 4 Lecture – Computer H/W Design (2) A critical review of single cycle datapath and control signals … Cont’d Rt busA 32 32 Zero Rd MemWr Clk Imm16 MemtoReg 32 Data In 32 ALUSrc Rs WrEn Adr 32 Mux 16 Extender imm16 ALUctr ALU Rw Ra Rb 32 32­bit Registers busB 32 Rt Rs Mux 32 Clk Clk Mux RegWr busW Rt RegDst Rd Instruction Fetch Unit nPC_sel Instruction Data Memory ExtOp MAC/VU-Advanced Computer Architecture Lecture – Computer H/W Design (2) Control Signals for Add rd,rs,rt R[rd]  R[rs] + R[rt] RegWr = 1 16 Extender imm16 32 Rs Rd Imm16 MemtoReg = 0 Zero MemWr = 0 32 Data In 32 Clk WrEn Adr 32 Mux busA Rw Ra Rb 32 32 32­bit Registers busB 32 Rt Mux 32 Clk ALUctr = Add Rt ALU busW Rs Mux Clk Rt Rd Instruction Fetch Unit RegDst = 1 nPC_sel= +4 Instruction Data Memory ALUSrc = 0 MAC/VU-Advanced Computer Architecture ExtOp = x Lecture – Computer H/W Design (2) Instruction Fetch Unit at the End of Add PC