S5-1

A Framework for Layout-Level Logic Restructuring Hosung Leo Kim John Lillis Motivation: Logical-to-Physical Disconnect Logic-level Optimization fixed netlist disconnect Physical-level Optimization Limited by the structure obtained from the logic-level • Performance is determined largely by physicallevel Interconnect delay • Problem: timing optimization at logic-level ≠ actual performance Past Layout-Driven Restructuring Work: Replication Based • Basic Operations: – Gate Splitting – Fanout Partitioning; Enables “Path Straightening” • [Schabas, Brown ISFPGA03] • [Beraudo, Lillis DAC03] • [Hrkic, Lillis, Beraudo TCAD06] • [Chen, Cong ISFPGA05] Limitation of Logic Replication • While interconnect delay can be significantly reduced, the LUT-depth of a path remains unchanged • The LUT-depth is typically determined by a technology mapper which does not have an accurate view of critical paths Candidate: Remapping Other Work • Redundant Wires (e.g., [Chang, Cheng, Suaris, MarekSadowska DAC00]) ƒ rewire connections while keeping logical equivalence ƒ Predictable, but optimization scope limited • [Lin, Jagannathan, and Cong ISFPGA03] ƒ Remap based on placement-level timing analysis ƒ Significant restructuring, but placement of remapped cells determined by initial placement (not simultaneous) • [Singh and Brown Integration07] ƒ Shannon’s expansion / precomputation ƒ Allows late signals to skip logic levels, but relatively local in nature Objectives • Overcome limitations of basic replication (e.g., fixed LUT-depth) • Large and flexible remapping space • Explicitly account for placement freedom of remapped LUTs • Tight coupling with placement Components of Approach (FPGA Domain) Placement-Level Static Timing Analysis Timing-Critical Fan-in Cone Extraction Induce Replication Tree [Hrkic,TCAD06] Components of Approach (cont’d) Mapper and Recursive, Exhaustive Embedder Ashenhurst LUT (Dynamic Decomposition Replication Subject Graph Programming) tree (Choice Tree) A A i j k choice node a l B C a b c d e f g h l i i choice node g1 g2 g4 d g5 c d c j k l C g6 g7 c d g8 ab c d choice node h e e h fh e g g3 f g a b a bR i k i j k j (a) Given LUT-tree B j l k l b c d e (b) Choice tree f g h e cR f d Legalizer Remapping Example A A B B C d e d e g h f E m D i j k l C m D a E b c a b c h f g i j k l (b) “Mini-LUT” tree after LUT-decompositions (a) Given LUT-tree A′ A′ B′ d e E E d e C B′ m D a b c a C b c D h f g i j (c) Alternative mapping k l f g h i j k l (d) Corresponding LUT-tree m Functional Decomposition • Simple Disjoint Functional Decomposition xy • Test for decomposability – Ashenhurst’s theorem wz 0 0 1 0 1 1 g1 f bit (Simple) • Recursively decompose w x y z x y g2 disjoint w z Algorithms • Mini-LUT Tree Mapping • Fan-in Tree Embedding [Hrkic,TCAD06] • Simultaneous Remapping and Embedding Tree Embedding [Hrkic,TCAD06] a a bR topology bR arrival time R d pin locations c e e f (0,3) (0,2) Embedding Algorithm target layout graph cost metrics a cR arrival time (0,4) d f a d e bR e f d cR f Algorithms • Mini-LUT Tree Mapping • Fan-in Tree Embedding [Hrkic,TCAD06] • Simultaneous Remapping and Embedding Simultaneous Remapping and Embedding • Formulation – Given a “mini-LUT” tree with fixed leaves and root, and arrival time at the leaves, a target layout graph – Simultaneously map the tree to K-input LUTs and embed Solution Set J Si [u][v] • The remapped root produces signal u and is placed at v in the target layout graph