Slide thiết kế vi mạch chapter6 fsm

Digital Design with the Verilog HDL Chapter 6: Finite State Machine Dr Phạm Quốc Cường Use some Prof Mike Schulte’s slides (schulte@engr.wisc.edu) Computer Engineering – CSE – HCMUT CuuDuongThanCong.com https://fb.com/tailieudientucntt Sequential Machine - Definition • State of a sequential machine contains current information (t) • Next state (t + 1) depends on the current state (t) and inputs • The number of states in a sequential machine finite => Finite State Machine - FSM Input Next-state Logic Next state (NS) Feedback of present state CuuDuongThanCong.com Present State (PS) Memory Block Diagram of a sequential machine https://fb.com/tailieudientucntt Synchronous Sequential Machine • Synchronous State Machine uses clock to synchronize input states • Clock is symmetric or asymmetric • Clock cycle must be larger than time required for state transaction calculation • Synchronous FSMs: – Number of states – Using clock to control state transaction CuuDuongThanCong.com https://fb.com/tailieudientucntt FSM Models & Types • Explicit – Declares a state register that stores the FSM state – May not be called “state” – might be a counter! • Implicit – Describes state implicitly by using multiple event controls • Moore – Outputs depend on state only (synchronous) • Mealy – Outputs depend on inputs and state (asynchronous) – Outputs can also be registered (synchronous) CuuDuongThanCong.com https://fb.com/tailieudientucntt Mealy machine vs Moore machine Block Diagram of a Mealy sequential machine Block Diagram of a Moore sequential machine CuuDuongThanCong.com https://fb.com/tailieudientucntt State Transaction Graph • Finite state machine can be described: – State transaction graph, State transaction table – Time chart – Abstract state machine • Finite state machine is a directed graph – Vertices show states (+outputs if Moore-style machine) – Edges show transactions from state to state • Edges’ name – Mealy machine: input/output – Moore machine: input CuuDuongThanCong.com https://fb.com/tailieudientucntt State Diagram a=0 S0 b=0 a = 1/ Z=1 reset = S1 Y=1 b = 1/ Z=1 S2 • Outputs Y and Z are 0, unless specified otherwise • We don’t care about the value of b in S0, or the value of a in S1, or either a or b in S2 CuuDuongThanCong.com https://fb.com/tailieudientucntt State Diagram: Mealy a=0 b = x/ Y = 0, Z=0 S0 a=1 b = x/ Y = 0, Z=1 reset = ab = xx/ YZ = 00 a=x b = 0/ Y = 1, Z=0 S1 • Outputs Y and Z are 0, unless specified otherwise • We don’t care about the value of b in S0, or a = x the value of a in S1, or b = 1/ either a or b in S2 Y = 1, S2 Z = CuuDuongThanCong.com https://fb.com/tailieudientucntt State Diagram: Moore a=0 S0 b=0 a=1 S1 Y=1 Outputs Y and Z are 0, unless specified otherwise If an input isn’t listed for a transition, we don’t care about its value for that transition b=1 reset = S2 Z=1 CuuDuongThanCong.com https://fb.com/tailieudientucntt Example - Mealy Next state/Output table reset Next state/output S_0 0/1 State 1/0 1/0 S_1 S_2 0/1 0/0 1/1 S_3 0/0 1/1 S_4 0/0, 1/1 0/1 S_5 S_6 0/1 State transition graph S_0 S_1 S_2 S_3 S_4 S_5 S_6 input S_1/1 S_3/1 S_4/0 S_5/0 S_5/1 S_0/0 S_0/1 S_2/0 S_4/0 S_4/1 S_5/1 S_6/0 S_0/1 -/- State transition table 10 CuuDuongThanCong.com https://fb.com/tailieudientucntt Input/output Relation Bin = (BCD) Bout = (Excess-3) 1 0 LSB MSB Excess-3 Code converter MSB 0 0 1 MSB clock 1 LSB Input-output bit stream in a BCD to Excess-3 serial code converter 14 CuuDuongThanCong.com https://fb.com/tailieudientucntt State Transaction Graph – State Transaction Table Next state/Output table reset Next state/output S_0 0/1 State 1/0 input 1/0 S_1 S_2 S_0 S_1 S_2 S_3 S_4 S_5 S_6 0/1 0/0 1/1 S_3 0/0 1/1 S_4 0/0, 1/1 0/1 S_5 S_6 0/1 State transition graph (Mealy type FSM) S_1/1 S_3/1 S_4/0 S_5/0 S_5/1 S_0/0 S_0/1 S_2/0 S_4/0 S_4/1 S_5/1 S_6/0 S_0/1 -/- State transition table (Mealy type FSM) 15 CuuDuongThanCong.com https://fb.com/tailieudientucntt State Encoding • States are stored by FFs Encoded Next state/output table • states, using FFs State Next state q2q1q0 q2 + q1 + q0+ State assignment Input q2q1q0 State 000 S_0 S_0 001 S_1 010 S_6 011 S_4 100 101 S_2 110 S_5 111 S_3 CuuDuongThanCong.com Output Input 1 000 001 101 S_1 001 111 011 S_2 101 011 011 S_3 111 110 110 S_4 011 110 010 S_5 110 000 000 S_6 010 000 - - 100 https://fb.com/tailieudientucntt - - - - 16 Simplify State Transaction Function q0Bin 00 01 11 10 00 1 1 01 X 11 0 10 X X q2q1 q0Bin 00 01 11 10 00 0 1 01 X 1 0 11 0 1 1 10 X X 1 q2q1 q0 + = q ’ q0Bin q1 + = q 00 01 11 10 00 1 01 X 11 0 10 X X q2q1 00 01 11 10 00 0 1 01 X 1 11 1 0 10 X X q2+ = q1’q0’Bin + q2’q0Bin’ + q2q1q0 CuuDuongThanCong.com q0Bin q2q1 Bout = q1’Bin’ + q2Bin https://fb.com/tailieudientucntt 17 Implementing BCD to Excess-3 Converter 18 CuuDuongThanCong.com https://fb.com/tailieudientucntt FSM Example: Serial-Line Code Converter • signals: – Clock – Handshaking signal – Data • Well-known encoding algorithms: – NRZ – NRZI: if input is 1, the previous output value is inversed while input keeps output unchanged – RZ: if input is 1, output is during the first half cycle and during the second half cycle while input produces output – Manchester: if input is 0, output is during the first half cycle and during the second half cycle while input produces output during the first half and output during the second half 19 CuuDuongThanCong.com https://fb.com/tailieudientucntt Serial Encoding Examples • Clock_2’s frequency is double clock_1’s frequency to implement the NRZI, RZ, and Manchester encoding algorithms 20 CuuDuongThanCong.com https://fb.com/tailieudientucntt Mealy FSM for Serial Encoding • The Manchester algorithm – Waiting state (S_0) – Just receiving state (S_2) – Just receiving state (S_1) 1/0 Next State/Output 0/1 S_2 S_0 State S_1 1/1 Input S_1/0 S_0/1 - S_2/1 S_0/0 0/0 State Next State q1q0 q1+q0+ S_0 S_1 S_2 Output Input Output q0 1 q1 S_0 00 01 10 S_0 S_1 S_1 01 00 00 - S_2 10 00 00 - S_2 CuuDuongThanCong.com 21 https://fb.com/tailieudientucntt Implementing the Mealy FSM Bin 00 01 11 10 q1q0 Bin 00 01 1 - - 11 - - 0 10 0 00 0 01 - - 11 0 10 q1+ = q1’ q0’Bin CuuDuongThanCong.com q1q0 Bin 0 q0+ = q1’ q0’Bin q1q0 Bout = q1’( q0 + Bin) https://fb.com/tailieudientucntt 22 Moore FSM for Serial Encoding • The Manchester Algorithm – – – – S_0: starting/second half of the cycle receiving 1, the output is S_1: first half of the cycle receiving 0, the output is S_2: second half of the cycle receiving 0, the output is S_3: first half of the cycle receiving 1, the output is State Input S_0 S_1 S_3 S_2 S_0/0 Next State/Output S_1/0 S_2/1 S_1/0 S_3/1 S_0/1 S_3/0 State Next State q1q0 q1+q0+ S_3/1 Output Input CuuDuongThanCong.com S_0 00 01 11 S_1 01 10 _ S_3 11 _ 00 11 https://fb.com/tailieudientucntt S_2 10 23 01 S_1/0 S_2/1 Implementing the Moore FSM Bin 00 01 X 11 - 10 q1q0 Bin 00 0 01 1 q1 q1+ = q1’ q0’Bin Bin 00 1 01 - 11 - 10 1 q1q0 CuuDuongThanCong.com https://fb.com/tailieudientucntt 24 Simplify Equivalent States • Two states are equivalent: – Output and the next states are the same in all inputs (c1) – Can be combined together without any changed behavior (c2) • Reducing two equivalent states reduces hardware cost • Each FSM has one and only one simplest equivalent FSM Next state Output Input Input State 1 S_0 S_1 S_2 S_3 S_4 S_5 S_6 S_7 S_6 S_1 S_2 S_7 S_7 S_7 S_0 S_4 S_3 S_6 S_4/S_ S_3 S_2 S_2 S_1 S_3 0 0 0 0 1 0 0 Equivalents states New state 25 CuuDuongThanCong.com https://fb.com/tailieudientucntt Simplify Equivalent States Algorithm • Step 1: Find basic equivalent states (c1) 0/0 0/0 S_1 S_1 1/0 1/1 1/0 0/0 1/1 S_6 S_0 0/0 S_4 is equivalent to S_5 0/0 S_6 S_0 0/0 1/0 1/0 1/1 S_4 S_3 0/0 1/0 0/0 1/0 1/1 0/0 0/0 S_7 0/0 0/0 S_2 1/0 S_5 0/0 26 CuuDuongThanCong.com S_3 0/0 1/0 1/1 S_2 1/1 S_4 0/0 https://fb.com/tailieudientucntt S_7 1/0 Simplify Equivalent States Algorithm • Step 2: Create a possible equivalent states table (c2) – Let impossible equivalent cells be empty – Fill conditions upon which two corresponding states can be equivalent S_1 S_0 tương đương S_1 S_2 S_6 S_4 S_3 S_1 S_7 S_6 S_3 S_2 S_1 tương đương S_6 S_4 tương đương S_2 S_7 S_4 S_3 S_4 S_6 S_7 S_3 S_2 S_6 S_3 S_1 S_7 S_0 S_2 S_1 S_7 S_6 S_4 S_2 S_3 S_0 S_4 S_1 S_3 S_4 S_6 S_0 S_1 S_2 S_3 Next state Outp ut Input Inpu t Stat e 1 S_0 S_1 S_2 S_3 S_4 S_6 S_7 S_6 S_1 S_2 S_7 S_7 S_0 S_4 S_3 S_6 S_4 S_3 S_2 S_1 S_3 0 0 0 0 1 0 27 CuuDuongThanCong.com https://fb.com/tailieudientucntt Simplify Equivalent States Algorithm • Step 3: Consider equivalent conditions of any two states, delete corresponding cell if the cell contains any inequivalent couple S_1 S_2 S_6 S_4 S_3 S_1 S_7 S_6 S_3 1/1 S_0  S_7 S_1  S_2 S_4  S_6 S_4 0/0 1/1 0/0 S_2 S_7 S_4 S_3 1/0 S_2 S_4 S_6 S_7 S_3 S_2 S_6 S_3 S_1 S_7 S_0 S_2 S_1 S_7 S_6 S_4 S_2 S_3 S_0 S_4 S_1 S_3 S_4 S_6 S_0 CuuDuongThanCong.com S_3 0/0 0/0 S_1 S_2 S_3 https://fb.com/tailieudientucntt 28 S_7 1/0 ... https://fb.com/tailieudientucntt Mealy FSM for Serial Encoding • The Manchester algorithm – Waiting state (S_0) – Just receiving state (S_2) – Just receiving state (S_1) 1/0 Next State/Output... https://fb.com/tailieudientucntt 22 Moore FSM for Serial Encoding • The Manchester Algorithm – – – – S_0: starting/second half of the cycle receiving 1, the output is S_1: first half of the cycle receiving 0, the output... combined together without any changed behavior (c2) • Reducing two equivalent states reduces hardware cost • Each FSM has one and only one simplest equivalent FSM Next state Output Input Input State