Slide thiết kế vi mạch chapter1 digital design review

Digital Design with the Verilog HDL Chapter 1: Digital Design Review Dr Phạm Quốc Cường Computer Engineering – CSE – HCMUT CuuDuongThanCong.com https://fb.com/tailieudientucntt Technology Tradeoffs Full-Custom IC Market Volume to Amortize Standard Cells Time to Prototype FPGAs, Gate Arrays PLDs Non-Recurring Engineering (NRE) Cost Process complexity Density, speed, complexity CuuDuongThanCong.com https://fb.com/tailieudientucntt Design Methodology Design Specification Design Partition Design Entry: Verilog Behavioral Modeling Simulation / Functional Verification Design Integration and Verification Pre-Synthesis Sign-Off Synthesize and Map Gate-Level Netlist Post-Synthesis Design Validation 10 11 Post-Synthesis Timing Verification Test Generation and Fault Simulation Extract Parasitics 13 Design Sign-Off 14 Cell Placement, Scan Chain and Clock Tree Insertion, Cell Routing Production-Ready Masks Verify Physical and Electrical Design Rules 12 Verilog-based CuuDuongThanCong.com https://fb.com/tailieudientucntt Combinational – Sequential Logic • Combinational logic: – The outputs at any time, t, are a function of only the inputs at time t a b c d y1 Combinational y2 Logic y3 • Sequential logic: – The outputs at time t are a function of the inputs at time t and the outputs at time t-1 a b c y1 Sequential y2 Circuit y3 CuuDuongThanCong.com https://fb.com/tailieudientucntt Transistor • nMos • pMos CuuDuongThanCong.com https://fb.com/tailieudientucntt CMOS Technology • Complementary metaloxide semiconductor • Outputs are always either or Invert gate pMos Pull-up network Input Output nMos Pull-down network NAND gate NOR gate CuuDuongThanCong.com https://fb.com/tailieudientucntt Parallel and Serial • nMOS: = ON • pMOS: = ON a a g1 g2 g2 b (b) a 1 1 a b b b b OFF OFF OFF ON a a g1 a b (a) a a a a 0 1 1 • Series: all transistors are on • Parallel: at least one transistor is on g1 g2 b (c) b b b ON OFF OFF OFF g1 g2 b (d) a 0 a b CuuDuongThanCong.com a a a 1 b b b b OFF ON ON ON a a a a 0 1 1 b b b b ON ON ON OFF7 https://fb.com/tailieudientucntt The “Conduction Complement” Rule • CMOS gate’s output is always either or • For example: NAND A Y – Y=0 if and only if both inputs are B – Y=1 if and only at least one input is – pMos transistors are parallel while nMos transistors are serial • The “Conduction Complements” rule – The pull-up network always complements the pull-down network – Parallel → Serial, Serial → Parallel CuuDuongThanCong.com https://fb.com/tailieudientucntt CMOS Inverter A VDD Y A A Y Y GND CuuDuongThanCong.com https://fb.com/tailieudientucntt CMOS Inverter A VDD Y OFF A=1 Y=0 ON A Y GND 10 CuuDuongThanCong.com https://fb.com/tailieudientucntt CMOS NAND Gate A 0 1 B 1 Y Y A B 12 CuuDuongThanCong.com https://fb.com/tailieudientucntt CMOS NAND Gate A 0 1 B 1 Y ON A=0 B=0 ON Y=1 OFF OFF 13 CuuDuongThanCong.com https://fb.com/tailieudientucntt CMOS NAND Gate A 0 1 B 1 Y 1 OFF A=0 B=1 ON Y=1 OFF ON 14 CuuDuongThanCong.com https://fb.com/tailieudientucntt CMOS NAND Gate A 0 1 B 1 Y 1 ON OFF Y=1 A=1 B=0 ON OFF 15 CuuDuongThanCong.com https://fb.com/tailieudientucntt CMOS NAND Gate A 0 1 B 1 Y 1 OFF OFF Y=0 A=1 B=1 ON ON 16 CuuDuongThanCong.com https://fb.com/tailieudientucntt CMOS NOR Gate A 0 1 B 1 Y 0 A B Y 17 CuuDuongThanCong.com https://fb.com/tailieudientucntt 3-input NAND Gate • Y is if and only if ALL inputs are • Y is if and only if AT LEAST one input is Y A B C 18 CuuDuongThanCong.com https://fb.com/tailieudientucntt Design CMOS Gates • Example: – Using the CMOS Technology, draw transistor structure of a 4-input NOR gate A B C D Y 19 CuuDuongThanCong.com https://fb.com/tailieudientucntt Design CMOS Gate (cont.) • Example (Homework): – Using the CMOS Technology, draw transistor structure of a 4-input NAND gate 20 CuuDuongThanCong.com https://fb.com/tailieudientucntt Compound Gates • Compound gates: can describe any inverter function (not function) 21 CuuDuongThanCong.com https://fb.com/tailieudientucntt Example: AOI22 Y = ( A • B) + (C • D) A C A C B D B D (a) A (b) B C D (c) C D A B (d) C D A B A B C D Y A C B D Y (f) (e) CuuDuongThanCong.com 22 https://fb.com/tailieudientucntt AOI22 • Use AND/OR gate to implement? – 20 transitors 23 CuuDuongThanCong.com https://fb.com/tailieudientucntt Example: O3AI Y= ( A + B + C) • D A B C D Y D A B C 24 CuuDuongThanCong.com https://fb.com/tailieudientucntt Standard Cells • • • • Library of common gates and structures (cells) Decompose hardware in terms of these cells Arrange the cells on the chip Connect them using metal wiring … 25 CuuDuongThanCong.com https://fb.com/tailieudientucntt FPGAs • • • • • “Programmable” hardware Use small memories as truth tables of functions Decompose circuit into these blocks Connect using programmable routing SRAM bits control functionality FPGA Tiles P P2 P4 P6 P8 P1 P3 OUT P5 P7 I1 I2 I3 CuuDuongThanCong.com https://fb.com/tailieudientucntt 26 ... https://fb.com/tailieudientucntt Design Methodology Design Specification Design Partition Design Entry: Verilog Behavioral Modeling Simulation / Functional Verification Design Integration and Verification... Map Gate-Level Netlist Post-Synthesis Design Validation 10 11 Post-Synthesis Timing Verification Test Generation and Fault Simulation Extract Parasitics 13 Design Sign-Off 14 Cell Placement, Scan... https://fb.com/tailieudientucntt Design CMOS Gates • Example: – Using the CMOS Technology, draw transistor structure of a 4-input NOR gate A B C D Y 19 CuuDuongThanCong.com https://fb.com/tailieudientucntt Design CMOS