Digital Design with the Verilog HDL Chapter 6: FSM with Verilog Dr Phạm Quốc Cường Computer Engineering – CSE – HCMUT CuuDuongThanCong.com https://fb.com/tailieudientucntt Explicit State Machines • Declare registers to store explicit states • Combination logic circuit controls states • Verilog: – Edge-trigger behaviour synchronizing the states – Level-trigger behaviour describing the next states and output logic CuuDuongThanCong.com https://fb.com/tailieudientucntt Mealy machine vs Moore machine Block Diagram of a Mealy sequential machine Block Diagram of a Moore sequential machine CuuDuongThanCong.com https://fb.com/tailieudientucntt BCD to Excess-3 Converter - FSM Next state/Output table Next state/output State S_0 S_1 S_2 S_3 S_4 S_5 S_6 State transition graph input S_1/1 S_3/1 S_4/0 S_5/0 S_5/1 S_0/0 S_0/1 S_2/0 S_4/0 S_4/1 S_5/1 S_6/0 S_0/1 -/- State transition table CuuDuongThanCong.com https://fb.com/tailieudientucntt BCD to Excess-3 Converter - Verilog module BCD_to_Excess3(B_out, B_in, clk, reset); input B_in, clk, reset; output B_out; parameter S_0 = 3’b000, //state encoding S_1 = 3’b001, S_2 = 3’b101, S_3 = 3’b111, S_4 = 3’b011, S_5 = 3’b110, S_6 = 3’b010, dont_care_state = 3’bx, dont_care_out = 1’bx; reg [2:0] state, next_state; reg B_out; always @(posedge clk, negedge reset) //edge-trigger behaviour if (reset == 1’b0) state