cmos analog integrated circuits amplifers comparators multipliers filters and oscillators pdf

CMOS Analog Integrated Circuits Amplifiers, Comparators, Multipliers, Filters, and Oscillators www.TechnicalBooksPDF.com www.TechnicalBooksPDF.com CMOS Analog Integrated Circuits Amplifiers, Comparators, Multipliers, Filters, and Oscillators Tertulien Ndjountche www.TechnicalBooksPDF.com CRC Press Taylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300 Boca Raton, FL 33487-2742 © 2019 by Taylor & Francis Group, LLC CRC Press is an imprint of Taylor & Francis Group, an Informa business No claim to original U.S Government works Printed on acid-free paper Version Date: 20180813 International Standard Book Number-13: 978-1-138-59972-7 (Hardback) International Standard Book Number-13: 978-1-138-59973-4 (Hardback) This book contains information obtained from authentic and highly regarded sources Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use The authors and publishers have attempted to trace the copyright holders of all material reproduced in this publication and apologize to copyright holders if permission to publish in this form has not been obtained If any copyright material has not been acknowledged please write and let us know so we may rectify in any future reprint Except as permitted under U.S Copyright Law, no part of this book may be reprinted, reproduced, transmitted, or utilized in any form by any electronic, mechanical, or other means, now known or hereafter invented, including photocopying, microfilming, and recording, or in any information storage or retrieval system, without written permission from the publishers For permission to photocopy or use material electronically from this work, please access www.copyright.com (http://www.copyright.com/) or contact the Copyright Clearance Center, Inc (CCC), 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400 CCC is a not-for-profit organization that provides licenses and registration for a variety of users For organizations that have been granted a photocopy license by the CCC, a separate system of payment has been arranged Trademark Notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identification and explanation without intent to infringe Visit the Taylor & Francis Web site at http://www.taylorandfrancis.com and the CRC Press Web site at http://www.crcpress.com www.TechnicalBooksPDF.com Contents Preface New to this edition Content overview Acknowledgments MOS Transistors 1.1 Transistor structure 1.1.1 I-V characteristics of MOS transistors 1.1.2 Drain current in the strong inversion approximation 1.1.3 Drain current in the subthreshold region 1.1.4 MOS transistor capacitances 1.1.5 Scaling effects on MOS transistors 1.2 Transistor SPICE models 1.2.1 Electrical characteristics 1.2.2 Temperature effects 1.2.3 Noise models 1.3 Drain-source current valid in all regions of operation 1.4 Small-geometry effects 1.5 Design-oriented MOSFET models 1.5.1 Small-signal transconductances 1.5.2 Transistor parameters in various CMOS technologies 1.5.3 Capacitances 1.6 Summary 1.7 Circuit design assessment Bibliography xi xii xii xiv 10 12 13 13 19 20 23 32 34 37 37 38 48 48 55 Physical Design of MOS Integrated Circuits 2.1 MOS transistors 2.1.1 MOS field-effect transistor 2.1.2 Fin field-effect transistor 2.2 Passive components 2.2.1 Capacitors 2.2.2 Resistors 2.2.3 Inductors 2.3 Integrated-circuit (IC) interconnects 57 58 58 59 61 61 64 65 67 v www.TechnicalBooksPDF.com vi Contents 2.4 2.5 2.6 2.7 Physical design considerations IC packaging Summary Circuit design assessment Bibliography 69 75 75 76 81 Bias and Current Reference Circuits 3.1 Current mirrors 3.1.1 Simple current mirror 3.1.2 Cascode current mirror 3.1.3 Low-voltage active current mirror 3.2 Current and voltage references 3.2.1 Supply-voltage independent current and voltage references 3.2.2 Bandgap references 3.2.2.1 Low-voltage bandgap voltage reference 3.2.2.2 Curvature-compensated bandgap voltage reference 3.2.3 Floating-gate voltage reference 3.3 Summary 3.4 Circuit design assessment Bibliography 83 84 84 86 99 100 103 107 110 112 114 116 116 125 CMOS Amplifiers 4.1 Differential amplifier 4.1.1 Dynamic range 4.1.2 Source-coupled differential transistor pair 4.1.3 Current mirror 4.1.4 Slew-rate limitation 4.1.5 Small-signal characteristics 4.1.6 Offset voltage 4.1.7 Noise 4.1.8 Operational amplifier 4.2 Linearization techniques for transconductors 4.3 Transconductor operating in the subthreshold region 4.4 Single-stage amplifier 4.5 Folded-cascode amplifier 4.6 Fully differential amplifier architectures 4.6.1 Fully differential folded-cascode amplifier 4.6.1.1 Basic structure 4.6.1.2 Gain-enhanced structure 4.6.2 Telescopic amplifier 4.6.3 Common-mode feedback circuits www.TechnicalBooksPDF.com 127 128 129 131 133 134 135 140 143 145 148 163 165 167 172 172 172 175 180 183 vii Contents 4.6.3.1 Continuous-time common-mode feedback circuit 4.6.3.2 Switched-capacitor common-mode feedback circuit 4.6.4 Pseudo fully differential amplifier 4.7 Multistage amplifier structures 4.7.1 Output stage 4.7.2 Two-stage amplifier 4.7.3 Optimization of a two-pole amplifier for fast settling response 4.7.4 Three-stage amplifier 4.8 Rail-to-rail amplifiers 4.8.1 Amplifier with a class AB input stage 4.8.2 Two-stage amplifier with class AB output stage 4.8.3 Amplifier with rail-to-rail input and output stages 4.9 Amplifier characterization 4.9.1 Finite gain and bandwidth 4.9.2 Phase margin 4.9.3 Input and output impedances 4.9.4 Power-supply rejection 4.9.5 Slew rate 4.9.6 Low-frequency noise and dc offset voltage 4.9.6.1 Auto-zero compensation scheme 4.9.6.2 Chopper technique 4.10 Summary 4.11 Circuit design assessment Bibliography 185 189 192 194 195 206 213 216 231 232 235 235 239 239 240 240 240 241 242 245 248 253 253 275 Nonlinear Analog Components 281 5.1 Comparators 282 5.1.1 Amplifier-based comparator 282 5.1.2 Comparator using charge balancing techniques 289 5.1.3 Latched comparators 290 5.1.3.1 Static comparator 291 5.1.3.2 Dynamic comparator 295 5.2 Multipliers 307 5.2.1 Multiplier cores 309 5.2.1.1 Multiplier core based on externally controlled transconductances 310 5.2.1.2 Multiplier core based on the quarter-square technique 315 5.2.1.3 Design issues 322 5.2.2 Design examples 322 5.3 Summary 325 www.TechnicalBooksPDF.com viii Contents 5.4 Circuit design assessment Bibliography 326 335 Continuous-Time Circuits 6.1 Wireless communication system 6.1.1 Receiver and transmitter architectures 6.1.2 Frequency translation and quadrature multiplexing 6.1.3 Architecture of a harmonic-rejection transceiver 6.1.4 Amplifiers 6.1.4.1 Power amplifier 6.1.4.2 Low-noise amplifier 6.1.5 Mixer 6.1.6 Voltage-controlled oscillator 6.1.7 Automatic gain control 6.2 Continuous-time filters 6.2.1 RC circuits 6.2.2 MOSFET-C circuits 6.2.3 gm -C circuits 6.2.4 gm -C operational amplifier (OA) circuits 6.2.5 Summer circuits 6.2.6 Gyrator 6.3 Filter characterization 6.4 Filter design methods 6.4.1 First-order filter design 6.4.2 Biquadratic filter design methods 6.4.2.1 Signal-flow graph-based design 6.4.2.2 Gyrator-based design 6.4.3 Ladder filter design methods 6.4.3.1 LC ladder network-based design 6.4.3.2 Signal-flow graph-based design 6.5 Design considerations for continuous-time filters 6.5.1 Automatic on-chip tuning of continuous-time filters 6.5.2 Nonideal integrator 6.6 Frequency-control systems 6.6.1 Phase-locked-loop-based technique 6.6.1.1 Operation principle 6.6.1.2 Architecture of the master: VCO or VCF 6.6.1.3 Phase detector 6.6.1.4 Implementation issues 6.6.2 Charge comparison-based technique 6.7 Quality-factor and bandwidth control systems 6.7.1 Magnitude-locked-loop-based technique 6.7.2 Envelope detection-based technique 6.8 Practical design considerations www.TechnicalBooksPDF.com 339 340 342 345 351 352 353 362 374 377 394 401 403 405 407 409 412 413 415 416 418 420 420 423 426 426 430 434 434 435 437 437 437 438 438 439 440 442 442 444 448 ix Contents 6.9 Other tuning strategies 6.9.1 Tuning scheme using an external resistor 6.9.2 Self-tuned filter 6.9.3 Tuning scheme based on adaptive filter technique 6.10 Summary 6.11 Circuit design assessment Bibliography 450 450 451 453 456 456 479 Switched-Capacitor Circuits 7.1 Anti-aliasing filter 7.2 Capacitors 7.3 Switches 7.3.1 Switch description 7.3.2 Switch error sources 7.3.3 Switch compensation techniques 7.4 Programmable capacitor arrays 7.5 Operational amplifiers 7.6 Track-and-hold (T/H) and sample-and-hold (S/H) circuits 7.6.1 Open-loop T/H circuit 7.6.2 Closed-loop T/H circuits 7.7 Switched-capacitor (SC) circuit principle 7.8 SC filter design 7.8.1 First-order filter 7.8.2 Biquad filter 7.8.3 Ladder filter 7.9 SC ladder filter based on the LDI transform 7.10 SC ladder filter based on the bilinear transform 7.10.1 RLC filter prototype-based design 7.10.2 Transfer function-based design of allpass filters 7.11 Effects of the amplifier finite gain and bandwidth 7.11.1 Amplifier dc gain 7.11.2 Amplifier finite bandwidth 7.11.2.1 Inverting integrator 7.11.2.2 Noninverting integrator 7.12 Settling time in the integrator 7.13 Amplifier dc offset voltage limitations 7.14 Computer-aided analysis of SC circuits 7.15 T/H and S/H circuits based on the SC circuit principle 7.16 Circuit structures with low sensitivity to nonidealities 7.16.1 Integrators 7.16.2 Gain stages 7.17 Low supply voltage SC circuits 7.18 Summary 7.19 Circuit design assessment www.TechnicalBooksPDF.com 487 488 490 491 491 493 497 499 500 502 508 510 511 517 518 519 527 528 537 537 543 546 547 550 550 552 553 556 556 560 565 566 572 577 581 581 639 Signal Flow Graph It can be deduced that the aforementioned RC circuit is a second-order lowpass filter, whose transfer function only exhibits finite poles Z2 Z1 Vi −R /Z L I− V0 V− −AV − R0 + − Vi V − 1/Z I − R0 V0 ZL −Z (a) (b) −1/Z −A FIGURE B.4 (a) Equivalent model of an amplifier and (b) its SFG representation As a second example of circuit analysis using Mason’s gain formula, consider the equivalent model of an amplifier shown in Figure B.4(a) Using Kirchhoff’s laws, the following equations can be derived: V − = Vi − Z1 I − (B.13) I− = (B.14) V − − V0 Z2 V0 = −AV − + R0 I − − V0 ZL (B.15) The corresponding SFG representation is obtained as illustrated in Figure B.4(b) Four individual loops can be identified Their gains are of the form P11 = −Z1 /Z2 , P21 = −R0 /Z2 , P31 = −AZ1 /Z2 , and P41 = −R0 /ZL We also have P12 = Z1 R0 /Z2 ZL because the loops P11 and P41 are nontouching The term △ is then given by △ = − (P11 + P21 + P31 + P41 ) + P12 = + Z1 /Z2 + R0 /Z2 + AZ1 /Z2 + R0 /ZL + Z1 R0 /Z2 ZL (B.16) (B.17) The SFG exhibits two forward paths, whose gains can be written as, T1 = −A and T2 = R0 /Z2 Each forward path has a common node with all loops, and it can then be found that △1 = and △2 = Therefore, the transfer function between the input and output nodes reads T = V0 T △1 + T △2 = Vi △ Z2 =− · Z1 (B.18) R0 · A Z2 Z2 R0 R0 Z2 R0 1+ 1+ + + + A Z1 Z1 ZL Z1 ZL 1− (B.19) For a high gain, A, the transfer function is reduced to the ratio −Z2 /Z1 and an inverting amplifier is realized 640 B.3 Amplifiers, Comparators, Multipliers, Filters, and Oscillators Bibliography [1] S J Mason, “Feedback theory — Some properties of signal flow graphs," Proc of the IRE, vol 41, pp 1144–1156, Sept 1953 [2] S J Mason, “Feedback theory — Further properties of signal flow graph," Proc of the IRE, vol 44, pp 920–926, July 1956 C Notes on Track-and-Hold Circuit Analysis CONTENTS C.1 T/H transfer function 641 C.2 Bibliography 644 A track-and-hold (T/H) circuit samples a continuous-time signal by periodically capturing and holding signal levels Its transfer function can be derived as follows C.1 T/H transfer function Let vi (t) and v0 (t) be the input and output voltages, respectively, of the linear time-variant network characterized by the next equation dv0 (t) + Ak v0 (t) = Bk vi (t) for dt nT + σk−1 ≤ t ≤ nT + σk (C.1) where Ak and Bk are constant coefficients To proceed further, the output voltage can be expressed as K v0 (t) = v0,k (t) (C.2) k=1 where v0,k (t) = v0 (t)wk (t) (C.3) nT + σk−1 ≤ t ≤ nT + σk otherwise (C.4) and wk (t) = For a T/H circuit controlled by a sampling signal with the period T , Figure C.1 shows waveform plots, where the duration of the sampling and hold intervals are τ and T − τ , respectively For k = 2, σ1 = τ and σ2 = T The response of the linear time-variant network can be constrained to take the value zero outside the definition interval by disconnecting the input 641 642 Amplifiers, Comparators, Multipliers, Filters, and Oscillators Vi t VC σk σ k−1 τ V0 t T v k+1 vk tk t k+1 t FIGURE C.1 T/H waveform representation source and subtracting the final conditions at the interval end [1,2,3] Hence, for −∞ ≤ t ≤ ∞, we have dv0,k (t) = Ak v0,k (t) + Bk vi,k (t) dt ∞ + (C.5) [v0 (t)δ(t − nT − σk−1 ) − v0 (t)δ(t − nT − σk )] n=−∞ where vi,k (t) = vi (t)wk (t) (C.6) and δ(t) is known as the delta or unit impulse function Equation (C.5) can be solved using the Fourier transform because it is valid for all t Hence, (jω − Ak )V0,k (ω) = Bk F [vi (t)wk (t)] + ∞ (F [v0 (t)δ(t − nT − σk−1 )] − F [v0 (t)δ(t − nT − σk )]) (C.7) n=−∞ and K V0 (ω) = V0,k (ω) (C.8) k=1 The multiplication of vi (t) and wk (t) in the time domain is transformed into a convolution product in the frequency domain That is, F [vi (t)wk (t)] = ∞ − e−jωs nτk −jωs nσk−1 e Vi (ω − nωs ) jnωs T n=−∞ (C.9) Assuming that the sampled output voltage and the input voltage are related 643 Notes on Track-and-Hold Circuit Analysis by Gk (ω) or the transfer function at the switching instant nT + σk , it can be shown that ∞ n=−∞ F [v0 (t)δ(t − nT − σk )] = ∞ (Gk (ω)F [vi (t)]) ∗ δ(ω − nωs ) n=−∞ e−jωs nσk T (C.10) where ∗ is the convolution operation Or equivalently, ∞ n=−∞ F [v0 (t)δ(t−nT −σk )] = ∞ Gk (ω−nωs ) n=−∞ e−jωs nσk Vi (ω−nωs ) (C.11) T Combining (C.7), (C.9), and (C.11), we obtain V0,k (ω) = ∞ n=−∞ Hn,k (ω)Vi (ω − nωs ) (C.12) where Hn,k (ω) = − e−jωs nτk −jωs nσk−1 Bk e jω − Ak jnωs T e−jωs nσk−1 e−jωs nσk + Gk−1 (ω − nωs ) − Gk (ω − nωs ) T T (C.13) The transfer function of the linear time-variant network is then of the form, K Hn (ω) = Hn,k (ω) (C.14) k=1 Note that K can be taken equal to for the T/H circuit Consider the next first-order differential equation dv0,k (t) + Ak v0,k (t) = Bk vi (t) dt (C.15) The output response can be obtained as t v0,k (t) = φk (t − t0 )v0,k (t0 ) + Bk φk (t) = eAk t t0 φk (t − τ )vi (τ )dτ (C.16) (C.17) where the initial condition is specified at the instant t0 In the case of a sinusoidal input voltage, vi (t) = ejωt , we have v0,1 (t) = e−ωc (t−t0 ) v0,1 (t0 ) + [ejω(t−t0 ) − e−ωc (t−t0 ) ]ejωt0 (C.18) + jω/ωc 644 Amplifiers, Comparators, Multipliers, Filters, and Oscillators during the sampling phase, where −A1 = B1 = 1/RC, and v0,2 (t) = v0,2 (t0 ) (C.19) during the hold phase, where A2 = B2 = Due to the fact that the output voltage is continuous, the initial value of an interval is equal to the final value of the previous interval Assuming that t0 = nT , we arrive at v0 ((n + 1)T ) = e−ωc τ v0 (nT ) + [ejωτ − e−ωc τ ]ejωnT + jω/ωc (C.20) Equation (C.20) can be considered as a first-order difference equation, whose solution is composed of steady-state and transient voltage terms After the transient voltage contribution has vanished, the frequency response remains only dependent on the steady-state voltage Using v0 ((n+1)T ) = v0 (nT )ejωT , the steady-state output voltage is obtained as v0 (nT ) = G(ω)ejωnT (C.21) where ejωτ − e−ωc τ + jω/ωc ejωT − e−ωc τ 1 − e−ωc τ e−jωτ −jω(T −τ ) = e + jω/ωc − e−ωc τ e−jωT G(ω) = (C.22) (C.23) The transfer function G(ω) can be modeled as a cascade of a first-order RC filter whose output is subtracted from its delayed and scaled version, and a network with the transfer function e−jω(T −τ ) /(1 − e−ωc τ e−jωT ) C.2 Bibliography [1] T Ström and S Signell, “Analysis of periodically switched linear circuits," IEEE Trans Circuits Syst I, vol 24, no 10, pp 531–541, Oct 1977 [2] A Opal and J Vlach, “Analysis and sensitivity of periodically switched linear networks," IEEE Trans Circuits Syst I, vol 36, no 4, pp 522–532, Apr 1989 [3] M C M Soer, E A M Klumperink, P.-T de Boer, F E van Vliet, and B Nauta, “Unified frequency-domain analysis of switched-series-RC passive mixers and samplers," IEEE Trans Circuits Syst I, vol 57, no 10, pp 2618–2631, Oct 2010 Index A Accumulation region, Active component, 116, 128, 430, 565 amplifier, 500 comparator, 281 multiplier, 281 transconductor, 407, 409 Active current mirror, 99 Active element transistor, Active filter, 402, 416, 426, 430, 474 Active load, 97, 168 ADC, see Analog-to-digital converter Admittance function, 432, 544, 545 Admittance matrix, 415 All-pole filter, 474 Allpass filter, 415, 426, 433, 471 first order, 420 gyrator, 426 high order, 431 second order, 423 Allpass network, 424 Amplifier, 50, 53, 606 1/f noise, 143, 244 active feedback, 221 bandwidth, 192, 254 cascode structure, 172 dc gain, 95, 171 design, 84 noise, 143, 145, 244 offset voltage, 95, 140, 143, 242, 244 operational, see Operational amplifier output stage active cascode, 176 thermal noise, 144 Amplifier-based comparator, 282 Analog multiplier, 281, 307, 332, 333 bandwidth, 281 cross-coupled transconductance stages, 310 dc characteristic, 323 distortion, 281 dynamic range, 281, 309, 320 low-voltage circuit, 315 quarter-square technique, 318 Analog-to-digital converter (ADC), 343 Anti-aliasing filter, 488 Approximation function, 416, 417 Attenuation, 415, 416 Auto-zero scheme, 245 residual offset voltage, 248 Automatic gain control (AGC), 352, 394, 397, 401 Automatic tuning, 340, 430, 435 Q tuning, 435, 443, 448 adaptive filter technique, 453 envelope detection technique, 444 frequency tuning, 435, 448 magnitude-locked loop, 442 master-slave technique, 435 master-slave tuning, 448 reference signal feedthrough, 449 B Bandgap, 20, 108 Bandgap reference, 107 curvature compensation, 114 parasitic bipolar devices, 115 proportional-to-absolute temperature, 110 self-biased, 109 645 646 temperature insensitivity, 107 Bandgap voltage, 108, 109 reversed, 111 Bandpass filter, 343, 348, 351, 423, 434, 451, 471 Bessel filter, 416, 417 Bilinear transform, 517, 539, 540 Bipolar transistor, 71, 72, 101, 107, 108, 111, 112, 114 base-emitter voltage, 108, 112 collector current, 107 forward-active region, 107 Biquad, 422, 438, 472, 522, 581, see also SC biquad gm -C circuit, 420 power-efficient, 522 RC circuit, 588 SC circuit, 521 bandpass, 524 Biquadratic filter, 417, 420, 438, 443, 444, 448, see also Biquad Body factor, 42 Boltzmann’s constant, 21, 22, 102, 105, 107, 144 Bootstrapped switch, 578 BSIM model, 19, 21, 34 Butterworth, 220, 223, 227 filter, 417 Index determinant, 529 two-pair network, 528 Channel length modulation, 32, 34 Charge conservation, 11, 41, 45, 48 Charge partition, 43 Charge-sheet formulation, 35, 42 Chebyshev filter, 417 Chopper technique, 248, 251 Clock signal, 495–517, 560, 562, 578 period, 539, 548, 562 two-phase nonoverlapping, 497, 560 CMF, see Common-mode feedback Common-mode feedback, 140, 172, 174, 180 based on two differential pairs, 185 source follower, 185 switched-capacitor circuit, 189 using an RC network, 185 Common-mode rejection ratio, 136 Comparator, 281, 282, 328, 444, 615 charge balancing technique, 289 hysteresis circuit, 289 input thresholds, 283 inverting, 283, 286 metastability, 282 noninverting, 282, 286 offset voltage, 283, 299 C output thresholds, 283 Capacitor, 2, 11, 20, 61 time delay, 296, 297 layout, 62 transfer characteristic, 284 MIM, 63 Complementary-to-absolute temperaMOM, 62 ture, 101, 108 MOSFET, 64 Correlated double sampling (CDS), Cascade, 402, 417, 426, 503, 517, 518, 488, 565 527 Coupled oscillator, 394 ordering, 426, 518 Current density, 626 Cascode, 175, 228 Current mirror, 83–86, 90–92, 95, 97 compensation, 224 active, 111 Cauer filter, 417 active cascode, 97, 120 CDS, see Correlated double sampling active-feedback cascode, 93, 94 Chain matrix, 529–531, 533 compliance voltage, 90 all-pole filter, 532 layout, 77 decomposition, 531 low voltage, 99 Index matching, 89, 93, 94 output impedance, 95 output resistance, 86 output swing, 83, 86, 95 regulated cascode, 92, 94, 95 self-biased cascode, 97, 98 Current reference, 100, 116 accuracy, 100 start-up circuit, 103 supply-voltage independent, 103 D DAC, see Digital-to-analog converter Delta-sigma modulator oscillator, 454 Demodulation, 345, 346 Depletion region, 3, 5, 10, 13, 49 capacitance, 6, 9, 16 charge, 5, 11, 49 Design rules λ rule, 70 micron rule, 70 Differential amplifier, 128, 139, 140, 147, 148, 172, 183, 185, 187, 260, 604 balanced, 140 layout, 78 Differential stage active cascode, 151 active source degeneration, 153 common-mode rejection ratio, 137 small-signal model, 135, 137 Diffusion resistor, 65 Digital signal processor (DSP), 343 Digital-to-analog converter (DAC), 343 Down-conversion, 348 Drain-induced barrier lowering, 19, 33, 34 DSP, see Digital signal processor Dynamic comparator, 291, 295, 299, 306, 307 E Early voltage, 14, 25, 29, 30, 34 647 Effective mobility, 18 Electromigration effect, 68 Electrostatic discharge (ESD), 370 Elliptic filter, see also Cauer filter, 427, 428, 476, 490 Envelope detector, 444 ESD, see Electrostatic discharge Excess phase, 382 Extrinsic capacitance, 38, 48 F Field region, 67 Figure of merit (FOM), 217, 384 Figure-of-merit (FOM), 384 Filter prototype, 416, 425, 528, 531, 537, 542, 591 specification, 415 stability, 415 transformation, 470 Filter transformation, 471 FinFET, 60 BSIM-CMG, 19 layout, 60 structure, 60 Flat-band voltage, 5, 8, 42 Floating-gate transistor, 115 erasing, 115 programming, 115 Folded-cascode amplifier, 174, 260, 610, 627 FOM, see Figure-of-merit Four-quadrant multiplication, 307 Fourier transform, 558 Fowler-Nordheim tunneling, 115 Frequency compensation, 172, 176, 206, 216, 217, 221, 265 Miller capacitors, 251 nested Miller, 218, 221 reversed nested Miller, 221, 266 Frequency translation, 348 Friis formula, 461 Fringing capacitance, 48 Full-wave rectifier, 444 648 Index G gm -C circuit, 407–409 Gain, 415, 416 MOSFET-C circuit, 405–406 Gain-bandwidth product, 216, 221, RC-circuit, 403 227 SC circuit, 512–516 Gate oxide thickness, 37 Interconnects, 57, 67, 68, 75 Group delay, 415, 417 equivalent model, 68 Guard ring, 72 parasitic effects, 69 Gyrator, 402, 413, 414, 420, 423 Intrinsic capacitance, 38, 48 small-signal model, 413 Inversion symbol, 413 charge, 45 coefficient, 27, 29, 36, 618, 619, H 621, 625, 626, 628 Hardware description language, 456 region, High speed, 26, 238, 281, 289, 291 Inverter, 371, 578 High-order filter, 417, 426 layout, 69 Highpass filter, 371, 419, 422, 470, 475 ISF, see Impulse sensitivity function Hot electron, 115 J Hurwitz polynomial, 432, 543 Jitter, 345, 507 Hysteresis, 284, 286, 289 Junction capacitance, 48 I Image rejection ratio (IRR), 350, 351 Image-rejection architectures Hartley, 349 Weaver, 349 Impedance matching, 369 Impulse sensitivity function (ISF), 382–384 Inductor, 65, 66 Input stage, 129, 130, 139, 166, 167, 175, 206, 221, 238 auxiliary inputs, 245 bias current, 241 class AB, 160, 234 gain, 242 rail-to-rail, 130, 235, 237 source follower, 234 Integrated circuit (IC) fabrication, 57, 67 interconnect, 67 packaging, 75 Integrator, 403 gm -C OA circuit, 409 active compensation, 411 passive compensation, 411 K Kirchhoff’s current law, 135–218, 225, 309–319, 379–428, 638 Kirchhoff’s voltage law, 90, 131–232, 308–320, 364, 506, 606, 638 L Ladder filter, 443, 531, 536, 540, 542, 590 Latch, 290, 294 D, 291, 616 kickback noise, 307 RS, 291 Latch-up effect, 71, 72 Latched comparator, 290 small-signal analysis, 292 Layout active, 58, 59, 70 common-centroid structure, 72, 75 design rules, 70 electrical rule checking, 70 floorplan, 74 LC network, 360, 378, 381, 427, 430 ladder, 426 Index LC VCO class B, 388 class C, 388 start-up, 378, 388 Least-mean square algorithm, 444 Level shifter, 145, 198, 333 Linear phase response, 417 Linear region, see Triode region Lithography, 57 LNA, see Low-noise amplifier Low-noise amplifier (LNA), 341, 343, 351, 362, 460 cascode structure, 364 common gate, 373 common source, 371, 372 inductively degenerated input, 372 pseudo-differential, 461 resistive feedback, 371 Lowpass filter, 343–401, 439, 444, 468, 470, 476 first order, 470 first-order gm -C circuit, 419 prototype, 489 second order, 422, 470, 590 third order, 427, 428, 476, 533 649 Moat region, 67 Mobility, 4, 9, 12, 17, 19, 21, 23, 32, 35, 42 constant, 17 degradation coefficient, 17 Moderate inversion, 36 Modulation, 345 MOS capacitor, 490–491 MOS transistor, 1, 600 ACM model, 35 Berkeley short-channel IGFET model (BSIM), 601 body effect, 14 BSIM model, 21, 34, 601 bulk, 2, 5, 11, 23 Fermi potential, capacitances, 10 extrinsic capacitance, 38 I-V characteristics, intrinsic capacitance, 38 inversion coefficient, 27, 29 noise, 20 short-channel effect, 17, 48 SPICE models, 13 structures, substrate, transconductance, 15, 23 M transconductance efficiency, 25, Matching network, 355, 360, 361 29 MATLAB, 456 Multiplier, see Analog multiplier Maximally flat response, 417 Multistage Metal-oxide-semiconductor field-effect amplifier, 216, 397 transistor (MOSFET), see comparator, 283 MOS transistor Metal-poly capacitor, 61 N Metastability, 282 NAND gate Miller layout, 77 effect, 170, 372 Negative resistance, 378–380 frequency compensation, 206, 213, Network, 424 217 doubly terminated, 417, 420 Minimal-reactance network, 540 impedance matching, 355 Mixed-signal integrated circuit input matching, 367, 369 substrate coupling, 72 lossless, 420 Mixer, 281, 343, 348, 350, 376 output matching, 361 single-balanced, 374 passive, 430 650 two-port, 414 Noise, 20, 143, 363, 365, 377, 497, 505 factor, 362, 460 figure, 362, 371 Norton’s theorem, 538 Notch filter, 423 second order highpass, 423 lowpass, 423 symmetrical, 423 O OA, see Operational amplifier Offset voltage, 140, 141, 143, 145, 242, 283, 290, 299, 300, 302, 306, 322, 326, 397, 399, 400, 447, 501, 556, 561, 563, 565, 567, 572, 581, 583 Operational amplifier auto-zeroing technique, 245–248 bandwidth, 128, 150, 167, 176, 177, 179, 209, 221, 239, 500 chopper technique, 245, 248–250 compensation network, 145 folded-cascode, 168, 169, 171, 255 frequency domain analysis, 172 gain enhancement, 176 small-signal model, 169 fully differential, 147, 175 gain, 500 gain-bandwidth product, 139, 167, 172, 175, 179, 194, 221, 224, 263, 264, 266, 267 gain-bandwidth trade-off, 206 linear output range, 501 noninverting, 115 offset voltage, 122, 501 phase margin, 171, 172, 175, 179, 180, 212, 215, 220, 224, 238, 240, 260, 264 pseudo-differential structure, 147 rail-to-rail input, 235–238 settling time, 175, 179, 192, 212, 213, 261, 501 minimum, 215, 220 Index single-ended, 145 slew rate, 134, 167, 175, 182, 209, 221, 224, 241, 256, 258, 260, 267, 500 specifications, 128 telescopic, 180, 182 three-stage, 217, 221, 224, 228 transconductance, 145 small-signal model, 138 two-stage, 206, 210, 213, 215 voltage-controlled voltage source, 500 Operational transconductance amplifier, 187, 546, 550–553 bandwidth, 550 voltage-controlled current source, 500 Ordering, 426, 518 Oscillation amplitude, 378, 388 frequency, 380 phase noise, 381 Oscillation period, 389 OTA, see Operational transconductance amplifier Output stage, 165, 169, 178, 194, 200, 203, 204, 206, 221, 235, 249 class A, 194, 199 class AB, 195, 201, 235, 238 class B, 195 common drain, 235 push-pull, 195 source follower, 198, 199, 251 Overdrive, 620 Overdrive voltage, 39 Overlap capacitance, 10, 48 Oxide overstress, 579 P PA, see Power amplifier Packaging, 75 PAE, see Power-added efficiency Passband, 416, 489 Passive element, 369, 378, 394, 469 capacitor, 61 651 Index inductor, 65 resistor, 65 Passive filter, 430 PCA, see Programmable capacitor array Peak detector, 443, 465 Phase, 415 shifter, 391–394, 456 Phase and frequency detector (PFD), 385 Phase detector, 437–439 analog multiplier, 437, 438 XOR gate, 437, 439 Phase margin, 172, 175, 215, 227 Phase shift network, 390, 392, 456 Photoresist, 57 Pinch-off voltage, 35 Poly, see Polycrystalline silicon Poly-diffusion capacitor, 61 Poly-poly capacitor, 61 Polycrystalline silicon, 2, 58, 59, 62, 65, 70 Polyphase filter, 392 Polysilicon, see Polycrystalline silicon Polysilicon resistor, 65 Power amplifier (PA), 341, 343, 352 class A, 354 class AB, 357, 360 class B, 356 class C, 357 class D, 358 class E, 358, 360 class F, 359 Power efficient, 500, 522 Power-added efficiency (PAE), 353, 361 Power-supply rejection ratio, 240 Prewarping, 590 Programmable capacitor array (PCA), 499, 500 Proportional-to-absolute temperature, 101, 108 R Reactance, 538, 540 Reactive element, 359 Receiver, 342 homodyne, 343 low-IF, 345 superheterodyne, 343 Reflection coefficient, 368 Resistor, 64 Reversed bandgap voltage, 112 Ripple, 416, 417 S S/H circuit, see Sample-and-hold circuit Sample-and-hold circuit frequency responses, 503 gain droop, 503 SC circuit, 560–565 unit-period delay, 503 Saturation coefficient, 48 current, 20 region, 7, 11, 14, 15, 17, 19, 21, 36 voltage, 25, 33, 36 SC biquad amplifier gain-bandwidth product, 527 capacitance scaling, 527 SC circuit CAD, 556, 557 frequency domain analysis, 557– 560 low supply voltage, 577 bootstraped switch, 578 switched amplifier, 578, 580 threshold voltage, 577 resistor implementation, 511 transient spike, 576 compensation, 576 SC gain stage CDS compensated, 573–575 un-compensated, 572 SC integrator amplifier finite bandwidth inverting, 550–551 652 noninverting, 552–553 CDS compensated, 567–572 dc offset voltage, 556 double-sampling, 514 inverting, 498, 512 LDI, 546 noninverting, 498, 546 parasitic capacitors, 514 phase error free, 566 slewing period, 555 Scaling, 426, 433, 522, 527, 536, 540 Scattering parameter, 369 Schmitt trigger, 286 Second-order filter, 423, see also Biquad gm -C implementation, 424 gyrator, 423 Self-tuned filter, 453 Settling time, 171, 175, 179, 282 SFG, see Signal-flow graph Short-channel effect, 32 Signal bandwidth, 250 Signal flow graph (SFG), 635 Mason’s gain formula, 637 reduction rules, 636 Signal-flow graph (SFG), 420, 430, 433, 518 all-pole lowpass filter, 533 discrete-time network, 530 highpass ladder network, 536 third-order allpass filter, 544 transformations, 536 Slew rate, 134, 206, 221, 241, 256 Slope factor, 37, 102 Smoothing filter, 488 Source follower, 371, 392 Specific current, 36 SpectreRF, 384, 560 SPICE, 456, 459 SC circuit, 557 Spurious-free dynamic range (SFDR), 455 Squarer, 316, 318 Squaring circuit, 330, 333 Stability, 224, 227, 240 Index Start-up circuit, 103, 109, 118, 390 Static comparator, 291, 294 Stopband, 416, 489 Strong inversion, 3, 36, 48 region, 17, 28 Structurally allpass filter, 585 Subthreshold region, 7, 16, 17, 163, 165 current, Surface potential, 42, 44 Switch, 488, 491–499, 503, 505, 511, 547, 577, 578, 580 charge injection, 495 charge transfer error, 495 clock feedthrough, 495 CMOS, 493 compensation technique, 497 conductance, 493 description, 491 dummy, 498 equivalent circuit, 495 leakage current, 496 nMOS, 493 noise, 497 pMOS, 493 Switched amplifier, 580 Switched-capacitor biquad, see SC biquad Switched-capacitor circuit, see SC circuit Switched-capacitor integrator, see SC integrator Switching noise, 72 System identification, 453 T T/H circuit, see Track-and-hold circuit Taylor series, 44 Technology current, 623 Temperature, 19, 22, 23, 83, 144, 256 coefficient, 20, 108, 490 Thermal voltage, 23, 42, 102, 107 Threshold voltage, 7, 12–19, 23, 33 Thyristor, 71 653 Index Track-and-hold circuit, 641 acquisition time, 505 aperture delay, 505 aperture uncertainty, 507 closed-loop configurations, 510 droop rate, 505 feedthrough attenuation, 505 half-period delay, 503 hold-to-track delay, 505 linear time-variant network, 641 open-loop structures, 510 SC circuit, 560 settling time, 505 thermal noise, 505 transfer function, 644 Transceiver, 342 Transconductance, 12–15, 20, 23–25, 28, 31, 37, 52, 129, 131, 132, 137, 138, 142, 145, 149, 151, 154, 163, 166, 170, 174, 187, 193, 194, 197–252, 371–430, 444, 450, 451, 600–631 efficiency, 25, 29, 163, 618, 626, 631 Transformer, 67 Transient spike, 576 Transistor sizing, 599, 624 gm /ID design method, 618 comparator, 617 folded-cascode amplifier, 611 latch, 616 single-stage amplifier, 604 two-stage amplifier, 610 Transit frequency, 38 Translinear loop, 200, 202, 204, 235 Transmitter, 342, 345, 353 homodyne, 343 low-IF, 345 superheterodyne, 343 Triode region, 6, 7, 11, 14, 52 Tuning, 194, 239, 352, 360, 378, 386, 438, 440–442, 444 accuracy, 447 range, 386, 387, 397 self-tuned filter, 453 sensitivity, 386 transconductor external reference resistor, 450 Two-quadrant multiplication, 308 Two-stage amplifier, 606 U Unity-gain frequency, 139, 171, 172, 175, 179, 180, 209, 215, 219, 220, 230, 239, 240, 251, 256 Up-conversion, 348 V Variable gain amplifier (VGA), 343, 352, 394, 401, 462, 463 VCO, see Voltage-controlled oscillator Velocity saturation, 17, 32, 39 VGA, see Variable gain amplifier Via, 62, 68, 70 Voltage coefficient, 490 Voltage reference, 100 floating-gate transistor, 115 matching, 115 Voltage-controlled current source, 121 Voltage-controlled filter (VCF), 435, 437, 438, 443 Voltage-controlled oscillator (VCO), 378, 380–382, 385–389, 392, 394, 437, 438, 443, 464 W Wafer, 57, 59, 66 Weak inversion, 3, 9, 24, 28, 36, 48 White noise, 250, 453 X XOR gate, 437, 438 Y Yield, 70 Z Zero back-gate bias, 14 Zero drain bias, 21