cmos digital integrated circuits a first course pdf

CMOS Digital Integrated Circuits: A First Course www.TechnicalBooksPDF.com www.TechnicalBooksPDF.com CMOS Digital Integrated Circuits: A First Course Charles Hawkins, Jaume Segura, and Payman Zarkesh-Ha University of Florida University of Balearic Islands University of New Mexico Edison, NJ scitechpub.com www.TechnicalBooksPDF.com Published by SciTech Publishing, an imprint of the IET www.scitechpub.com www.theiet.org Copyright © 2013 by SciTech Publishing, Edison, NJ All rights reserved No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except as permitted under Sections 107 or 108 of the 1976 United Stated Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 646-8600, or on the web at copyright.com Requests to the Publisher for permission should be addressed to The Institution of Engineering and Technology, Michael Faraday House, Six Hills Way, Stevenage, Herts, SG1 2AY, United Kingdom While the author and publisher believe that the information and guidance given in this work are correct, all parties must rely upon their own skill and judgement when making use of them Neither the author nor publisher assumes any liability to anyone for any loss or damage caused by any error or omission in the work, whether such an error or omission is the result of negligence or any other cause Any and all such liability is disclaimed 10 ISBN 978-1-61353-002-3 Typeset in India by MPS Ltd Printed in the USA by Sheridan Books, Inc www.TechnicalBooksPDF.com CONTENTS Preface xiii Introduction xix Transistors and Computers—Until Death Do They Part xx Transistors and Computers—How Deep Can the Friendship Go? xxi Computers—Is There a Limit? xxiii Future xxiv Basic Logic Gate and Circuit Theory 1.1 Logic Gates and Boolean Algebra 1.2 Boolean and Logic Gate Reduction 1.3 Sequential Circuits 1.4 Voltage and Current Laws 1.4.1 1.4.2 1.4.3 1.4.4 Terminal Resistance Analysis by Inspection Kirchhoff’s Voltage Law and Analysis by Inspection Kirchhoff’s Current Law and Analysis by Inspection Mixing Voltage and Current Divider Analysis by Inspection 12 14 16 1.5 Power Loss in Resistors 18 1.6 Capacitance 21 1.6.1 1.6.2 Capacitor Energy and Power Capacitive Voltage Dividers 22 24 1.7 Inductance 26 1.8 Diode Nonlinear Circuit Analysis 27 1.8.1 Diode Resistor Analysis 28 1.9 Some Words about Power 31 1.10 Summary 32 v www.TechnicalBooksPDF.com vi Contents Semiconductor Physics 39 2.1 Material Fundamentals 39 2.1.1 2.1.2 2.1.3 Metals, Insulators, and Semiconductors Carriers in Semiconductors: Electrons and Holes Determining Carrier Concentrations 2.2 Intrinsic and Extrinsic Semiconductors 2.2.1 n-Type Semiconductors 2.2.2 p-Type Semiconductors 2.2.3 Carrier Concentration in n- and p-Doped Semiconductors 2.3 Carrier Transport in Semiconductors 2.3.1 2.3.2 45 48 49 51 51 52 56 2.5 Biasing the pn Junction 59 The pn Junction under Forward Bias The pn Junction under Reverse Biasing 60 60 2.6 Diode Junction Capacitance 62 2.7 Summary 64 MOSFET Transistors 67 3.1 Principles of Operation 67 3.1.1 The MOSFET as a Digital Switch 3.1.2 Physical Structure of MOSFETs 3.1.3 MOS Transistor Operation: a Descriptive Approach 45 2.4 The pn Junction 2.5.1 2.5.2 Drift Current Diffusion Current 39 41 43 68 69 70 3.2 MOSFET Input Characteristics 73 3.3 nMOS Transistor Output Characteristics and Circuit Analysis 74 3.4 pMOS Transistor Output Characteristics and Circuit Analysis 83 3.5 MOSFET with Source and Drain Resistors 89 3.6 Threshold Voltage in MOS Transistors 90 3.7 Summary 93 Metal Interconnection Properties 99 4.1 Metal Interconnect Resistance 100 4.1.1 4.1.2 4.1.3 Resistance and Thermal Effects Sheet Resistance Via Resistance www.TechnicalBooksPDF.com 103 104 106 Contents vii 4.2 Capacitance 4.2.1 4.2.2 110 Parallel Plate Model Capacitive Power 4.3 Inductance 113 4.3.1 4.3.2 4.3.3 113 115 116 Inductive Voltage Line Inductance Inductive Power 4.4 Interconnect RC Models 4.4.1 4.4.2 C-model for Short Lines RC Model for Long Lines 4.5 Summary 117 117 119 122 The CMOS Inverter 125 5.1 The CMOS Inverter 125 5.2 Voltage Transfer Curve 127 5.3 Noise Margins 129 5.4 Symmetrical Voltage Transfer Curve (VTC) 131 5.5 Current Transfer Curve 132 5.6 Graphical Analysis of VTC 134 5.6.1 5.6.2 Static Transfer Curves Dynamic Transfer Curves 134 138 5.7 Inverter Transition Speed Model 140 5.8 CMOS Inverter Power 143 5.8.1 5.8.2 5.8.3 110 112 Transient Power Short-Circuit Power Quiescent Leakage Power 143 145 147 5.9 Power and Power Supply Scaling 147 5.10 Sizing Inverter Buffers to Drive Large Loads 150 5.11 Summary 152 CMOS NAND, NOR, and Transmission Gates 6.1 NAND Gates 6.1.1 6.1.2 157 157 Electronic Operation NAND Noncontrolling Logic State 6.2 NAND Gate Transistor Sizing www.TechnicalBooksPDF.com 158 159 162 viii Contents 6.3 NOR Gates 6.3.1 6.3.2 164 Electronic Operation NOR Noncontrolling Logic State 6.4 NOR Gate Transistor Sizing 168 6.5 Pass Gates and CMOS Transmission Gates 173 6.5.1 6.5.2 6.5.3 Pass Gates CMOS Transmission Gates Tristate Logic Gates 6.6 Summary 173 175 176 177 CMOS Circuit Design Styles 185 7.1 Boolean Algebra to Transistor Schematic Transformation 185 7.2 Synthesis of DeMorgan Circuits 190 7.3 Dynamic CMOS Logic 194 7.3.1 7.3.2 164 165 Dynamic CMOS Logic Properties Charge Sharing in Dynamic Circuits 194 196 7.4 Domino CMOS Logic 199 7.5 NORA CMOS Logic 202 7.6 Pass Transistor Logic 203 7.7 CMOS Transmission Gate Logic Design 205 7.8 Power and Activity Coefficient 206 7.9 Summary 211 Sequential Logic Gate Design and Timing 8.1 CMOS Latches 8.1.1 8.1.2 219 221 Clocked Latch Gated Latches 221 222 8.2 Edge-Triggered Storage Element 223 8.2.1 8.2.2 8.2.3 The D-FF Clock Logic States A Tristate D-FF Design 8.3 Timing Rules for Edge-Triggered Flip-Flops 8.3.1 8.3.2 Timing Measurements Timing Rule Violation Effect www.TechnicalBooksPDF.com 224 225 226 228 228 230 Contents ix 8.4 Application of D-FFs in ICs 231 8.5 tsu and thold with Delay Elements 232 8.6 Edge-Triggered Flip-Flop with Set and Reset 235 8.7 Clock Generation Circuitry 236 8.7.1 237 8.8 Metal Interconnect Parasitic Effects 241 8.9 Timing Skew and Jitter 241 8.10 Overall System Timing in Chip Designs 242 8.10.1 8.10.2 8.10.3 8.10.4 Phase Locked Loop Circuit Period Constraint Period Constraint and Skew Hold Time Constraint Period Constraint with Skew and Jitter 243 244 245 246 8.11 Timing and Environmental Noise 249 8.12 Summary 251 IC Memory Circuits 261 9.1 Memory Circuit Organization 262 9.2 Memory Cell 264 9.3 Memory Decoders 266 9.3.1 9.3.2 Row Decoders Column Decoders 266 267 9.4 The Read Operation 269 9.5 Sizing Transistor Width to Length Ratio for Read Operation 270 9.6 Memory Write Operation 272 9.6.1 9.6.2 Cell Write Operation Latch Transfer Curve 272 273 9.7 Sizing Transistor Width to Length Ratio for Write Operation 273 9.8 Column Write Circuits 277 9.9 Read Operation and Sense Amplifier 278 9.10 Dynamic Memories 281 9.10.1 3-Transistor DRAM Cell 9.10.2 1-Transistor DRAM Cell 9.11 Summary 283 284 285 www.TechnicalBooksPDF.com 366 C CAD See Computer-aided design (CAD) Campbell, Joseph, 219 Capacitance (C), 21–26, 22 f, 110–113 capacitive power, 112–113 capacitive voltage dividers, 22–26 capacitor energy and power, 22–24, 22 f C-model for short lines, 117–119, 117 f, 118 f parallel plate model, 110–112, 110t Capacitive power, 112–113 Capacitive voltage dividers, 22–26 Capacitor, energy and power, 22–24, 22 f Cell write operation, 272, 272 f Channel, 69–70 length (L), 70 width (W), 70 Charge pumps, 239 Charge sharing, in dynamic circuits, 196–199, 196 f Chemical mechanical planarization (CMP), 346 Chemical vapor deposition (CVD), 341, 342t Chip designs, overall system timing in See Overall system timing, in chip designs Chip making See also Overall system timing, in chip designs BOL fabrication, 337–338 techniques See Back end of Line (BOL) fabrication cleaning and safety operations, 342–344 CMOS inverter, fabricating, 347–349 die packaging, 349–350, 349 f FOL fabrication, 337–338 techniques See Back end of Line (BOL) fabrication overview, 336 testing, 350 transistor fabrication, 344, 345 f wafer construction, 336, 337 f Circuit design styles, CMOS, 185–211 Boolean algebra to transistor schematic transformation, 185–190, 186 f CMOS transmission gate logic design, 205–206, 206 f complementary static, 185 Index DeMorgan circuits, synthesis of, 190–193, 191 f domino CMOS logic, 199–202, 199 f, 200 f, 201 f dynamic CMOS logic See Dynamic CMOS logic NORA CMOS logic, 202, 202 f pass transistor logic, 203–205, 203 f, 204 f power and activity coefficient, 206–211 Circuit extraction, 334 Circuit layout, CMOS, 317–334 basics, 333 Boolean equations, 319–321, 320 f, 321 f CAD tools, 321, 334 completed, drawn to design rule minimum dimensions, 327–328, 328 f design rules, 317–319, 318 f minimum layout spacing, 322–323, 322t, 323 f inverter, 323–327 See also Inverter, CMOS merging transistors to common polygate, 326, 327 f nMOS transistor layout See nMOS transistors pMOS transistor layout See pMOS transistor(s) logic gate standard cell layouts, merging, 331–333 multi-input logic gate layouts See Multi-input logic gate layouts with PowerPoint, 317, 319, 321–322, 323–324 stick diagrams, 319–321, 320 f, 321 f transistor schematics, 319–321, 320 f, 321 f Circuit theory, Boolean algebra and See Boolean algebra, circuit theory and CLB See Configurable logic blocks (CLB) CLE See Configurable logic elements (CLE) Cleaning and safety operations, chip making, 342–344 Clock active edge, 226 Clock (Clk)-line, delay elements in, 233–235, 234 f Clocked latches, 221–222, 221 f Clock generation circuitry, 236–241 phase locked loop See Phase locked loop (PLL) Index printed circuit board, 236 Clock logic states, 225–226 clock active edge, 226 clock = state, 225–226 clock = state, 226 Clock network, 207 Clock period constraint, 242 Clock pulse width, edge-triggered FFs and, 229 Clock = state, 225–226 Clock = state, 226 Clock to Q time, edge-triggered FFs and, 229 C-model for short lines, 117–119, 117 f, 118 f CMOS inverter See Inverter, CMOS CMOS transmission gate logic design, 205–206, 206 f CMP See Chemical mechanical planarization (CMP) Cobalt tungsten phosphide (CoWP), barrier metals, 100, 108 Column decoders, 266 f, 267–269, 267 f, 268 f Column write circuits, 277–278, 277 f Compensated doping, 49 Complementary static design style, 185 Complex programmable logic device (CPLD), 292–294, 293 f, 294 f, 295 f advanced, 294–300, 296 f –300 f Altera Max CPLDs, 295–297, 296 f, 297 f Xilinx CoolRunner CPLD Series, 298–300, 298 f –300 f Computer-aided design (CAD), 287 layout, 321, 334 Computer architecture, Conduction band, 2, f Configurable logic blocks (CLB), 301 Configurable logic elements (CLE), 301 Contacts, 100 Contamination delays (cd), 245 Control term set (CTS), 299 Copper (Cu) technologies resistivity, 101, 102, 102t, 103, 107–109 for contacts, 100 Coupling capacitance, 138, 139 CPLD See Complex programmable logic device (CPLD) Cross-talk, 21–22 circuits, 111 coupling, 241 367 CTS See Control term set (CTS) Current divider analysis, by inspection, 14–18 Current transfer curve (ITC), 132–134, 133 f Custom layouts, 333 CVD See Chemical vapor deposition (CVD) D Delay elements, tsu and thold with, 232–235 in Clk-line, 233–235, 234 f in D-line, 232–233, 233 f DeMorgan circuits, synthesis of, 190–193, 191 f DeMorgan’s theorem, 3–5 Dennard, Robert, 281 Deposition, 338 implantation and, FOL fabrication, 341–342, 342t, 343 f Design rules (DR), 317–319, 318 f minimum dimensions, completed CMOS inverter and, 327–328, 328 f minimum layout spacing and, 322–323, 322t, 323 f of pMOS transistor layout, revisiting, 325, 325 f Design styles, circuit CMOS See Circuit design styles, CMOS D-FF (Delay-FF) design, 220–221 edge-triggered, 224–225, 224 f in ICs, application, 231–232, 232 f tristate, 226–227, 226 f Dielectrics, low-k, 110–111 Die packaging, 349–350, 349 f Differential amplifier, 269 Diffusion, 341 coefficient, 53 current, 52–54, 53 f, 54 f Digital switch, MOSFET as, 68, 69 f Diode junction capacitance, 62–63, 63 f Diode nonlinear circuit analysis, 27–31, 27 f diode resistor analysis, 27 f, 28–31 Diode resistor analysis, 27 f, 28–31 DIP See Dual-In-Line (DIP) Distributed gates, 288 D-line, delay elements in, 232–233, 233 f Domino CMOS logic, 199–202, 199 f, 200 f, 201 f Donor, 46, 46 f 368 Doping, 45 compensated, 49 DOWN waveform, 238, 238 f, 239 Drain, MOSFET, 67, 68 f Drain resistors, MOSFET with, 89–90 DRAM See Dynamic random access memory (DRAM) Drift current, 51–52, 51 f Drive large loads, sizing inverter buffers to, 150–152, 150 f Dry etch, 340 Dual damascene, BOL fabrication, 346 Dual-In-Line (DIP), 349, 349 f Dynamic CMOS logic, 185, 194–199 basic structure, 194 f charge sharing in dynamic circuits, 196–199, 196 f evaluation phase, 194–195 precharge phase, 194–195 properties, 194–196 advantages, 195 disadvantages, 195–196 Dynamic power (Pd ), 143 Dynamic random access memory (DRAM), 261, 262, 281–285 1-transistor DRAM cell, 284–285, 284 f 3-transistor DRAM cell, 283–284, 283 f vs SRAMs, 281, 282t Dynamic transfer curves, VTC, 138–140, 138 f, 139 f E Eccles, William, 219–220 Edge-sensitive memory element, 224 Edge-triggered flip-flops with set and reset, 235, 236 f timing rules for See Timing, rules for edge-triggered flip-flops Edge-triggered storage element, 223–227, 224 f clock logic states See Clock logic states D-FF, 224–225, 224 f tristate D-FF design, 226–227, 226 f EEPROM technology, 313–314, 314 f Electrically programmable read-only memories (EPROMs), 261 Electrical resistivity (ρ), 101 Index Electron–hole pair generation, 44, 45 f Electron–hole recombination, 44, 45 f Electronic operation NAND gates, 158, 159 f NOR gates, 164–165, 165 f Elmore’s analysis, 119–120 Endcap, 317 Energy levels in a single atom, 39, 40 f Environmental noise, timing and, 249–251, 250 f, 251 f Epitaxial layer, 341, 347 EPROMs See Electrically programmable read-only memories (EPROMs) Etching, FOL fabrication, 340–341 Evaluation phase, dynamic CMOS logic and, 194–195 Extrinsic semiconductors, 45 F FBs See Function blocks (FBs) Feynman, Richard, 39 Field-programmable gate arrays (FPGAs), 287–315, 300–310, 301 f Actel ACT FGPAs, 302–303, 302 f –304 f advantages, 287–288 Altera Cyclone III FPGAs, 307–309, 307 f –309 f design tools, working with, 309–310, 310 f structure, 301, 301 f Xilinx Spartan FPGAs, 304–306 FIFO See First-in, first-out (FIFO) memories First-in, first-out (FIFO) memories, 261 Fixed tapered buffer, 150, 150 f FLASH, 261 Flip-flops (FF) Eccles–Jordan, 219–220, 220 f edge-triggered, timing rules for See Timing, rules for edge-triggered flip-flops symbol, sequential circuits, 7–8, f, f Floating nodes, 176 Flux, 51 FOL See Front end of Line (FOL) Forward bias, pn junction under, 60, 60 f Foundry, 335 FPGAs See Field-programmable gate arrays (FPGAs) Index Front end of Line (FOL) fabrication, 337–338 operation, CMOS inverter, 347–348 techniques, 338–342 deposition and implantation, 341–342, 342t, 343 f etching, 340–341 oxidation of silicon, 338–339 photolithography, 339–340, 340 f Function blocks (FBs), 298, 299 G Gate, MOSFET, 67, 68 f Gated latches, 222–223, 222 f, 223 f Global clock (GC), 202, 202 f Global set/reset condition (GSR), 299 Gold (Au), resistivity, 102, 102t GSR See Global set/reset condition (GSR) H Hierarchical design, High-Z state, See also Tristate logic gates Hold time (thold ) constraint, 242, 245 with delay elements See Delay elements, tsu and thold with edge-triggered FFs and, 228–229, 228 f Hole, 42 I ICs See Integrated circuits (ICs) Ideal interconnects, properties, 99 Implantation, 338 Inductance, 26, 113–116 inductive power, 116 inductive voltage, 113–115, 114 f line, 115–116 Inductive power, 116 Inductive voltages, 241 Input/output buffers (IOB), 301 Input–output capacitance, 138 Insulator, energy bands of, 40, 41 f In-system programming (ISP), 298 Integrated circuits (ICs), 336 chip making, 335–350 D-FFs, application, 231–232, 232 f See also D-FF (Delay-FF) design 369 fabrication, 336 testing, 350 Interconnection, metal properties See Metal interconnection properties Interconnect parasitic effects, metal, 241 Interlevel dielectric, BOL fabrication, 347, 347t Internal parasitic capacitance, 62 Intrinsic semiconductors, 45 Inverter, CMOS, 125–152 Boolean values detection in, 126 cross section, 126–127, 127 f current transfer curve, 132–134, 133 f electronic symbol, truth table, and schematic, 126 f fabricating, 347–349 back end of line operation, 348–349 front end of line operation, 347–348 laying out, 323–327 See also Circuit layout, CMOS merging transistors to common polygate, 326, 327 f nMOS transistor layout See nMOS transistors pMOS transistor layout See pMOS transistor(s) NAND gates See NAND gates noise margins, 129–131, 129 f NOR gates See NOR gates on–off tandem operation, 125–126 overview, 125–127 pass gates See Pass gates power of See Power, of CMOS inverter sizing inverter buffers to drive large loads, 150–152, 150 f symmetrical VTC, 131–132 T-gates See Transmission gates (T-gates) transition speed model, 140–143, 140 f, 141 f VTC of See Voltage transfer curve (VTC) IOB See Input/output buffers (IOB) Ion implantation, 341 Isotropic etch, 341 ISP See In-system programming (ISP) ITC See Current transfer curve (ITC) 370 J Jitter, 241–242 period constraint with, 246–249, 246 f Jitter noise, RO and, 240 Jordan, F W., 219–220 K Kirchhoff’s voltage law (KVL), 12–14, 12 f KVL See Kirchhoff’s voltage law (KVL) L LAB See Logic array blocks (LAB) Last-in, first-out (LIFO) memories, 261 Latches, CMOS, 221–223, 221 f clocked, 221–222, 221 f defined, 220 gated, 222–223, 222 f, 223 f transparency property of, 221 Latch transfer curve, 273, 273 f Layouts, integrated circuit, 317–319, 318 f LED See Light-emitting diodes (LED) L-edit, 317 LEs See Logic elements (LEs) LIFO See Last-in, first-out (LIFO) memories Light-emitting diodes (LED), 44 Linear state, 72 Line inductance, 115–116 Lloyd, Jim, Load capacitance, charge or discharge, 206–207 Logic-0, Logic-1, Logic array blocks (LAB), 295–296 Logic blocks Actel ACT FGPAs, 302–303, 302 f –303 f Altera Cyclone III FPGAs, 307–308, 307 f –309 f Logic elements (LEs), 301 Logic gates boolean algebra and See Boolean algebra, logic gates and layouts, multi-input, 328–331 standard cell layouts, merging, 331–333 types in ASIC design, 157, 158 f See also NAND gates; NOR gates; Pass gates; Transmission gates (T-gates); Tristate logic gates Index Long lines, RC model for, 119–122, 119 f Low-k dielectrics, 110–111 M Master latch, 224–225, 224 f Maximum delay (tcq ), edge-triggered FFs and, 228 f, 229 Memory cell, 264–266, 264 f Memory circuits, IC, 261–285 column write circuits, 277–278, 277 f DRAM, 261, 262, 281–285 1-transistor DRAM cell, 284–285, 284 f 3-transistor DRAM cell, 283–284, 283 f vs SRAMs, 281, 282t memory cell, 264–266, 264 f memory decoders, 266–269 memory write operation, 272–273 organization, 262–263, 263 f Read operation, 269–270, 270 f, 278–280, 279 f, 281 f sizing transistor width to length ratio for, 270–272, 270 f sense amplifier, 278–280, 279 f, 280 f sizing transistor width to length ratio for write operation, 273–276, 274 f Memory decoders, 266–269 column decoders, 266 f, 267–269, 267 f, 268 f row decoders, 266–267, 266 f, 267 f Memory write operation, 272–273 cell write operation, 272, 272 f latch transfer curve, 273, 273 f Metal interconnection properties, 99–122 capacitance See Capacitance (C) inductance See Inductance overview, 99–100 RC models See RC models, interconnect resistance See Resistance, metal interconnect Metal interconnect parasitic effects, 241 Metal-oxide semiconductor field-effect transistor (MOSFET) bulk, 67, 68 f as a digital switch, 68, 69 f drain, 67, 68 f gate, 67, 68 f input characteristics, 73–74, 74 f nMOS transistor, 68 Index normal biasing, 70 f operation, 70–73, 70 f –73 f output characteristics, 74–83, 75 f, 77 f physical structure of, 69–70, 69 f pMOS transistor, 68 normal biasing, 70 f operation, 70–73, 70 f –73 f output characteristics, 83–88, 84 f principles of operation, 67–73 source, 67, 68 f with source and drain resistors, 89–90 threshold voltage in MOS transistors, 90–93 Metals, energy bands of, 40, 41 f Metal-to-metal antifuse, 311–313, 312 f, 313 f Microprocessor, lower metal levels of, 99, 100 f Minimal time (tsu ) with delay elements See Delay elements, tsu and thold with edge-triggered FFs and, 228, 228 f Minimum layout spacing, design rules and, 322–323, 322t, 323 f Minority carriers, 71 Minterms, 290 Mixing voltage analysis, by inspection, 14–18 Mobility, electrons, 51 MOSFET See Metal-oxide semiconductor field-effect transistor (MOSFET) MOS transistors operation, 70–73, 70 f –73 f threshold voltage in, 90–93 Multi-input logic gate layouts, 328–331 2NAND gate layout, 328–331, 329 f, 329t, 330 f, 331 f Multiplexer (MUX), 205–206, 206 f MUX See Top-most multiplexer (MUX) N NAND gates, 157–164 electronic operation, 158, 159 f gate symbols and truth table, 158 f 2NAND layout, 328–331, 329 f, 329t, 330 f, 331 f noncontrolling logic state, 159–161 noncontrolling states, 158 transistor sizing, 162–164, 162 f Negative photoresist, 340 Negative skew, 249 371 Neuman, John von, 335 nMOS transistors, 68, 90–92, 91 f, 239 Boolean functions and, 185, 186, 186 f, 187–190 layout, 325–326, 326 f normal biasing, 70 f operation, 70–73, 70 f –73 f output characteristics, 74–83, 75 f, 77 f Noise environmental, timing and, 249–251, 250 f, 251 f margins, 129–131, 129 f Noncontrolling logic state NAND, 159–161 NOR, 165–168 Noncontrolling states, 158 Nonsaturated state, 72 NORA See No Race (NORA) No Race (NORA), CMOS logic, 202, 202 f NOR gates, 164–173 electronic operation, 164–165, 165 f gate symbol and truth table, 165 f noncontrolling logic state, 165–168 transistor sizing, 168–173, 169 f n-type semiconductors, 45–48, 45 f carrier concentration in, 49–50 O Ohmic bias state, 72 One-time programmable (OTP), 310 1-transistor DRAM cell, 284–285, 284 f ONO See Oxide-nitride-oxide (ONO) layer OTP See One-time programmable (OTP) Overall system timing, in chip designs, 242–249, 242 f timing constraints, 242 clock period constraint, 242 hold time constraint, 242, 245 period constraint See Period constraint Oxidation of silicon, FOL fabrication, 338–339 Oxide-nitride-oxide (ONO) layer, 311 P Parallel plate model, capacitance, 110–112 low-k dielectrics, 110–111 relative permittivity of insulators, 110, 110t Parasitic effects, metal interconnect, 241 372 Parasitic elements, 62 Pass gates, 173–175, 174 f Passivation, BOL fabrication, 347 Pass transistor logic, 203–205, 203 f, 204 f Pass transistors, 173, 174 f PC See Precharge pulse (PC) PCB See Printed circuit board (PCB) Period constraint, 243–244, 243 f skew and, 244–245, 244 f, 246–249 with skew and jitter, 246–249, 246 f PGA See Pin grid aray (PGA) Phase locked loop (PLL), 236, 237–241, 237 f, 238 f charge pumps, 239 UP and DOWN waveforms, 238, 238 f, 239 Phase splitter, 89 Photolithography description, 339 FOL fabrication, 339–340, 340 f Photoresist material, 340 negative, 340 positive, 340 PIA See Programmable interconnect array (PIA) Pinched off, 73 Pinch-off point, 73 Pin grid aray (PGA), 349, 349 f Pipelining, 219 PLA See Programmable logic array (PLA) PLC See Programmable logic circuit (PLC) PLICE See Programmable low impedance circuit element (PLICE) PLL See Phase locked loop (PLL) pMOS transistor(s), 68, 90–92, 91 f, 239 Boolean functions and, 185–186, 186 f, 187–190 layout, 323–325, 324 f revisiting design rules of, 325, 325 f normal biasing, 70 f operation, 70–73, 70 f –73 f output characteristics, 83–88, 84 f pn junction, semiconductors, 56–59, 56 f, 57 f biasing, 59–62, 60 f, 61 f under forward bias, 60, 60 f under reverse biasing, 60–61, 61 f Poly-diffusion antifuse, 311, 311 f Positive photoresist, 340 Positive skew, 249 Index Power, 31–32 capacitor, 22–23, 112, 206–207 of CMOS inverter, 143–150 dynamic, 143 quiescent leakage, 147 short-circuit, 145–147, 146 f supply scaling, 147–150, 148 f transient, 143–145 dissipation, 206–211 inductor, 116 loss in resistors, 18–21 PowerPoint, laying out circuit with, 317, 319, 321–322, 323–324 Precharge phase, dynamic CMOS logic and, 194–195 Precharge pulse (PC), 265 Printed circuit board (PCB), 236 Programmable interconnect array (PIA), 295–296 Programmable interconnect or programmable switch matrix (PSM), 301 Programmable logic array (PLA), 288–292 AND/OR matrix gates, 290–292, 291 f programmable logic gates, 288–292, 289 f, 290 f Programmable logic circuit (PLC), 287 Programmable logic gates, 288–292, 289 f, 290 f Programmable low impedance circuit element (PLICE), 311 Programmable technology antifuse technology, 311–313 EEPROM technology, 313–314 static RAM switch technology, 314–315 PSM See Programmable interconnect or programmable switch matrix (PSM) p-type semiconductors, 48–49, 48 f carrier concentration in, 49–50 Pull-down network, 186, 186 f Pull-up network, 186, 186 f Q QFP See Quad flat package (QFP) Quad flat package (QFP), 349, 349 f Quad no leads package (TQFN), 349, 349 f Quiescent leakage power, 147 Index R RC models, interconnect, 117–112 C-model for short lines, 117–119, 117 f, 118 f for long lines, 119–122, 119 f Read-only memories (ROMs), 261 Read operation, 269–270, 270 f, 278–280, 279 f, 281 f sense amplifier and, 278–281, 279 f, 280 f, 281 f sizing transistor width to length ratio for, 270–272, 270 f Real interconnects, properties, 99 Relative permittivity, of insulators, 110, 110t Reset control, edge-triggered FFs with, 235, 236 f Resistance, metal interconnect, 100–110, 101 f Ag, resistivity, 102, 102t Al technologies, 100, 101, 102, 102t Au, resistivity, 102, 102t contacts, 100 Cu technologies, 100, 101, 102, 102t, 103, 107–109 network with parasitic, 100, 101 f sheet resistance, 104–106 thermal effects and, 103–104 tungsten, resistivity, 100, 101, 102, 102t, 108 via resistance, 106–110, 106 f Resistivity, defined, 101 Resistors, power loss in, 18–21 Reverse biasing, pn junction under, 60–61, 61 f, 73 Reverse bias saturation current, 60 Ring oscillator (RO), VCO design and, 239–241, 240 f RO See Ring oscillator (RO) ROMs See Read-only memories (ROMs) Row decoders, 266–267, 266 f, 267 f S Sagan, Carl, 261 Saturation region, 73 Scattering, 51 SE See Sense enable (SE) signal Semiconductors, 39–64 carriers in, 41–45, 42 f 373 concentrations, 43–45, 43 f, 45 f carrier transport in, 51–56 diffusion current, 52–54, 53 f, 54 f drift current, 51–52, 51 f diode junction capacitance, 62–63, 63 f energy bands of, 41, 41 f extrinsic, 45 intrinsic, 45 n-type, 45–48, 45 f pn junction, 56–59, 56 f, 57 f biasing, 59–62, 60 f, 61 f p-type, 48–49, 48 f Sense amplifier, 269, 278–280, 279 f, 280 f Read operation and, 278–281, 279 f, 280 f, 281 f Sense enable (SE) signal, 278 Sense Output node, 278, 279 f Sequential circuits, 7–9, f, f computer architecture, implementing, 292–300 advanced CPLD, 294–300, 296 f –300 f CPLD, 292–294, 293 f, 294 f, 295 f Sequential logic gate design and timing, 219–251 clock generation circuitry See Clock generation circuitry D-FFs in ICs, application, 231–232, 232 f See also D-FF (Delay-FF) design edge-triggered flip-flops with set and reset, 235, 236 f timing rules for See Timing, rules for edge-triggered flip-flops edge-triggered storage element See Edge-triggered storage element latches See Latches, CMOS metal interconnect parasitic effects, 241 overall system timing in chip designs See Overall system timing, in chip designs overview, 219–221 symbol, 220 f timing environmental noise and, 249–251, 250 f, 251 f skew and jitter, 241–242 tsu and thold with delay elements See Delay elements Set control, edge-triggered FFs with, 235, 236 f 374 Setup time, edge-triggered FFs and, 228, 228 f Shallow trench isolation (STI), 344, 347 Sheet resistance, 104–106 Short-circuit power, 145–147, 146 f Short-line capacitance model, 117–119, 117 f Silicide, 344 Silver (Ag), resistivity, 102, 102t Skew period constraint and, 244–245, 244 f timing, 241–242 Slave latch, 224–225, 224 f SLICEL, 305, 306 SLICEM, 305, 306 Source, MOSFET, 67, 68 f Spartan CLBs, 305–306, 306 f Sputtering, BOL fabrication, 344, 345–346 SRAM See Static random access memory (SRAM) Standard cell layouts, merging logic gate, 331–333 Static random access memory (SRAM), 261–262 switch technology, 314–315 vs DRAMs, 281, 282t Static transfer curves, VTC, 134–138, 134 f STI See Shallow trench isolation (STI) Stick diagrams, CMOS circuit layout, 319–321, 320 f, 321 f Symmetrical VTC, 131–132 Synchronous designs, 8, 219 T Tantalum nitride (TaN) liners, 100, 108, 109–110 Tantalum (Ta), barrier metals, 100 Tapered buffer, 150, 150 f Terminal resistance analysis, by inspection, 9–12 Thermal budget, 341 Thermal coefficient of resistivity (α), 103 Thermal effects, resistance and, 103–104 Thermal voltage (VT ), 27 3-transistor DRAM cell, 283–284, 283 f Threshold voltage, in MOS transistors, 90–93 Time constant, defined, 118 Index Timing environmental noise and, 249–251, 250 f, 251 f measurements, 228–230 clock pulse width, 229 clock to Q time, 229 hold time, 228–229, 228 f minimum tcq , 228 f, 229 minimum tsu , 228, 228 f setup time, 228, 228 f overall system, in chip designs See Overall system timing, in chip designs rules for edge-triggered flip-flops, 228–231 timing measurements See Timing, measurements violation effect, 230–231, 231 f sequential logic gate design and See Sequential logic gate design and timing skew, 241–242 Titanium nitride (TiN) liners, 108 Top-most multiplexer (MUX), 292–293 TQFN See Quad no leads package (TQFN) Transient power, 143–145 Transistor(s) defined, 317 fabrication, 344, 345 f layout merging to common polygate, 326, 327 f nMOS, 325–326, 326 f pMOS See pMOS transistor(s) schematics, CMOS circuit, 319–321, 320 f, 321 f pass, 173, 174 f schematic transformation, Boolean algebra to, 185–190, 186 f sizing NAND gates, 162–164, 162 f NOR gates, 168–173, 169 f width to length ratio for Read operation, 270–272, 270 f width to length ratio for Write operation, 273–276, 274 f threshold voltage, 68 Transition activity coefficient, 208 Transition speed model, inverter, 140–143, 140 f, 141 f Index 375 Transmission gates (T-gates), 173–177 CMOS, 175–177, 222 symbol, truth table, and schematics, 176 f tristate logic gates, 176–177, 177 f Tristate D-FF design, 226–227, 226 f Tristate logic gates, 176–177, 177 f Tungsten (W), resistivity, 100, 101, 102, 102t, 108 dynamic transfer curves, 138–140, 138 f, 139 f static transfer curves, 134–138, 134 f regions in, 128–129, 128 f symmetrical, 131–132 VTC See Voltage transfer curve (VTC) U Wafer construction, 336, 337 f Weak logic voltages, 129 Well, 90 Wet etch method, 341 Worst-case fall time transitions, 162 Worst-case pull-down for NAND gate, 162–163, 162 f for NOR gate, 168–170, 169 f Worst-case pull-up for NAND gate, 162–163, 162 f for NOR gate, 168–170, 169 f Worst-case rise time transitions, 162 Write operation, sizing transistor width to length ratio for, 273–276, 274 f UP waveform, 238, 238 f, 239 V Valence band, 2, f VCO See Voltage-controlled oscillator (VCO) Via resistance, 106–110, 106 f Violation effect, timing rule, 230–231, 231 f Voltage, inductive, 113–115, 114 f Voltage analysis, mixing by inspection, 14–18 Voltage and current laws, 9–18 inspection KVL, 12–14, 12 f mixing voltage and current divider analysis, 14–18 terminal resistance analysis, 9–12 Voltage-controlled oscillator (VCO), 237, 239, 242 Voltage transfer curve (VTC), of CMOS inverter, 127–129, 127 f, 128 f graphical analysis of, 134–140 W X Xilinx Advanced Interconnect Matrix (AIM), 298 Xilinx CoolRunner CPLD Series, 298–300, 298 f –300 f Xilinx Spartan FPGAs, 304–306 functional elements, 304–305, 305 f Spartan CLBs, 305–306, 306 f FIGURE 11-1 VDD 4W A B B 2W A GND FIGURE 11-2 Calibration squares 1, 2, 3, units FIGURE 11-7 ␮m overlap ϫ ␮m square contact ␮m contact-poly space ␮m poly endcap ␮m metal overlap of contact space FIGURE 11-8 VDD B GND GND Calibration squares 1, 2, 3, units FIGURE 11-9 FIGURE 11-10 VDD VDD B A B A GND GND FIGURE 11-13 FIGURE 11-11 VDD C A B GND FIGURE 11-14 VDD VDD C A B A B GND GND VDD C A B GND EXAMPLE 11-1 .. .CMOS Digital Integrated Circuits: A First Course www.TechnicalBooksPDF.com www.TechnicalBooksPDF.com CMOS Digital Integrated Circuits: A First Course Charles Hawkins, Jaume Segura, and Payman... plate capacitor and symbol are shown in Figure 1-7 Capacitors are characterized by a parameter called capacitance (C), which is measured in farads Capacitor properties appear in CMOS digital circuits. .. making a digital chip work at high frequency, or at any frequency A collection of flip-flops can form a parallel register described as parallel data in and parallel data out Figure 1-4 shows a