schematic và boardview lah792p rev 2.0 Mã main EH7LW LA_H792P Rev: 2.0 Sơ đồ kĩ thuật và map linh kiện acer aspire 3 n19c1 Dành cho kĩ thuật sửa chữa phần cứng laptop và nghiên cứu học tập khoa học phần cứng
A B C D E Vinafix.com 1 Compal Confidential 2 EH7LW/EH5LW/FH5TW/EH7LC/EH5LC UMA MB Schematic Document LA-H792P 3 Rev: 2.0 2019.05.29 4 Compal Secret Data Security Classification 2018/12/27 Issued Date Deciphered Date 2019/12/27 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Cover Sheet Size Document Number Custom B C D Rev 0.1 EH7LW M/B LA-H792P Date: A Compal Electronics, Inc Thursday, June 06, 2019 Sheet E of 46 A B C D E eDP HDMI Conn Interleaved Memory DDR4-ON BOARD 4G 8Gbx16 Vinafix.com page 29 page 19 Memory BUS page 28 Dual Channel DDI2 HDMI x lanes 260pin DDR4-SO-DIMM X1 1.2V DDR4 2400 eDP page 20 DDI USB 3.0 USB 2.0 CMOS x2 conn x1 conn USB2 port2 (MB) Camera USB3 port Intel Whiskey lake U Intel Comet lake U USB2 port4(SUB) USB2 port USB2 port Processor Card Reader RTS5140 Reserved page 31 SATA Gen 6.0 Gb/s (SATA2) NGFF WLAN support CNVi USB2 port 10 PCIe 1.0 2.5GT/s PCIe 1.0 2.5GT/s port port PCIE 3.0 x4 Flexible IO 8GT/s Port 9-12 Base-U PCIE 3.0x2 (CML) SATA Gen SATA Gen 6.0 Gb/s 1.5 Gb/s port (SATA0) page 35 Cannon Lake PCH-LP port (SATA1A) SATA ODD Conn page 30 RJ45 conn 15W 1528pin BGA WHL-U 4+2 WHL-U 2+2 page 07~18 LPC/eSPI BUS page 33 CLK=24MHz SPI ROM 128Mb page Fan Controlpage RTC CKT 32 page 15 3.3V 24MHz HDA Codec ALC255page 32 page 26 page 31 LS-H781P IO/B LS-H784P ODD/B page 31 page 26 page 28 page 32 LS-H783P LID/B USB2 port Sub Board LS-H802P HDD/B USB2 port Touch Screen Int Speaker page 36 USB2 port 6(SUB) Finger Printer SPI ENE KB9022 page 28 48MHz HD Audio 46x24 mm page 31 LAN(GbE) SATA HDD Realtek 8111H Conn USBx8 page 35 Int DMIC on Camera page 28 UAJ page 35 Touch Pad PS2 (from EC) / I2C (from SOC) Int.KBD USB2 port (FP) Power On/Off CKT page 30 DC/DC Interface CKT page 37 page 37 page 33 2018/12/27 Issued Date Power Circuit DC/DC Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2019/12/27 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC page 34~43 Title B C D Rev 0.1 EH7LW M/B LA-H792P Date: A Block Diagrams Size Document Number Custom Thursday, June 06, 2019 Sheet E of 46 A B C D E Board ID Table for AD channel Vcc Ra Board ID 1 3.3V +/- 5% 100K +/- 1% Rb 12K +/- 1% 15K +/- 1% 20K +/- 1% 27K +/- 1% 33K +/- 1% 43K +/- 1% 56K +/- 1% Power State V BID 0.347 0.423 0.541 0.691 0.807 0.978 1.169 V V V V V V V V V BID typ V 0.345 V 0.430 V 0.550 V 0.702 V 0.819 V 0.992 V 1.185 V V BID max 0.300 V 0.360 V 0.438 V 0.559 V 0.713 V 0.831 V 1.006 V 1.200 V Vinafix.com EC 0x00 0x14 0x1F 0x26 0x31 0x3B 0x46 0x55 AD3 - 0x13 - 0x1E - 0x25 - 0x30 - 0x3A - 0x45 - 0x54 - 0x64 PCB Revision SIGNAL STATE 0.1(EVT) 0.2(DVT) 0.3(PVT) 1.0(PreMP) SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS HIGH HIGH ON ON ON ON LOW HIGH HIGH ON ON OFF OFF LOW LOW HIGH ON OFF OFF OFF LOW LOW LOW ON OFF OFF OFF S0 (Full ON) HIGH S3 (Suspend to RAM) S4 (Suspend to Disk) S5 (Soft OFF) Clock Voltage Rails BOM Structure Table BOM Option Table Item Unpop Connector BOM Structure @ CONN@ CODEC EC Mode Select For Intel CMC CNVi /BT PCM Select EMI requirement ESD requirement RF requirement TPM Finger Print Finger print power UMA or DGPU CPU Select SATA/ODD select USB charger 255@/256@ LPC@ / ESPI@ CMC@ CNVI@/PCM@ EMI@ / @EMI@ ESD@ / @ESD@ @RF@ TPM@ BOM Option Table Power Plane Description S0 S3 +19V_VIN Adapter power supply N/A N/A S4/S5 N/A N/A +12.6V_BATT Battery power supply N/A N/A +19VB AC or battery power rail for power circuit N/A N/A N/A +VCC_CORE Processor IA Cores Power Rail ON OFF OFF OFF +VCC_GT Processor Graphics Power Rails ON OFF +VCC_SA System Agent power rail ON OFF OFF +0.6VS_VTT DDR +0.6VS power rail for DDR terminator ON OFF OFF +1.05V Always power rail ON ON ON*1 Sustain voltage for processor in Standby modes ON ON OFF CPU IO power rail ON OFF OFF +1.05VS_VCCSTG +1.0VALW_PRIM Gated version of VCCST ON OFF OFF +1.2V_VDDQ DDR4 +1.2V Power Rail ON ON OFF +1.8VALW_PRIM +1.8V Always power rail ON ON ON*1 +1.8VS System +1.8V power rail ON OFF OFF +3VLP +19VB to +3VLP power rail for suspend power ON ON ON +3VALW System +3VALW always on power rail ON ON ON*1 +3VS System +3V power rail ON OFF OFF +5VALW +5V Always power rail ON ON ON +5VS System +5V power rail ON OFF OFF ON Item MB Stage G Sensor For over cell battery BOM Structure EVT@/DVT@/PVT@/MP@ GSEN@ 3S@ +1.05VALW_PRIM +1.05V_VCCSTU MD BOM Select NOX76@/X76DSAM@/ X76DMIC@/X76DHYN@/ +VCCIO SPD@/DDP@/MEM@ Memory related CPU C10 support BOM select C10@ 15DIS@/15@/ FP@/FPEMC@ FP3V@/FP5V@ UMA@/VGA@ WHL@/CML@ RD@/NRD@/ODD@ CHG@ +RTCVCC RTC Battery Power ON +1.0VSDGPU +1.0VS power rail for N17S ON*2 OFF OFF +1.35VSDGPU +1.35VS power rail for GPU ON*2 OFF OFF +1.8VSDGPU_AON +1.8VS power rail for N17S(AON) ON*2 OFF OFF +1.8VSDGPU_MAIN +1.8VS power rail for N17S(MAIN) ON*2 OFF OFF +VGA_CORE Core power for discrete GPU ON*2 OFF OFF ON 3 Note : ON*1 means power plane is ON only when WOL enable and RTC wake at BIOS setting, otherwise it is OFF ON*2 power plane is ON when DGPU turn on 43 level BOM table 43 Level Description BOM Structure 431AI6BOL01 SMT MB AH792 EH5LW I38145U22 HDMI 431AI6BOL02 SMT MB AH792 EH5LW I58265U42 HDMI 8265U@/WHL@/PCB@/MEM@/SDP@/X76DHYN@/UMA@/NC10@/CNVI@/NCHG@/NRD@/3S@/LPC@/CMC@/255@/EVT@/X4E@/15@ 431AI6BOL51 SMT MB AH792 EH7LW I38145U22 HDMI 8145U@/WHL@/PCB@/MEM@/SDP@/X76DHYN@/UMA@/NC10@/CNVI@/NCHG@/RD@/ODD@/3S@/LPC@/CMC@/255@/EVT@/X4E@/17@ 431AI6BOL52 SMT MB AH792 EH7LW I58265U42 HDMI 8265U@/WHL@/PCB@/MEM@/SDP@/X76DHYN@/UMA@/NC10@/CNVI@/NCHG@/RD@/ODD@/3S@/LPC@/CMC@/255@/EVT@/X4E@/17@ 8145U@/WHL@/PCB@/MEM@/SDP@/X76DHYN@/UMA@/NC10@/CNVI@/NCHG@/NRD@/3S@/LPC@/CMC@/255@/EVT@/X4E@/15@ 4 Compal Secret Data Security Classification Issued Date 2018/12/27 Deciphered Date 2019/12/27 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Notes List Size Document Number Custom B C D Rev 0.1 EH7LW M/B LA-H792P Date: A Compal Electronics, Inc Thursday, June 06, 2019 Sheet E of 46 A DRVEN_CPU B RT9610CGQW (PUZ2) C D E +VCC_CORE RT9610CGQW (PUZ3) U42@ RT9610CGQW (PUG1) +VCC_GT RT9610CGQW (PUA1) +VCC_SA Vinafix.com ADAPTER SYSON JUMP (PJM3) +1.2VP SM_PG_CTRL RT8207PGQW (PUM1) JUMP (PJM4) +0.6VSP +19VB BATTERY 5V_EN SY8288CRAC (PU501) +5VALWP JUMP (PJ501) R-0ohm (RC464) +1.2V_VDDQ +1.2V_VCCPLL_OC +0.6VS_VTT +5VALW CHARGER (PU301) SUSP# AOZ1331DI (UQ1) CHG_EN SLGC55544CVTR (US12) CHG@ USB_EN SY6288C20AAC (US21) LDO JUMP (JPQ2) +5VS_OUT +5VS +USB3_VCCA JUMP (JPC10) +USB3_VCCB R-Short (RX8) +TS_PWR AP2330W (UY1) +HDMI_5V_OUT R-Short (RO3) +5VS_HDD R-short (RO26) +5VS_ODD JUMP (JPA1) +VDDA R-Short (RF1) +VCC_FAN1 KBL_EN NCHG@ SY6288C20AAC (U1) +5VS_BL JIO1 (IO/B) +3VLP ohm (RS155) 3V_EN SY8286BRAC (PU301) +3VALWP JUMP (PJ301) +3VALW R-Short (RC173) +3VALW_DSW JUMP (JPC7) +3VALW_PRIM SYSON +3VALW_USB3RD +2.5VP LAN_PWR_EN SY6288C20AAC (UL1)/R-Short TP_PWR_EN SY6288C20AAC (UK1) WLAN_ON SY6288C20AAC (UM1) ohm (RS10) SUSP# EN_1.8VALW R-Short (RC198) +3VALW_HDA R-Short (RC154) +3VALW_SPI SY8288RAC (PUF1) +1.05VALWP JUMP (PJF1) +LCDVDD SY8032ABC (PU1101) VGA@ +1.05VSDGPUP +3VS_SSD_NGFF +3V_LAN R-Short (RC178) +1.8VS_3VS_PGPPA +3V_PTP R-Short (RW2) +3VS_TPM +3VS_WLAN R-Short (RA2) +3VS_DVDDIO +3VS_DVDD +3VALW_CC R-Short (RA5) SY6288C20AAC (UK6)FP@ +FP_VCC JEDP1 (CAMERA) 0-ohm (RW1) TPM@ +3VALW_TPM JMIC1 (4DMIC) AOZ1331DI (UQ2) +3VS_OUT G9661MF11U (PU1801) JUMP (JPQ3) +1.8VALWP R-Short (RC243) +1.05VALW_PRIM +1.05VALW_MPHYPLL Inductor (LC2) +VCCA_XTAL_1.05V AOZ1331DI (UC5) SUSP# AOZ1334DI-02 (UC6) +1.05VS_1.0VSDGPU +3VS JUMP (PJ1802) +1.8VALW_PRIM AOZ1331DI (UC5) +1.8VS R-Short (RA6) +1.8VS_VDDA +1.05VALW_MPHY Inductor (LC1) SYSON JUMP (PJ1101) +3VS_WLAN R-Short (RM9) SUSP# EN_1VALW SY6288C20AAC (UX1) PEX_VDD_EN ohm (RM1)NBYOC@ G9661MF11UI (PUM2) FP_PWR_EN SOC_ENVDD ohm (RC143) +1.05V_VCCSFR +1.05V_VCCSTU ohm (RC140) +1.05V_VCCST +1.05VS_VCCSTG_IO ohm (RC462) +1.05VS_VCCSTG JUMP (JPC5) +VCCIO 4 EN_12VSP HCB2012KF (LX1) 3S@ +INVPWR_B+ Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2018/12/27 Deciphered Date 2019/12/27 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D Number Re v 0.1 EH7LW M/B LA-H792P Date : A Power Rail Size Document Custom Thursday, June 06, 2019 E Sheet of 46 A B C 2.2K SOC_SMBCLK CK14 Vinafix.com 2.2K E 2.2K +3VALW_PRIM +3VS 2.2K 2N7002DW SOC_SMBDATA D SO-DIMM CH15 Whiskeylake SOC SOC_SML0CLK CH14 SOC_SML0DATA CF15 2.2K G-Sensor +3VALW_PRIM 2.2K 2.2K 2.2K CN15 SOC_SML1CLK CM15 SOC_SML1DATA +3VALW_PRIM 2 2.2K 2.2K 77 EC_SMB_CK1 78 EC_SMB_DA1 SCL1 SDA1 +3VLP_EC 100 ohm 100 ohm EC_SMB_CK1-1 EC_SMB_DA1-1 BATTERY CONN 12 11 KBC SCL2 79 SOC_SML1CLK SDA2 80 SOC_SML1DATA Charger KB9022 I2C Address Table BUS I2C_0 (+3VS) I2C_1 (+3VALW_PRIM) SOC_SMBCLK (+3VS) SOC_SML1CLK (+3VALW_PRIM) EC_SMB_CK1 (+3VLP) Address (8 bit) Device Reserved TM-P3393-003 (TP) FA577E-1206 (TP-ELAN) SA577C-12A0 (TP-ELAN) SO-DIMM2 G-Sensor EC 0x2C 0x15 0x15 0xA4 0x30 BQ24781 (Charger IC) BATTERY PACK 0x12 0x16 Compal Secret Data Security Classification 2018/12/27 Issued Date Deciphered Date 2019/12/27 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D Compal Electronics, Inc SMBUS_Routing_Table Size Document Number Custom Rev 0.1 EH7LW M/B LA-H792P Date: A Thursday, June 06, 2019 Sheet E of 46 A B C D E PWR Sequence_SKL-U2+2_DDR3L_Value_NON CS +RTCVCC SOC_RTCRST# tPCH01_Min : ms Vinafix.com 1 +19VB +3VLP EC_ON tPCH04_Min : ms +5VALW/+3VALW(+3VALW_DSW ) tPCH34_Max : 20 ms SPOK tPCH06_Min : 200 us (+3VALW stable (@95% of full value) to +1.0VALW_PRIM starting to ramp) +1.8VALW_PRIM +1.8VALW_PG +VCCPRIM_CORE/+1.0VALW_PRIM tPCH03_Min : 10 ms EC_RSMRST# ON/OFF PBTN_OUT# tPCH43_Min : 95 ms Minimum duration of PWRBTN# assertion = 16mS PWRBTN# can assert before or after RSMRST# PM_SLP_S5# tPCH18_Min : 90 us ESPI_RST# PM_SLP_S4# SYSON +1.0V_VCCSTU +1.2V_VDDQ PM_SLP_S3# SUSP# tCPU04 Min : 100 ns +1.0VS_VCCSTG tCPU10 Min : ms +VCCIO 3 +5VS/+3VS/+1.8VS/+1.5VS tCPU00 Min : ms EC_VCCST_PG VR_ON tCPU19 Max : 100 ns SM_PG_CTRL tCPU18 Max : 35 us +0.6VS_VTT tCPU09 Min : ms +VCC_SA VR_PWRGD tCPU16 Min : ns tPLT05 Min : Platform dependent PCH_PWROK (SYS_PWROK) H_CPUPWRGD PLT_RST# +VCC_CORE / +VCC_GT 4 Compal Secret Data Security Classification Issued Date 2018/12/27 2019/12/27 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Power Sequence Size Document Number Custom B C D R ev 0.1 EH7LW M/B LA-H792P Date: A Compal Electronics, Inc Thursday, June 06, 2019 Sheet E of 46 A B UC1 C D E UC1 S IC FJ8068404064702 SRD1V W0 2.1G ABO! 8145W0@ S IC CL8068404064409 SRFFW V0 1.8G ABO! 8565U@ SA0000C6R60 SA0000CNR50 UC1 UC1 UC1A AL5 AL6 AJ5 AJ6 AF6 AF5 AE5 AE6 Vinafix.com S IC FJ8068404064604 SREJQ W0 1.6G ABO! 8265W0@ S IC FJ8070104303905 SRGKW V0 1.8G BGA 10510U@ SA0000C6Q60 SA0000CNR50 HDMI change to DDI2 port 11/26 HDMI UC1 UC1 S IC FJ8070104307606 SRGL0 V0 2.1G BGA 10110U@ S IC CL8068404064708 SRFFZ V0 2.1G ABO! 8145U@ AC4 AC3 AC1 AC2 AE4 AE3 AE1 AE2 SOC_DP2_N0 SOC_DP2_P0 SOC_DP2_N1 SOC_DP2_P1 SOC_DP2_N2 SOC_DP2_P2 SOC_DP2_N3 SOC_DP2_P3 DDI1_TXN_0 DDI1_TXP_0 DDI1_TXN_1 DDI1_TXP_1 DDI1_TXN_2 DDI1_TXP_2 DDI1_TXN_3 DDI1_TXP_3 AM6 CC8 CC9 UC1 UC1 S IC FJ8070104307504 SRGKY V0 1.6G BGA 10210U@ S IC CL8068404064610 SRFFX V0 1.6G ABO! 8265U@ SA0000CNR50 SOC_DP2_CTRL_CLK CH4 SOC_DP2_CTRL_DATA CH3 SOC_DP2_CTRL_CLK SOC_DP2_CTRL_DATA DDI EDP_AUX_N EDP_AUX_P DISP_UTILS DDI1_AUX_N DDI1_AUX_P DDI2_AUX_N DDI2_AUX_P DDI3_AUX_N DDI3_AUX_P DISPLAY SIDEBANDS EDP_COMP HDMI DDC (Port B) EDP DDI2_TXN_0 DDI2_TXP_0 DDI2_TXN_1 DDI2_TXP_1 DDI2_TXN_2 DDI2_TXP_2 DDI2_TXN_3 DDI2_TXP_3 SA0000CNR50 SA0000CNT60 EDP_TXN_0 EDP_TXP_0 EDP_TXN_1 EDP_TXP_1 EDP_TXN_2 EDP_TXP_2 EDP_TXN_3 EDP_TXP_3 CP4 CN4 SA0000CNS70 CR26 CP26 AG4 AG3 AG2 AG1 AJ4 AJ3 AJ2 AJ1 EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3 AH4 AH3 EDP_AUXN EDP_AUXP eDP AM7 AC7 AC6 AD4 AD3 AG7 AG6 DISP_RCOMP GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE# GPP_E19/DPPB_CTRLDATA GPP_E13/DDPB_HPD0/DISP_MISC0 GPP_E14/DDPC_HPD1/DISP_MISC1 GPP_E15/DPPD_HPD2/DISP_MISC2 GPP_E16/DPPE_HPD3/DISP_MISC3 GPP_E17/EDP_HPD/DISP_MISC4 GPP_E20/DPPC_CTRLCLK GPP_E21/DPPC_CTRLDATA GPP_E22/DPPD_CTRLCLK GPP_E23/DPPD_CTRLDATA EDP_BKLTEN EDP_VDDEN EDP_BKLTCTL CN6 CM6 CP7 CP6 CM7 CK11 CG11 CH11 SOC_DP2_HPD EC_SCI# CPU_EDP_HPD ENBKL SOC_ENVDD SOC_BKL_PWM From HDMI SOC_DP2_HPD EC_SCI# CPU_EDP_HPD From eDP ENBKL SOC_ENVDD SOC_BKL_PWM GPP_H16/DDPF_CTRLCLK GPP_H17/DDPF_CTRLDATA 12/21 PU #571021 CFL-U PDG R0.7 p.104 WHL-U42_BGA1528 @ EC_SCI# +3VS RC212 10K_0402_5% @ of 20 EC_SCI# SOC internal PU #545659 PCH EDS1.51 P.131 SCI capability is available on all GPIOs, while NMI and SMI capability is available on only select GPIOs Below are the PCH GPIOs that can be routed to generate SMI# or NMI: ‧ GPP_B14, GPP_B20, GPP_B23 ‧ GPP_C 23 : 22 ‧ GPP_ D : ‧GPP_E : , GPP_E 16 : 13 +VCCIO RC1 24.9_0402_1% EDP_COMP #571021 CFL-U PDG R0.7 p.39 PU 24.9ohm for eDP +1.05VS_VCCSTG RC2 1K_0402_5% H_THERMTRIP# CC132 ESD@ 1000P_0402_50V7K Reserved CATERR# for sight i ngs i ss ue check #571021 CFL-U PDG R0.7 p.248 PU 1Kohm to VCCST +1.05V_VCCST H_PROCHOT# RC3 1K_0402_5% RC4 499_0402_1% @ T166 H_PECI @ T160 @ T161 EC_TP_INT# CC52 @ESD@ 1U_0402_16V7K H_PECI H_PROCHOT#_R ESD@ CC53 1000P_0402_50V7K RC137 @ 0_0402_5% SOC_XDP_TRST# H_CATERR# H_PECI H_PROCHOT#_R H_THERMTRIP# XDP_BPM#0 XDP_BPM#1 UC1D AA4 AR1 Y4 BJ1 U1 U2 U3 U4 CE9 CN3 CB34 CC35 TP_INT# RC5 RC6 2 49.9_0402_1% CPU_POPIRCOMP 49.9_0402_1% PCH_OPIRCOMP RC7 RC8 @ @ 49.9_0402_1% EDRAM_OPIO_RCOMP 49.9_0402_1% EOPIO_RCOMP BP27 BW25 L5 N5 #575412 WHL-U PDG R0.8 For CFL U43e, Pins L5 and N5 are OPCE_RCOMP and OPC_RCOMP respect i vel y whil e i n WHL, CNL SoCs these pins are RSVD CATERR# PECI PROCHOT# THRMTRIP# CPU MISC JTAG BPM#_0 BPM#_1 BPM#_2 BPM#_3 PROC_TCK PROC_TDI PROC_TDO PROC_TMS PROC_TRST# PCH_TCK PCH_TDI PCH_TDO PCH_TMS PCH_TRST# PCH_JTAGX GPP_E3/CPU_GP0 GPP_E7/CPU_GP1 GPP_B3/CPU_GP2 GPP_B4/CPU_GP3 PROC_PREQ# PROC_PRDY# CPU_XDP_TCK0 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST# T6 U6 Y5 T5 AB6 ZZZ PCB@ PCH_JTAG_TCK1 SOC_XDP_TDI SOC_XDP_TDO SOC_XDP_TMS SOC_XDP_TRST# CPU_XDP_TCK0 W6 U5 W5 P5 Y6 P6 XDP_PREQ# XDP_PRDY# W2 W1 PCB EH7LW LA-H792P LS-H781P/H783P/H784P T280 @ DAZ2MF00203 ZZZ PCB20@ PCB EH7LW LA-H792P LS-H781P/H783P/H784P DAZ2MF00204 T197 @ T196 @ PROC_POPIRCOMP PCH_OPIRCOMP ZZZ RSVD70 RSVD71 WHL-U42_BGA1528 @ @ESD@ CC81 1U_0402_16V7K HDMI LOGO LOGO@ RO0000003HM of 20 ZZZ X4E@ +1.05VS_VCCSTG For Intel debug, place to CPU side #575412 WHL-U PDG R0.8 Figure.13-6 RC11 CMC@ 51_0402_5% SOC_XDP_TMS RC13 CMC@ 51_0402_5% SOC_XDP_TDI SMT EMC EE AH791 EH7LW X4EAI6BOL01 RC15 CMC@ 51_0402_5% SOC_XDP_TDO RC35 CMC@ 51_0402_5% CPU_XDP_TCK0 ZZZ X4E@ SMT EMC UMA AH792 EH5LC X4EAI6BOLD1 Compal Secret Data Security Classification Issued Date 2018/12/27 2019/12/27 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom EH7LW M/B LA-H792P Date: A B C D Compal Electronics, Inc WHL-U(1/12)DDI,MSIC,XDP,EDP Friday, August 02, 2019 Sheet E of 46 R ev 0.1 A B C D E Interleaved Memory UC1B DDR_A_D[0 15] DDR_A_D[16 31] DDR_A_D[32 47] DDR_A_D[48 63] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 A26 D26 D28 C28 B26 C26 B28 A28 B30 D30 B33 D32 A30 C30 B32 C32 H37 H34 K34 K35 H36 H35 K36 K37 N36 N34 R37 R34 N37 N35 R36 R35 AN35 AN34 AR35 AR34 AN37 AN36 AR36 AR37 AU35 AU34 AW35 AW34 AU37 AU36 AW36 AW37 BA35 BA34 BC35 BC34 BA37 BA36 BC36 BC37 BE35 BE34 BG35 BG34 BE37 BE36 BG36 BG37 UC1C Interleave / Non-Interleaved DDR0_DQ_0/DDR0_DQ_0 DDR0_DQ_1/DDR0_DQ_1 DDR0_DQ_2/DDR0_DQ_2 DDR0_DQ_3/DDR0_DQ_3 DDR0_DQ_4/DDR0_DQ_4 DDR0_DQ_5/DDR0_DQ_5 DDR0_DQ_6/DDR0_DQ_6 DDR0_DQ_7/DDR0_DQ_7 DDR0_DQ_8/DDR0_DQ_8 DDR0_DQ_9/DDR0_DQ_9 DDR0_DQ_10/DDR0_DQ_10 DDR0_DQ_11/DDR0_DQ_11 DDR0_DQ_12/DDR0_DQ_12 DDR0_DQ_13/DDR0_DQ_13 DDR0_DQ_14/DDR0_DQ_14 DDR0_DQ_15/DDR0_DQ_15 DDR0_DQ_16/DDR0_DQ_32 DDR0_DQ_17/DDR0_DQ_33 DDR0_DQ_18/DDR0_DQ_34 DDR0_DQ_19/DDR0_DQ_35 DDR0_DQ_20/DDR0_DQ_36 DDR0_DQ_21/DDR0_DQ_37 DDR0_DQ_22/DDR0_DQ_38 DDR0_DQ_23/DDR0_DQ_39 DDR0_DQ_24/DDR0_DQ_40 DDR0_DQ_25/DDR0_DQ_41 DDR0_DQ_26/DDR0_DQ_42 DDR0_DQ_27/DDR0_DQ_43 DDR0_DQ_28/DDR0_DQ_44 DDR0_DQ_29/DDR0_DQ_45 DDR0_DQ_30/DDR0_DQ_46 DDR0_DQ_31/DDR0_DQ_47 DDR0_DQ_32/DDR1_DQ_0 DDR0_DQ_33/DDR1_DQ_1 DDR0_DQ_34/DDR1_DQ_2 DDR0_DQ_35/DDR1_DQ_3 DDR0_DQ_36/DDR1_DQ_4 DDR0_DQ_37/DDR1_DQ_5 DDR0_DQ_38/DDR1_DQ_6 DDR0_DQ_39/DDR1_DQ_7 DDR0_DQ_40/DDR1_DQ_8 DDR0_DQ_41/DDR1_DQ_9 DDR0_DQ_42/DDR1_DQ_10 DDR0_DQ_43/DDR1_DQ_11 DDR0_DQ_44/DDR1_DQ_12 DDR0_DQ_45/DDR1_DQ_13 DDR0_DQ_46/DDR1_DQ_14 DDR0_DQ_47/DDR1_DQ_15 DDR0_DQ_48/DDR1_DQ_32 DDR0_DQ_49/DDR1_DQ_33 DDR0_DQ_50/DDR1_DQ_34 DDR0_DQ_51/DDR1_DQ_35 DDR0_DQ_52/DDR1_DQ_36 DDR0_DQ_53/DDR1_DQ_37 DDR0_DQ_54/DDR1_DQ_38 DDR0_DQ_55/DDR1_DQ_39 DDR0_DQ_56/DDR1_DQ_40 DDR0_DQ_57/DDR1_DQ_41 DDR0_DQ_58/DDR1_DQ_42 DDR0_DQ_59/DDR1_DQ_43 DDR0_DQ_60/DDR1_DQ_44 DDR0_DQ_61/DDR1_DQ_45 DDR0_DQ_62/DDR1_DQ_46 DDR0_DQ_63/DDR1_DQ_47 WHL-U42_BGA1528 @ LPDDR3 / DDR4 DDR0_CKN_0/DDR0_CKN_0 DDR0_CKP_0/DDR0_CKP_0 DDR0_CKN_1/DDR0_CKN_1 DDR0_CKP_1/DDR0_CKP_1 Vinafix.com DDR0_CKE_0/DDR0_CKE_0 DDR0_CKE_1/DDR0_CKE_1 DDR0_CKE_2/NC DDR0_CKE_3/NC DDR0_CS#_0/DDR0_CS#_0 DDR0_CS#_1/DDR0_CS#_1 DDR0_ODT_0/DDR0_ODT_0 NC/DDR0_ODT_1 DDR0_CAB_9/DDR0_MA_0 DDR0_CAB_8/DDR0_MA_1 DDR0_CAB_5/DDR0_MA_2 NC/DDR0_MA_3 NC/DDR0_MA_4 DDR0_CAA_0/DDR0_MA_5 DDR0_CAA_2/DDR0_MA_6 DDR0_CAA_4/DDR0_MA_7 DDR0_CAA_3/DDR0_MA_8 DDR0_CAA_1/DDR0_MA_9 DDR0_CAB_7/DDR0_MA_10 DDR0_CAA_7/DDR0_MA_11 DDR0_CAA_6/DDR0_MA_12 DDR0_CAB_0/DDR0_MA_13 DDR0_CAB_2/DDR0_MA_14 DDR0_CAB_1/DDR0_MA_15 DDR0_CAB_3/DDR0_MA_16 DDR0_CAB_4/DDR0_BA_0 DDR0_CAB_6/DDR0_BA_1 DDR0_CAA_5/DDR0_BG_0 DDR0_CAA_8/DDR0_ACT# DDR0_CAA_9/DDR0_BG_1 Interleave / Non-Interleaved DDR0_DQSN_0/DDR0_DQSN_0 DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQSN_1/DDR0_DQSN_1 DDR0_DQSP_1/DDR0_DQSP_1 DDR0_DQSN_2/DDR0_DQSN_4 DDR0_DQSP_2/DDR0_DQSP_4 DDR0_DQSN_3/DDR0_DQSN_5 DDR0_DQSP_3/DDR0_DQSP_5 DDR0_DQSN_4/DDR1_DQSN_0 DDR0_DQSP_4/DDR1_DQSP_0 DDR0_DQSN_5/DDR1_DQSN_1 DDR0_DQSP_5/DDR1_DQSP_1 DDR0_DQSN_6/DDR1_DQSN_4 DDR0_DQSP_6/DDR1_DQSP_4 DDR0_DQSN_7/DDR1_DQSN_5 DDR0_DQSP_7/DDR1_DQSP_5 LPDDR3 / DDR4 NC/DDR0_ALERT# NC/DDR0_PAR DDR_VREF_CA DDR0_VREF_DQ_0 DDR0_VREF_DQ_1 DDR1_VREF_DQ DDR_VTT_CTL V32 V31 T32 T31 DDR_A_CLK#0 DDR_A_CLK0 DDR_A_CLK#1 DDR_A_CLK1 U36 U37 U34 U35 DDR_A_CKE0 DDR_A_CKE1 AE32 AF32 AE31 AF31 DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0 DDR_A_ODT1 AC37 AC36 AC34 AC35 AA35 AB35 AA37 AA36 AB34 W36 Y31 W34 AA34 AC32 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 AC31 AB32 Y32 DDR_A_MA14 DDR_A_MA15 DDR_A_MA16 W32 AB31 V34 DDR_A_BA0 DDR_A_BA1 DDR_A_BG0 V35 W35 DDR_A_ACT# DDR_A_BG1 C27 D27 D31 C31 J35 J34 P34 P35 AP35 AP34 AV34 AV35 BB35 BB34 BF34 BF35 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7 W37 W31 DDR_A_ALERT# DDR_A_PAR F36 D35 D37 E36 C35 +0.6V_A_VREFCA DDR_B_D[0 15] DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 DDR_A_CLK#0 DDR_A_CLK0 @ T286 @ T285 DDR_A_CKE0 T289 DDR_A_CS#0 T287 DDR_A_ODT0 @ T288 @ @ DDR_B_D[16 31] DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_MA16 DDR_B_D[32 47] DDR_A_BA0 DDR_A_BA1 DDR_A_BG0 DDR_A_ACT# DDR_A_BG1 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_DQS#7 DDR_A_DQS7 DDR_B_D[48 63] DDR_A_ALERT# DDR_A_PAR +0.6V_B_VREFCA DDR_PG_CTRL +0.6V_A_VREFCA +0.6V_B_VREFCA J22 H25 G22 H22 F25 J25 G25 F22 D22 C22 C24 D24 A22 B22 A24 B24 G31 G32 H29 H28 G28 G29 H31 H32 L31 L32 N29 N28 L28 L29 N31 N32 AJ29 AJ30 AM32 AM31 AM30 AM29 AJ31 AJ32 AR31 AR32 AV30 AV29 AR30 AR29 AV32 AV31 BA32 BA31 BD31 BD32 BA30 BA29 BD29 BD30 BG31 BG32 BK32 BK31 BG29 BG30 BK30 BK29 lnterleave / Non-lnterleav e d LPDDR3 / DDR4 DDR1_DQ_0/DDR0_DQ_16 DDR1_DQ_1/DDR0_DQ_17 DDR1_DQ_2/DDR0_DQ_18 DDR1_DQ_3/DDR0_DQ_19 DDR1_DQ_4/DDR0_DQ_20 DDR1_DQ_5/DDR0_DQ_21 DDR1_DQ_6/DDR0_DQ_22 DDR1_DQ_7/DDR0_DQ_23 DDR1_DQ_8/DDR0_DQ_24 DDR1_DQ_9/DDR0_DQ_25 DDR1_DQ_10/DDR0_DQ_26 DDR1_DQ_11/DDR0_DQ_27 DDR1_DQ_12/DDR0_DQ_28 DDR1_DQ_13/DDR0_DQ_29 DDR1_DQ_14/DDR0_DQ_30 DDR1_DQ_15/DDR0_DQ_31 DDR1_DQ_16/DDR0_DQ_48 DDR1_DQ_17/DDR0_DQ_49 DDR1_DQ_18/DDR0_DQ_50 DDR1_DQ_19/DDR0_DQ_51 DDR1_DQ_20/DDR0_DQ_52 DDR1_DQ_21/DDR0_DQ_53 DDR1_DQ_22/DDR0_DQ_54 DDR1_DQ_23/DDR0_DQ_55 DDR1_DQ_24/DDR0_DQ_56 DDR1_DQ_25/DDR0_DQ_57 DDR1_DQ_26/DDR0_DQ_58 DDR1_DQ_27/DDR0_DQ_59 DDR1_DQ_28/DDR0_DQ_60 DDR1_DQ_29/DDR0_DQ_61 DDR1_DQ_30/DDR0_DQ_62 DDR1_DQ_31/DDR0_DQ_63 DDR1_DQ_32/DDR1_DQ_16 DDR1_DQ_33/DDR1_DQ_17 DDR1_DQ_34/DDR1_DQ_18 DDR1_DQ_35/DDR1_DQ_19 DDR1_DQ_36/DDR1_DQ_20 DDR1_DQ_37/DDR1_DQ_21 DDR1_DQ_38/DDR1_DQ_22 DDR1_DQ_39/DDR1_DQ_23 DDR1_DQ_40/DDR1_DQ_24 DDR1_DQ_41/DDR1_DQ_25 DDR1_DQ_42/DDR1_DQ_26 DDR1_DQ_43/DDR1_DQ_27 DDR1_DQ_44/DDR1_DQ_28 DDR1_DQ_45/DDR1_DQ_29 DDR1_DQ_46/DDR1_DQ_30 DDR1_DQ_47/DDR1_DQ_31 DDR1_DQ_48/DDR1_DQ_48 DDR1_DQ_49/DDR1_DQ_49 DDR1_DQ_50/DDR1_DQ_50 DDR1_DQ_51/DDR1_DQ_51 DDR1_DQ_52/DDR1_DQ_52 DDR1_DQ_53/DDR1_DQ_53 DDR1_DQ_54/DDR1_DQ_54 DDR1_DQ_55/DDR1_DQ_55 DDR1_DQ_56/DDR1_DQ_56 DDR1_DQ_57/DDR1_DQ_57 DDR1_DQ_58/DDR1_DQ_58 DDR1_DQ_59/DDR1_DQ_59 DDR1_DQ_60/DDR1_DQ_60 DDR1_DQ_61/DDR1_DQ_61 DDR1_DQ_62/DDR1_DQ_62 DDR1_DQ_63/DDR1_DQ_63 WHL-U42_BGA1528 @ #571021 CFL-U PDG0.7 p.64 Trace width/Spacing >= 20mils DDR1_CKN_0/DDR1_CKN_0 DDR1_CKP_0/DDR1_CKP_0 DDR1_CKN_1/DDR1_CKN_1 DDR1_CKP_1/DDR1_CKP_1 DDR1_CKE_0/DDR1_CKE_0 DDR1_CKE_1/DDR1_CKE_1 DDR1_CKE_2/NC DDR1_CKE_3/NC DDR1_CS#_0/DDR1_CS#_0 DDR1_CS#_1/DDR1_CS#_1 DDR1_ODT_0/DDR1_ODT_0 NC/DDR1_ODT_1 DDR1_CAB_9/DDR1_MA_0 DDR1_CAB_8/DDR1_MA_1 DDR1_CAB_5/DDR1_MA_2 NC/DDR1_MA_3 NC/DDR1_MA_4 DDR1_CAA_0/DDR1_MA_5 DDR1_CAA_2/DDR1_MA_6 DDR1_CAA_4/DDR1_MA_7 DDR1_CAA_3/DDR1_MA_8 DDR1_CAA_1/DDR1_MA_9 DDR1_CAB_7/DDR1_MA_10 DDR1_CAA_7/DDR1_MA_11 DDR1_CAA_6/DDR1_MA_12 DDR1_CAB_0/DDR1_MA_13 DDR1_CAB_2/DDR1_MA_14 DDR1_CAB_1/DDR1_MA_15 DDR1_CAB_3/DDR1_MA_16 DDR1_CAB_4/DDR1_BA_0 DDR1_CAB_6/DDR1_BA_1 DDR1_CAA_5/DDR1_BG_0 DDR1_CAA_9/DDR1_BG_1 DDR1_CAA_8/DDR1_ACT# lnterleave / Non-lnterleaved DDR1_DQSN_0/DDR0_DQSN_2 DDR1_DQSP_0/DDR0_DQSP_2 DDR1_DQSN_1/DDR0_DQSN_3 DDR1_DQSP_1/DDR0_DQSP_3 DDR1_DQSN_2/DDR0_DQSN_6 DDR1_DQSP_2/DDR0_DQSP_6 DDR1_DQSN_3/DDR0_DQSN_7 DDR1_DQSP_3/DDR0_DQSP_7 DDR1_DQSN_4/DDR1_DQSN_2 DDR1_DQSP_4/DDR1_DQSP_2 DDR1_DQSN_5/DDR1_DQSN_3 DDR1_DQSP_5/DDR1_DQSP_3 DDR1_DQSN_6/DDR1_DQSN_6 DDR1_DQSP_6/DDR1_DQSP_6 DDR1_DQSN_7/DDR1_DQSN_7 DDR1_DQSP_7/DDR1_DQSP_7 NC/DDR1_ALERT# NC/DDR1_PAR DRAM_RESET# DDR_RCOMP_0 DDR_RCOMP_1 DDR_RCOMP_2 AF28 AF29 AE28 AE29 DDR_B_CLK#0 DDR_B_CLK0 DDR_B_CLK#1 DDR_B_CLK1 T28 T29 V28 V29 DDR_B_CKE0 DDR_B_CKE1 AL37 AL35 AL36 AL34 AG36 AG35 AF34 AG37 AE35 AF35 AE37 AC29 AE36 AB29 AG34 AC28 AB28 AK35 DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 AJ35 AK34 AJ34 DDR_B_MA14 DDR_B_MA15 DDR_B_MA16 AJ37 AJ36 W29 DDR_B_BA0 DDR_B_BA1 DDR_B_BG0 Y28 W28 DDR_B_BG1 DDR_B_ACT# DDR_B_CLK#0 DDR_B_CLK0 DDR_B_CLK#1 DDR_B_CLK1 DDR_B_CKE0 DDR_B_CKE1 DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_MA16 DDR_B_BA0 DDR_B_BA1 DDR_B_BG0 DDR_B_BG1 DDR_B_ACT# H24 G24 C23 D23 G30 H30 L30 N30 AL31 AL30 AU31 AU30 BC31 BC30 BH31 BH30 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7 Y29 AE34 BU31 DDR_B_ALERT# DDR_B_PAR BN28 BN27 BN29 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_DQS#3 DDR_B_DQS3 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_DQS#5 DDR_B_DQS5 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_ALERT# DDR_B_PAR DDR_DRAMRST# of 20 of 20 3 +1.2V_VDDQ +3VS CC57 UC7 NC VCC A Y RC10 100K_0402_5% SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_PG_CTRL @ RC16 1M_0402_5% Change PN to SA00007WE00 121_0402_1% 80.6_0402_1% 100_0402_1% @ESD@ DDR_DRAMRST# CC70 1U_0402_16V7K GND 74AUP1G07SE-7_SOT353_5P RC38 RC39 RC40 #571021 PDG P.64 W=15 Space= 20/25 L=500mil 2 DDR_PG_CTRL #595182 P38 0.1U_0201_10V6K DDR_VTT_CNTL to DDR VTT supplied ramped Provides cadence for 44.1 kHz based sample rate output > Support 1.5V, 1.8V, and 3.3V modes * +3VALW_PRIM UC1I TOP Swap Override = Disable TOP Swap mode = Enable TOP Swap Mode Add PU resistor 12/20 RC467 100K_0402_5% C10@ RC258 20K_0402_5% @ #570990 CFL-U CRB R1.0 XTAL_FREQ_SELECT LOW: 38.4/19.2MHz HIGH: 24MHz Compal Secret Data Security Classification Issued Date 2018/12/27 2019/12/27 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D Compal Electronics, Inc WHL-U(4/12)HDA,EMMC,SDIO,CNVI Size Document Number Custom R ev 0.1 EH7LW M/B LA-H792P Date: A Thursday, June 06, 2019 Sheet E 10 of 46 A B C D FAN1 Conn Screw Hole +5VS 40mil H5 H6 H_3P3 H_3P3 H7 H8 H_3P0-G H_4P5X4P0 @ @ @ @ @ @ @ FIDUCIAL_C40M80 FIDUCIAL_C40M80 FD3 FD4 +3VS H20 H_2P0N H22 H_2P7X2P0N @ 1 @ FD2 @ FIDUCIAL_C40M80 1 @ 1 FD1 1 H1 H2 H3 H4 H_3P0-G H_3P0-G H_3P3 H_3P3 CF1 4.7U_0402_6.3V6M Vinafix.com 0_0603_5% +VCC_FAN1 @EMI@ CF2 1000P_0402_50V7K 1 RF1 E @ FIDUCIAL_C40M80 FAN_SPEED1 FAN_PWM1 CF3 1000P_0402_50V7K @EMI@ JFAN1 @ @ 40mil +VCC_FAN1 FAN_SPEED1 FAN_PWM1 RF2 10K_0402_5% G1 G2 ACES_50278-00401-001 CONN@ SP02000RR00 2 Reset Circuit +3VLP RG1 RG2 @ 0_0402_5% MAINPWON RG3 10K_0402_5% BI_GATE# BI_GATE BI_GATE D 2N7002KDW_SOT363-6 QG1A QG1B 2N7002KDW_SOT363-6 S S G 3 EC_RST# D G BI_GATE PH to +RTCVCC at PWR side 0_0402_5% C70 0.1U_0201_10V6K Reset Button SWG2 BI_GATE BI_GATE SKRPABE010_4P 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2018/12/27 2019/12/27 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title FAN & Screw Hole & Reset Size Document Number Custom Date: A B C D R ev 0.1 EH7LW M/B LA-H792P Thursday, June 06, 2019 Sheet E 32 of 46 B Vinafix.com @ CT1 VIN1 VIN1 UQ1 VOUT1 VOUT1 13 14 CQ11 @ JPQ3 +3VS_OUT 1 2 +3VS Q2B 2N7002KDW_SOT363-6 SUSP# JUMP_43X118 1000P_0402_50V7K Q3A @ 2N7002KDW_SOT363-6 S R27 470_0603_5% @ PM_SLP_S4# Q6B 2N7002KDW_SOT363-6 G 1 Q5A @ 2N7002KDW_SOT363-6 G S SYSON# D Q7 L2N7002WT1G_SC-70-3 @ SYSON# SYSON# D Q5B @ 2N7002KDW_SOT363-6 G SYSON SYSON G S MOW14, For tPLT15 200us(max) SLP_S4# to VDDQ ramp down D S SYSON 4 R30 10K_0402_5% @ S +1.2V_VDDQ_R 3 SUSP G R28 100K_0402_5% @ PM_SLP_S4 D D Q4B @ 2N7002KDW_SOT363-6 D S 2 R31 470_0603_5% @ +0.6VS_VTT_R G S Q6A 2N7002KDW_SOT363-6 2 @ SUSP# +5VALW S D D +1.2V_VDDQ PCH_PWROK G Q4A @ 2N7002KDW_SOT363-6 @ Q3B @ 2N7002KDW_SOT363-6 R29 100K_0402_5% +2.5V SUSP SYS_PWROK G +3VALW +5VALW +0.6VS_VTT R26 470_0603_5% MOW14, For tPLT18 200us(max) SLP_S3# to VCCIO VR disable CQ3 R25 100K_0402_5% MOW14, For tPLT17 200us(max) SLP_S3# to IMVP VR_ON deassertion S D G S @ PM_SLP_S3# @ D D CQ7 1U_0402_16V7K Q1B 2N7002KDW_SOT363-6 VR_ON D +5VALW G 1U_0402_16V7K 1U_0402_16V7K CQ2 AOZ1331DI_DFN14_2X3 15 GPAD VIN2 VOUT2 VIN2 VOUT2 10 ON2 CT2 11 VBIAS GND 12 ON1 CT1 13 VIN1 VOUT1 14 VIN1 VOUT1 UQ2 S 3VS_ON 0_0402_5% EC_VCCST_PG_R MOW14, For tCPU28 200us(max) SLP_S3# to VCCST_PWRGD deassertion G 1U_0402_10V7 CQ9 RQ1 SUSP# S Q2A 2N7002KDW_SOT363-6 +3VALW Q1A 2N7002KDW_SOT363-6 R24 100K_0402_5% 12 G GND ON1 PM_SLP_S3 +3VALW 1000P_0402_50V7K 11 D @ 1U_0402_16V7K CQ10 VBIAS CT2 S ON2 For Power ON/Off Sequence +5VS CQ1 +5VALW 1U_0402_16V7K 10 G CQ4 5VS_ON E 1U_0402_10V7 CQ8 RQ2 0_0402_5% SUSP# CQ5 1U_0402_16V7K AOZ1331DI_DFN14_2X3 15 GPAD VIN2 VOUT2 VIN2 VOUT2 +5VALW D DC Interface C A 3 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2018/12/27 2019/12/27 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title DC Interface Size Document Number Custom Date: A B C D R ev 0.1 EH7LW M/B LA-H792P Thursday, June 06, 2019 Sheet E 33 of 46 A B C D E Vinafix.com 1 EMI@ PL101 +19V_ADPIN 5A_Z120_25M_0805_2P @ PJP101 +19V_VIN ACES_50278-00401-001 PC102 EMI@ 100P_0402_50V8J EMI@ PC105 1000P_0402_50V7K 1 2 G2 G1 EMI@ PC104 1000P_0402_50V7K 2 @ PR101 +3VLP +CHGRTC 0_0402_5% 3 4 Compal Secret Data Security Classification Issued Date 2018/12/27 2019/12/27 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR DCIN / Pre-charge Size Document Number Custom B C D R ev 0.1 EH7LW M/B LA-H792P Date: A Compal Electronics, Inc Thursday, June 06, 2019 Sheet E 34 of 46 A B C D E Vinafix.com 1 MB:Battery Con Put TOP Side PR207 PR205 100_0402_1% 100_0402_1% Battery Bot Side PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 PIN8 GND GND SMD SMC TEMP BI Batt+ Batt+ PR202 200K_0402_1% @ PJP201 1 2 3 4 5 6 7 8 GND 10 GND EC_SMB_DA1-1 EC_SMB_CK1-1 BATT_TS BATT_B/I PR203 EC_SMB_DA1 EC_SMB_CK1 +3VLP BATT_TEMP 1K_0402_1% +RTCVCC 2016/11/16 update CVILU_CI9908M2HR0-NH PR212 100K_0402_5% 2 BI_GATE change PL201, PL202 SM01000C000 to comm part SM01000P200 +12.6V_BATT PL202 S @ PR217 0_0402_5% 58.5W,1V Active=recovery 65W PR206 7.87K ohm 84.5W,1V Active=recovery 90W PR20K ohm W, V Active=recovery 1 5A_Z120_25M_0805_2P EMI@ EMI@ PC201 1000P_0402_50V7K 2 45W PR206 2.32K ohm 1 Recovery PQ201 LBSS139LT1G 1N SOT-23-3 G EMI@ PL201 5A_Z120_25M_0805_2P Active D +12.6V_BATT+ For KB9022 sense 20mΩ PQ201 Change to SB00000QO00, SB501380010(BSS138LT1G Del) EMI@ PC202 0.01U_0402_25V7K PH1 2V PH1 under CPU botten side : CPU thermal protection at 89 +-3 degree C Recovery at 56 +-3 degree C 1V 2013/06/07 Add for ENE9022 Battery Voltage drop detection Connect to ENE9022 pin64 AD1 +3VLP_ECA PR204 16.9K_0402_1% 45W@ PR206 2.32K_0402_1% 2 PH201 PC203 must close to EC pin @ PC203 0.1U_0402_25V6 VCIN1_ADP_PROCHOT 100K_0402_1%_NCP15WF104F03RC 1 VCIN1_BATT_DROP PR208 T202 T201 must close to PH201 T202@ 10K_0402_1% PR211 150K_0402_1% 65W@ PR206 7.87K_0402_1% 0_0402_5% PR210 @ VCIN0_PH PR209 750K_0402_1% PC204 0.1U_0402_25V6 +19VB_5V VAL50/ZAL20 Battery is 3-cell NVDC design B+=9V Change PR12=50k if Battery is 2-cell NVDC design B+=6V ADP_I T201@ ECAGND 4 Compal Secret Data Security Classification Issued Date 2018/12/27 2019/12/27 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR-BATTERY CONN/OTP Size Document Number Custom B C D R ev 0.1 EH7LW M/B LA-H792P Date: A Compal Electronics, Inc Thursday, June 06, 2019 Sheet E 35 of 46 A B S 0.1U_0402_25V7K 0.022U_0603_25V7K 10_0402_1% 0.01U_0402_25V7K~N ACDRV_CHGR_R PRB7 4.02K_0402_1% ACDRV_CHGR PRB5 4.02K_0402_1% 1 PCB13 EMI@ PCB10 0.1U_0402_25V6 BATDRV_CHGR PRB8 1CMSRC_CHGR +12.6V_BATT_CHG PCB2 EMI@ PCB9 0.1U_0402_25V6 PCB12 0.1U_0402_25V6 ACN PCB8 @ 10U_0603_25V6M ACP 10U_0603_25V6M PCB7 EMI@ PCB6 2200P_0402_50V7K PCB11 +19V_CHG EMI@ PLB1 HCB2012KF-121T50_0805 PCB4 PCB3 0.047U_0603_25V7M Vinafix.com PRB3 0.01_1206_1% PQB4 AON7506_DFN33-8-5 ACFET MDU1512 SB00000SY00 Rds(on):4.2~5m Ohm Vgs=20V Vds=30V ID= 24.2A (Ta=70C) AON7506_DFN33-8-5 +19V_P2 @EMI@ PCB5 68P_0402_50V8J +19V_P1 10U_0603_25V6M 1 PRB4 4.7_0603_1% PRB9 0_0402_5% 0_0402_5% 2 ACN_CHGR PRB10 ACP_CHGR PCB1 1000P_0402_50V7K PQB2 PQB3 3M_0402_5% EMB04N03H_EDFN5X6-8-5 +19VB PQB1 E L2N7002SW T1G_SOT323-3 G D PRB2 +19V_VIN C PRB6 D PRB1 1M_0402_1% BATSRC_CHGR 4.02K_0402_1% 0_0402_5% 100P_0402_50V8J DCHG_I 10 @ PCB21 100P_0402_50V8J @ PRB23 H_PROCHOT# 13 14 @ 0_0402_5% 20160601 colay BQ24781 15 16 29 LG_CHGR IDCHG LODRV PMON /PROCHOT GND GND ILIM NC /BATPRES /TB_STAT PWPD SRN BATDRV BATSRC 22 PRB22 21 20 SRP_CHGR PRB25 10_0402_1% 19 SRN_CHGR 18 BATDRV_CHGR PRB27 10_0402_1% 17 BATSRC_CHGR BATT_4S +3VLP 78.7K_0402_1% 2 PQB6 PCB25 0.1U_0402_25V6 SRP SRN +6V_CHG_REGN BQ24781RUYR_W QFN28_4X4 @ PRB36 10K_0402_1% 4S_BATT@ PRB28 2M_0402_1% 3.3*100/(316+100)=0.79 ICHG= 0.79 /(20*0.01)=3.95A H/L Side AON7506 SB000010A00 Rds(on):13~15.8mohm Vgs=20V Vds=30V ID= 10.5A (Ta=70C) 3.3*78.7/(316+78.7)=0.66 ICHG= 0.66 /(20*0.01)=3.28A +6V_CHG_REGN 4S_BATT@ PRB31 0_0402_5% PRB32 10K_0402_1% AC_IN PRB34 10K_0402_1% 2 4S_BATT@ PQB7 LTC015EUBFS8TL_UMT3F ACPRN_CHGR 1 4S_BATT@ PRB33 100K_0402_1% 316K_0402_1% PRB24 ILIM_CHGR LX_CHGR 23 2 27 PRB19 0.01_1206_1% BATT_TEMP CHG_TB_STAT ACDET PHASE SRP +12.6V_BATT PLB2 4.7UH_PCMB063T-4R7MS_8A_20% IADP PRB26 0_0402_5% For 4S per cell 4.35V battery ACOK 0_0603_5% PCB23 10U_0603_25V6M 1 UG_CHGR PRB18 26 EMI@ PRB20 4.7_1206_5% PCB20 HIDRV ADP_I SCL 1SNUB_CHGR ACPRN_CHGR BST_CHGR1 EC_SMB_CK1_CHGR 12 25 SDA EMI@ PCB24 680P_0402_50V7K 0_0402_5% BTST PRB14 0_0603_5% 2DH_CHGR_R AON7506_DFN33-8-5 ACDET PCB19 0.047U_0603_25V7M 2BST_CHGR_R 2 Choke 4.7uH SH00000YC00 (Common Part) (Size:6.6 x 7.3 x mm) (DCR:28m~33m) EC_SMB_DA1_CHGR 11 PRB16 0_0402_5% @ PCB27 0.1U_0402_25V6 EC_SMB_CK1 24 @ PRB15 @ PRB17 REGN PCB26 0.1U_0402_25V6 EC_SMB_DA1 CMSRC PQB5 AON7506_DFN33-8-5 VCC CMSRC_CHGR PRB13 66.5K_0402_1% 28 PCB18 2.2U_0603_25V7M PUB1 PCB22 10U_0603_25V6M +6V_CHG_REGN ACDET PCB17 2200P_0402_25V7K 2016/03/13 SE158225K80 X1 down size SE00000WP00 S CER CAP 2.2U 25V K X5R 0603 ACDRV_CHGR ACN @ PCB15 1000P_0402_50V7K 1U_0603_25V6K ACDRV 2 PCB16 +19VB ACP PRB11 422K_0402_1% PRB12 10_1206_5% PDB1 S SCH DIO BAS40CW SOT-323 +19V_VIN +19V_VIN PRB35 12K_0402_1% SUSP# D G L2N7002SW T1G_SOT323-3S Compal Secret Data Security Classification 4S_BATT@ PQB9 2 2018/12/27 Issued Date Deciphered Date 2019/12/27 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom B C D R ev 0.1 EH7LW M/B LA-H792P Date: A Compal Electronics, Inc charger Thursday, June 06, 2019 Sheet E 36 of 46 A B C Vinafix.com D E BST_3V PC306 10U_0603_25V6M PC302 0.1U_0402_25V7K 2 SPOK_3V PC312 22U_0603_6.3V6M PC311 22U_0603_6.3V6M @ PC310 22U_0603_6.3V6M PC309 22U_0603_6.3V6M PC308 22U_0603_6.3V6M 1 @ PC307 22U_0603_6.3V6M 1 3V_SN 21 PC313 4.7U_0402_6.3V6M @EMI@ PC314 680P_0402_50V7K 11 16 GND @EMI@ PR305 4.7_1206_5% +3VLP NC NC NC 2 BS IN IN LDO EN2 18 17 PG +3VALWP 19 GND GND SY8286BRAC_QFN20_3X3 PR301 100K_0402_5% PL302 1.5UH_6A_20%_5X5X3_M LX_3V 20 15 10 LX OUT SPOK_3V GND FF +3VALWP LX 14 PU301 LX EN1 13 LX_3V IN IN 0_0603_5% 12 @ PC305 10U_0603_25V6M EMI@ PC304 2200P_0402_50V7K +19VB_3V +19VB PR303 150K_0402_1% @ PR304 EMI@ PC301 0.1U_0402_25V6 1 EMI@ PL301 FBMA-L11-201209-800LMA50T @EMI@ PC303 0.1U_0402_25V6 +19VB PR302 499K_0402_1% ENLDO_3V EN1 and EN2 dont't floating Vout is 3.234V~3.366V 3.3V LDO 150mA~300mA ENLDO_3V PC315 1000P_0402_50V7K 3V_FB PR306 1K_0402_5% 3V_EN @ PJ301 +3VALWP keep short pad, snubber is for EMI only @ PR502 1BST_5V 0_0402_5% Fsw : 600K Hz +5VALWP PC516 1000P_0402_50V7K 5V_FB 5V_FB_1 680P_0402_50V7K PC514 15V_SN +5VLP 5V LDO 150mA~300mA PC513 22U_0603_6.3V6M PC512 22U_0603_6.3V6M PC511 22U_0603_6.3V6M @ PC510 22U_0603_6.3V6M 2 PC507 2.2U_0402_6.3V6M 21 PC509 22U_0603_6.3V6M 16 @EMI@ EN1 and EN2 dont't be floating EN :H>0.8V ; L