A B C D E 1 Compal Confidential 2 KAW60 Schematics Document AMD AM2 / RS690MC / SB600 2008 / 08 / 08 Rev:1.0 FOR Pre-MP 3 4 Compal Secret Data Security Classification 2005/05/09 Issued Date Deciphered Date 2006/03/08 A B C Title Cover Sheet THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC D Size Document Number Custom KAW60 LA-4661P Date: Friday, August 08, 2008 Rev 2.0 Sheet E of 50 Compal confidential Project Code: KAW60 File Name : LA-4661P Thermal Sensor ADM1032ARM page D AMD AM2 CPU Clock Generator ICS951462 940P PGA DDRII 533/667 DDRII-SO-DIMM X2 page 10,11 page 6,7,8,9 Dual Channel page 17 D H_A#(3 31) H_D#(0 63) HT 16x16 1000MHZ CRT & TV-OUT SIG1 : 35mm x 35mm x (2.20mm+2.11mm) 638pin AM2 : 40mm x 40mm x (4.56mm+2.11mm) 940pin ATI-RS690MC page 24 465 BGA LCD CONN Mini card RS485 : 21mm x 21mm (19.2mm x 19.2mm) x2.33mm 465pin RS690 : 21mm x 21mm (19.2mm x 19.2mm) x2.33mm 465pin page 12,13,14,15,16 page 25 SB460 : 27mm x 27mm (21.6mm x 21.6mm) x2.33mm 549pin SB600 : 23mm x 23mm (21.6mm x 21.6mm) x2.33mm 549pin page 31 A-Link Express x PCIE PCIE X1 USB conn x / New card / Camera USB 2.0 PCIE X1 C page 34 ATI-SB600 BT Conn USB 2.0 page 38 HDA Codec ALC268 HD Audio page 31 page 18,19,20,21,22 Realtek RTL8100CL RTL8110SCL ENE Controller CB714 page 26 page 32 page 39 1394 Controller VT6311S B RJ45 CONN 6in1 CardReader Slot page 33 Slot page 27 page 33 AMP & Audio Jack APA2057 page 40 MDC Conn page 41 page 35 HDD Conn SATA Realtek RTL8102EL C 549 BGA PCI BUS Mini PCI Socket Mini card page 31 page 23 LPC BUS 1394 Conn B page 35 SATA page 26 CDROM Conn page 23 Power On/Off CKT / LID switch / Power OK CKT page 37 DC/DC Interface CKT CIR/LED RTC CKT page 41 page 38 page 18 Power Circuit DC/DC SMsC LPC47N207 ENE KB926 page 36 page 28 Int KBD FIR module page 42~48 page 29 Touch Pad CONN page page 36 29 SPI BIOS page 30 A Compal Secret Data Security Classification 2005/03/08 Issued Date 2006/03/08 Deciphered Date Title BLOCK DIAGRAM THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Size Document Number Custom KAW60 LA-4661P Date: Rev 2.0 Sheet Sunday, July 20, 2008 of 50 SIGNAL STATE Voltage Rails D Full ON SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock HIGH HIGH HIGH HIGH ON ON ON ON Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF +0.9V 0.9V switched power rail for DDR terminator ON ON OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF +1.2V_HT 1.2V switched power rail ON OFF OFF +1.5VS 1.5V switched power rail ON OFF OFF +1.8VALW 1.8V always on power rail ON ON ON* +1.8V 1.8V power rail for DDR ON ON OFF +1.8VS 1.8V switched power rail ON OFF OFF Vcc Ra/Rc/Re +2.5VS 2.5V switched power rail ON OFF OFF Board ID +3VALW 3.3V always on power rail ON ON ON* +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON D Board ID / SKU ID Table for AD channel C Board ID External PCI Devices IDSEL# REQ#/GNT# V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V Device Address Smart Battery 0001 011X b Interrupts EEPROM(24C16/02) 1010 000X b (24C04) EC SM Bus2 address Device ADM1032 BTO Item WITH AMD HDT Debug port WITH USBx2 USBX1 WITH CHOKE USBX1 WITHOUT CHOKE USBx2 WITH CHOKE USBx2 WITHOUT CHOKE WITH MODEM SPI ROM under SB600 Address SKU ID 1001 100X b SB600 SM Bus address A Address Clock Generator (ICS951462) 1101 001Xb DDR DIMM0 1001 000Xb DDR DIMM2 1001 010Xb B SKU A Compal Secret Data Security Classification 2005/03/08 Issued Date 2006/03/08 Deciphered Date Title TABLE OF CONTENTS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC BOM Structure HDT@ USB2@ EMI@ WOEMI@ USB2EMI@ USB2WOEMI@ MDC@ SB600SPI@ SKU ID Table 1011 000X b Device C BTO Option Table PCB Revision B EC SM Bus1 address V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BOARD ID Table Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF Device 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC Size Document Number Custom HCW51 LA-3121P Date: Rev 2.0 Sheet Thursday, July 24, 2008 of 50 D D DIMM3 DIMM4 PCI CLKFB PCI CLK 33MHZ PAIR MEM CLK PAIR MEM CLK PAIR MEM CLK DIMM2 PAIR MEM CLK DIMM1 HTREFCLK 66MHZ NB-OSC 14.318MHZ M2 SOCKET NB PCIE CLK 100MHZ SB PCIE CLK 100MHZ SB-OSCIN 14.318MHZ EXTERNAL 14.318MHZ OSC INPUT (OPTION) SB-OSCIN 14.318MHZ TVCLKIN C PAIR CPU CLK 200MHZ PCI SLOT0 PCI CLK1 33MHZ PCI SLOT1 PCI CLK1 33MHZ PCI SLOT2 PCI CLK6 33MHZ LPC BIOS ATI SB ATI NB -RS690 M2 CPU PCI CLK0 33MHZ SB600 C PCI CLK5 33MHZ SIO_CLK 24/48MHZ SB-OSCIN 14.318MHZ KB_CLK SUPER IO IT8712F KEYBOARD MS_CLK MOUSE CLK GEN PCIE GFX SLOT - 16 LANES PCIE CLK 100MHZ PCIE GPP SLOT - LANE PCIE CLK 100MHZ PCIE GPP SLOT - LANE PCIE CLK 100MHZ PCIE GBE AZ_BITCLK B PCIE CLK 100MHZ AC97 CODEC AZALIA 24.576MHZ OSC INPUT 25M Hz PCIE CLK 100MHZ B PCIE STAT 32.768K Hz PCIE CLK 100MHZ USB CLK 48MHZ 48MHZ OSC INPUT FOR USB (OPTION) 14.31818MHz A A Compal Secret Data Security Classification 2005/10/10 Issued Date 2006/10/10 Deciphered Date Title CLOCK DISTRIBUTION THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Custom KAW60 LA-4661P Date: Rev 2.0 Sheet Tuesday, June 17, 2008 of 50 ATX P/S WITH 1A STBY CURRENT 5VSB +/-5% 5V +/-5% 3.3V +/-5% 12V +/-5% -12V +/-5% 2.5V SHUNT REGULATOR CPU PW 12V +/-5% VRM SW REGULATOR DDRII DIMMs 0.9V VTT_DDR REGULATOR D +5VDUAL_MEM (S0,S5) M2 CPU_VDDA_RUN (S0, S1) VDDA 2.5V 0.1A CPU_VDD_RUN (S0, S1) VDDCORE 0.8-1.55V 80A CPU_VTT_SUS (S0,S1,S3) DDRII MEM I/F VTT CPU_VDDIO_SUS(S0,S1,S3) 0.125A, VDD 3A VLDT 1.2V 0.5A VTT_DDR 2A 1.8V VDD SW REGULATOR VDDHT 1.2V 0.5A VDD MEM 12A 1.8V LINEAR REGULATOR +1.8V(S0, S1) VCC 1.2V SW REGULATOR VCC_NB (S0, S1) D RS690 PCI-E CORE&VCO & I/O &PLL 2.25A NB CORE VDDC 1.2V 5A DAC 200mA LVDS 1.8V 300mA PLL & DAC-Q 0.1A PCI-E PLL +3.3VSB (S0, S1, S3, S4, S5) +3.3VDUAL (S0, S1, S3, S4, S5) +3.3VSB REGULATOR ACPI CONTROLLER SB600 X4 PCI-E 0.8A +5VDUAL (S0, S1, S3, S4, S5) ATA I/O 0.2A C C ATA PLL 0.01A PCI-E PVDD 80mA SB CORE 0.6A 1.2V STB LDO REGULATOR +1.2VSB (S5) 1.2V S5 PW 0.22A 3.3V S5 PW 0.01A USB CORE I/O 0.2A 3.3V I/O 0.45A AZALIA CODEC 3.3V CORE 0.3A 5V ANALOG 0.1A B B SUPER I/O +5V SD 0.01A +5V 0.1A PCI Slot (per slot) A 5V 5.0A 3.3V 7.6A 12V 0.5A 3.3Vaux 0.375A -12V 0.1A X1 PCIE per X16 PCIE 3.3V 3.0A 3.3V 3.0A 12V 0.5A 12V 5.5A 3.3Vaux 0.1A CNR CONNECTOR USB X4 FR USB X6 RL 5V 1.0A VDD VDD 3.3V 1.0A 5VDual 5VDual 12V 0.5A 2.0A 2.0A 3.3Vaux 1.0A -12V 0.1A 5VDual 0.5A 2XPS/2 5VDual 1.0A SATA 3.3V 0.5A (S0, S1) 3.3V 0.3A (S0, S1) 3.3V 0.1A (S3) A Compal Secret Data Security Classification +3.3VDUAL (S0, S1, S3) GBE 2005/10/10 Issued Date 2006/10/10 Deciphered Date Title POWER DELIVERY CHART THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Custom KAW60 LA-4661P Date: Rev 2.0 Sheet Tuesday, June 17, 2008 of 50 PROCESSOR HYPERTRANSPORT INTERFACE D D VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER SUPPLY THROUGH THE PACKAGE OR ON THE DIE IT IS ONLY CONNECTED ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE +1.2V_HT JCPU1A +1.2V_HT 12 12 H_CLKIP1 H_CLKIN1 12 12 H_CLKIP0 H_CLKIN0 R38 R37 51_0402_1% 51_0402_1% 12 12 B H_CTLIP0 H_CTLIN0 L0_CADOUT_H15 L0_CADOUT_L15 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H0 L0_CADOUT_L0 H_CADOP15 H_CADON15 H_CADOP14 H_CADON14 H_CADOP13 H_CADON13 H_CADOP12 H_CADON12 H_CADOP11 H_CADON11 H_CADOP10 H_CADON10 H_CADOP9 H_CADON9 H_CADOP8 H_CADON8 H_CADOP7 H_CADON7 H_CADOP6 H_CADON6 H_CADOP5 H_CADON5 H_CADOP4 H_CADON4 H_CADOP3 H_CADON3 H_CADOP2 H_CADON2 H_CADOP1 H_CADON1 H_CADOP0 H_CADON0 N6 P6 L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKOUT_H1 L0_CLKOUT_L1 AD5 AD4 H_CLKOP1 H_CLKON1 H_CLKIP0 H_CLKIN0 H_CLKOP0 H_CLKON0 N3 N2 L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKOUT_H0 L0_CLKOUT_L0 AD1 AC1 H_CTLIP1 H_CTLIN1 V4 V5 L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLOUT_H1 L0_CTLOUT_L1 Y6 W6 H_CTLIP0 H_CTLIN0 U1 V1 L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLOUT_H0 L0_CTLOUT_L0 W2 W3 H_CTLOP0 H_CTLON0 H_CADOP15 H_CADON15 H_CADOP14 H_CADON14 H_CADOP13 H_CADON13 H_CADOP12 H_CADON12 H_CADOP11 H_CADON11 H_CADOP10 H_CADON10 H_CADOP9 H_CADON9 H_CADOP8 H_CADON8 H_CADOP7 H_CADON7 H_CADOP6 H_CADON6 H_CADOP5 H_CADON5 H_CADOP4 H_CADON4 H_CADOP3 H_CADON3 H_CADOP2 H_CADON2 H_CADOP1 H_CADON1 H_CADOP0 H_CADON0 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 +5VS C47 28 EN_DFAN1 10U_0805_10V4Z U1 VEN GND VIN GND +VCC_FAN1 GND EN_DFAN1_R VO VSET GND APL5605_SOP8L R733 0_0402_5% C760 @ 0.01U_0402_16V7K PVT +5VS H_CLKIP1 H_CLKIN1 FAN Conn Y5 Y4 AB6 AA6 AB5 AB4 AD6 AC6 AF6 AE6 AF5 AF4 AH6 AG6 AH5 AH4 Y1 W1 AA2 AA3 AB1 AA1 AC2 AC3 AE2 AE3 AF1 AE1 AG2 AG3 AH1 AG1 D3 CH355PT_SOD323 W=40mils +VCC_FAN1 L0_CADIN_H15 L0_CADIN_L15 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H0 L0_CADIN_L0 C455 4.7U_0805_10V4Z FAN1 C83 U6 V6 T4 T5 R6 T6 P4 P5 M4 M5 L6 M6 K4 K5 J6 K6 U3 U2 R1 T1 R3 R2 N1 P1 L1 M1 L3 L2 J1 K1 J3 J2 1 10U_0805_10V4Z 1000P_0402_50V7K C D4 BAS16_SOT23-3 C90 H_CADIP15 H_CADIN15 H_CADIP14 H_CADIN14 H_CADIP13 H_CADIN13 H_CADIP12 H_CADIN12 H_CADIP11 H_CADIN11 H_CADIP10 H_CADIN10 H_CADIP9 H_CADIN9 H_CADIP8 H_CADIN8 H_CADIP7 H_CADIN7 H_CADIP6 H_CADIN6 H_CADIP5 H_CADIN5 H_CADIP4 H_CADIN4 H_CADIP3 H_CADIN3 H_CADIP2 H_CADIN2 H_CADIP1 H_CADIN1 H_CADIP0 H_CADIN0 H6 H5 H2 H1 JP20 PVT +3VS 3 GND GND C H_CADIP15 H_CADIN15 H_CADIP14 H_CADIN14 H_CADIP13 H_CADIN13 H_CADIP12 H_CADIN12 H_CADIP11 H_CADIN11 H_CADIP10 H_CADIN10 H_CADIP9 H_CADIN9 H_CADIP8 H_CADIN8 H_CADIP7 H_CADIN7 H_CADIP6 H_CADIN6 H_CADIP5 H_CADIN5 H_CADIP4 H_CADIN4 H_CADIP3 H_CADIN3 H_CADIP2 H_CADIN2 H_CADIP1 H_CADIN1 H_CADIP0 H_CADIN0 VLDT_08 VLDT_07 VLDT_04 VLDT_03 R34 10K_0402_5% 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 VLDT_06 VLDT_05 VLDT_02 VLDT_01 HT LINK AJ4 AJ3 AJ2 AJ1 C92 1000P_0402_50V7K ACES_85205-03001 CONN@ 28 FAN_SPEED1 H_CLKOP1 12 H_CLKON1 12 H_CLKOP0 12 H_CLKON0 12 H_CTLOP0 12 H_CTLON0 12 TYCO_1-1735315-4_940P Trace length limit (Don't care) B CONN@ SOC127MM48X51-948! 6090022000; JCPU1 TEMP SYMBOL +1.2V_HT C164 C156 C158 C163 2 2 4.7U_0805_10V4Z 0.22U_0402_10V4Z 4.7U_0805_10V4Z 0.22U_0402_10V4Z C145 180P_0402_50V8J 2 C152 180P_0402_50V8J LAYOUT: Place bypass cap on topside of board NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY TO OTHER HT POWER PINS PLACE CLOSE TO VLDT0 POWER PINS A A Compal Secret Data Security Classification 2005/10/11 Issued Date 2006/10/11 Deciphered Date Title AMD CPU HT I/F THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Custom KAW60 LA-4661P Date: Rev 2.0 Sheet Friday, August 08, 2008 of 50 A B C D Processor DDR2 Memory Interface +0.9V JCPU1B M_ZN M_ZP R22 39.2_0402_1%~D VTT_SENSE TP3 PAD PLACE THEM CLOSE TO CPU WITHIN 1" DDR_CS3_DIMMA# DDR_CS2_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMA# 11 11 11 11 DDR_CS3_DIMMB# DDR_CS2_DIMMB# DDR_CS1_DIMMB# DDR_CS0_DIMMB# 11 11 10 10 10 DDR_CKE1_DIMMB DDR_CKE0_DIMMB DDR_CKE1_DIMMA DDR_CKE0_DIMMA DDR_A_MA[15 0] AE20 AE19 G20 G21 V27 W27 AG21 DDR_A_CLK2 AG20 DDR_A_CLK#2 G19 DDR_A_CLK1 H19 DDR_A_CLK#1 U27 U26 MB1_CLK_H2 MB1_CLK_L2 MB1_CLK_H1 MB1_CLK_L1 MB1_CLK_H0 MB1_CLK_L0 MB0_CLK_H2 MB0_CLK_L2 MB0_CLK_H1 MB0_CLK_L1 MB0_CLK_H0 MB0_CLK_L0 AL19 AL18 C19 D19 W29 W28 AJ19 AK19 A18 A19 U31 U30 MB_CKE1 MB_CKE0 MA_CKE1 MA_CKE0 MB1_ODT0 MB0_ODT0 MA1_ODT0 MA0_ODT0 AD31 AD29 AC27 AC28 DDR_B_ODT1 DDR_B_ODT0 DDR_A_ODT1 DDR_A_ODT0 DDR_B_MA15 DDR_B_MA14 DDR_B_MA13 DDR_B_MA12 DDR_B_MA11 DDR_B_MA10 DDR_B_MA9 DDR_B_MA8 DDR_B_MA7 DDR_B_MA6 DDR_B_MA5 DDR_B_MA4 DDR_B_MA3 DDR_B_MA2 DDR_B_MA1 DDR_B_MA0 F12 MEMVREF E12 VTT_SENSE AH11 AJ11 10:8:10:8:10 DDR_CS3_DIMMA# 10 10 10 10 MA1_CLK_H2 MA1_CLK_L2 MA1_CLK_H1 MA1_CLK_L1 MA1_CLK_H0 MA1_CLK_L0 MA0_CLK_H2 MA0_CLK_L2 MA0_CLK_H1 MA0_CLK_L1 MA0_CLK_H0 MA0_CLK_L0 AD27 DDR_CS2_DIMMA# AA25 DDR_CS1_DIMMA# AC25 DDR_CS0_DIMMA# AA24 MEMZN MEMZP MA1_CS_L1 MA1_CS_L0 MA0_CS_L1 MA0_CS_L0 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK1 DDR_B_CLK#1 DDR_A_CLK2 DDR_A_CLK#2 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 11 DDR_B_CLK#2 11 DDR_B_CLK1 11 DDR_B_CLK#1 11 DDR_CS3_DIMMB# DDR_CS2_DIMMB# DDR_CS1_DIMMB# DDR_CS0_DIMMB# AE29 AB31 AE30 AC31 DDR_CKE1_DIMMB DDR_CKE0_DIMMB DDR_CKE1_DIMMA DDR_CKE0_DIMMA M31 M29 L27 M25 DDR_A_MA15 DDR_A_MA14 DDR_A_MA13 DDR_A_MA12 DDR_A_MA11 DDR_A_MA10 DDR_A_MA9 DDR_A_MA8 DDR_A_MA7 DDR_A_MA6 DDR_A_MA5 DDR_A_MA4 DDR_A_MA3 DDR_A_MA2 DDR_A_MA1 DDR_A_MA0 M27 N24 AC26 N26 P25 Y25 N27 R24 P27 R25 R26 R27 T25 U25 T27 W24 MA_ADD15 MA_ADD14 MA_ADD13 MA_ADD12 MA_ADD11 MA_ADD10 MA_ADD9 MA_ADD8 MA_ADD7 MA_ADD6 MA_ADD5 MA_ADD4 MA_ADD3 MA_ADD2 MA_ADD1 MA_ADD0 MB_ADD15 MB_ADD14 MB_ADD13 MB_ADD12 MB_ADD11 MB_ADD10 MB_ADD9 MB_ADD8 MB_ADD7 MB_ADD6 MB_ADD5 MB_ADD4 MB_ADD3 MB_ADD2 MB_ADD1 MB_ADD0 N28 N29 AE31 N30 P29 AA29 P31 R29 R28 R31 R30 T31 T29 U29 U28 AA30 DDR_A_BS#2 DDR_A_BS#1 DDR_A_BS#0 N25 Y27 AA27 MA_BANK2 MA_BANK1 MA_BANK0 MB_BANK2 MB_BANK1 MB_BANK0 N31 DDR_B_BS#2 AA31 DDR_B_BS#1 AA28 DDR_B_BS#0 DDR_B_BS#2 11 DDR_B_BS#1 11 DDR_B_BS#0 11 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# AA26 AB25 AB27 MA_RAS_L MA_CAS_L MA_WE_L MB_RAS_L MB_CAS_L MB_WE_L AB29 DDR_B_RAS# AC29 DDR_B_CAS# AC30 DDR_B_WE# DDR_B_RAS# 11 DDR_B_CAS# 11 DDR_B_WE# 11 10 DDR_A_BS#2 10 DDR_A_BS#1 10 DDR_A_BS#0 10 DDR_A_RAS# 10 DDR_A_CAS# 10 DDR_A_WE# MB1_CS_L1 MB1_CS_L0 MB0_CS_L1 MB0_CS_L0 10 10 10 10 To reverse SODIMM socket +0.9VREF_CPU R13 39.2_0402_1%~D VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8 VTT9 DDR II: CMD/CTRL/CLK D12 C12 B12 A12 AK12 AJ12 AH12 AG12 AL12 DDR_B_ODT1 11 DDR_B_ODT0 11 DDR_A_ODT1 10 DDR_A_ODT0 10 DDR_B_MA[15 0] 11 TYCO_1-1735315-4_940P CONN@ DDR_A_CLK2 11 DDR_B_DM[7 0] DDR_B_CLK2 1 C66 1.5P_0402_50V8C 2 DDR_A_CLK#2 DDR_B_CLK#2 DDR_A_CLK1 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 1 C132 1.5P_0402_50V8C DDR_B_CLK#1 PLACE CLOSE TO PROCESSOR WITHIN 1.2 INCH C173 1.5P_0402_50V8C PLACE CLOSE TO PROCESSOR WITHIN 1.2 INCH DDR_B_DQS7 DDR_B_DQS#7 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS0 DDR_B_DQS#0 AH13 AL13 AL15 AJ15 AF13 AG13 AL14 AK15 AL16 AL17 AK21 AL21 AH15 AJ16 AH19 AL20 AJ22 AL22 AL24 AK25 AJ21 AH21 AH23 AJ24 AL27 AK27 AH31 AG30 AL25 AL26 AJ30 AJ31 E31 E30 B27 A27 F29 F31 A29 A28 A25 A24 C22 D21 A26 B25 B23 A22 B21 A20 C16 D15 C21 A21 A17 A16 B15 A14 E13 F13 C15 A15 A13 D13 MB_DATA63 MB_DATA62 MB_DATA61 MB_DATA60 MB_DATA59 MB_DATA58 MB_DATA57 MB_DATA56 MB_DATA55 MB_DATA54 MB_DATA53 MB_DATA52 MB_DATA51 MB_DATA50 MB_DATA49 MB_DATA48 MB_DATA47 MB_DATA46 MB_DATA45 MB_DATA44 MB_DATA43 MB_DATA42 MB_DATA41 MB_DATA40 MB_DATA39 MB_DATA38 MB_DATA37 MB_DATA36 MB_DATA35 MB_DATA34 MB_DATA33 MB_DATA32 MB_DATA31 MB_DATA30 MB_DATA29 MB_DATA28 MB_DATA27 MB_DATA26 MB_DATA25 MB_DATA24 MB_DATA23 MB_DATA22 MB_DATA21 MB_DATA20 MB_DATA19 MB_DATA18 MB_DATA17 MB_DATA16 MB_DATA15 MB_DATA14 MB_DATA13 MB_DATA12 MB_DATA11 MB_DATA10 MB_DATA9 MB_DATA8 MB_DATA7 MB_DATA6 MB_DATA5 MB_DATA4 MB_DATA3 MB_DATA2 MB_DATA1 MB_DATA0 K29 K31 G30 G29 L29 L28 H31 G31 MB_CHECK7 MB_CHECK6 MB_CHECK5 MB_CHECK4 MB_CHECK3 MB_CHECK2 MB_CHECK1 MB_CHECK0 DDR_B_DM7 DDR_B_DM6 DDR_B_DM5 DDR_B_DM4 DDR_B_DM3 DDR_B_DM2 DDR_B_DM1 DDR_B_DM0 J29 AJ14 AH17 AJ23 AK29 C30 A23 B17 B13 MB_DM8 MB_DM7 MB_DM6 MB_DM5 MB_DM4 MB_DM3 MB_DM2 MB_DM1 MB_DM0 DDR_B_DQS7 DDR_B_DQS#7 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS0 DDR_B_DQS#0 J31 J30 AK13 AJ13 AK17 AJ17 AK23 AL23 AL28 AL29 D31 C31 C24 C23 D17 C17 C14 C13 MB_DQS_H8 MB_DQS_L8 MB_DQS_H7 MB_DQS_L7 MB_DQS_H6 MB_DQS_L6 MB_DQS_H5 MB_DQS_L5 MB_DQS_H4 MB_DQS_L4 MB_DQS_H3 MB_DQS_L3 MB_DQS_H2 MB_DQS_L2 MB_DQS_H1 MB_DQS_L1 MB_DQS_H0 MB_DQS_L0 C35 1.5P_0402_50V8C DDR_B_CLK1 DDR_A_CLK#1 JCPU1C DDR_B_D63 DDR_B_D62 DDR_B_D61 DDR_B_D60 DDR_B_D59 DDR_B_D58 DDR_B_D57 DDR_B_D56 DDR_B_D55 DDR_B_D54 DDR_B_D53 DDR_B_D52 DDR_B_D51 DDR_B_D50 DDR_B_D49 DDR_B_D48 DDR_B_D47 DDR_B_D46 DDR_B_D45 DDR_B_D44 DDR_B_D43 DDR_B_D42 DDR_B_D41 DDR_B_D40 DDR_B_D39 DDR_B_D38 DDR_B_D37 DDR_B_D36 DDR_B_D35 DDR_B_D34 DDR_B_D33 DDR_B_D32 DDR_B_D31 DDR_B_D30 DDR_B_D29 DDR_B_D28 DDR_B_D27 DDR_B_D26 DDR_B_D25 DDR_B_D24 DDR_B_D23 DDR_B_D22 DDR_B_D21 DDR_B_D20 DDR_B_D19 DDR_B_D18 DDR_B_D17 DDR_B_D16 DDR_B_D15 DDR_B_D14 DDR_B_D13 DDR_B_D12 DDR_B_D11 DDR_B_D10 DDR_B_D9 DDR_B_D8 DDR_B_D7 DDR_B_D6 DDR_B_D5 DDR_B_D4 DDR_B_D3 DDR_B_D2 DDR_B_D1 DDR_B_D0 MA_DATA63 MA_DATA62 MA_DATA61 MA_DATA60 MA_DATA59 MA_DATA58 MA_DATA57 MA_DATA56 MA_DATA55 MA_DATA54 MA_DATA53 MA_DATA52 MA_DATA51 MA_DATA50 MA_DATA49 MA_DATA48 MA_DATA47 MA_DATA46 MA_DATA45 MA_DATA44 MA_DATA43 MA_DATA42 MA_DATA41 MA_DATA40 MA_DATA39 MA_DATA38 MA_DATA37 MA_DATA36 MA_DATA35 MA_DATA34 MA_DATA33 MA_DATA32 MA_DATA31 MA_DATA30 MA_DATA29 MA_DATA28 MA_DATA27 MA_DATA26 MA_DATA25 MA_DATA24 MA_DATA23 MA_DATA22 MA_DATA21 MA_DATA20 MA_DATA19 MA_DATA18 MA_DATA17 MA_DATA16 MA_DATA15 MA_DATA14 MA_DATA13 MA_DATA12 MA_DATA11 MA_DATA10 MA_DATA9 MA_DATA8 MA_DATA7 MA_DATA6 MA_DATA5 MA_DATA4 MA_DATA3 MA_DATA2 MA_DATA1 MA_DATA0 AE14 AG14 AG16 AD17 AD13 AE13 AG15 AE16 AG17 AE18 AD21 AG22 AE17 AF17 AF21 AE21 AF23 AE23 AJ26 AG26 AE22 AG23 AH25 AF25 AJ28 AJ29 AF29 AE26 AJ27 AH27 AG29 AF27 E29 E28 D27 C27 G26 F27 C28 E27 F25 E25 E23 D23 E26 C26 G23 F23 E22 E21 F17 G17 G22 F21 G18 E17 G16 E15 G13 H13 H17 E16 E14 G14 MA_CHECK7 MA_CHECK6 MA_CHECK5 MA_CHECK4 MA_CHECK3 MA_CHECK2 MA_CHECK1 MA_CHECK0 K25 J26 G28 G27 L24 K27 H29 H27 DDR_A_D63 DDR_A_D62 DDR_A_D61 DDR_A_D60 DDR_A_D59 DDR_A_D58 DDR_A_D57 DDR_A_D56 DDR_A_D55 DDR_A_D54 DDR_A_D53 DDR_A_D52 DDR_A_D51 DDR_A_D50 DDR_A_D49 DDR_A_D48 DDR_A_D47 DDR_A_D46 DDR_A_D45 DDR_A_D44 DDR_A_D43 DDR_A_D42 DDR_A_D41 DDR_A_D40 DDR_A_D39 DDR_A_D38 DDR_A_D37 DDR_A_D36 DDR_A_D35 DDR_A_D34 DDR_A_D33 DDR_A_D32 DDR_A_D31 DDR_A_D30 DDR_A_D29 DDR_A_D28 DDR_A_D27 DDR_A_D26 DDR_A_D25 DDR_A_D24 DDR_A_D23 DDR_A_D22 DDR_A_D21 DDR_A_D20 DDR_A_D19 DDR_A_D18 DDR_A_D17 DDR_A_D16 DDR_A_D15 DDR_A_D14 DDR_A_D13 DDR_A_D12 DDR_A_D11 DDR_A_D10 DDR_A_D9 DDR_A_D8 DDR_A_D7 DDR_A_D6 DDR_A_D5 DDR_A_D4 DDR_A_D3 DDR_A_D2 DDR_A_D1 DDR_A_D0 MA_DM8 MA_DM7 MA_DM6 MA_DM5 MA_DM4 MA_DM3 MA_DM2 MA_DM1 MA_DM0 J25 AF15 AF19 AJ25 AH29 B29 E24 E18 H15 DDR_A_DM7 DDR_A_DM6 DDR_A_DM5 DDR_A_DM4 DDR_A_DM3 DDR_A_DM2 DDR_A_DM1 DDR_A_DM0 MA_DQS_H8 MA_DQS_L8 MA_DQS_H7 MA_DQS_L7 MA_DQS_H6 MA_DQS_L6 MA_DQS_H5 MA_DQS_L5 MA_DQS_H4 MA_DQS_L4 MA_DQS_H3 MA_DQS_L3 MA_DQS_H2 MA_DQS_L2 MA_DQS_H1 MA_DQS_L1 MA_DQS_H0 MA_DQS_L0 J28 J27 AD15 AE15 AG18 AG19 AG24 AG25 AG27 AG28 D29 C29 C25 D25 E19 F19 F15 G15 DDR_A_DQS7 DDR_A_DQS#7 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS0 DDR_A_DQS#0 DDR_A_D[63 0] 10 To normal SODIMM socket 11 DDR_B_D[63 0] DDRII: DATA VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER SUPPLY THROUGH THE PACKAGE OR ON THE DIE IT IS ONLY CONNECTED ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE +1.8V E DDR_A_DM[7 0] 10 DDR_A_DQS7 DDR_A_DQS#7 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS0 DDR_A_DQS#0 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 TYCO_1-1735315-4_940P CONN@ +1.8V A26 A1 R33 1K_0402_1% +0.9VREF_CPU Athlon 64 S1g1 uPGA638 CPU_VREF_REF C32 C33 C34 1 2 C29 Top View C28 R23 1K_0402_1% 1000P_0402_50V7K 0.1U_0402_16V4Z 1U_0402_6.3V4Z 1000P_0402_50V7K AF1 1000P_0402_50V7K VDD_VREF_SUS_CPU Compal Secret Data Security Classification LAYOUT:PLACE CLOSE TO CPU Issued Date 2005/10/11 Deciphered Date 2006/10/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title AMD CPU DDRII MEMORY I/F Size Document Number Custom KAW60 LA-4661P Date: Rev 2.0 Friday, August 08, 2008 Sheet E of 50 ATHLON Control and Debug +1.8V LAYOUT: ROUTE VDDA TRACE APPROX 50 mils WIDE (USE 2x25 mil TRACES TO EXIT BALL FIELD) AND 500 mils LONG R7 300_0402_5% +2.5VS 4.7U_0805_10V4Z C187 0.22U_0603_16V7K R372 C136 3300P_0402_50V7K 300_0402_5% R582 R583 +1.8VS @ 1 12/22 Modify CPU_HT_RESET# CPU_ALL_PWROK CPU_LDTSTOP# 300_0402_5% 300_0402_5% 2 C7 C9 D8 @ Un-stuff 18 18 R584 R585 CPU_SIC CPU_SID @ @ R36 R35 +1.2V_HT CPU_SIC_R CPU_SID_R 0_0402_5% 0_0402_5% 2 44.2_0603_1% 44.2_0603_1% 1 AL6 AK6 CPU_HTREF1 CPU_HTREF0 +1.8V C501 CPUCLK G NC7SZ08P5X_NL_SC70-5 17 CPUCLK# 0_0402_5% C502 CPU_TMS CPU_TCK CPU_TRST# CPU_TDI HT_REF1 HT_REF0 VDD_FB_H VDD_FB_L CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1 +1.8VS +1.8V @ U8 CPU_LDTSTOP# G 0_0402_5% NC7SZ08P5X_NL_SC70-5 R544 CLKIN_H CLKIN_L B6 DBRDY AL9 AH10 AJ10 AL10 TMS TCK TRST_L TDI CPU_THERMDC CPU_THERMDA 0_0402_5% 10:10 TP5 TP6 TP8 TP9 U6 @ Y A @ R690 680_0402_5% SCAN Connector @ P B R65 CPU_HT_RESET# 0_0402_5% +1.8V NC7SZ08P5X_NL_SC70-5 JP38 CPU_TEST18_PLLTEST1 CPU_TEST19_PLLTEST0 CPU_TEST21_SCANEN CPU_TEST22_SCANSHIFTEN CPU_TEST12_SCANSHIFTENB CPU_TEST24_SCANCLK1 CPU_TEST20_SCANCLK2 HDT Connector 10 12 14 16 18 20 22 24 H3 H4 H20 H21 DBREQ_L TDO A5 CPU_DBREQ# AK10 CPU_TDO TEST29_H TEST29_L NC#5 NC#6 NC#7 NC#8 TEST24 TEST23 TEST22 TEST21 TEST20 R68 C11 CPU_TEST29_H_FBCLKOUT_P 80.6_0402_1% D11 CPU_TEST29_L_FBCLKOUT_N AE7 AD19 AE8 AD18 CPU_TEST24_SCANCLK1 AK8 TP7 PAD AH8 CPU_TEST22_SCANSHIFTEN AJ9 CPU_TEST21_SCANEN AL8 CPU_TEST20_SCANCLK2 AJ8 E5 AJ5 AG9 AG8 AH7 AJ6 TEST7 TEST6 TEST5 TEST4 TEST3 TEST2 TEST28_H TEST28_L TEST27 TEST26 TEST10 TEST8 J10 H9 AK9 AK5 G7 D4 L25 L26 L31 L30 RSVD0 RSVD1 RSVD2 RSVD3 RSVD22 RSVD23 E20 B19 W26 W25 AE27 U24 V24 AE28 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD24 RSVD25 RSVD26 AL4 AK4 AK3 RSVD27 RSVD28 F2 F3 AD25 AE24 AE25 AJ18 AJ20 C18 C20 G24 G25 H25 V29 W30 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD29 RSVD30 RSVD31 G4 G3 G5 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 Y31 Y30 AG31 V31 W31 AF31 C CPU_TEST26_BURNIN# TYCO_1-1735315-4_940P CONN@ KEY AMD AM2 Processor Socket B JP4 +1.8V +3VALW +3VALW R4 1 S CPU_HT_RESET#_R R683 0_0402_5% CPU_HT_RESET# H_THERMTRIP_S# 10K_0402_5% Q3 1H_THERMTRIP# MMBT3904_SOT23 +1.8V Q33 R366 R369 R47 300_0402_5% 1K_0402_5% 510_0402_5% H_THERMTRIP# 18 CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1 CPU_TEST12_SCANSHIFTENB CPU_TEST22_SCANSHIFTEN R684 R685 R686 R687 1 1 2 2 300_0402_5% 300_0402_5% 300_0402_5% 300_0402_5% CPU_TEST21_SCANEN CPU_TEST25_L_BYPASSCLK_L CPU_TEST19_PLLTEST0 CPU_TEST18_PLLTEST1 R368 R54 R92 R91 2 2 300_0402_5% 510_0402_5% 300_0402_5% 300_0402_5% +1.8V VDD1 D- ALERT# THERM# GND SCLK SDATA +3VS CPU_PH_G Q4 R6 4.7K_0402_5% @ A CPU_PROCHOT#_1.8 MMBT3904_SOT23 C D+ EC_SMB_DA2 R8 10K_0402_5% E 28 EC_SMB_DA2 CPU_THERMDC R374 @ 10K_0402_5% 0.1U_0402_16V4Z CPU_THERMDA EC_SMB_CK2 @ @ @ @ B 28 EC_SMB_CK2 Q2 @ MMBT3904_SOT23 MAINPWON 42,43,45 CPU_TEST26_BURNIN# CPU_PRESENT# CPU_TEST25_H_BYPASSCLK_H C454 U38 HDT@ 2N7002_SOT23 2 R2 @ 1K_0402_5% R3 2 G @ SAMTEC_ASP-68200-07 CONN@ 1K_0402_5% R5 300_0402_5% D 3V_LDT_RST# +3VALW +1.8V R572 220_0402_5% HDT@ 2 +3VS 10 12 14 16 18 20 22 24 26 11 13 15 17 19 21 23 2200P_0402_50V7K ROUTE AS 80 Ohm DIFFERENTIAL PAIR PLACE IT CLOSE TO CPU WITHIN 1" 5:4:5 +3VS A 48 +1.8V NOTE: HDT TERMINATION IS REQUIRED FOR REV Ax SILICON ONLY C451 PSI# ASP-68200-03 CONN@ 2 2 CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO HDT@ R361 220_0402_5% HDT@ R362 220_0402_5% HDT@ R363 220_0402_5% HDT@ R364 220_0402_5% HDT@ R365 220_0402_5% +1.8V B 11 13 15 17 19 21 23 25 0_0402_5% PSI# NC#1 NC#2 NC#3 NC#4 2 R545 CPU_PRESENT# F1 D 48 48 48 48 48 48 LDT_RST# G SB_PWROK_R 0_0402_5% LDT_RST# 18 R82 C282 0.1U_0402_16V4Z @ 18,28,37 SB_PWROK AL3 TEST25_H TEST25_L TEST19 TEST18 TEST13 TEST9 TEST17 TEST16 TEST15 TEST14 TEST12 +1.8V @ VID5 VID4 VID3 VID2 VID1 VID0 A10 B10 F10 E9 AJ7 F6 D6 E7 F8 C5 AH9 +1.8VS R71 300_0402_5% VID5 VID4 VID3 VID2 VID1 VID0 R78 300_0402_5% A @ R689 680_0402_5% R79 Y 14,18 LDT_STOP# C PAD PAD PAD PAD CPU_TEST12_SCANSHIFTENB @ @ B P R88 300_0402_5% C155 0.1U_0402_16V4Z VDDIO_FB_H VDDIO_FB_L D2 D1 C1 E3 E2 E1 PSI_L CPU_PRESENT_L A8 B8 3900P_0402_50V7K R543 CPU_DBRDY VID5 VID4 VID3 VID2 VID1 VID0 SIC SID G2 G1 AK11 AL11 CPU_CLKIN_SC_P CPU_CLKIN_SC_N 3900P_0402_50V7K R389 169_0402_1% CPU_ALL_PWROK 0_0402_5% TP2 TP1 RESET_L PWROK LDTSTOP_L AK7 H_THERMTRIP_S# AL7 CPU_PROCHOT#_1.8 A @ R688 680_0402_5% R70 Y 18 CPU_PWRGD 17 @ B @ U5 @ PAD PAD C147 0.1U_0402_16V4Z P R63 300_0402_5% R64 4.7K_0402_5% place them to CPU within 1" @ CPU_VCC_SENSE CPU_VSS_SENSE 48 CPU_VCC_SENSE 48 CPU_VSS_SENSE +3VS THERMTRIP_L PROCHOT_L V8 V7 5:10 +1.8VS VDDA2 VDDA1 D C10 D10 150U_D2_6.3VM @ JCPU1D VDDA=300mA + W=50mils MISC FCM2012C-800_0.25ohm/600mA_0805 L4 C506 C189 1 EC_THERM# 19,28 ADM1032ARMZ-2REEL_MSOP8 Compal Secret Data Security Classification U4524 CLOSE CPU, CPU_THERMDA&CPU_THERMDC PLACE CLOSE TO PROCESSOR WITHIN 1" INCH Issued Date 2005/03/08 Deciphered Date 2006/03/08 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title AMD CPU CTRL & DEBUG Size C Date: Document Number Rev 2.0 KAW60 LA-4661P Friday, August 08, 2008 Sheet of 50 CPU_CORE 820u HCW51 +CPU_CORE +CPU_CORE +CPU_CORE C VDD106 VDD105 VDD104 VDD103 VDD102 VDD101 VDD100 VDD99 VDD98 VDD97 VDD96 VDD95 VDD94 VDD93 VDD92 VDD91 VDD90 VDD89 VDD88 VDD87 VDD86 VDD85 VDD84 VDD83 VDD82 VDD81 VDD80 VDD79 VDD78 VDD77 VDD76 VDD75 VDD74 VDD73 VDD72 VDD71 VDD70 VDD69 VDD68 VDD67 VDD66 VDD65 VDD64 VDD63 VDD62 VDD61 VDD60 VDD59 VDD58 VDD57 VDD56 VDD55 VDD54 R10 R8 R5 R4 P19 P17 P15 P13 P11 P9 P7 N18 N16 N14 N12 N10 N8 M19 M17 M15 M13 M11 M9 M7 M3 M2 L18 L16 L14 Y19 Y17 L12 L10 L8 L5 L4 K23 K21 K19 K17 K15 K13 K11 K9 K7 J24 J22 J20 J18 J16 J14 J12 J8 TYCO_1-1735315-4_940P CONN@ R12 R14 R16 R18 R20 T2 T3 T7 T9 T11 T13 T15 T17 T19 T21 U8 U10 U12 U14 U16 U18 U20 V9 V11 V13 V15 V17 V19 V21 W4 W5 W8 W10 W12 W14 W16 W18 W20 Y2 Y3 Y7 Y9 Y11 Y13 Y15 Y21 AA20 AA22 AB13 AB15 AB17 AB19 AB21 AB23 VDD107 VDD108 VDD109 VDD110 VDD111 VDD112 VDD113 VDD114 VDD115 VDD116 VDD117 VDD118 VDD119 VDD120 VDD121 VDD122 VDD123 VDD124 VDD125 VDD126 VDD127 VDD128 VDD129 VDD130 VDD131 VDD132 VDD133 VDD134 VDD135 VDD136 VDD137 VDD138 VDD139 VDD140 VDD141 VDD142 VDD143 VDD144 VDD145 VDD146 VDD147 VDD148 VDD149 VDD150 VDD151 VDD152 VDD153 VDD154 VDD155 VDD156 VDD157 VDD158 VDD159 VDD160 POWER2 POWER1 D VDDIO28 VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13 VDDIO12 VDDIO11 VDDIO10 VDDIO9 VDDIO VDDIO8 VDDIO7 VDDIO6 VDDIO5 VDDIO4 VDDIO3 VDDIO2 VDDIO1 Y29 Y28 Y26 Y24 V30 V28 V26 V25 T30 T28 T26 T24 P30 P28 P26 P24 M30 M28 M26 M24 AF30 AD30 AD28 AD26 AC24 AB30 AB28 AB26 AB24 VDD184 VDD183 VDD182 VDD181 VDD180 VDD179 VDD178 VDD177 VDD176 VDD175 VDD174 VDD173 VDD172 VDD171 VDD170 VDD169 VDD168 VDD167 VDD166 VDD165 VDD164 VDD163 VDD162 VDD161 Y23 W22 V23 U22 T23 R22 P23 P21 N22 N20 M23 M21 L22 L20 AF11 AE12 AD23 AD11 AC22 AC20 AC18 AC16 AC14 AC12 T22 T20 T18 T16 T14 T12 T10 T8 R23 R21 R19 R17 R15 R13 R11 R9 R7 P22 P20 P18 P16 P14 P12 P10 P8 P3 P2 N23 N21 N19 N17 Y18 K22 K20 K18 K16 K14 K12 K10 K8 K3 K2 J23 J21 J19 J17 J15 J13 J11 J9 J7 J5 J4 H30 H28 H26 H24 H22 H18 H16 H14 H12 H10 H8 G11 G9 F30 F28 F26 F24 F22 F20 F18 F16 F14 F4 E11 D30 D28 D26 D24 D22 D20 D18 D16 D14 C3 B30 B28 B26 B24 B22 B20 B18 B16 B14 B11 B9 B4 AL5 AK30 AK28 AK26 AK24 AK22 AK20 Y16 Y14 AK18 AK16 AK14 AK2 AH30 AH28 AH26 AH24 AH22 AH20 AH18 AH16 AH14 AG11 TYCO_1-1735315-4_940P VSS183 VSS182 VSS181 VSS180 VSS179 VSS178 VSS177 VSS176 VSS175 VSS174 VSS173 VSS172 VSS171 VSS170 VSS169 VSS168 VSS167 VSS166 VSS165 VSS164 VSS163 VSS162 VSS161 VSS160 VSS159 VSS158 VSS157 VSS156 VSS155 VSS154 VSS153 VSS152 VSS151 VSS150 VSS149 VSS148 VSS147 VSS146 VSS145 VSS144 VSS143 VSS142 VSS141 VSS140 VSS139 VSS138 VSS137 VSS136 VSS135 VSS134 VSS133 VSS132 VSS131 VSS130 VSS129 VSS128 VSS127 VSS126 VSS125 VSS124 VSS123 VSS122 + C505 + C504 330U_D2E_2.5VM_R9 2 330U_D2E_2.5VM_R9 22u 01u 180p 1 1 12 15 15 1 + C453 + C452 @ 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 KAW60 D +CPU_CORE +CPU_CORE 10U_0805_10V6M 10U_0805_10V6M 22U_0805_6.3V6M 1 1 1 C17 C194 C193 C192 C97 C16 @ @ @ @ C195 @ 10U_0805_10V6M 2 10U_0805_10V6M 2 22U_0805_6.3V6M + 10U_0805_10V6M + C450 560U_25V_M_R10 CPU SOCKET AM2 DECOUPLING +CPU_CORE C449 560U_25V_M_R10 SMD POLY CAP SF000001K00 S_A-P_CAP 560U 2.5V M 6.3X5.7 LESR10M H5.7 SF000001J00 S_A-P_CAP 560U 2.5V M 6.3X5.7 LESR13M H5.7 +CPU_CORE C73 22U_0805_6.3V6M C76 22U_0805_6.3V6M C86 @ 10U_0805_10V6M C118 22U_0805_6.3V6M C109 22U_0805_6.3V6M 2 C96 @ 10U_0805_10V6M C89 22U_0805_6.3V6M C113 22U_0805_6.3V6M C124 22U_0805_6.3V6M KAW60 +CPU_CORE C70 0.22U_0402_10V4Z VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 U4 U5 U7 U9 U11 U13 U15 U17 U19 U21 U23 V2 V3 V10 V12 V14 V16 V18 V20 V22 W9 W11 W13 W15 W17 W19 W21 W23 Y8 Y10 Y12 W7 Y20 Y22 K24 K26 K28 K30 L7 L9 L11 L13 L15 L17 L19 L21 L23 M8 M10 M12 M14 M16 M18 M20 M22 N4 N5 N7 N9 N11 N13 N15 C120 0.22U_0402_10V4Z C100 180P_0402_50V8J C91 C738 C739 C740 C741 C742 C743 C C744 0.01U_0402_16V7K 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 0.22U_0402_10V4Z 2 2 2 2 KAW60 C82 22U_0805_6.3V6M C102 22U_0805_6.3V6M C72 0.22U_0402_10V4Z DECOUPLING BETWEEN PROCESSOR AND DIMMs PLACE CLOSE TO PROCESSOR AS POSSIBLE C116 0.22U_0402_10V4Z 22u +1.8V 10u 4.7u 22u 01u 2 HCW51 180p 0047u Moray 2 KAW60 +1.8V 2 C472 4.7U_0805_10V4Z 4.7U_0805_10V4Z C127 0.22U_0402_10V4Z C471 2 C479 4.7U_0805_10V4Z C128 0.01U_0402_16V7K 2 C480 4.7U_0805_10V4Z C85 0.01U_0402_16V7K C104 0.22U_0402_10V4Z 1 C68 180P_0402_50V8J 2 C84 0.22U_0402_10V4Z C129 0.22U_0402_10V4Z C105 180P_0402_50V8J B C745 180P_0402_50V8J +0.9V 2 A1 C188 4.7U_0805_10V4Z 4.7U_0805_10V4Z C39 1000P_0402_50V7K C30 2 C36 4.7U_0805_10V4Z C41 1000P_0402_50V7K 2 C181 4.7U_0805_10V4Z C178 1000P_0402_50V7K 2 C184 0.22U_0402_10V4Z C22 1000P_0402_50V7K C185 0.22U_0402_10V4Z C27 0.22U_0402_10V4Z C23 0.22U_0402_10V4Z 1 1 C179 180P_0402_50V8J C26 180P_0402_50V8J C175 180P_0402_50V8J C182 180P_0402_50V8J A26 +0.9V 4.7u HCW51 22u 0047u Athlon 64 S1g1 Moray uPGA638 KAW60 4 1000p 180p 4 4 4 Top View TYCO_1-1735315-4_940P A KAW60 PVT +1.8V GND2 GND1 B VSS121 VSS120 VSS119 VSS118 VSS117 VSS116 VSS115 VSS114 VSS113 VSS112 VSS111 VSS110 VSS109 VSS108 VSS107 VSS106 VSS105 VSS104 VSS103 VSS102 VSS101 VSS100 VSS99 VSS98 VSS97 VSS96 VSS95 VSS94 VSS93 VSS92 VSS91 VSS90 VSS89 VSS88 VSS87 VSS86 VSS85 VSS84 VSS83 VSS82 VSS81 VSS80 VSS79 VSS78 VSS77 VSS76 VSS75 VSS74 VSS73 VSS72 VSS71 VSS70 VSS69 VSS68 VSS67 VSS66 VSS65 VSS64 VSS63 VSS62 2 10u CONN@ JCPU1G VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS61 22u TYCO_1-1735315-4_940P AM2 Processor Socket JCPU1H A3 A7 A9 A11 AA4 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AB2 AB3 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AD8 AD10 AD12 AD14 AD16 AD20 AD22 AD24 AE4 AE5 AE9 AE11 AF2 AF3 AF8 AF10 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AG10 +CPU_CORE JCPU1F VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32 VDD33 VDD34 VDD35 VDD36 VDD37 VDD38 VDD39 VDD40 VDD41 VDD42 VDD43 VDD44 VDD45 VDD46 VDD47 VDD48 VDD49 VDD50 VDD51 VDD52 VDD53 330u Moray +1.8V JCPU1E A4 A6 AA8 AA10 AA12 AA14 AA16 AA18 AB7 AB9 AB11 AC4 AC5 AC8 AC10 AD2 AD3 AD7 AD9 AE10 AF7 AF9 AG4 AG5 AG7 AH2 AH3 B3 B5 B7 C2 C4 C6 C8 D3 D5 D7 D9 E4 E6 E8 E10 F5 F7 F9 F11 G6 G8 G10 G12 H7 H11 H23 560u A CONN@ CONN@ PROCESSOR POWER AND GROUND AF1 AM2 Processor Socket Compal Secret Data Security Classification Issued Date 2005/03/08 Deciphered Date 2006/03/08 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title AMD CPU PWR & GND Size C Date: Document Number Rev 2.0 KAW60 LA-4661P Tuesday, July 29, 2008 Sheet of 50 +DIMM_VREF DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 4.7U_0805_10V4Z + C477 220U_D2_4VM_R15 C58 C463 C57 C473 4.7U_0805_10V4Z 4.7U_0805_10V4Z 2 2 1 C636 + 2 150U_D2_6.3VM C51 C101 C65 C45 C88 C74 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_CS3_DIMMA# DDR_A_MA9 DDR_A_MA8 DDR_A_DM4 DDR_A_MA5 DDR_A_MA3 DDR_A_D38 DDR_A_D39 DDR_A_MA1 DDR_A_MA10 DDR_A_D44 DDR_A_D45 DDR_A_BS#0 DDR_A_WE# DDR_A_DQS#5 DDR_A_DQS5 DDR_A_CAS# DDR_CS1_DIMMA# DDR_A_D46 DDR_A_D47 DDR_A_ODT1 R32 DDR_CS3_DIMMA# R28 DDR_A_D52 DDR_A_D53 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0404_4P2R_5% 47_0402_1% 47_0402_1% DDR_A_MA15 DDR_CKE1_DIMMA 47_0404_4P2R_5% DDR_A_MA7 DDR_A_MA14 47_0404_4P2R_5% DDR_A_MA6 DDR_A_MA11 47_0404_4P2R_5% DDR_A_MA2 DDR_A_MA4 47_0404_4P2R_5% DDR_A_BS#1 DDR_A_MA0 47_0404_4P2R_5% DDR_CS0_DIMMA# DDR_A_RAS# 47_0404_4P2R_5% DDR_A_MA13 DDR_A_ODT0 47_0404_4P2R_5% RP22 RP17 RP14 RP10 RP6 RP2 RP1 +0.9V 2 2 2 C623 C622 C621 C620 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z C56 DDR_A_D60 DDR_A_D61 0.1U_0402_16V4Z DDR_A_D54 DDR_A_D55 B +1.8V 0.1U_0402_16V4Z DDR_A_CLK2 DDR_A_CLK#2 DDR_A_DM6 DDR_A_DQS#7 DDR_A_DQS7 A Layout Note: Place one 0.1uF cap close to every pullup resistors terminated to +0.9V DDR_A_D62 DDR_A_D63 R12 R10 1 10K_0402_5% 10K_0402_5% Compal Secret Data Security Classification 2005/10/11 2006/10/11 Deciphered Date Title DDR2 SO-DIMM I THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 4.7U_0805_10V4Z RP28 RP25 RP21 RP18 RP13 RP9 RP5 1 DDR_A_BS#2 DDR_A_MA12 DDR_A_D36 DDR_A_D37 DDR_A_CLK2 DDR_A_CLK#2 C69 0.1U_0402_16V4Z DDR_CKE0_DIMMA DDR_CS2_DIMMA# DDR_A_ODT0 Issued Date P-TWO_A5692C-A0G16 CONN@ C55 C448 DDR_CS3_DIMMA# 0.1U_0402_16V4Z DDR_A_ODT0 DDR_A_MA13 C619 SB_CK_SDAT SB_CK_SCLK +3VS 1 +0.9V DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# C618 11,17,19,31 SB_CK_SDAT 11,17,19,31 SB_CK_SCLK Layout Note: Place one cap close to every pullup resistors terminated to +0.9V DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# 0.1U_0402_16V4Z DDR_A_D58 DDR_A_D59 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 C617 A 0.1U_0402_16V4Z DDR_A_DM7 C616 DDR_A_D56 DDR_A_D57 0.1U_0402_16V4Z DDR_A_D50 DDR_A_D51 0.1U_0402_16V4Z DDR_A_DQS#6 DDR_A_DQS6 C475 DDR_A_D48 DDR_A_D49 4.7U_0805_10V4Z DDR_A_D42 DDR_A_D43 DDR_A_MA15 DDR_A_MA14 C95 DDR_A_DM5 DDR_CKE1_DIMMA 0.1U_0402_16V4Z DDR_A_D40 DDR_A_D41 4.7U_0805_10V4Z DDR_A_D34 DDR_A_D35 DDR_CKE1_DIMMA C107 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D30 DDR_A_D31 0.1U_0402_16V4Z B C98 DDR_A_D32 DDR_A_D33 C C114 DDR_A_ODT1 DDR_A_ODT1 +0.9V 0.1U_0402_16V4Z DDR_A_CAS# DDR_CS1_DIMMA# DDR_A_DQS#3 DDR_A_DQS3 C80 DDR_A_CAS# DDR_CS1_DIMMA# DDR_A_DQS#[0 7] C71 DDR_A_MA10 DDR_A_BS#0 DDR_A_WE# DDR_A_BS#0 DDR_A_WE# DDR_A_MA[0 15] 0.1U_0402_16V4Z DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_DQS#[0 7] C67 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_D28 DDR_A_D29 0.1U_0402_16V4Z DDR_CS2_DIMMA# DDR_A_BS#2 DDR_A_DQS[0 7] DDR_A_DQS[0 7] DDR_A_MA[0 15] C63 DDR_CS2_DIMMA# DDR_A_BS#2 DDR_A_DM[0 7] DDR_A_D22 DDR_A_D23 0.1U_0402_16V4Z DDR_CKE0_DIMMA DDR_CKE0_DIMMA DDR_A_DM[0 7] 0.1U_0402_16V4Z DDR_A_D26 DDR_A_D27 DDR_A_DM2 DDR_A_D[0 63] DDR_A_D[0 63] 4.7U_0805_10V4Z DDR_A_DM3 +1.8V DDR_A_CLK1 DDR_A_CLK#1 DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 D R397 C77 C C652 0.22U_0603_16V7K 2 2 2 2 2 2 2 C639 C641 C643 C645 C647 C649 C651 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 0.01U_0402_16V7K10P_0402_25V8K 0.22U_0603_16V7K0.22U_0603_16V7K0.22U_0603_16V7K 1K_0402_1% DDR_A_DM1 DDR_A_CLK1 DDR_A_CLK#1 1K_0402_1% 4.7U_0805_10V4Z DDR_A_D24 DDR_A_D25 VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 DDR_A_D12 DDR_A_D13 C62 DDR_A_D18 DDR_A_D19 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD DDR_A_D6 DDR_A_D7 C470 DDR_A_DQS#2 DDR_A_DQS2 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DDR_A_DM0 4.7U_0805_10V4Z DDR_A_D16 DDR_A_D17 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 DDR_A_D4 DDR_A_D5 4.7U_0805_10V4Z DDR_A_D10 DDR_A_D11 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS C640 C642 C644 C646 C648 C650 4.7U_0805_6.3V6K 4.7U_0805_6.3V6K 0.01U_0402_16V7K10P_0402_25V8K 0.22U_0603_16V7K0.22U_0603_16V7K 1 1 1 1 1 1 R398 DDR_A_DQS#0 DDR_A_DQS0 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS 4.7U_0805_10V4Z D 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 +1.8V C503 DDR_A_D0 DDR_A_D1 C507 0.1U_0402_16V4Z JDIMM2 +1.8V +1.8V +1.8V Size Document Number Custom KAW60 LA-4661P Date: Rev 2.0 Sheet Friday, August 08, 2008 10 of 50 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2005/06/20 Deciphered Date 2006/06/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size B Date: Document Number Rev 2.0 KAW60 LA-4661P Tuesday, June 17, 2008 Sheet 36 of 50 A B +3VS +3VALW U10B SN74LVC14APWR_TSSOP14 I C204 1U_0805_25V4Z 2006/02/22 Change R100 to 47K SB_PWROK 8,18,28 +3V POWER 14 R105 100K_0402_5% @ R108 10_0402_5% NB_PWROK 14,28 U10D SN74LVC14APWR_TSSOP14 O I O G I I P P @ R109 10_0402_5% @ G 13 +3VALW 14 +3VALW O 10 +3V POWER G 11 P 14 O +3V POWER U10F SN74LVC14APWR_TSSOP14 R104 10_0402_5% O 12 I G G O +3V POWER I P P U10E SN74LVC14APWR_TSSOP14 P R112 100K_0402_1% U10A SN74LVC14APWR_TSSOP14 14 C203 1U_0603_10V4Z E +3VALW 14 PVT R106 10K_0402_5% +3VALW R100 47K_0402_1% VLDT_EN G 28,41 VLDT_EN +3VALW D R111 10K_0402_5% @ 14 D5 BAS16_SOT23-3 @ +3VALW Power ON Circuit C R113 180K_0402_5% U10C SN74LVC14APWR_TSSOP14 note:T1 minimum 15ms,T2 minimum 33ms/maximum 500ms, SUSP# goes to low after SB_PWRGD goes to low for power down T1 2 VLDT_EN NB_PWRGD SB_PWRGD T2 TOP Side @ Power Button 10K_0603_5% @ R281 10K_0603_5% 100K_0402_5% Bottom Side D10 ON/OFFBTN# 38 ON/OFFBTN# J4 +1.8VS J3 SUSP# +3VALW 51ON# ON/OFF 28 51ON# 42 CHN202UPT_SC70 3 2 EC_ON EC_ON 28 C358 1000P_0402_50V7K D11 RLZ20A_LL34 ON/OFFBTN# SW10 SMT1-05-A_4P D 2N7002_SOT23 Q17 G R290 S 10K_0402_5% MP remove 4 Compal Secret Data Security Classification 2005/03/08 Issued Date Deciphered Date 2006/03/08 A B C Title PWR_OK/ PWR BTN THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC D Size B Date: Document Number Rev 2.0 KAW60 LA-4661P Friday, August 08, 2008 Sheet E 37 of 50 W/O Modem MDC Conn JMDC1 19 R538 300_0402_5% LED5 R357 AC_RST# PWR_LED# 1 D C3 MDC@ 1U_0603_10V4Z 2N7002_SOT23 Q1 G PWR_LED 10 12 GND1 RES0 IAC_SDATA_OUT RES1 GND2 3.3V IAC_SYNC GND3 IAC_SDATA_IN GND4 IAC_RESET# IAC_BITCLK 20mil +3VALW AC_BITCLK AC_BITCLK 19 C432 MDC@ 22P_0402_50V8J +3VALW HT-110UYG_1204 ACES_88018-124G CONN@ Connector for MDC Rev1.5 S +5VALW R331 300_0402_5% LED4 PWR_SUSP_LED# PWR_SUSP_LED# 28 BATT_FULL_LED# BATT_FULL_LED# 28 HT-110UD_1204 +5VALW R332 300_0402_5% LED2 +5VALW HT-110UYG_1204 C435 + 0.1U_0402_16V4Z To LED/B Conn R537 300_0402_5% LED6 BATT_CHGI_LED# JP2 BATT_CHGI_LED# 28 PWR_LED# MEDIA_LED# PVT 28 CAPS_LED# 28 NUM_LED# 28 E-MAIL_LED# 37 ON/OFFBTN# 28 E-MAIL_BTN# 28 IE_BTN# 28 USER_BTN# 28 EMPWR_BTN# PVT 3 4 300_0402_5% R522 100K_0402_5% 11 13 15 17 19 21 23 25 27 29 10 12 14 16 18 20 22 24 26 28 30 +5VALW USB20_N4 19 USB20_P4 19 USB20_N6 19 USB20_P6 19 USB_EN# 28,34 ACES_88018-304G CONN@ LED3 HT-110UD_1204 WLSW_EN# 28 SW9 HSS110_4P 10 12 14 16 18 20 22 24 26 28 30 Wireless SWITCH WL_ON_LED# WL_ON_LED# 28,31 PVT +3VS G 31 32 33 34 35 36 R329 11 13 15 17 19 21 23 25 27 29 +3VALW 5 +3VS D29 DAN217_SC59 @ C436 150U_D2_6.3VM +5VS HT-110UD_1204 +3VALW GND GND GND GND GND GND +5VALW 28 AC_SYNC 33_0402_5% MDC@ GND GND GND GND GND GND +5VS AC_SYNC ACZ_SDIN1 AC_RST# 11 AC_SDOUT 13 14 15 16 17 18 PWR_LED# 19 19 19 AC_SDOUT SATA_LED# MEDIA_LED# D SATA_LED# S 19 Q67 2N7002_SOT23 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2005/06/20 Deciphered Date 2006/06/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title MDC / LED / SW Size B Date: Document Number Rev 2.0 KAW60 LA-4661P Friday, August 08, 2008 Sheet 38 of 50 A B C D E F G H +VDDA +5VAMP L21 C390 KC FBM-L11-201209-221LMAT_0805 10U_0805_10V4Z 2 C387 60mil L19 KC FBM-L11-201209-221LMAT_0805 +5VS 1U_0402_6.3V4Z (output = 300 mA) U34 R309 10K_0402_5% IN C397 BYP 40mil +VDDA GND 0.1U_0402_16V4Z OUT SHDN G9191-475T1U_SOT23-5 R307 10K_0402_5% C737 4.75V C388 4.7U_0805_10V4Z 2 C380 1U_0402_6.3V4Z MONO_IN 1 0.01U_0402_16V7K 28 BEEP# C378 1U_0402_6.3V4Z R304 C E C376 1U_0402_6.3V4Z R302 2.4K_0402_1% 2SC2411K_SOT23 560_0402_5% HD Audio Codec D12 CH751H-40PT_SOD323-2 MBK1608121YZF_0603 2 R301 10K_0402_5% L50 20mil SB_SPKR 19 R308 Q20 B 560_0402_5% C375 C373 +3VS C369 0.1U_0402_16V4Z 10U_0805_10V4Z 2 10U_0805_10V4Z +AVDD_HDA MIC1_L 40 MIC1_R C386 MIC1_R C392 19 40 Sense Pin SENSE A Impedance SENSE B MIC_PLUG# R679 19 PORT-A (PIN 39, 41) 20K PORT-B (PIN 21, 22) 10K PORT-C (PIN 23, 24) PORT-E (PIN 14, 15) 20K PORT-F (PIN 16, 17) 10K PORT-G (PIN 43, 44) 5.1K PORT-H (PIN 45, 46) HP_LEFT MIC2_R HP_OUT_R 41 HP_RIGHT LINE1_L NC 45 24 LINE1_R DMIC_CLK 46 18 CD_L NC 43 20 CD_R NC 44 19 CD_GND BIT_CLK AMP_LEFT 40 AMP_RIGHT 40 HP_LEFT 40 HP_RIGHT 40 For EMI R660 MIC2_VREFO C374 22P_0402_50V8J 10_0402_5% INT(Analog) MIC AZ_BITCLK 19 MIC1_L MIC1_R SDATA_IN PCBEEP 37 LINE1_VREFO 29 GPIO1 31 MIC1_VREFO_L 28 SYNC SDATA_OUT SENSE_A GPIO0 GPIO3 SENSE A SENSE B EAPD_R 47 EAPD MONO_OUT RESET# 13 34 20K_0402_1% 39 AZ_SDOUT DVDD HP_OUT_L 10 39.2K_0402_1% R297 48 SPDIFO DVSS1 DVSS2 28 R696 EAPD R661 2.2K_0402_5% ACZ_SDIN0 19 15mil 10mil MIC1_VREFO_L MIC1_VREFO_R 32 MIC1_VREFO_R MIC2_VREFO 30 MIC2_VREFO VREF 27 JDREF 40 NC 33 AVSS1 AVSS2 26 42 CODEC_VREF C735 JP13 2 MIC_R 0_0603_5% GND_R 0_0603_5% 15mil 220P_0402_50V7K ACES_85204-0200 CONN@ C736 C391 0.1U_0402_16V4Z 10U_0805_10V4Z 2 R306 20K_0402_1% 0_0402_5% EAPD_R R664 0_0805_5% R665 0_0805_5% R666 0_0805_5% R667 0_0805_5% R668 0_0805_5% R669 0_0805_5% C755 @ 220P_0402_50V7K GND Issued Date C D GNDA E GND GNDA Compal Electronics, Inc Compal Secret Data 2007/09/20 2008/09/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B R662 R663 10mil AGND Security Classification A INT_MIC_R MIC_GND_R ALC268-GR_LQFP48_9X9 DGND 33_0402_5% For EMI request PORT-D (PIN 35, 36) 39.2K MIC2_L 11 AZ_SYNC Codec Signals 39.2K 5.1K HP_PLUG# AMP_RIGHT 40 R677 AMP_LEFT 36 MIC1_C_L 21 4.7U_0805_6.3V6K MIC1_C_R 22 4.7U_0805_6.3V6K MONO_IN 12 AZ_RST# 19 Place close to Codec 2 35 LINE_OUT_R MIC2_C_L 16 4.7U_0805_6.3V6K MIC2_C_R 17 4.7U_0805_6.3V6K 23 LINE_OUT_L NC MIC1_L NC 15 40 14 INT_MIC1 C733 C734 R659 1K_0402_1% INT_MIC_R 2 DVDD_IO U33 38 AVDD1 25 C381 10U_0805_10V4Z AVDD2 +VDDA 40mil 0.1U_0402_16V4Z 1 C389 L18 FBM-L11-160808-800LMT_0603 F Title HDA Codec ALC268 Size B Document Number Rev 0.1 KAW60 LA-4661P Date: Friday, August 08, 2008 G Sheet 39 H of 50 A B C D E +5VAMP W=40mil +3VS +5VAMP 39 HP_LEFT HP_RIGHT C683 HP_LEFT C684 2 S 0.01U_0402_16V7K C687 EC_MUTE G Q37 2N7002_SOT23 HP EN INR_H INL_H 17 18 HPOUT_R HPOUT_L VOL_AMP 39K_0402_5% EC_MUTE 28 C688 26 /SD 28 BEEP 12 14 CP+ CP- 25 BIAS HP_R HP_L CVSS 15 VSS 16 GND PGND PGND CGND GND 23 13 29 1 D S HP_PLUG# 39 Q60 G 24 HP_RIGHT_R 39K_0402_5% HP_LEFT_R VDD 19 20 10 100K_0402_5% SPKL+ SPKL- R627 LOUT+ LOUT- C685 1U_0603_10V4Z 1 PVDD PVDD ROUT+ ROUT- /AMP EN 2 R631 100K_0402_1% 11 INR_A INL_A 27 D PLUG# 100K_0402_5% R630 30K_0402_5% VOL_AMP SPKR+ SPKR- R626 HP_PLUG# R670 100K_0402_5% R671 100K_0402_5% 22 21 HP_RIGHT_C 4.7U_0805_6.3V6K R628 HP_LEFT_C 4.7U_0805_6.3V6K R629 +5VAMP HPF Fc = 604Hz HP_RIGHT U43 560_0402_5% 560_0402_5% 39 AMP_RIGHT_C 1U_0402_6.3V4Z AMP_LEFT_C 1U_0402_6.3V4Z HVDD C680 AMP_LEFT_C-1 C681 C682 0.47U_0603_16V4Z R624 R625 +5VAMP CVDD AMP_LEFT 1 AMP_RIGHT 39 C676 0.1U_0402_16V4Z AMP_RIGHT_C-1 39 C679 0.47U_0603_16V4Z +5VAMP C677 C678 0.1U_0402_16V4Z 2 4.7U_0805_10V4Z D 3 S Q61 2N7002_SOT23 G 2N7002_SOT23 R672 0_0402_5% @ C686 1U_0603_10V4Z APA2057A_TSSOP28 2.2U_0805_10V6K TOP/R Gain= 14dB 2 LINE Out / HP Out JACK JHP1 20mil C401 HPOUT_L R322 54.9_0603_1% HPOUT_R_1 2 ESD C400 PLUG# FSOV_Change 75 to 54.9 ohm HPOUT_R 330P_0402_50V7K 330P_0402_50V7K 1 HPOUT_R_2 FBM-11-160808-700T_0603 HPOUT_L_2 FBM-11-160808-700T_0603 L28 HPOUT_L_1 R321 54.9_0603_1% L27 SINGA_2SJ-S351-S39 CONN@ (HDA Jack for KAW60) JP12 SPKL+ SPKLSPKR+ SPKR- R673 R674 R675 R676 1 1 20mil 2 2 0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5% SPK_L+ SPK_LSPK_R+ SPK_R- TOP/L ACES_85204-0400 Speaker Conn MIC JACK MIC1_R 39 MIC1_L MIC1_L_L R681 1K_0402_1% ESD_Change 75 to 1K ohm L24 L23 2 MIC_PLUG# ESD MIC_PLUG# MIC1_R_1 FBM-11-160808-700T_0603 MIC1_L_1 FBM-11-160808-700T_0603 C404 220P_0402_50V7K 39 39 R327 2.2K_0402_5% R326 2.2K_0402_5% R561 1K_0402_1% MIC1_R_R JMIC1 MIC1_VREFO_R MIC1_VREFO_L C405 220P_0402_50V7K SINGA_2SJ-S351-S21 CONN@ (HDA Jack for KAW60) 4 2007/09/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2008/09/20 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Amplifier & Audio Jack Size B Date: Document Number Rev 0.1 KAW60 LA-4661P Sheet Friday, August 08, 2008 E 40 of 50 A B C D E +5VALW +1.8VALW TO +1.8V +3VALW TO +3VS +1.8V +3VS R167 10K_0402_5% 10U_0805_10V4Z R288 Q58 D S SYSON# G Q18 2N7002_SOT23 S +5VALW R31 10K_0402_5% 2N7002_SOT23 +5VALW TO +5VS 28 +1.8VS 1 C447 C446 SI4856ADY-T1-E3_SO8 +5VS R589 100K_0402_5% 10U_0805_10V4Z 1U_0603_10V4Z C443 4.7U_0805_10V4Z D D D D S S S G SI4800BDY_SO8 2 R563 60.4K_0402_1% 10U_0805_10V4Z C165 1U_0603_10V4Z +5VALW 5VS_GATE 1 C166 0_0402_5% 5VS_GATE R725 10K_0402_5% C658 0.1U_0603_25V7K VLDT_EN# C632 0.1U_0603_25V7K 12/30 Change R563 to 60.4K 28,37 VLDT_EN VLDT_EN G Q66 2006/2/22 Add C658 0.1uF R726 100K_0402_5% +1.2VALW TO +1.2V_HT D S 2N7002_SOT23 3 S 2N7002_SOT23 C143 4.7U_0805_10V4Z R728 1 D 2 2 G Q5 S S S G SYSON SYSON U37 D D D D SYSON# SYSON# U7 2N7002_SOT23 Q59 +1.8VALW TO +1.8VS +5VALW S G 2N7002_SOT23 +1.8VALW D PVT 46 R586 10K_0402_5% 1 +VSB C359 0.1U_0603_25V7K G Q12 SUSP# D ACIN S R289 100K_0402_5% SYSON_ALW SI4856ADY-T1-E3_SO8 C119 G @ 0_0402_5% R727 D G Q29 2N7002_SOT23 ACIN ACIN 28,45 28 SUSP 1 @ S 100K_0402_5% R500 SUSP S S S G 1 10U_0805_10V4Z D C570 0.1U_0603_25V7K D D D D 100K_0402_5% +VSB C560 SUSP SI4800BDY_SO8 46 U3 R508 100K_0402_5% 5VS_GATE 20K_0402_5% R562 10U_0805_10V4Z 2 2 S S S G C122 D D D D 1U_0603_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z +1.8VALW U41 C121 C562 C559 +3VALW +1.2V_HT +1.2VALW S 1 D SUSP G Q14 2N7002_SOT23 S R181 470_0402_5% D SUSP G Q15 2N7002_SOT23 S S R270 470_0402_5% 1 D SYSON# G Q6 2N7002_SOT23 +5VS 2 1 S D SUSP G Q35 2N7002_SOT23 R224 470_0402_5% S D SUSP G Q34 2N7002_SOT23 R26 470_0402_5% 3 S D SYSON# G Q36 2N7002_SOT23 +1.8VS +3VS D 2N7002_SOT23-3 S 4.7U_0805_10V4Z Q64 +1.8V R588 470_0402_5% 3 C758 G R587 470_0402_5% S VLDT_EN# G 2N7002_SOT23-3 D Q63 C759 0.1U_0603_25V7K +1.5VS R604 470_0402_5% +VSB D 1 R699 33K_0402_5% Near PU12 +2.5VS 2 +0.9V SI4856ADY-T1-E3_SO8 R698 470_0805_5% 2 10U_0805_10V4Z S S S G Near PU8 C757 D D D D 1U_0603_10V4Z C756 U46 SUSP G Q10 2N7002_SOT23 R700 33K_0402_5% ACIN D S Q65 G 2N7002_SOT23 Compal Secret Data Security Classification 2005/03/08 Issued Date Deciphered Date 2006/03/08 A B C Title DC INTERFACE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC D Size B Date: Document Number Rev 2.0 KAW60 LA-4661P Friday, August 08, 2008 Sheet E 41 of 50 A B PL1 VIN PR1 10_1206_5% PR2 1K_1206_5% 2 PD1 RLZ24B_LL34 PQ1 TP0610K_SOT23 PR3 1K_1206_5% PR7 1K_1206_5% B+ PR5 PR4 1K_1206_5% 2 VIN PD2 RLS4148_LL34-2 1 100K_0402_5% 560P_0402_50V7K PC4 12P_0402_50V8J PC3 12P_0402_50V8J PC2 2 PC1 560P_0402_50V7K G G PR6 1 FBMA-L18-453215-900LMA90T_1812 2 ADPIN D 100K_0402_5% PJP1 SINGA_2DC-G756-I06 C VIN 28,44 PR9 33_1206_5% PQ4 TP0610K_SOT23 ACOFF PQ2 DTC115EUA_SC70 1 BATT+ VS PQ3 DTC115EUA_SC70 2 PR8 100K_0402_5% PD3 RLS4148_LL34-2 PD4 RLS4148_LL34-2 51ON# 3 PC6 0.1U_0603_25V7K 2 B+ PR12 2.2M_0402_5% VL 37 PR11 22K_0402_5% 2 PR10 100K_0402_5% 0.22U_1206_25V7K PC5 1 CHGRTCP PR13 499K_0402_1% ACIN + ML1220T13RE 45@ +RTCBATT +RTCBATT RTCVREF D 2008/06/11 PC9 0.01U_0402_25V7K PR21 47K_0402_5% PACIN 44,45 PQ6 DTC115EUA_SC70 @ PR22 66.5K_0402_1% +5VALW Deciphered Date Compal Electronics, Inc 2009/06/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B G Compal Secret Data Security Classification A PQ5 2N7002W T/R7 1N SOT-323 S BATT ONLY Precharge detector Min typ Max H >L 6.138V 6.214V 6.359V L >H 7.196V 7.349V 7.505V Issued Date PR20 34K_0402_1% PBJ1 PR19 499K_0402_1% - Precharge detector Min typ Max H >L 14.589V 14.84V 15.243V L >H 15.562V 15.97V 16.388V PR18 191K_0402_1% PC10 0.1U_0603_25V7K PRG++ 2 RB715F_SOT323 - 32.4 PC7 1U_0805_25V4Z + O 1 ACON PC11 1000P_0402_50V7K GND 44 P 2 PU2A LM393DR_SO8 IN OUT 2 560_0603_5% 560_0603_5% PD5 G 8,43,45 MAINPWON PR17 2 PC8 +CHGRTC 4.7U_0805_6.3V6K PR16 PR14 100K_0402_1% PR15 200_0805_5% PU1 G920AT24U_SOT89 RTCVREF 3.3V 1 VS C Title DCIN/DECTOR Size B Date: Document Number Rev 0.1 KAW60 Sheet Friday, August 08, 2008 D 42 of 50 A B C D BST5B PD6 CHP202UPT_SOT323-3 PC12 0.1U_0603_25V7K PC13 0.1U_0603_25V7K BST3B B+++ 1 PC18 4.7U_1206_25V6K 2 D2 D2 G1 S1 G2 S2/D1 S2/D1 S2/D1 AO4932_SO8 3HG LX3 28 26 24 27 22 PL4 10UH_SIL104R-100PF_4.4A_30% PR31 0_0603_5% PR33 499K_0402_1% PR30 100K_0402_1% 2 BST3A DL3 DH3 2 @ PR39 3.57K_0402_1% 1 + PR42 0_0402_5% 45,47 PR41 0_0402_5% +3VALWP PRO# GND LDO3 4.7U_0805_10V4Z 10 PR43 25 0_0402_5% 2 PC24 0.047U_0603_16V7K REF PC27 PR38 12 2VREF_19998 PZD1 PR37 RLZ5.1B_LL34 47K_0402_5% 2 23 PR35 0_0402_5% 11 PR29 100K_0402_1% 2 PC20 1U_0805_16V7K 17 LX5 DL5 ILIM5 OUT5 PU3 FB5 BST3 N.C.MAX8734AEEI+_QSOP28 DH3 DL3 SHDN# LX3 ON5 OUT3 ON3 FB3 SKIP# PGOOD PR28 0_0603_5% PQ8 PC17 2200P_0402_50V7K PR24 47_0402_5% 15 19 21 ILIM3 1 PR40 100K_0402_5% 2 PR26 DH5 VS @ + PR36 0_0402_5% PC23 150U_D_6.3VM BST5 16 PC26 0.22U_0603_16V7K PR34 10.2K_0402_1% +5VALWP PC22 0.1U_0603_25V7K 14 PR32 499K_0402_1% BST5A VCC PL3 10UH_SIL104R-100PF_4.4A_30% B+++ PC16 0.1U_0603_25V7K 2VREF_1999 TON PC21 4.7U_0805_10V4Z VL LX5 @ 13 DH5 V+ 5HG PR27 0_0603_5% 4.7_1206_5% B+++ 20 PR23 0_0603_5% AO4932_SO8 18 DL5 LD05 D2 D2 G1 S1 G2 S2/D1 S2/D1 S2/D1 PC19 PR25 1U_1206_25V7K 4.7_1206_5% 2 VL 4.7U_1206_25V6K PC15 PQ7 PC14 2200P_0402_50V7K 1 PL2 FBMA-L11-322513-151LMA50T_1210 B+ SPOK 2 PC25 330U_D3L_6.3VM_R25M 47K_0402_5% PC28 0.047U_0603_16V7K +3.3V Iocp = 5.36A ~ 9.03A Ipeak=4.5A +5V Iocp = 5.35A ~ 8.65A Ipeak=4.5A Imax=3.5A Imax=3.5A MAINPWON 8,42,45 PC29 1U_0603_16V6K 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2008/06/11 Deciphered Date 2009/06/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title +5VALWP/+3VALWP Size Document Number Custom Date: KAW60 Friday, August 08, 2008 D Rev 0.1 Sheet 43 of 50 A B C D E Charger CP Point: 85% CP Point, 3.42A*0.85=2.907A~2.912A Iadp=0~2.912A(65W) Iinput=(34.8K/44.8K)*(75/20)=2.912A P2 REFIN LX 23 charger_LX PU4 MAX1908ETI+T_QFN28 VCTL ICTL 11 10 ACOK# SHDN# ACIN ICHG 28 IINP CCV charger_DLO BST 24 charger_BST DLOV 22 charger_DLOV PR56 0_0402_5% PC41 0.1U_0603_25V7K PU5A 1 PR68 511K_0402_1% PR67 10K_0402_5% + D PR69 200K_0402_1% PU5B LM358ADR_SO8 PC53 0.01U_0402_25V7K PQ20 2N7002W T/R7 1N SOT-323 G S - LM358ADR_SO8 D @ PR174 4.3K_0402_5% 2 PGND PC132 1000P_0402_50V7K PQ42 2N7002W T/R7 1N SOT-323 S - S + PQ21 2N7002W T/R7 1N SOT-323 6C/8C# 45 G 4 28 BATT_OVP VS PR173 221K_0402_1% 2 D G 28 CALIBRATE# G VCTL GND PR171 0_0402_5% +3VALW PR66 300K_0603_0.1% S D PR172 100K_0402_1% OVP-Voltage: LI-3SBattery Pack=13.5V BATT-OVP=2.0061V Battery-OVP=0.1486*BATT+ 20 PQ41 SI2301BDS_SOT23 1908LDO 14 PR170 665K_0402_1% IREF=0.73~3.3V 2P3S:4400mAH 0.8C=3.52A 1908REFIN @PR169 @ PR169 0_0402_5% IREF=0.832*Icharge PR65 845K_0603_1% Vbatt=CELLS*(4+(0.4*(Vvctl/Vrefin))) =3*(4+(0.4*(0.83087/3.331)))=12.29v @ 221K @ PC52 0.01U_0402_25V7K 665K H L 4.2V BATT+ VS 4.1V Vvctl=3.331*(221K/(221K+665K))=0.83087V P @ PC47 1U_0805_25V4Z G @ BATT+ L BATT+ PC51 0.1U_0402_16V7K 4.0V Vrefin=V1908LDO*(15K/(9.31K+15K)) =5.4V**(15K/(9.31K+15K))=3.331V P PR173 CSIN G PR170 Calibrate# PR64 10K_0402_5% Charger ADJ PC46 1U_0603_10V6K CSIP 1 CCS CCI PR63 100K_0402_5% 19 18 16 PC49 0.01U_0402_25V7K FSTCHG PR62 0_0402_5% CSIP CSIN BATT PD10 1SS355_SOD323 PR57 MAX1908-CCS 28 ACON PC50 0.1U_0402_16V7K 1 42 PR61 22K_0402_5% PACIN 42,45 RLS4148_LL34-2 PR59 100K_0402_1% 2 33_1206_5% PD11 ACOFF# LDO 1908LDO PC48 0.01U_0402_25V7K 1 S PR58 24.9K_0402_1% PQ19 2N7002W T/R7 1N SOT-323 28 IREF PR60 10K_0402_1% D G PC45 0.01U_0402_25V7K 1 15 13 21 DLO PR52 0.015_2512_1% PC44 4.7U_1206_25V6K charger_DHI 25 DHI @ PC39 @PC39 1000P_0402_50V7K 26 ACOFF 28,42 PC43 4.7U_1206_25V6K CLS PR54 15K_0402_1% VCTL CSSN ACOFF PC42 4.7U_1206_25V6K REF 12 29 10U_LF919AS-100M-P3_4.5A_20% 1908REFIN TP PL6 PR53 9.31K_0402_1% ACOFF# 2 27 1 CSSP CELLS 1908LDO 1908LDO PQ17 SI4810BDY-T1-E3_SO8 17 DCIN D D D D G S S S PC40 0.1U_0402_16V7K S PR55 34.8K_0402_1% PQ18 2N7002W T/R7 1N SOT-323 G PR50 10K_0402_0.1% PR51 150K_0402_5% D 0_0402_5% @ PR49 2 PQ16 DTC115EUA_SC70 VIN PQ14 DTC115EUA_SC70 D PQ15 SI2301BDS_SOT23 S PC38 1U_0603_10V6K D D D D G S S S 6C/8C# 45 PC37 0.1U_0603_25V7K 1 VIN 2 CSSP PD9 G CSSN 1SS355_SOD323 1 PC36 0.1U_0603_25V7K PQ13 47K DTA144EUA_SC70 47K PR45 47K_0402_1% PR48 10K_0402_1% 2 PR47 47K_0402_5% PC35 0.1U_0603_25V7K PQ12 SI4810BDY-T1-E3_SO8 PQ11 AO4407A_SO8 PC33 2200P_0402_50V7K PC34 0.1U_0603_25V7K PR46 200K_0402_1% PC32 0.1U_0603_25V7K PC31 4.7U_1206_25V6K 1 1 CHG_B+ PL5 FBMA-L18-453215-900LMA90T_1812 B+ PR44 0.02_2512_1% P3 VIN PQ10 AO4407A_SO8 PC30 4.7U_1206_25V6K PQ9 AO4407A_SO8 Vbatt=CELLS*(4V+(0.4*(Vvctl/Vrefin))) Charge voltage 3S CC-CV MODE : 12.6V 2008/06/11 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2009/06/11 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Charger Size B Date: Document Number Rev 0.1 KAW60 Sheet Friday, August 08, 2008 E 44 of 50 A B BATT+ BATT++ PR70 100K_0402_5% BATT+ PL7 FBMA-L18-453215-900LMA90T_1812 D PH1 under CPU botten side : CPU thermal protection at 90 degree C Recovery at 70 degree C +3VALWP PR71 1K_0402_5% 6C/8C# 44 BATT++ VL 1 +3VALWP PC57 1000P_0402_50V7K PR81 100_0402_5% SUYIN_200275MR007G161ZL PJP2 PR76 442K_0603_1% 1 PR73 150K_0402_1% + - G O TM_REF1 P PR77 82.5K_0603_1% MAINPWON 8,42,43 PU2B LM393DR_SO8 PR80 150K_0402_1% VL EC_SMB_DA1 28,30 PC56 0.1U_0603_25V7K PH1 100K_0603_1%_TH11-4H104FT PR79 6.49K_0402_1% 1 BATT_TEMP 28 SMART Battery: 1.GND 2.SMC 3.SMD 4.TS 5.B/I 6.ID 7.BATT+ PR74 9.76K_0402_1% PC58 1U_0805_16V7K PR75 1K_0402_5% BATT_TEMP PR78 1K_0402_5% PJP2 battery connector VL VS @PR72 @PR72 1K_0402_5% PC54 0.01U_0402_25V7K PC55 1000P_0402_50V7K 2 PR83 100_0402_5% PR82 150K_0402_1% EC_SMB_CK1 28,30 2 C KAW60 is used JAL90 battery connector footprint, but pin definition is reverse compare with KAW60 original battery connector, so schematic must be change to satisfy with JAL90 connector Vin Detector Min typ Max H >L 16.976V 17.257V 17.728V L >H 17.430V 17.901V 18.384V +VSBP PR84 1M_0402_1% PU6A ACIN 28,41 PACIN 42,44 O PC62 0.1U_0603_25V7K ACIN PACIN LM393DR_SO8 1 - PR89 10K_0402_5% P + 2 PR87 10K_0402_5% PZD2 RLZ4.3B_LL34 PR94 10K_0402_5% S PR92 20K_0402_1% PC61 1000P_0402_50V7K PQ23 2N7002W T/R7 1N SOT-323 PR91 22K_0402_5% PR95 10K_0402_5% RTCVREF @ PC63 0.1U_0402_16V7K D G 1 PR93 0_0402_5% SPOK 1 43,47 VS PR86 84.5K_0402_1% PR90 100K_0402_5% VIN VIN PC60 0.1U_0603_25V7K 2 PC59 0.22U_1206_25V7K VL PR88 22K_0402_5% 2 PR85 100K_0402_5% 1 1 G B+ PQ22 TP0610K_SOT23 + - PU6B P G O LM393DR_SO8 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2008/06/11 Deciphered Date 2009/06/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title BATTERY CONN / OTP Size B Date: Document Number Rev 0.1 KAW60 Sheet Friday, August 08, 2008 D 45 of 50 1 +3VALW PJP3 JUMP_43X79 PJP4 JUMP_43X79 NC TP +2.5VSP PGND VFB AGND VTT VCCA VTT REFEN PC72 0.1U_0603_25V7K D C S PJP5 2 PJP6 1 +3VALW +1.8VALWP 2 PQ25 2N7002W T/R7 1N SOT-323 2 G PR163 0_0402_5% SUSP 41 C +1.8VALW 1 +1.8VALW JUMP_43X113 JUMP_43X113 PJP7 PJP8 +5VALW +2.5VSP PJP10 PJP11 1 +1.2VALW +1.5VSP JUMP_43X113 2 RTCVREF VIN PGND VFB AGND VTT VCCA VTT REFEN PJP14 +0.9V +VSBP B 1 +VSB +1.5VSP JUMP_43X113 2 PR165 60.4K_0402_1% 1 PC125 22U_1206_10V6M JUMP_43X113 PC124 1U_0603_16V6K PC126 0.047U_0402_16V7K 1 +5VALW PU12 CM8562IS_PSOP8 PR166 51K_0402_1% +0.9VP +1.5VS PJP12 B 1 JUMP_43X113 AGND +2.5VS 1 PR164 10_0603_1% +1.2VALWP JUMP_43X113 PC123 4.7U_1206_25V6K PC127 0.1U_0603_25V7K JUMP_43X113 2 +5VALWP PJP13 JUMP_43X79 1 +3VALWP PR98 60.4K_0402_1% 1 1 PC70 22U_1206_10V6M 2 PC68 22U_1206_10V6M +0.9VP @ PC69 0.1U_0402_16V7K S G PQ24 2N7002W T/R7 1N SOT-323 PR99 1K_0402_1% SYSON# 41 D APL5331KAC-TRL_SO8 @ PR162 @PR162 0_0402_5% VIN PC67 1U_0603_16V6K VOUT PR96 1K_0402_1% PC71 0.047U_0402_16V7K NC PC66 1U_0603_6.3V6M VREF PU8 CM8562IS_PSOP8 PR100 200K_0402_1% NC +3VALW PR97 10_0603_1% GND RTCVREF VCNTL 2 PC65 10U_1206_25VAK VIN 1 PU7 AGND +1.8V D +5VALW D PC64 4.7U_1206_25V6K 1 2 +1.8VALW D S PQ40 2N7002W T/R7 1N SOT-323 2 G PR167 0_0402_5% SUSP 41 A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2008/06/11 2009/06/11 Deciphered Date +0.9VSP/+1.5VSP/+2.5VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom Date: Rev 0.1 KAW60 Sheet Friday, August 08, 2008 46 of 50 PL8 FBMA-L11-322513-151LMA50T_1210 2 PR107 0_0603_5% BST_1.8VP-1 23 UGATE1 UGATE2 24 DH_1.8VP PHASE1 PHASE2 25 LX_1.8VP PC90 0.1U_0402_16V7K 26 10 15 VOUT1 VSEN1 EN1 PG1 VOUT2 VSEN2 EN2 PG2/REF 20 19 21 16 OCSET2 18 PR120 56.2K_0402_1% +3VALW @ 10K_0402_1% @ PR118 0_0402_5% +5VALW PR117 10K_0402_1% PR168 10K_0402_5% B 2 PR121 56.2K_0402_1% PC95 0.1U_0402_16V7K PR115 13 1 PR113 10.2K_0402_1% VSE_1.8VP OCSET1 DDR GND 11 PGND2 PGND1 PC94 0.01U_0402_25V7K DL_1.8V 27 PC92 220U_D2_4VM_R15 LGATE2 PR112 0_0402_5% LGATE1 2 + 22 @ PR176 4.7_1206_5% ISEN2 PR111 1.5K_0402_1% ISE_1.8VP 12 ISEN1 PU10 ISL6227CAZ-T_SSOP28 +1.8VALWP PL10 1.8UH_SIL104R-1R8PF_9.5A_30% 2 PR110 1.27K_0402_1% ISE_1.2VSP PC96 0.1U_0402_16V7K 1 C @ PC134 680P_0402_50V7K LX_1.2VSP PQ30 SI4810BDY-T1-E3_SO8 G D S D S D S D DH_1.2VSP PR114 10K_0402_1% @ PR119 0_0402_5% B PQ28 SI4800BDY-T1-E3_SO8 BOOT2 D D D D SOFT2 PC88 0.01U_0402_25V7K 17 S S S G 28 VCC 14 SOFT1 PR106 0_0603_5% 2BST_1.2VSP-1 BOOT1 DL_1.2VSP 43,45 SPOK PC83 2200P_0402_25V7K PC82 10U_1206_25VAK 2 VIN BST_1.2VSP PC87 0.01U_0402_25V7K 12 VSE_1.2VSP PR116 10K_0402_1% PC86 2.2U_0805_10V6K D D D D PC89 0.1U_0402_16V7K PQ29 SI4810BDY-T1-E3_SO8 PR109 0_0402_5% PR105 2.2_0603_5% PC93 0.01U_0402_25V7K PR108 3.48K_0402_1% 2 @ PC133 680P_0402_50V7K 2 @ PR175 4.7_1206_5% +5VALW D BST_1.8VP S S S G + D D D D 1 PC91 220U_D2_4VM_R15 S S S G C PL9 1.8UH_SIL104R-1R8PF_9.5A_30% 2 +1.2VALWP PC81 2200P_0402_25V7K PC80 10U_1206_25VAK 1 PC85 0.1U_0603_25V7K PD12 DAP202U_SOT323 PQ27 SI4800BDY-T1-E3_SO8 PR104 51_1206_5% B+ PC84 4.7U_0805_6.3V6K PC79 PC78 10U_1206_25VAK D 10U_1206_25VAK ISL6227B+ Ipeak=8.5A, Imax=6A Iocpmin=8.76A Iocpmax=13.46A Ipeak=6.47A, Imax=6.47*0.7=4.53A Iocpmin=7.79A Iocpmax=11.83A A A Compal Secret Data Security Classification 2008/06/11 Issued Date Deciphered Date 2009/06/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title +1.2VSP/+1.8VP Size Document Number Custom Date: Rev 0.1 KAW60 Friday, August 08, 2008 Sheet 47 of 50 OCP Setting: Rcs=((R2+Rntc)/(R1+R2+Rntc))*DCR VILIM=14.5mV (min) 17.5mV(typ) PGND1 27 PWRGD CSP1 16 17 PHASEGD CSN1 15 37 TWO-PH GND 18 38 SHDN# IC 40 For EC ATE 2 PC128 220P_0402_50V8J PC129 220P_0402_50V8J PQ32 AO4456_SO8 @ AGND DL2 PGND2 23 CSP2 13 CSN2 14 VRHOT# SKIP# PC118 4700P_0603_50V7K PC131 220P_0402_50V8J PR153 100_0402_1% D PQ35 SI7686DP-T1-E3_SO8 PR155 0_0603_5% S PQ38 AO4456_SO8 PR158 10_0402_5% PQ37 FDV301N_NL_SOT23-3 PC101 100U_25V_M PC100 2200P_0402_50V7K PC99 0.01U_0402_25V7K Ceq CPU_B+ 3 2 PSI# PC109 0.22U_0603_16V7K PR146 0_0402_5% 3 1 0_0402_5% PQ36 2N7002W T/R7 1N SOT-323 G C 220P_0402_50V8J 2 PR152 200K_0402_1% PC130 1 PR137 10_0402_5% R2 LX2 24 PR142 100_0402_1% 22 DL2 PR154 200K_0402_1% LX2 OFS PR144 Rntc PR136 PH2 5.11K_0402_1% 10KB_0603_5%_ERTJ1VR103J 2 @ PC121 CPU_VSS_SENSE CPU_VCC_SENSE B 39 TON 0_0603_5% +3VS B DH2 0.22U_0603_16V7K PR150 0_0402_5% 21 2 20 DH2 PR151 BST2 REF POUT PC119 10 EP S G 150P_0402_50V8J MAX8774_REF 0.1U_0603_16V7K 200K_0402_1% 1 D PR149 169K_0603_1% 12 CPU_B+ MAX8774_REF PR148 31.6K_0402_1% 11 CCI PR147 FB CCV 1 PC113 TIME 2 PR141 PC108 4.32K_0603_1% 4700P_0402_25V7K FB PR143 20K_0402_1% 2 PC111 470P_0402_50V8J 71.5K_0402_1% PC110 R1 D5 DL1 36 SHORT PADS PL13 0.45UH_ETQP4LR45XFC_25A_-25+20% 2 26 +CPU_CORE PL12 0.45UH_ETQP4LR45XFC_25A_-25+20% 4700P_0402_25V7K PR157 2.1K_0402_1% R1 PH3 PR159 10KB_0603_5%_ERTJ1VR103J 5.11K_0402_1% 2 LX1 DL1 D PC97 4.7U_1206_25V6K PC98 4.7U_1206_25V6K 28 D4 41 POUT PC112 0.1U_0402_16V7K D3 MAX8774GTL+_TQFN40 LX1 35 GNDS PR140 100K_0402_5% PR145 10K_0402_1% 34 28 DH1 MAX8774_VCC @ PR139 PQ34 2N7002W T/R7 1N SOT-323 VR_ON 29 PR138 0_0402_5% C DH1 PU11 PC117 0.01U_0402_25V7K VGATE +3VS D2 + PR128 0_0603_5% PR134 2.1K_0402_1% 28 J1 33 2 VID5 30 2200P_0402_50V7K PC115 4.7U_1206_25V6K PC116 4.7U_1206_25V6K BST1 PC107 PR131 1000P_0603_50V7K 3.3_1206_5% 1 VID4 D1 PC114 VID3 32 PC120 1000P_0603_50V7K THRM VID2 PR126 0_0603_5% D0 8 VDD 31 PQ31 SI7686DP-T1-E3_SO8 VID1 VCC 25 PC106 4700P_0402_25V7K PR124 0_0402_5% PR125 0_0402_5% PR127 0_0402_5% PR129 0_0402_5% PR130 0_0402_5% PR132 0_0402_5% PR133 0_0402_5% PR135 100K_0402_1% B+ PL11 FBMA-L18-453215-900LMA90T_1812 PC105 0.22U_0603_16V7K MAX8774_VCC 19 PC104 0.01U_0402_25V7K PC103 2.2U_0603_10V6K Iocp=36A~44A PC102 2.2U_0603_6.3V6K DeltaI=((Vin-Vo)*D)/(F*L) PR123 10K_0402_5% D CPU_B+ Req=(R1*(R2+Rntc))/(R1+R2+Rntc) PR122 10_0402_5% +3VS Iocp=Ivalley+1/2 DeltaI VID0 PR156 3.3_1206_5% +5VS Ivalley=17.5mV/Rcs (min) 14.5Mv/Rcs(typ) Rcs*Ceq=L/Req must be satisfy! Rntc R2 PC122 0.22U_0603_16V7K CSP2 Ceq PR160 A A 0_0402_5% Compal Secret Data Security Classification 2008/06/11 Issued Date Deciphered Date 2009/06/11 Title +CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Custom Date: Rev 0.1 KAW60 Friday, August 08, 2008 Sheet 48 of 50 Version change list (P.I.R List) Item D Reason for change Rev PG# Modify List Page of for PWR Date Phase material issue Change to currently design 0.1 44 Change PQ9, PQ10, PQ11 from SB944070000(S TR AO4407 1P SO8 W/D) to SB00000DL00(S TR S TR AO4407A 1P SO8) 08,07/22 to PVT material issue Change to currently design 0.1 48 Change PQ31 and PQ35 from SB578400080(S TR SI7840-T1 -E3 1N SO8) to SB000008L80(S TR SI7686DP-T1-E3 1N POWERPAK SO8) 08,07/22 to PVT material issue AO4916 will be EOL, change to AO4932 0.1 43 Change PQ7 and PQ8 from SB000002W80(S TR AO4916 2N SO8) to SB00000BG00(S TR AO4932 2N SO8) 08,07/22 to PVT BOM error BOM error 0.1 48 Change PR141 from SD014200180(S RES 1/10W 2K 0603 1%) 08,07/22 to SD014432180(S RES 1/10W 4.32K 0603 1%) to PVT material issue SI4810 will be EOL, change to SI4894 0.1 47 Change PQ12, PQ17, PQ29, PQ30 from SB548100020(S TR SI4810BDY-T1-E3 1N SO8) to SB00000D300(S TR SI4894BDY- 08,07/22 T1-E3 1N SO8) to PVT Add VGATE pull high resistor Add VGATE pull high resistor 0.1 48 C Fixed Issue Add PR123 SD028100280(S RES 1/16W 10K 0402 5%) 08,07/22 D to PVT C 10 11 B 12 B 13 14 15 16 17 18 A A Compal Secret Data Security Classification Issued Date 2008/06/11 Deciphered Date 2009/06/11 Title PIR(PWR) THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Custom Date: Rev 0.1 KAW60 Friday, August 08, 2008 Sheet 49 of 50 PVT/MP P.19 & 24 Update CRT_DET & CRT_DET# net name NA P.18 & 19 Change CRT_DET from GPIO61 to GPIO0 & reserved R741 , R742 , R743 For ACER AP test CRT detect feature P.20 Remove L71 , C694 & C697 For +3Vs (1.5V) , +5Vs (0.388V) , +1.8Vs (0.154V) on S5 leakege issue P.28 Change R519 from 100K to 10K For RS690MC ENBKL had unexpected 3.3V pulse before normal display & white screen flash symptom appear P.14 Reserved U48 , U49 , R744 , R745 , R746 , R747 , C763 For RS690MC ENBKL , ENVDD if had unexpected 3.3V pulse before normal display P.28 & 31 Modify WL_ON_LED# from KB926 to JMINI1 control WL LED activity behavior controlled by wireless mini card itself P.38 Update SW9 Footprint & P/N NA P.41 Change R586 from 100K to 10K For Susp# had 3V level glitch when G3 to S5 (Plug AC in) & caused +5Vs /+3Vs had leakege immediately D P.6 Change D4 as SC1BAS16000(S DIO BAS16PT SOT-23) Sourcer recommend P.26 Change U11 as SA000019910(S IC EE 1K CAT93C46VI-GT3 SOIC 8P) SA093461070 (S IC EE 1K SO-8 I AT93C46-10SI-2.7) EOL P.50 Change T1 as SP050001210 / S X'FORM_ NS0013LF LAN (BOTHHAND) MHPC X'form part not for ABO , Sourcer recommend P.18 Delete R695,R179,R484 for SB_TEST pin AMD reference schematic P.20 Reserved C764 (1u_0402) AMD reference schematic & design guide P.38 Modify WL_LED power rail as +3Vs NA P.28 & 38 Modify LED control of SATA drive from EC to SB (Add Q67) EC(media_led#/pin86 , reference sata_led# from SB) control behavior abnormal P.17 Change C510 , C511 of 14.318MHz as 27P from 22P NA P.37 & 25 Change D5 , D21 as SC1BAS16000 NA P.26 Add L77 , C765 , C766 , C767 & change R645 / R647 as L78 / L79 , reserved C719 , C724 EMI request P.31 & 34 Stuff L66 , L67 , L68 & remove R615 , R616 , R598 , R599 , R600 , R601 EMI request P.29 Stuff D28 ESD request P.6 Update net EN_DFAN1_R NA P.6 Update JCPU1 PCB footprint as SOC127MM48X51-948 NA P.26 Add R749 , R750 (300ohm_0402) For LAN external EEPROM program issue P.31 Add D32 (SCA00000A00) ESD request P.28 & 31 Reserved R751 & R752 Reserved WL_LED controlled by EC (Navarrow project) P.24 Change C411 & C412 PN from SE081680k80 to SE071680J80 AP Code D C C P.6 Change U1 as SA00001Z900 (S IC APL5605KI-TRL SOP 8P) (SA009930010) S IC G993P1UF SOP 8P FAN LDO P.15 Change C330 as 0402 package NA EOL B B ZZZ LA4661MB Rev0 : DA600009Z00 PCB 06B LA-4661P REV1 M/B LA4661MB with Sub/B Rev1 : DAZ06B00100 A A Compal Secret Data Security Classification 2005/03/08 Issued Date Deciphered Date 2006/03/08 Title PIR-HW & Option Component THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Custom KAW60 LA-4661P Date: Friday, August 08, 2008 Rev 2.0 Sheet 50 of 50 ... 98 10 0 10 2 10 4 10 6 10 8 11 0 11 2 11 4 11 6 11 8 12 0 12 2 12 4 12 6 12 8 13 0 13 2 13 4 13 6 13 8 14 0 14 2 14 4 14 6 14 8 15 0 15 2 15 4 15 6 15 8 16 0 16 2 16 4 16 6 16 8 17 0 17 2 17 4 17 6 17 8 18 0 18 2 18 4 18 6 18 8 19 0 19 2 19 4... 4.7U _08 05 _ 10 V4Z 4.7U _08 05 _ 10 V4Z C39 10 00P _04 02_50V7K C 30 2 C36 4.7U _08 05 _ 10 V4Z C 41 100 0P _04 02_50V7K 2 C1 81 4.7U _08 05 _ 10 V4Z C178 10 00P _04 02_50V7K 2 C184 0. 22U _04 02 _ 10 V4Z C22 10 00P _04 02_50V7K C185 0. 22U _04 02 _ 10 V4Z... C366 C3 51 C349 1 C347 C346 1 C368 0. 1U _04 02 _16 V4Z 10 U _08 05 _ 10 V4Z 10 00P _04 02_50V7K 2 0. 1U _04 02 _16 V4Z 1 C1 50 10 U _08 05 _ 10 V4Z 2 1U _04 02_6.3V4Z 10 00P _04 02_50V7K C148 C153 2 C149 10 00P _04 02_50V7K C