5 JE43-CP Block Diagram Clock Generator ICS9LRS3197AKLFT DDRIII 1066/1333 Slot DDRIII 1066/1333 Slot PCB P/N REVISION : 91.4NI01.001 : 10277-1 X1 14.318Mhz Arrandale CPU DC/DC DCBATOUT DDR3 800MHz N12P-GV PCI EXPRESS GRAPHIC VCC_CORE SYSTEM DC/DC 50 RT8209E INPUTS OUTPUTS VRAM 2GB/1GB/512MB Nvida DCBATOUT 1D05V_VTT 1D05V_S0 88,89,90,91 SYSTEM DC/DC 4,5, ,9,10 DDR II Channel B 21 91.4NI01.001(JE43-CP) N12P-GS X16 D Project code: 54 ISL62881 INPUTS OUTPUTS Intel CPU DDRII Channel A 20 X8601 27Mhz D 60, ,68 49 INPUTS OUTPUTS RT8223 FDIx8 Discreet/UMA/PX Co-lay DMIx4 5V_S5 3D3V_S5 DCBATOUT SYSTEM DC/DC Mini-Card WLAN 37 INTEL PCIE(Port2) USB 2.0(Port3) Level 23 shifter HDMI PCH SIM Mini-Card 3G 37 37 HDMI ETHERNET LCD 23 SYSTEM DC/DC 54 ISL62881 INPUTS OUTPUTS RGB CRT (10/100/1000Mb) High Definition Audio Giga LAN AR8151 PCIE ports Port1 PCIE Port4 ACPI 1.1 31 PCI/PCI BRIDGE X4 25Mhz WEBCAM CRT VGA 24 55 RT8208B INPUTS OUTPUTS 23 LPC I/F 30 Port11 X3 25Mhz DCBATOUT BLUETOOTH Port1 & Port9 USB 2.0 C 28 USB x VGA_CORE TI CHARGER 53 BQ24745 INPUTS OUTPUTS 29 DCBATOUT INT MIC HD AUDIO CODEC ALC271 32 AZALIA Port13 CardReader RTS5138 26 SD/MMC MS/MS Pro/xD36 SYSTEM DC/DC 3D3V_S0 USB_BD uPD720200 PCIE*1(Port4) 38 USB2.0*1(Port0) SATA 11,12, ,18,19 Port0 3D3V_VGA_S0 SATA HDD 26 Port4 LPC debug LPC Bus SATA ODD 27 Flash ROM 4MB 41 1D5V_VGA_S0 3D3V_S0 3D3V_VGA_S0 1V_VGA_S0 B PCB STACKUP X6 32.768Khz ENE 3930 1D5V_S3 1D05V_VTT 41 B KBC 1D8V_VGA_S0 56 Switches INPUTS OUTPUTS X2 32.768Khz SPI 56 RT9025 INPUTS OUTPUTS 26 38 SPI 2CH SPEAKER 1D8V_S0 SYSTEM DC/DC USB_BD uPD720200 C BT+ 52 RT9025 INPUTS OUTPUTS 36 MIC IN HP1 VCC_GFXCORE_PWR DCBATOUT SATA ports RJ45 CONN 1D5V_S3 0D75V_S0 DDR_VREF_S3 DCBATOUT LVDS(Single Channel) 14 USB 2.0/1.1 ports PCIE(Port3) USB 2.0(Port12) 50 RT8209E INPUTS OUTPUTS 25 TOP 40 GND S CardReader >5138 Audio >271X Thermal Sensor G787 39 Flash ROM 128KB 41 S Power_ BD Touch PAD43 GND Int KB40 BOTTOM CPU FAN A A Hynix 1G 800M N11PGV SKU Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Block Diagram Size A2 Date: Document Number Rev -1 JE43-CP Wednesday, November 24, 2010 Sheet of 69 A B PCH Strapping Name SPKR Schematics Notes Reboot option at power-up Default Mode: Internal weak Pull-down No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-kΩ - 10-kΩ weak pull-up resistor INIT3_3V# Weak internal pull-down Do not pull high GNT3#/ GPIO55 Default Mode: Internal pull-up Low (0) = Top Block Swap Mode (Connect to ground with 4.7-kΩ weak pull-down resistor) INTVRMEN High (1) = Integrated VRM is enabled Low (0) = Integrated VRM is disabled Default (SPI): Left both GNT0# and GNT1# floating No pull up required Boot from PCI: Connect GNT1# to ground with 1-kΩ pull-down resistor Leave GNT0# Floating Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-kΩ pull-down resistor GNT0#, GNT1# GNT2#/ GPIO53 Default - Internal pull-up Low (0)= Configures DMI for ESI compatible operation (for servers only Not for mobile/desktops) GPIO33 Default: Do not pull low Disable ME in Manufacturing Mode: Connect to ground with 1-kΩ pull-down resistor SPI_MOSI Enable iTPM: Connect to Vcc3_3 with 8.2-kΩ weak pull-up resistor Disable iTPM: Left floating, no pull-down required Enable Danbury: Connect to Vcc3_3 with 8.2-kΩ weak pull-up resistor Disable Danbury: Connect to ground with 4.7-kΩ weak pull-down resistor NV_ALE NC_CLE Weak internal pull-up Do not pull low HAD_DOCK_EN# /GPIO[33] HDA_SDO Low (0): Flash Descriptor Security will be overridden High (1) : Flash Descriptor Security will be in effect Weak internal pull-down Do not pull high HDA_SYNC Weak internal pull-down Do not pull high GPIO15 Weak internal pull-down Do not pull high GPIO8 Weak internal pull-up Do not pull low GPIO27 Default = Do not connect (floating) High(1) = Enables the internal VccVRM to have a clean supply for analog rails No need to use on-board filter circuit Low (0) = Disables the VccVRM Need to use on-board filter circuits for analog rails PCIE Routing LAN USB3 LANE2 MiniCard1 USB2 USB4 MINICARD1 MiniCard2 E Pin Name Strap Description Configuration (Default value for each bit is unless specified otherwise) Default Value CFG[4] Embedded DisplayPort Presence CFG[3] PCI-Express Static Lane Reversal 1: Disabled - No Physical Display Port attached to Embedded DisplayPort 0: Enabled - An external Display Port device is connected to the Embedded Display Port 1: Normal Operation 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, CFG[0] PCI-Express Configuration Select 1: Single PCI-Express Graphics 0: Bifurcation enabled CFG[7] Reserved Temporarily used for early Clarksfield samples Clarksfield (only for early samples pre-ES1) Connect to GND with 3.01K Ohm/5% resistor Note: Only temporary for early CFD samples (rPGA/BGA) [For details please refer to the WW33 MoW and sighting report] For a common motherboard design (for AUB and CFD), the pull-down resistor should be used Does not impact AUB functionality Device LANE1 LANE3 D USB Table Pair C Processor Strapping WECAM Touch Panel NC NC NC USB1(HS) 10 Finger Print 11 Blue Tooth 12 MINIC2 13 Cardreader Hynix 1G 800M N11PGV SKU Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Table of Content Size A3 Date: Document Number Rev -1 JE43-CP W ednesday, November 24, 2010 Sheet of 69 A B C D E 1D5V_S0_CLKGEN Do Not Stuff R3 2 C3 DY 1D05V_VTT Do Not Stuff R2 3D3V_S0 R5 Do Not Stuff DY DY C10 SC10U6D3V3MX-GP C9 Do Not Stuff DY C8 C7 C6 SCD1U16V2ZY-2GP 3D3V_CK505_IO R4 Do Not Stuff Do Not Stuff SC10U6D3V3MX-GP DY SCD1U16V2ZY-2GP C5 C4 SCD1U16V2ZY-2GP 3D3V_CK505 20101108 C2 Do Not Stuff 20101026 3D3V_S0 C1 SC10U6D3V3MX-GP Do Not Stuff 1D5V_S0 SCD1U16V2ZY-2GP 1D5V_S0_CLKGEN R1 SA 0622 EMI VGA_XIN1_L OSC_SPREAD_L 2 Do Not Stuff Do Not Stuff DY EC1 DY EC2 U1 1D5V_S0_CLKGEN 3D3V_CK505 3D3V_CK505_IO DY RN42 Do Not Stuff 63 OSC_SPREAD 63 VGA_XIN1 VGA_XIN1_L OSC_SPREAD_L 12,20,21 PCH_SMBCLK 12,20,21 PCH_SMBDATA GEN_XTAL_IN GEN_XTAL_OUT R14 CLK_ICH14 33R2J-2-GP C11 CPU_STOP# 27FIX 27SS 32 31 SCLK_3_3 SDATA_3_3 28 27 X1 X2 25 30 VTTPWRGD/PD#_3_3 REF/FSLC 16 SATAT_LR SATAC_LR NC#16 10 11 DOT96T_LR DOT96C_LR CPUT_LR0 CPUC_LR0 CPUT_LR1 CPUC_LR1 23 22 20 19 PCIEXT_LR PCIEXC_LR 13 14 GND96 GND27 GNDSATA GNDPCIEX GNDCPU GNDREF GND 12 21 26 33 CLK_PCIE_SATA_R Do Not Stuff CLK_PCIE_SATA#_R2 Do Not Stuff DREFCLK_R DREFCLK#_R R8 Do Not Stuff Do Not1Stuff R9 CLK_CPU_BCLK_R Do Not Stuff CLK_CPU_BCLK#_RDo Not Stuff CLKIN_DMI_R CLKIN_DMI#_R R6 R7 Do Not Stuff Do Not Stuff CLK_PCIE_SATA 12 CLK_PCIE_SATA# 12 DREFCLK 12 DREFCLK# 12 R10 R11 CLK_CPU_BCLK 12 CLK_CPU_BCLK# 12 R12 R13 CLKIN_DMI 12 CLKIN_DMI# 12 SA 0629 RF PCH_SMBDATA 3D3V_S0 9LVS3197BKLFT-GP PCH_SMBCLK 71.93197.B03 2ND = 71.08595.003 DY ECT1 Do Not Stuff DY ECT2 Do Not Stuff RN1 SRN10KJ-5-GP Do Not Stuff DY 12 CLK_EN FSC VDD96_1_5 VDD27_3_3 VDDPCIEX_IO_LV VDDPCIEX_1_5 VDDCPU_IO_LV VDDCPU_1_5 VDDREF_3_3 3 15 17 18 24 29 CPU_STOP# FSC C12 SC12P50V2JN-3GP GEN_XTAL_IN SPEED D DY DY 84.2N702.D31 2ND = 84.2N702.E31 3rd = 82.30005.B81 VR_CLKEN# 47 2N7002E-1-GP FSC 2ND = 82.30005.901 G S GEN_XTAL_OUT 82.30005.A51 R18 2K2R2J-2-GP CL = 10pF Freq tolertance :+/- 30 ppm SB 0813 Q1 R16 Do Not Stuff GEN_XTAL_OUT_R R17 200R2J-L1-GP (Default) 100MHz 2 C13 SC12P50V2JN-3GP R15 Do Not Stuff X1 X-14D31818M-50GP 133MHz CLK_EN 1D05V_VTT 1 Hynix 1G 800M N11PGV SKU 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Clock Generator Size A3 Date: A B C D Document Number Rev -1 JE43-CP W ednesday, November 24, 2010 Sheet E of 69 D OF 13 13 13 13 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 B24 D23 B23 A22 DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3 DMI_RX0# DMI_RX1# DMI_RX2# DMI_RX3# 13 13 13 13 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 D24 G24 F23 H23 DMI_TX0# DMI_TX1# DMI_TX2# DMI_TX3# 13 13 13 13 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 D25 F24 E23 G23 DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3 FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 E22 D21 D19 D18 G21 E19 F21 G18 FDI_TX0# FDI_TX1# FDI_TX2# FDI_TX3# FDI_TX4# FDI_TX5# FDI_TX6# FDI_TX7# 13 13 13 13 13 13 13 13 FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 D22 C21 D20 C18 G22 E20 F20 G19 FDI_TX0 FDI_TX1 FDI_TX2 FDI_TX3 FDI_TX4 FDI_TX5 FDI_TX6 FDI_TX7 13 FDI_FSYNC0 13 FDI_FSYNC1 F17 E17 FDI_FSYNC0 FDI_FSYNC1 13 FDI_INT C17 FDI_INT 13 FDI_LSYNC0 13 FDI_LSYNC1 F18 D17 FDI_LSYNC0 FDI_LSYNC1 SA 0813 R21 Do Not Stuff RN2 FDI_LSYNC1 FDI_FSYNC1 FDI_FSYNC0 FDI_LSYNC0 DIS 2 Do Not Stuff DIS For Graphics Disable , Pull-down to GND via 1-k ± 5% resistor D R19 PEG_IRCOMP_R 49D9R2F-GP B26 A26 B27 A25 PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0 PEG_RXN[0 15] 60 PEG_RX0# PEG_RX1# PEG_RX2# PEG_RX3# PEG_RX4# PEG_RX5# PEG_RX6# PEG_RX7# PEG_RX8# PEG_RX9# PEG_RX10# PEG_RX11# PEG_RX12# PEG_RX13# PEG_RX14# PEG_RX15# K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0 PEG_RXP[0 15] 60 PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15 PEG_TX0# PEG_TX1# PEG_TX2# PEG_TX3# PEG_TX4# PEG_TX5# PEG_TX6# PEG_TX7# PEG_TX8# PEG_TX9# PEG_TX10# PEG_TX11# PEG_TX12# PEG_TX13# PEG_TX14# PEG_TX15# L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 PEG_TXN15_L PEG_TXN14_L PEG_TXN13_L PEG_TXN12_L PEG_TXN11_L PEG_TXN10_L PEG_TXN9_L PEG_TXN8_L PEG_TXN7_L PEG_TXN6_L PEG_TXN5_L PEG_TXN4_L PEG_TXN3_L PEG_TXN2_L PEG_TXN1_L PEG_TXN0_L C14 DIS_Muxless C15 DIS_Muxless C16 DIS_Muxless C17 DIS_Muxless C18 DIS_Muxless C19 DIS_Muxless C20 DIS_Muxless C21 DIS_Muxless C22 DIS_Muxless C23 DIS_Muxless C24 DIS_Muxless C25 DIS_Muxless C26 DIS_Muxless C27 DIS_Muxless C28 DIS_Muxless C29 DIS_Muxless SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXN15 PEG_TXN14 PEG_TXN13 PEG_TXN12 PEG_TXN11 PEG_TXN10 PEG_TXN9 PEG_TXN8 PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0 PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15 L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25 PEG_TXP15_L PEG_TXP14_L PEG_TXP13_L PEG_TXP12_L PEG_TXP11_L PEG_TXP10_L PEG_TXP9_L PEG_TXP8_L PEG_TXP7_L PEG_TXP6_L PEG_TXP5_L PEG_TXP4_L PEG_TXP3_L PEG_TXP2_L PEG_TXP1_L PEG_TXP0_L C30 DIS_Muxless C31 DIS_Muxless C32 DIS_Muxless C33 DIS_Muxless C34 DIS_Muxless C35 DIS_Muxless C36 DIS_Muxless C37 DIS_Muxless C38 DIS_Muxless C39 DIS_Muxless C40 DIS_Muxless C41 DIS_Muxless C42 DIS_Muxless C43 DIS_Muxless C44 DIS_Muxless C45 DIS_Muxless SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP PEG_TXP15 PEG_TXP14 PEG_TXP13 PEG_TXP12 PEG_TXP11 PEG_TXP10 PEG_TXP9 PEG_TXP8 PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0 Intel(R) FDI 13 13 13 13 13 13 13 13 PCI EXPRESS GRAPHICS DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS DMI 13 13 13 13 A24 C23 B22 A21 AUBURNDALE CPU1_CPA C B R20 EXP_RBIAS 750R2F-GP C PEG_TXN[0 15] 60 PEG_TXP[0 15] 60 B AUBURNF,CLARKUNF 62.10055.321 3RD = 62.10055.341 4th = 62.10040.611 0113 -1 A 2ND = 62.10053.561 Del 3rd 62.10055.341 and 4th 62.10055.321 3rd and 4th have been purged CE will confrim SQM if it can add BOM CE will release EC to add to BOM lab stuff 2nd,3rd and th in BOM Eng add 1st source(62.10040.611) Eng not stuff th in BOM becasue th have been purge ,so stuff 1st in BOM but CE said, 4th need stuff in PD if not any Hynix concern 1G 800M N11PGV SKU A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (1/7) Size A3 Date: Document Number Rev -1 JE43-CP W ednesday, November 24, 2010 Sheet of 69 1D05V_VTT CPU1_CPB PROCHOT# R26 68R2-GP H_COMP2 AT24 H_COMP1 G16 COMP1 H_COMP0 AT26 COMP0 SKTOCC#_R AH24 SKTOCC# H_CATERR# AK14 20R2F-GP 2 R27 49D9R2F-GP R23 49D9R2F-GP D Do Not Stuff TP3 R31 47 H_PROCHOT# Do Not Stuff DY PROCHOT# AN26 AK15 16,45 PM_THRMTRIP-A# Do Not Stuff TP5 H_CPURST# 13 H_PM_SYNC 16,59 R34 Do Not Stuff H_PW RGD 13 PM_DRAM_PW RGD THERMTRIP# AP26 RESET_OBS# AL15 PM_SYNC AN14 VCCPWRGOOD_1 VCCPW RGOOD_0 AN27 VCCPWRGOOD_0 R36 Do Not Stuff DRAMPW ROK AK13 SM_DRAMPWROK AM15 VTTPWRGOOD H_PW RGD_XDP AM26 TAPPWRGOOD PLT_RST#_R AL14 RSTIN# TP6 1 PEG_CLK PEG_CLK# E16 D16 DPLL_REF_SSCLK DPLL_REF_SSCLK# A18 A17 BCLK_CPU_P 16 BCLK_CPU_N 16 PEG_CLK_R PEG_CLK#_R PEG_CLK_R 12 PEG_CLK#_R 12 DPLL_REF_SSCLK DPLL_REF_SSCLK# SM_RCOMP_0 R28 SM_RCOMP_1 R29 SM_RCOMP_2 R30 DPLL_REF_SSCLK 12 DPLL_REF_SSCLK# 12 SM_DRAMRST# SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 F6 SM_DRAMRST# 16 SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 AL1 AM1 AN1 PM_EXT_TS0# PM_EXT_TS1# AN15 AP15 PRDY# PREQ# AT28 AP27 XDP_PRDY# XDP_PREQ# TCK TMS TRST# AN28 AP28 AT27 XDP_TCLK XDP_TMS XDP_TRST# TDI TDO TDI_M TDO_M AT29 AR27 AR29 AP29 XDP_TDI XDP_TDO XDP_TDI_M XDP_TDO_M DBR# AN25 XDP_DBRESET# BPM0# BPM1# BPM2# BPM3# BPM4# BPM5# BPM6# BPM7# AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23 1D05V_VTT RN3 SRN10KJ-5-GP 2 D 100R2F-L1-GP-U 24D9R2F-L-GP 130R2F-1-GP PM_EXTTS#0_R 20 PM_EXTTS#1_R 21 TP4 Do Not Stuff DPLL_REF_SSCLK DPLL_REF_SSCLK# R32 R33 1Do Not Stuff2 1Do Not Stuff2 C R37 PLT_RST# PROCHOT# VCCPW RGOOD_1 Do Not Stuff 15,30,37,38,40,41,45,59 PECI R35 Do Not Stuff 51 H_VTTPW RGD BCLK_ITP BCLK_ITP# BCLK_CPU_P BCLK_CPU_N CATERR# PWR MANAGEMENT A16 B16 AR30 AT30 THERMAL AT15 16 H_PECI COMP2 MISC R25 BCLK BCLK# CLOCKS 49D9R2F-GP OF COMP3 AUBURNDALE H_CATERR# AT23 20R2F-GP DDR3 MISC R24 H_COMP3 JTAG & BPM R22 C 1K5R2F-2-GP R38 750R2F-GP AUBURNF,CLARKUNF 62.10055.321 2ND = 62.10053.561 3rd = 62.10055.341 4th = 62.10040.611 R39 PM_DRAM_PW RGD PM_DRAM_PW RGD_1 1K5R2F-2-GP S3 B B 1D5V_S0_DDR 1D5V_S0_DDR XDP_TMS XDP_PREQ# 3D3V_S0 DY Do Not Stuff XDP_DBRESET# R43 Do Not Stuff 1KR2J-1-GP XDP_TDO_M Do Not Stuff R49 Do Not Stuff R48 750R2F-GP XDP_TDI_M S3 NON-S3 DY R45 R47 Do Not Stuff DY R44 PM_DRAM_PW RGD DRAMPW ROK R42 XDP_TDI DY NON-S3 R41 Do Not Stuff R40 Do Not Stuff XDP_TCLK R50 DY 1 CPU JTAG 1D05V_VTT Do Not Stuff PreMp 0321 ECR: R1004944 3D3V_S5 R52 S3 1D05V_VTT U2 1D5V_S0_PW RGD_2 1KR2F-3-GP C46 SCD1U16V2ZY-2GP 1D5V_S0_PW RGD S3 A45,50 B S3 A GND VCC Y A Hynix 1G 800M N11PGV SKU RN77 PM_DRAM_PW RGD_1 74LVC1G08GW -1-GP 73.01G08.L04 2ND = 73.7SZ08.DAH XDP_TDO XDP_TRST# Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C SRN56J-4-GP Title CPU (2/7) Size A3 Date: Document Number Rev -1 JE43-CP W ednesday, November 24, 2010 Sheet of 69 4 CPU1_CPD B 20 20 20 20 20 20 M_A_BS0 M_A_BS1 M_A_BS2 AC3 AB2 U7 M_A_CAS# M_A_RAS# M_A_W E# AE1 AB3 AE9 SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 SA_BS0 SA_BS1 SA_BS2 SA_CAS# SA_RAS# SA_WE# 21 M_B_DQ[63 0] SA_CK0 SA_CK0# SA_CKE0 AA6 AA7 P7 SA_CK1 SA_CK1# SA_CKE1 Y6 Y5 P6 M_CLK_DDR1 20 M_CLK_DDR#1 20 M_CKE1 20 SA_CS0# SA_CS1# AE2 AE8 M_CS#0 20 M_CS#1 20 SA_ODT0 SA_ODT1 AD8 AF9 M_ODT0 20 M_ODT1 20 SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7 B9 D7 H7 M7 AG6 AM7 AN10 AN13 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 M_CLK_DDR0 20 M_CLK_DDR#0 20 M_CKE0 20 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7# C9 F8 J9 N9 AH7 AK9 AP11 AT13 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7 C8 F9 H9 M9 AH8 AK10 AN11 AR13 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15 Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 M_A_DM[7 0] 20 M_A_DQS#[7 0] 20 M_A_DQS[7 0] 20 M_A_A[15 0] 20 B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10 SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 21 21 21 M_B_BS0 M_B_BS1 M_B_BS2 AB1 W5 R7 SB_BS0 SB_BS1 SB_BS2 21 21 21 M_B_CAS# M_B_RAS# M_B_W E# AC5 Y7 AC6 SB_CAS# SB_RAS# SB_WE# DDR SYSTEM MEMORY - B C A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14 AUBURNDALE M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 D DDR SYSTEM MEMORY A 20 M_A_DQ[63 0] OF OF AUBURNDALE CPU1_CPC SB_CK0 SB_CK0# SB_CKE0 W8 W9 M3 M_CLK_DDR2 21 M_CLK_DDR#2 21 M_CKE2 21 SB_CK1 SB_CK1# SB_CKE1 V7 V6 M2 M_CLK_DDR3 21 M_CLK_DDR#3 21 M_CKE3 21 SB_CS0# SB_CS1# AB8 AD6 M_CS#2 21 M_CS#3 21 SB_ODT0 SB_ODT1 AC7 AD1 M_ODT2 21 M_ODT3 21 SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7 D4 E1 H3 K1 AH1 AL2 AR4 AT8 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7# D5 F4 J4 L4 AH2 AL4 AR5 AR8 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7 C5 E3 H4 M5 AG2 AL5 AP5 AR7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15 U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 D M_B_DM[7 0] 21 C M_B_DQS#[7 0] 21 M_B_DQS[7 0] 21 B M_B_A[15 0] 21 AUBURNF,CLARKUNF 62.10055.321 2ND = 62.10053.561 A AUBURNF,CLARKUNF 62.10055.321 2ND = 62.10053.561 3rd = 62.10055.341 4th = 62.10040.611 Hynix 1G 800M N11PGV SKU A Wistron Corporation 3rd = 62.10055.341 4th = 62.10040.611 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (3/7) Size A3 Date: Document Number Rev -1 JE43-CP W ednesday, November 24, 2010 Sheet of 69 CPU1_CPF A AUBURNDALE 1.1V RAIL POWER CPU VIDS 2 2 1 D 1 C73 2 DY +VTT_43 +VTT_44 1D05V_VTT R53 R54 Do Not Stuff Do Not Stuff 1 PSI# AN33 VID0 VID1 VID2 VID3 VID4 VID5 VID6 PROC_DPRSLPVR AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34 VTT_SELECT PSI# 47 H_VID[6 0] H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 47 B PM_DPRSLPVR 47 H_VTTVID1 G15 TP7 Do Not Stuff Clarksfield H_VTTVID1 = Low, VTT = 1.1V Arrandale H_VTTVID1 = High, VTT = 1.05V VCC_CORE AN35 VCC_SENSE VSS_SENSE AJ34 AJ35 R55 100R2F-L1-GP-U IMVP_IMON 47 ISENSE VCC_SENSE 47 VSS_SENSE 47 VTT_SENSE VSS_SENSE_VTT B15 A15 TP_VSS_SENSE_VTT R56 100R2F-L1-GP-U VTT_SENSE 51 TP8 Do Not Stuff 2 2 B C51 Please note that the VTT Rail Values are Auburndale VTT=1.05V; Clarksfield VTT=1.1V POWER 2 1 1 2 2 2 1 C79 SC10U6D3V3MX-GP C78 SC10U6D3V3MX-GP DY C77 Do Not Stuff SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP C76 C50 C C72 SC10U6D3V3MX-GP C75 AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15 C49 The decoupling capacitors, filter recommendations and sense resistors on the CPU/PCH Rails are specific to the CRB Implementation Customers need to follow the recommendations in the Calpella Platform Design Guide Do Not Stuff C74 20101117 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 C57 DY 1D05V_VTT CPU CORE SUPPLY 20101117 C71 SC10U6D3V3MX-GP 20101117 2 2 2 C70 SC10U6D3V3MX-GP Do Not Stuff SC10U6D3V3MX-GP DY C69 C65 SC10U6D3V3MX-GP C68 C64 SC10U6D3V3MX-GP C67 SC10U6D3V3MX-GP 20101117 SC10U6D3V3MX-GP SC10U6D3V3MX-GP DY C63 C55 SC10U6D3V3MX-GP C62 SC10U6D3V3MX-GP C66 C61 SC10U6D3V3MX-GP SC10U6D3V3MX-GP C C60 SC10U6D3V3MX-GP Do Not Stuff 20101117 C54 C48 SC10U6D3V3MX-GP C53 C56 SC10U6D3V3MX-GP C59 Do Not Stuff SC10U6D3V3MX-GP SC10U6D3V3MX-GP DY DY SC10U6D3V3MX-GP C58 C47 SC10U6D3V3MX-GP C52 AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 Do Not Stuff D 1D05V_VTT VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 SC10U6D3V3MX-GP 48A 20101117 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC OF Do Not Stuff VCC_CORE AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 SENSE LINES VCC_CORE PROCESSOR CORE POWER 2 A Hynix 1G 800M N11PGV SKU Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (4/7) AUBURNF,CLARKUNF Size Custom 62.10055.321 2ND = 62.10053.561 3rd = 62.10055.341 4th = 62.10040.611 Date: Document Number Rev -1 JE43-CP W ednesday, November 24, 2010 Sheet of 69 VCC_GFXCORE 1 1 PM_SLP_S3_CTL_D Q2 G 1D05V_VTT D S3 2N7002E-1-GP 1 Do Not Stuff 3G C 84.2N702.D31 2ND = 84.2N702.E31 C95 C106 1Do Not Stuff2 C105 R67 Do Not Stuff SC10U6D3V3MX-GP SC4D7U6D3V3KX-GP Do Not Stuff DY C104 DY C103 1D8V_S0 0.6A 2 +V1.8S_VCCSFR B C101 DY L26 L27 M26 2 2 SENSE LINES GRAPHICS VIDs 1 2 2 2 2 S3 Do Not Stuff VTT1 VTT1 VTT1 R66 220R2F-GP 1D05V_VTT 1.1V J22 J20 J18 H21 H20 H19 C100 1.8V VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 NON-S3 1D5V_S0_DDR C91 S 0123 -1 RF 2 1 2 - 1.5V RAILS 1 1 DDR3 2 2 1 C90 oringal reservation 10uF SC1U6D3V2KX-GP 3rd = 62.10055.341 4th = 62.10040.611 DY C89 13,20 PM_SLP_S3_CTL SC1U6D3V2KX-GP SC1U6D3V2KX-GP 62.10055.321 2ND = 62.10053.561 C88 VDDQ 3A for Auburndale VDDQ 6A for Clarksfield C102 AUBURNF,CLARKUNF C87 Do Not Stuff C99 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 C86 R60 Do Not Stuff C98 K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25 C85 NON-S3 VTT1 VTT1 VTT1 VTT1 P10 N10 L10 K10 DY C84 R59 NON-S3 DY Do Not Stuff SC10U6D3V3MX-GP SC10U6D3V3MX-GP Do Not Stuff DY C97 AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1 SC1U6D3V2KX-GP 18A C96 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ C94 PEG & DMI TC1 B C93 Do Not Stuff 1D05V_VTT SA 0626 DY VTT1 VTT1 VTT1 NON-S3 DIS FDI C92 J24 J23 H25 R61 Do Not Stuff R58 Do Not Stuff 1D05V_VTT SC10U6D3V3MX-GP Please note that the VTT Rail Values are Auburndale VTT=1.05V; Clarksfield VTT=1.1V R57 GFX_VR_EN 54 GFX_DPRSLPVR 54 GFX_IMON 54 SC10U6D3V3MX-GP DIS 54 SC10U6D3V3MX-GP DIS AR25 AT25 AM24 1D5V_S3 GFX_VID[6 0] SC10U6D3V3MX-GP DIS GFX_VR_EN GFX_DPRSLPVR GFX_IMON GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4 GFX_VID5 GFX_VID6 Do Not Stuff DIS AM22 AP22 AN22 AP23 AM23 AP24 AN24 SC1U6D3V2KX-GP R65 Do Not Stuff GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4 GFX_VID5 GFX_VID6 D VCC_AXG_SENSE 54 VSS_AXG_SENSE 54 SC1U6D3V2KX-GP R64 Do Not Stuff AR22 AT22 SC1U6D3V2KX-GP R63 Do Not Stuff VAXG_SENSE VSSAXG_SENSE Do Not Stuff R62 Do Not Stuff OF Do Not Stuff VCC_GFXCORE AUBURNDALE UMA_Muxless and DIS_3G UMA_Muxless and DIS_3G VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 GRAPHICS SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP UMA_Muxless and DIS_3G UMA_Muxless and DIS_3G 1 C83 C82 C81 C80 AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16 POWER D C CPU1_CPG 15A Hynix 1G 800M N11PGV SKU A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (5/7) Size A3 Date: Document Number Rev -1 JE43-CP W ednesday, November 24, 2010 Sheet of 69 CPU1_CPH OF 9 C B VSS AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30 K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS OF AUBURNDALE VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS D C VSS NCTF TEST PIN: A35,AT1,AT35,B1,A3,A33,A34,AP1,AP35, AR1,AR35,AT2,AT3,AT33,AT34,B35,C1,C35 D VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AUBURNDALE CPU1_CPI AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35 VSS_NCTF#AR34 VSS_NCTF#B34 VSS_NCTF#B2 AR34 B34 B2 VSS_NCTF#B1 VSS_NCTF#A35 VSS_NCTF#AT1 VSS_NCTF#AT35 RSVD_NCTF#AT33 RSVD_NCTF#AT34 RSVD_NCTF#AP35 RSVD_NCTF#AR35 RSVD_NCTF#AT3 RSVD_NCTF#AR1 RSVD_NCTF#AP1 RSVD_NCTF#AT2 RSVD_NCTF#C1 RSVD_NCTF#A3 RSVD_NCTF#C35 RSVD_NCTF#B35 RSVD_NCTF#A34 RSVD_NCTF#A33 B1 A35 AT1 AT35 AT33 AT34 AP35 AR35 AT3 AR1 AP1 AT2 C1 A3 C35 B35 A34 A33 TP_MCP_VSS_NCTF6 TP_MCP_VSS_NCTF1 TP_MCP_VSS_NCTF2 TP_MCP_VSS_NCTF7 1 1 TP9 TP10 TP11 TP12 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff B AUBURNF,CLARKUNF AUBURNF,CLARKUNF 62.10055.321 2ND = 62.10053.561 62.10055.321 2ND = 62.10053.561 3rd = 62.10055.341 4th = 62.10040.611 3rd = 62.10055.341 4th = 62.10040.611 A A Hynix 1G 800M N11PGV SKU Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (6/7) Size A3 Date: Document Number Rev -1 JE43-CP W ednesday, November 24, 2010 Sheet of 69 Processor Strapping CPU1_CPE OF D RN4 20 M_VREF_DQ_DIMM0 21 M_VREF_DQ_DIMM1 H_RSVD9_R H_RSVD10_R Do Not Stuff DY RSVD#AP25 RSVD#AL25 RSVD#AL24 RSVD#AL22 RSVD#AJ33 RSVD#AG9 RSVD#M27 RSVD#L28 SA_DIMM_VREF# SB_DIMM_VREF# RSVD#G25 RSVD#G17 RSVD#E31 RSVD#E30 AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 RSVD_TP#H16 AH25 AK26 RSVD#AL26 RSVD_NCTF#AR2 AL26 AR2 RSVD#AJ26 RSVD#AJ27 AJ26 AJ27 PCI-Express Configuration Select RSVD#AH25 RSVD#AK26 CFG0 DY R68 Do Not Stuff CFG0 CFG3 CFG3 - PCI-Express Static Lane Reversal R69 3KR2F-GP CFG3 R74 R75 Do Not Stuff Do Not Stuff TP15 TP16 Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff Do Not Stuff TP17 TP18 TP19 TP20 TP21 TP22 TP23 TP24 TP25 TP26 1Do Not Stuff2 1Do Not Stuff2 1 1 1 1 1 1 H_RSVD17_R H_RSVD18_R B19 A19 RSVD#B19 RSVD#A19 A20 B20 RSVD#A20 RSVD#B20 U9 T9 AC9 AB9 B J29 J28 AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 RSVD#AR32 AR32 RSVD_TP#E15 RSVD_TP#F15 KEY RSVD#D15 RSVD#C15 RSVD#AJ15 RSVD#AH15 E15 F15 A2 D15 C15 AJ15 AH15 RSVD_TP#AA5 RSVD_TP#AA4 RSVD_TP#R8 RSVD_TP#AD3 RSVD_TP#AD2 RSVD_TP#AA2 RSVD_TP#AA1 RSVD_TP#R9 RSVD_TP#AG7 RSVD_TP#AE3 AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 RSVD_TP#V4 RSVD_TP#V5 RSVD_TP#N2 RSVD_TP#AD5 RSVD_TP#AD7 RSVD_TP#W3 RSVD_TP#W2 RSVD_TP#N3 RSVD_TP#AE5 RSVD_TP#AD9 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 CFG4 CFG4 - Display Port Presence DY R70 Do Not Stuff CFG4 CFG7 RSVD64_R RSVD65_R R71 R72 1Do Not Stuff2 1Do Not Stuff2 DY RSVD#AC9 RSVD#AB9 RSVD#J29 RSVD#J28 C 1:Disabled; No Physical Display Port attached to Embedded Display Port (Default) 0:Enabled; An external Display Port device is connected to the Embedded Display Port CFG7(Reserved) - Temporarily used for early Clarksfield samples R73 Do Not Stuff CFG7 Clarksfield (only for early samples pre-ES1) Connect to GND with 3.01K Ohm/5% resistor Note: Only temporary for early CFD sample (rPGA/BGA) [For details please refer to the WW33 MoW and sighting report] For a common M/B design (for AUB and CFD), the pull-down resistor shouble be used Does not impact AUB functionality 1130 -SC RSVD#U9 RSVD#T9 :Normal Operation(Default) :Lane Numbers Reversed 15 -> 0, 14 -> 1, RSVD#AL28 RSVD#AL29 RSVD#AP30 RSVD#AP32 RSVD#AL27 RSVD#AT31 RSVD#AT32 RSVD#AP33 RSVD#AR33 C CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 1 TP13 TP14 RESERVED Do Not Stuff Do Not Stuff 1:Single PEG(Default) 0:Bifurcation enabled SA 0623 20101108 AJ13 AJ12 AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30 RSVD#AJ13 RSVD#AJ12 SO-DIMM VREFDQ (M3) Circuit for Clarksfield Processor AUBURNDALE D B VSS (AP34) can be left NC is CRB implementation; EDS/DG recommendation to GND R76 VSS AP34 RSVD_VSS Do Not Stuff AUBURNF,CLARKUNF 62.10055.321 2ND = 62.10053.561 3rd = 62.10055.341 4th = 62.10040.611 A Hynix 1G 800M N11PGV SKU A Wistron Corporation 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU (7/7) Size A3 Date: Document Number Rev -1 JE43-CP W ednesday, November 24, 2010 Sheet 10 of 69 20100717 DCBATOUT PWR_DCBATOUT_VGA_CORE G5501 SSID = PWR.Plane.Regulator_GFX N12P-GV and N11P-GV, PR6換 換換9.1K (part number: 64.91015.6DL) , MOSFET 請請TPCA8065-H +TPCA8062-Hx2 上上上上 20100813 Do Not Stuff G5502 D 20101121 Do Not Stuff G5503 2 1 DIS_Muxless DIS_Muxless DIS_Muxless DIS_Muxless PR8 0R2J-2-GP VGACORE_VDD_SENSE Do Not Stuff G5505 Do Not Stuff G5518 Do Not Stuff G5508 Do Not Stuff G5517 Do Not Stuff G5507 Do Not Stuff G5520 Do Not Stuff G5510 Do Not Stuff G5519 Do Not Stuff G5509 Do Not Stuff G5522 Do Not Stuff G5512 Do Not Stuff G5521 Do Not Stuff G5511 Do Not Stuff G5524 Do Not Stuff G5514 Do Not Stuff G5523 Do Not Stuff G5513 Do Not Stuff G5526 Do Not Stuff G5516 Do Not Stuff G5525 Do Not Stuff Do Not Stuff H 0.90V H L 0.95V H H DY PWR_VGA_CORE_EN_R# DIS_Muxless 20101020 Switching freq >350KHz Frequency setting 470K >165KHz 200K >323KHz 100K >500KHz 1GND_SENSE_1 DGPU_PWROK 16,56 PR18 0R2J-2-GP 8209A_EN/DEM_VGA DIS_Muxless VGACORE_GND_SENSE Do Not Stuff TP82 PR19 DIS_Muxless 10R2J-2-GP 33.2K=64.33225.6DL 43K=64.43025.6DL 75K=64.75025.6DL 100K=64.10035.6DL 150K=64.15035.6DL DIS_Muxless N12P_GS PWR_VGA_CORE_D1 PWR_VGA_CORE_D0 P-State VGA_CORE_PWR P8 , P12 L L 0.825V P0 - HOT L H 0.975V P0 - COLD H L 1.05V H H A N12P GS:PR11=10K,PR14=100K,PR13=49.9K,PR15=33.2K N12P GV: PR11=10K,PR14=75K,PR13=49.9K,PR15=43K N11P GV: PR11=10K,PR14=75K,PR13=150K,PR15=75K N12P_GV P-State PWR_VGA_CORE_D1 PWR_VGA_CORE_D0 P8 , P12 L P0 - HOT L P0 - COLD PQ9206_3 B 2 DIS_Muxless 2 DIS_Muxless DIS_Muxless PWR_VGA_CORE_D1 PC12 SC100P50V2JN-3GP PR17 Do Not Stuff DIS_Muxless PR12 DY Do Not Stuff PR15 33K2R2F-GP 201000806 8209A_PGOOD_VGA I/P cap: 10U 25V K1206 X5R/ 78.10622.52L Inductor: 1.5UH PCMC104T-1R5MN Cyntec DCR:4.2mohm Isat =33Arms 68.1R510.10J O/P cap: 330U 2V EEFSX0D331ER 9mOhm 3Arms Panasonic/ 79.33719.L01 H/S: SI7686DP/ POWERPAK-8/11mOhm/14mOhm@4.5Vgs/ 84.07686.037 L/S: SiR460DP/ POWERPAK-8/ 4.9mOhm/6.1mohm@4.5Vgs/ 84.00460.037 PWR_VGA_CORE_D0 DIS_Muxless PR14 100KR2F-L1-GP PR13 49K9R2F-L-GP PR16 10KR2J-3-GP DY R4 R2 R3 3D3V_VGA_S0 B VGA_CORE PQ1 Do Not Stuff PWR_VGA_CORE_FB L P0 - COLD DY P0 - HOT R1 0.85V L L A Hynix 1G 800M N11PGV SKU Wistron Corporation VGA_CORE_PWR 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 0.85V H 1.00V H L 1.02V H H Title RT8208B_+VGA_CORE Size Custom Date: C VGA_CORE_PWR L PWR_VGA_CORE_D1 PWR_VGA_CORE_D0 P8 , P12 P-State N11P-GV 8209A_EN/DEM_VGA PC11 SCD1U10V2KX-4GP DIS_Muxless VGA_CORE DYPR10 Do Not Stuff PC10 Do Not Stuff DIS_Muxless DY 1 13,40,45,50,51,52,54 PM_SLP_S3# 1 PC9 PR11 10KR2F-2-GP DIS_Muxless PD1 Do Not Stuff 1KR2J-1-GP 3D3V_AUX_S5 DIS_Muxless Do Not Stuff DIS_Muxless PR9 SE330U2VDM-L-GP 1 PTC4 2 DIS_Muxless PTC3 DIS_Muxless RT8208A:74.08208.073 Do Not Stuff PWR_VGA_CORE_VOUT PTC2 SE330U2VDM-L-GP DIS_Muxless SE330U2VDM-L-GP 20101123 DIS_Muxless PU5 PC8 SCD1U10V2KX-4GP RT8208AGQW-GP DIS_Muxless PWR_VGA_CORE_VOUT PU3 63 1 PWRCNTL_1 84.07686.A37 Design Current = 21.94A CYNTEC,11.5*10*4 24.14A