Acer nitro AN515 34 FH500 FH50Q LA j621p r1 0

A B C D E 1 Compal Confidential FH50Q MB Schematics Document 2 AMD Picasso Platform nVidia N17P-G1 & N18P-G0 LA-J621P REV:1.0 3 2019-11-26 4 Issued Date A B Compal Electronics, Inc Compal Secret Data Security Classification 2019/07/24 Deciphered Date 2020/07/24 Title COVER PAGE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Custom Shared with Compal Date: C D Rev 1.0 FH50Q M/B LA-J621P Monday, November 25, 2019 Sheet E of 100 A B C D E Compal Confidential Model Name : FH50Q (Channel A) GDDR5 x4 128-bits Memory GPU N18P-G0 or N17P-G1 page 35~36 PEG x8 BUS(DDR4) AMD Port Port Type-C Conn HDMI Conn page 38 260pin DDRIV SO-DIMM Port Port Port Port Picasso Port eDP Conn page 24 USB2.0 Port Port (Channel B) 1.2V DDRIV 2400Mhz page 27~33 Display page 23 260pin DDRIV SO-DIMM Type-A (CHG) Conn Type-A Conn WLAN/BT NGFF Conn Camera Type-A (SUB) page 38 page 52 page 73 page 40 page 42~43 page 71 page 72 2 USB3.0 Port Port Port AMD FP5 APU BGA 1140-balls PCIE Port Port 0, 1, 2, SSD1 page 68~70 NGFF Conn Port LAN RTL8118ASA page 6~12 WLAN/BT NGFF Conn page 51 HD Audio page 52 SATA III SPI Transformer RJ45page 51 Audio ALC255 I2C LPC page 56 3 page 10 BIOS (8M, 1.8V) ENE KBC9022 page 38 page 58 Port PS2 Port HDD Conn PTP page 63 page 63 Int.KBD Port SSD2 page 68 NGFF Conn page 67 page 73 Int DMIC on Camera Int Speaker Conn page 56 UAJ on Sub/B Fan Control page 77 RTC CKT page 11 Power On/Off CKT page 63 4 DC/DC Interface CKT page 78 Power Circuit DC/DC page 82~97 VRAM Config Table page 29 Sub Board LS-J621P IO/B page 73 Issued Date LS-H502 Hall Sensor/B Compal Electronics, Inc Compal Secret Data Security Classification 2019/07/24 Deciphered Date 2020/07/24 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC page 66 Title BLOCK DIAGRAMS Size Document Number Custom A B C D R ev 1.0 FH50Q M/B LA-J621P Date: Monday, November 25, 2019 Sheet E of 100 A B Voltage Rails Description Power Plane S0 S3 S5 +19V_VIN Adapter power supply (19V) ON ON ON +19VB AC or battery power rail for power circuit ON ON ON +APU_CORE Core voltage for APU ON OFF OFF +APU_CORE_SOC Core voltage for APU ON OFF OFF +1.8VALW 1.8V always on power rail ON ON OFF +1.8VS 1.8V switched power rail ON OFF OFF +2.5V 2.5V power rail for APU and DDR ON ON OFF +1.2V 1.2V power rail for APU and DDR ON ON OFF +0.6VS 0.6V switched power rail for DDR terminator ON OFF OFF +3VALW 3.3V always on power rail ON ON OFF +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON +5VS 5V switched power rail ON OFF OFF +0.9VALW 0.9V always on power rail ON ON ON +0.9VS 0.9V switched power rail ON OFF OFF +RTC_APU RTC power ON ON ON +3V_LAN 3.3V LAN IC power ON ON OFF +TP_VCC 3.3V Touch Pad power ON ON OFF +FP_VCC 3.3V Finger Print power ON ON OFF +3VSDGPU VGA power ON OFF OFF +1.8VSDGPU_AON VGA power ON OFF OFF +1.8VSDGPU_MAIN VGA power ON OFF +1.35VSDGPU VGA power ON OFF OFF +1.0VSDGPU VGA power ON OFF OFF +NVVDD1 VGA power ON OFF OFF OFF C D Board ID / SKU ID Table for AD channel BOARD ID Table Board ID E PCB Revision EVT PVT BOM Structure Table BOM Structure @ EMC@/@EMC@ 45@ CONN@ JP@ RS@ TP@ LDO@/SWR@ R5/R7APUQC@ R5/R7APU@ TMS@ TMSIEC@ EVT@/PVT@/MP@ KBLED@/LED14P@ BTO Item Unpop EMI/ESD Pop/Unpop HDMI Royalty Mechanical Connector Jump R-Short Test Point RTL8118ASA Switching-Mode only APU PN Refer p.6 APU PN Refer p.6 Thermal Sensor POWER SEQUENCE Thermal Sensor for IEC safety Test BOM for EVT/PVT/MP +RTCBATT G-A Keyboard back light / RGB back light EC_ON +5VALW 3V_EN +3VALW G-B 0.9_1.8VALW_PWREN N17P@ N18P@ DIS@ VRAM4G@ N17P-G1 +1.8VALW/+0.9VALW N18P-G0 VGA Circuits SYSON GDDR5*4 G-C +1.2V/+2.5V SUSP# +5VS/+3VS/+1.8VS/+0.6VS GC6@/NGC6@ ON_X76@ uPI_X76@ APU SMBus/I2C Address Table Master Device Address[7:1] nVidia DGPU GC6 2.0 0.9VS_PWR_EN# OVRM-ON +0.9VS OVRM-uPI* VR_ON Address [7:0] Write +APU_CORE Read I2C Port (+1.8VS) G-D +APU_CORE_SOC EC SMBus Address Table I2C Port (+1.8VS) SMBus Port (+3VALW) I2C Port (+3VS) SBMus Port (+3VS) I2C Port (+3VALW) JDIMM1 0101 0000b 50h 1010 0000b A0h 1010 0001b A1h JDIMM2 0101 0001b 51h 1010 0010b A2h 1010 0011b A3h PTP (Synaptics) 0010 1100b 2Ch 0101 1000b 58h 0101 1001b 59h PTP (ELAN) 0001 1111b 15h 0011 1110b 3Eh 0011 1111b 3Fh SMBus Port (+3VALW) SMBus Port (+3VS) SMBus Port (+3VALW) 0000 1011b Smart Battery 0Bh 0001 0110b 16h 0001 0111b 17h Charger IC (BQ24735) 0000 1001b 09h 0001 0010b 12h 0001 0011b 13h APU Temp (TSI) 0100 1100b 4Ch 1001 1000b 98h 1001 1001b 99h GPU Temp 1001 1110b 9Eh Thermal Sensor G781-1 1001 1010b 9Ah 1001 1011b 9Bh Thermal Sensor IEC 62368-1 1001 0000b 90h 1001 0001b 91h LED driver 1100 0000b C0h 1100 0001b C1h Compal Electronics, Inc Compal Secret Data Security Classification Issued Date 2019/07/24 Deciphered Date 2020/07/24 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title NOTES LIST Size Document Number Custom Date: A B C D R ev 1.0 FH50Q M/B LA-J621P Monday, November 25, 2019 Sheet E of 100 PJP101 AC-IN APU Power Rail 24810mA +APU_CORE 70000mA +APU_CORE_SOC 13000mA +APU_CORE +19V_VIN +19VB 5243mA PU301 PU801 +APU_CORE_SOC VDDCR_VDD @0.65-TBD VDDCR_SOC @0.72-TBD Group C, S0 domain +17.4V_BATT D D 250mA PJP201 DC-IN +3VS VDD_33 @0.25A 2000mA +1.8VS VDD_18 @2.0A Group B, S0 domain 4000mA 4000mA +0.9VS +0.9VS VDDP @4.0A U4 +1.2V 9500mA 6000mA +1.2V +0.6VS 1200mA 250mA +3VALW 638mA PU501 VDDIO_MEM_S3 VDD_33_S5 2026mA To VGA 1013mA +1.8VALW PU602 +1.8VALW 200mA +1.8VS 1000mA +0.9VALW VDD_18_S5 @0.5A 2660mA +1.8VS 2200mA 5000mA +0.9VALW 237mA 500mA @6.0A @0.25A Group B, S3 domain VDDIO_AUDIO UG27 @0.2A VDDP_S5 @1.0A PU601 +RTCVCC +RTC_APU_R 0.045mA +RTC_APU_R VDDBT_RTC_G UC8 JRTC1 DDR4 528mA 528mA +2.5V SO-DIMM1/SO-DIMM2 +2.5V +2.5V PU502 C Group A, S5 domain @0.045mA 4160mA C +1.2V +1.2V 1500mA +0.6VS +0.6VS 280mA SATA Redriver*2 (M.2 & HDD) 2790mA +3VS_SSD1 300mA +3V_LAN M.2 PCIE SSD 2311mA 13347mA +3VALW PU401 UL1 RL2 LAN RTL8118ASA +3VLP 30mA +TP_VCC 1500mA +3VS_WLAN U13 KB9022 RM101 Touch Pad WLAN UM3 1500mA +LCDVDD UX1 Panel Logic 10mA To VGA M.2 SATA SSD 200mA GPU Power Rail (N17P-G1/N18P-G0) +1.2V_HDMI U1302 B HDMI Retimer B 110000mA +19VB 8330mA +3VS 14700mA +5VALW 4200mA U3 200mA +5VS_BL 250mA +5VALW_MUX 3000mA +USB3_VCCC 2000mA +USB3_VCCA 2000mA +USB3_VCCB U2616 NVVDD @110A KB Light +5VS US14 US11 US12 Type C RTS5441E USB3.0(Charger) US13 1900mA +3VALW +1.8VSDGPU_AON UG27 PEX_HVDD @2A +5VS_HDD RO4 HDD 1000mA +VCC_FAN1 +VCC_FAN2 1500mA +5VS_PVDD +1.8VALW +1.8VSDGPU_MAIN UV45 FAN1/FAN2 LA1 15000mA +1.35VSDGPU +19VB PUW1 100mA A 5160mA +1.35VSDGPU +FP_VCC UK6 VRAM x4pcs Finger Print 100mA +TS_PWR RX17 Touch Screen +3VSDGPU OVRM +INVPWR_B+ Panel BackLight Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2019/07/24 Deciphered Date 2020/07/24 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title POWER MAP Size Document Number Custom Rev 1.0 FH50Q M/B LA-J621P Date: FBVDDQ @15A Audio A LX1 @1.9A U2 +1.8VALW USB/B RF4/RF7 PEX_DVDD +3VS 2500mA 1500mA +1.0VSDGPU PU1002 USB3.0 JIO2 2000mA +NVVDD1 PUV1 Camera +3VS_SSD1 PU401 +3VS_CAM RX18 U2 3869mA 200mA Monday, November 25, 2019 Sheet of 100 AMD Picasso Platform Power Sequence AC-IN S0 > S3 G3 > S0 S3 > S0 S0 > S5 +3VLP +3VLP D ACIN 1.88ms EC_ON 236.1us +5VALW ON/OFFBTN# 3V_EN ACIN EC_ON 197.4ms ON/OFFBTN# 233.5us 88.57ms +3VALW 0.9_1.8VALW_PWREN +1.8VALW +0.9VALW D +5VALW 1.855ms, Tr = 452.2us 3V_EN 8.598s 588us, Tr = 761us +3VALW 4.491ms, Tf = 4.266ms 0.9_1.8VALW_PWREN 9.27ms 88.7ms 302us, Tr = 293us +1.8VALW 3.955ms, Tf = 3.752ms 696us, Tr = 453us +0.9VALW 4.095ms, Tf = 3.908ms 197.8ms PBTN_OUT# EC_RSMRST# 98.6ms 114.4ms SLP_S5# 178us SLP_S3# 178us SYSON 8.598s PBTN_OUT# 8.598s EC_RSMRST# SLP_S5# SLP_S3# 119ms SYSON 64.4ms +1.2V 562us, Tr = 169.6us 37.32ms, Tf = 36.98ms +2.5V 1.291ms, Tr = 1.468ms 12.14ms, Tf = 11.83ms SUSP# C 6.798ms 19.76ms +2.5V SUSP# 51.69ms 14.6ms 56ms +1.2V +5VS 350.5us, Tr = 512.4us 13.05ms Tf = 12.81ms 361.5us, Tr = 535.9us 13.68ms, Tf = 13.42ms +5VS +3VS 363.2us, Tr = 492.6us 10.19ms, Tf = 9.948ms 364us, Tr = 481.6us 9.84ms, Tf = 9.577ms +3VS C +1.8VS 1.582ms, Tr = 1.783ms 10.92ms, Tf = 10.63ms 1.605ms, Tr = 1.786ms 11.85ms, Tf = 11.61ms +1.8VS +0.6VS 1.59us, Tr = 17.02us 6.46ms, Tf = 6.148ms 4.9us, Tr = 13.75us 999.5us, Tf = 908.5us +0.6VS KBRST# 22.58ms 0.9VS_PWR_EN# +0.9VS 42.56ms 53.77ms 249.3us, Tr = 105.3us VR_ON 20.98ms 53.72ms 40.48ms 2.299ms, Tf = 2.254ms 19.32ms 83.36ms 59.66ms KBRST# 59.74ms 0.9VS_PWR_EN# 245.5us, Tr = 102us 2.033ms, Tf = 1.993ms 19.31ms 89.04ms +0.9VS VR_ON +APU_CORE 2.269ms, Tr = 320.4us 397.6us, Tf = 354us 2.267ms, Tr = 368us 394.8us, Tf = 342us +APU_CORE +APU_CORE_SOC 2.266ms, Tr = 333.1us 398.5us, Tf = 352us 2.256ms, Tr = 336.1us 396.8us, Tf = 350us +APU_CORE_NB VGATE 16.51ms 2.626ms SYS_PWRGD_EC 38.59ms 27.45ms APU_PWROK 17.75ms LPC_RST# 13.15ms VGATE 17.19ms 2.624ms 39.45ms 17.81ms 1.31ms 4.83ms SYS_PWRGD_EC 28.47ms APU_PWROK 1.32ms 13.31ms 4.832ms LPC_RST# 5.184ms APU_PCIE_RST# 10ms APU_PCIE_RST# B 15.42ms 600ms APU_RST# 4.921ms 9.1ms 15.35ms VGA Sequence PE_GPIO1(DGPU_PWR_EN) B APU_RST# 8.99ms 4.92ms VGA Sequence 267ms 443.7ms +1.8VSDGPU_AON 136.4us, Tr = 135.6us 1.8VSDGPU_MAIN_EN +1.8VSDGPU_MAIN +NVVDD1 42us, Tr = 426.3us 1VSDGPU_EN 3.638ms +1.0VSDGPU +1.35VSDGPU 155.3us, Tr = 96.61us PE_GPIO0(DGPU_HOLD_RST#) 10ms 171.2ms PLTRST_VGA#_1V8 1us, Tr = 553.4us 9.956us 3.255ms 2.846ms, Tf = 2.727ms 87.5us, Tr = 91.72us 4.3ms, Tf = 3.816ms 10ms 115.3ms 1VSDGPU_EN +1.0VSDGPU 1.35VSDGPU_EN 7.935us 3.266ms 1.121ms +NVVDD1 1us 3.653ms 2.704ms, Tf = 2.544ms 1us, Tr = 555.2us 1.35VSDGPU_EN NVVDD1_EN 3.679ms, Tf = 5.334ms 6.173ms, Tr = 84.5us 1us +1.8VSDGPU_MAIN 36.76ms, Tf = 40.89ms 4.976ms 1.762ms 3.568ms, Tf = 5.214ms +1.8VSDGPU_AON 1.8VSDGPU_MAIN_EN 32.46ms 882.4us, Tr = 512.3us 5.13ms 1.659ms 33.17us, Tf = 9.152ms 136.3us 38.66ms, Tf = 42.75ms 874.8us, Tr = 519.6us NVVDD1_EN 136.7ms, Tr = 136.2us 32.88ms 139.2u PE_GPIO1(DGPU_PWR_EN) 1.89s 202.1ms 33.17us, Tf = 9.152ms +1.35VSDGPU 4.376ms, Tf = 3.927ms PE_GPIO0(DGPU_HOLD_RST#) 1.21ms PLTRST_VGA#_1V8 1us 1us A A Compal Electronics, Inc Compal Secret Data Security Classification 2019/07/24 Issued Date Deciphered Date 2020/07/24 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title POWER SEQUENCE Size Document Custom Rev 1.0 FH50Q M/B LA-J621P Date: Number Monday, November 25, 2019 Sheet of 100 Main Func = CPU UC1B PEG PEG PCIE D D 27 27 PEG_ARX_C_GTX_P0 PEG_ARX_C_GTX_N0 27 27 PEG_ARX_C_GTX_P1 PEG_ARX_C_GTX_N1 27 27 27 27 PEG_ARX_C_GTX_P2 PEG_ARX_C_GTX_N2 PEG_ARX_C_GTX_P3 PEG_ARX_C_GTX_N3 27 27 PEG_ARX_C_GTX_P4 PEG_ARX_C_GTX_N4 27 27 PEG_ARX_C_GTX_P5 PEG_ARX_C_GTX_N5 27 27 27 27 PEG_ARX_C_GTX_P6 PEG_ARX_C_GTX_N6 PEG_ARX_C_GTX_P7 PEG_ARX_C_GTX_N7 PEG_ARX_C_GTX_P0 PEG_ARX_C_GTX_N0 CC401 DIS@ CC402 DIS@ 0.22U_0201_6.3V6K PEG_ARX_GTX_P0 0.22U_0201_6.3V6K PEG_ARX_GTX_N0 P8 P9 P_GFX_RXP0 P_GFX_TXP0 P_GFX_RXN0 P_GFX_TXN0 PEG_ARX_C_GTX_P1 PEG_ARX_C_GTX_N1 CC403 DIS@ CC404 DIS@ 0.22U_0201_6.3V6K PEG_ARX_GTX_P1 0.22U_0201_6.3V6K PEG_ARX_GTX_N1 N6 N7 P_GFX_RXP1 P_GFX_TXP1 P_GFX_RXN1 P_GFX_TXN1 PEG_ARX_C_GTX_P2 PEG_ARX_C_GTX_N2 CC405 DIS@ CC406 DIS@ 0.22U_0201_6.3V6K PEG_ARX_GTX_P2 0.22U_0201_6.3V6K PEG_ARX_GTX_N2 M8 M9 P_GFX_RXP2 P_GFX_TXP2 P_GFX_RXN2 P_GFX_TXN2 PEG_ARX_C_GTX_P3 PEG_ARX_C_GTX_N3 CC407 DIS@ CC408 DIS@ 0.22U_0201_6.3V6K PEG_ARX_GTX_P3 0.22U_0201_6.3V6K PEG_ARX_GTX_N3 L6 L7 P_GFX_RXP3 P_GFX_TXP3 P_GFX_RXN3 P_GFX_TXN3 PEG_ARX_C_GTX_P4 PEG_ARX_C_GTX_N4 CC409 DIS@ CC410 DIS@ 0.22U_0201_6.3V6K PEG_ARX_GTX_P4 0.22U_0201_6.3V6K PEG_ARX_GTX_N4 K11 J11 P_GFX_RXP4 P_GFX_TXP4 P_GFX_RXN4 P_GFX_TXN4 PEG_ARX_C_GTX_P5 PEG_ARX_C_GTX_N5 CC411 DIS@ CC412 DIS@ 0.22U_0201_6.3V6K PEG_ARX_GTX_P5 0.22U_0201_6.3V6K PEG_ARX_GTX_N5 H6 H7 P_GFX_RXP5 P_GFX_TXP5 P_GFX_RXN5 P_GFX_TXN5 PEG_ARX_C_GTX_P6 PEG_ARX_C_GTX_N6 CC413 DIS@ CC414 DIS@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_ARX_GTX_P6 PEG_ARX_GTX_N6 G6 F7 PEG_ARX_C_GTX_P7 PEG_ARX_C_GTX_N7 CC415 DIS@ CC416 DIS@ 0.22U_0201_6.3V6K PEG_ARX_GTX_P7 0.22U_0201_6.3V6K PEG_ARX_GTX_N7 G8 F8 P_GFX_RXP7 P_GFX_TXP7 P_GFX_RXN7 P_GFX_TXN7 PCIE_ARX_DTX_P0 PCIE_ARX_DTX_N0 N10 N9 P_GPP_RXP0 P_GPP_TXP0 P_GPP_RXN0 P_GPP_TXN0 PCIE_ARX_DTX_P1 PCIE_ARX_DTX_N1 L10 L9 P_GPP_RXP1 P_GPP_TXP1 P_GPP_RXN1 P_GPP_TXN1 PCIE_ARX_DTX_P2 PCIE_ARX_DTX_N2 L12 M11 P_GPP_RXP2 P_GPP_TXP2 P_GPP_RXN2 P_GPP_TXN2 PCIE_ARX_DTX_P3 PCIE_ARX_DTX_N3 P12 P11 P_GPP_RXP3 P_GPP_TXP3 P_GPP_RXN3 P_GPP_TXN3 PCIE_ARX_DTX_P4 PCIE_ARX_DTX_N4 V6 V7 P_GPP_RXP4 P_GPP_TXP4 P_GPP_RXN4 P_GPP_TXN4 PCIE_ARX_DTX_P5 PCIE_ARX_DTX_N5 T8 T9 P_GPP_RXP5 P_GPP_TXP5 SATA_ARX_DTX_P0 SATA_ARX_DTX_N0 R6 R7 P_GPP_RXP6/SATA_RXP0 P_GPP_TXP6/SATA_TXP0 P_GPP_RXN6/SATA_RXN0 P_GPP_TXN6/SATA_TXN0 SATA_ARX_DTX_P1 SATA_ARX_DTX_N1 R9 R10 P_GPP_RXP7/SATA_RXP1 P_GPP_TXP7/SATA_TXP1 68 68 C M.2 SSD1 LAN PCIE_ARX_DTX_P0 PCIE_ARX_DTX_N0 68 68 PCIE_ARX_DTX_P1 PCIE_ARX_DTX_N1 68 68 PCIE_ARX_DTX_P2 PCIE_ARX_DTX_N2 68 68 PCIE_ARX_DTX_P3 PCIE_ARX_DTX_N3 51 51 PCIE_ARX_DTX_P4 PCIE_ARX_DTX_N4 WLAN 52 52 PCIE_ARX_DTX_P5 PCIE_ARX_DTX_N5 HDD 67 67 SATA_ARX_DTX_P0 SATA_ARX_DTX_N0 M.2 SSD2 69 69 SATA_ARX_DTX_P1 SATA_ARX_DTX_N1 N1 N3 PEG_ATX_GRX_P0 PEG_ATX_GRX_N0 CC417 DIS@ CC418 DIS@ 0.22U_0201_6.3V6K PEG_ATX_C_GRX_P0 0.22U_0201_6.3V6K PEG_ATX_C_GRX_N0 M2 M4 PEG_ATX_GRX_P1 PEG_ATX_GRX_N1 CC419 DIS@ CC420 DIS@ 0.22U_0201_6.3V6K PEG_ATX_C_GRX_P1 0.22U_0201_6.3V6K PEG_ATX_C_GRX_N1 L2 L4 PEG_ATX_GRX_P2 PEG_ATX_GRX_N2 CC422 DIS@ CC421 DIS@ 0.22U_0201_6.3V6K PEG_ATX_C_GRX_P2 0.22U_0201_6.3V6K PEG_ATX_C_GRX_N2 L1 L3 PEG_ATX_GRX_P3 PEG_ATX_GRX_N3 CC423 DIS@ CC424 DIS@ 0.22U_0201_6.3V6K PEG_ATX_C_GRX_P3 0.22U_0201_6.3V6K PEG_ATX_C_GRX_N3 K2 K4 PEG_ATX_GRX_P4 PEG_ATX_GRX_N4 CC425 DIS@ CC426 DIS@ 0.22U_0201_6.3V6K PEG_ATX_C_GRX_P4 0.22U_0201_6.3V6K PEG_ATX_C_GRX_N4 J2 J4 PEG_ATX_GRX_P5 PEG_ATX_GRX_N5 CC427 DIS@ CC428 DIS@ 0.22U_0201_6.3V6K PEG_ATX_C_GRX_P5 0.22U_0201_6.3V6K PEG_ATX_C_GRX_N5 H1 H3 PEG_ATX_GRX_P6 PEG_ATX_GRX_N6 CC429 DIS@ CC430 DIS@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_ATX_C_GRX_P6 PEG_ATX_C_GRX_N6 H2 H4 PEG_ATX_GRX_P7 PEG_ATX_GRX_N7 CC431 DIS@ CC432 DIS@ 0.22U_0201_6.3V6K PEG_ATX_C_GRX_P7 0.22U_0201_6.3V6K PEG_ATX_C_GRX_N7 N2 P3 PCIE_ATX_DRX_P0 PCIE_ATX_DRX_N0 CC1204 CC1203 0.22U_0402_16V7K 0.22U_0402_16V7K P4 P2 PCIE_ATX_DRX_P1 PCIE_ATX_DRX_N1 CC1206 CC1205 0.22U_0402_16V7K 0.22U_0402_16V7K R3 R1 PCIE_ATX_DRX_P2 PCIE_ATX_DRX_N2 CC1212 CC1211 0.22U_0402_16V7K 0.22U_0402_16V7K T4 T2 PCIE_ATX_DRX_P3 PCIE_ATX_DRX_N3 CC1214 CC1213 0.22U_0402_16V7K 0.22U_0402_16V7K W2 W4 PCIE_ATX_DRX_P4 PCIE_ATX_DRX_N4 CC1 CC2 1 1U_0402_16V7K 1U_0402_16V7K W3 V2 PCIE_ATX_DRX_P5 PCIE_ATX_DRX_N5 CC3 CC4 1 1U_0402_16V7K 1U_0402_16V7K V1 V3 SATA_ATX_DRX_P0 SATA_ATX_DRX_N0 U2 P_GPP_TXN7/SATA_TXN1 U4 SATA_ATX_DRX_P1 SATA_ATX_DRX_N1 P_GFX_RXP6 P_GFX_TXP6 P_GFX_RXN6 P_GFX_TXN6 P_GPP_RXN5 P_GPP_TXN5 P_GPP_RXN7/SATA_RXN1 PEG_ATX_C_GRX_P0 PEG_ATX_C_GRX_N0 27 27 PEG_ATX_C_GRX_P1 PEG_ATX_C_GRX_N1 27 27 PEG_ATX_C_GRX_P2 PEG_ATX_C_GRX_N2 27 27 PEG_ATX_C_GRX_P3 PEG_ATX_C_GRX_N3 27 27 PEG_ATX_C_GRX_P4 PEG_ATX_C_GRX_N4 27 27 PEG_ATX_C_GRX_P5 PEG_ATX_C_GRX_N5 27 27 PEG_ATX_C_GRX_P6 PEG_ATX_C_GRX_N6 27 27 PEG_ATX_C_GRX_P7 PEG_ATX_C_GRX_N7 27 27 PCIE_ATX_C_DRX_P0 PCIE_ATX_C_DRX_N0 68 68 PCIE_ATX_C_DRX_P1 PCIE_ATX_C_DRX_N1 68 68 PCIE_ATX_C_DRX_P2 PCIE_ATX_C_DRX_N2 68 68 PCIE_ATX_C_DRX_P3 PCIE_ATX_C_DRX_N3 68 68 PCIE_ATX_C_DRX_P4 PCIE_ATX_C_DRX_N4 51 51 LAN PCIE_ATX_C_DRX_P5 PCIE_ATX_C_DRX_N5 52 52 WLAN C M.2 SSD1 SATA_ATX_DRX_P0 67 SATA_ATX_DRX_N0 67 HDD SATA_ATX_DRX_P1 69 SATA_ATX_DRX_N1 69 M.2 SSD2 FP5 REV 0.90 PART OF 13 B FP5_BGA_1140P @ B APU PN Table APU Platform Customer PN UC1 R5APUQC@ Customer PN UC1 Customer PN R7APUQC@ UC1 Customer PN R5APU@ UC1 Compal PN Compal PN R7APU@ Picasso S IC RYZEN5 YM3500C4T4MFG 2.1G BGA APU S IC RYZEN7 YM3700C4T4MFG 2.3G BGA APU S IC RYZEN5 YM3500C4T4MFG 2.1G APU ABO! S IC RYZEN7 YM3700C4T4MFG 2.3G APU ABO! SA0000CCR20 SA0000C7640 SA0000CCR60 SA0000C7680 PCB Number A A ZZZ EVT@ PCB 2W M LA-J621P REV0 MB DA8001LZ000 ZZZ1 PVT@ PCB FH50Q LA-J621P LS-J621P/H502P DAZ2W M00100 2019/07/24 Issued Date ZZZ2 MP@ PCB FH50Q LA-J621P LS-J621P/H502P DAZ2W M00100 Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2020/07/24 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title FP5_(1/7)_PEG/PCIE/SATA Size Document Number Custom Rev 1.0 FH50Q M/B LA-J621P Date: Monday, November 25, 2019 Sheet of 100 Main Func = CPU UC1A 23 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14_WE# DDR_A_MA15_CAS# DDR_A_MA16_RAS# D 23 23 23 UC1I MEMORY A DDR_A_MA[13 0] DDR_A_MA14_WE# DDR_A_MA15_CAS# DDR_A_MA16_RAS# AF25 AE23 AD27 AE21 AC24 AC26 AD21 AC27 AD22 AC21 AF22 AA24 AC23 AJ25 AG27 AG23 AG26 DDR_A_DQ[63 0] MA_ADD0 MA_ADD1 MA_DATA0 MA_ADD2 MA_DATA1 MA_ADD3 MA_DATA2 MA_ADD4 MA_DATA3 MA_ADD5 MA_DATA4 MA_ADD6 MA_DATA5 MA_ADD7 MA_DATA6 MA_ADD8 MA_DATA7 MA_ADD9 MA_ADD10 MA_DATA8 MA_ADD11 MA_DATA9 MA_ADD12 MA_DATA10 MA_ADD13_BANK2 MA_DATA11 MA_WE_L_ADD14 MA_DATA12 MA_CAS_L_ADD15 MA_DATA13 MA_RAS_L_ADD16 MA_DATA14 MA_DATA15 23 23 DDR_A_BA0 DDR_A_BA1 DDR_A_BA0 DDR_A_BA1 23 23 DDR_A_BG0 DDR_A_BG1 23 DDR_A_ACT# 23 DDR_A_DM[7 0] C 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 23 MA_DATA16 MA_BANK1 MA_DATA17 MA_DATA18 AA21 AA27 MA_BG0 MA_DATA19 MA_BG1 MA_DATA20 DDR_A_ACT# AA22 MA_ACT_L DDR_A_DQS0 DDR_A_DQS0# DDR_A_DQS1 DDR_A_DQS1# DDR_A_DQS2 DDR_A_DQS2# DDR_A_DQS3 DDR_A_DQS3# DDR_A_DQS4 DDR_A_DQS4# DDR_A_DQS5 DDR_A_DQS5# DDR_A_DQS6 DDR_A_DQS6# DDR_A_DQS7 DDR_A_DQS7# DDR_A_CLK0 DDR_A_CLK0# DDR_A_CLK1 DDR_A_CLK1# DDR_A_CLK0 DDR_A_CLK0# DDR_A_CLK1 DDR_A_CLK1# MA_BANK0 DDR_A_BG0 DDR_A_BG1 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 DDR_A_DQS0 DDR_A_DQS0# DDR_A_DQS1 DDR_A_DQS1# DDR_A_DQS2 DDR_A_DQS2# DDR_A_DQS3 DDR_A_DQS3# DDR_A_DQS4 DDR_A_DQS4# DDR_A_DQS5 DDR_A_DQS5# DDR_A_DQS6 DDR_A_DQS6# DDR_A_DQS7 DDR_A_DQS7# AF21 AF27 MA_DATA21 MA_DATA22 MA_DATA23 F21 G27 N24 N23 AL24 AN27 AW25 AT21 T27 F22 G22 H27 H26 N27 N26 R21 P21 AM26 AM27 AN24 AN25 AU23 AT23 AV20 AW20 V24 V23 AD25 AD24 AE26 AE27 MA_DM1 MA_DATA24 MA_DM2 MA_DATA25 MA_DM3 MA_DATA26 MA_DM4 MA_DATA27 MA_DM5 MA_DATA28 MA_DM6 MA_DATA29 MA_DM7 MA_DATA30 RSVD_36 MA_DATA31 MA_DQS_H0 MA_DATA32 MA_DQS_L0 MA_DATA33 MA_DQS_H1 MA_DATA34 MA_DQS_L1 MA_DATA35 MA_DQS_H2 MA_DATA36 MA_DQS_L2 MA_DATA37 MA_DQS_H3 MA_DATA38 MA_DQS_L3 MA_DATA39 MA_DQS_H4 MA_DQS_L4 MA_DATA40 MA_DQS_H5 MA_DATA41 MA_DQS_L5 MA_DATA42 MA_DQS_H6 MA_DATA43 MA_DQS_L6 MA_DATA44 MA_DQS_H7 MA_DATA45 MA_DQS_L7 MA_DATA46 RSVD_41 MA_DATA47 MA_DATA48 MA_CLK_H0 MA_DATA49 MA_CLK_L0 MA_DATA50 MA_CLK_H1 MA_DATA51 MA_CLK_L1 MA_DATA52 MA_DATA54 MA_DATA55 23 23 DDR_A_CS0# DDR_A_CS1# MA_DATA56 AG21 AJ27 MA_CS_L0 MA_DATA57 MA_CS_L1 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 23 23 DDR_A_CKE0 DDR_A_CKE1 DDR_A_CKE0 DDR_A_CKE1 MA_DATA63 Y23 Y26 MA_CKE1 RSVD_34 RSVD_51 23 23 B DDR_A_ODT0 DDR_A_ODT1 RSVD_52 AG24 AJ22 MA_ODT0 RSVD_27 MA_ODT1 RSVD_28 RSVD_43 RSVD_42 23 DDR_A_ALERT# 23 23 DDR_A_EVENT# DDR_A_RST# M25 M27 P27 R24 L27 M24 P24 P25 DDR_A_DQ16 DDR_A_DQ17 DDR_A_DQ18 DDR_A_DQ19 DDR_A_DQ20 DDR_A_DQ21 DDR_A_DQ22 DDR_A_DQ23 M22 N21 T22 V21 L21 M20 R23 T21 DDR_A_DQ24 DDR_A_DQ25 DDR_A_DQ26 DDR_A_DQ27 DDR_A_DQ28 DDR_A_DQ29 DDR_A_DQ30 DDR_A_DQ31 AL27 AL25 AP26 AR27 AK26 AK24 AM24 AP27 DDR_A_DQ32 DDR_A_DQ33 DDR_A_DQ34 DDR_A_DQ35 DDR_A_DQ36 DDR_A_DQ37 DDR_A_DQ38 DDR_A_DQ39 AM23 AM21 AR25 AU27 AL22 AL21 AP24 AP23 DDR_A_DQ40 DDR_A_DQ41 DDR_A_DQ42 DDR_A_DQ43 DDR_A_DQ44 DDR_A_DQ45 DDR_A_DQ46 DDR_A_DQ47 AW26 AV25 AV22 AW22 AU26 AV27 AW23 AT22 AW21 AU21 AP21 AN20 AR22 AN22 AT20 AR20 24 24 24 DDR_B_MA14_WE# DDR_B_MA15_CAS# DDR_B_MA16_RAS# 24 24 DDR_B_BA0 DDR_B_BA1 24 24 DDR_B_BG0 DDR_B_BG1 24 DDR_B_ACT# 24 DDR_B_DM[7 0] 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 24 DDR_A_DQ48 DDR_A_DQ49 DDR_A_DQ50 DDR_A_DQ51 DDR_A_DQ52 DDR_A_DQ53 DDR_A_DQ54 DDR_A_DQ55 DDR_B_DQS0 DDR_B_DQS0# DDR_B_DQS1 DDR_B_DQS1# DDR_B_DQS2 DDR_B_DQS2# DDR_B_DQS3 DDR_B_DQS3# DDR_B_DQS4 DDR_B_DQS4# DDR_B_DQS5 DDR_B_DQS5# DDR_B_DQS6 DDR_B_DQS6# DDR_B_DQS7 DDR_B_DQS7# 24 24 24 24 DDR_A_DQ56 DDR_A_DQ57 DDR_A_DQ58 DDR_A_DQ59 DDR_A_DQ60 DDR_A_DQ61 DDR_A_DQ62 DDR_A_DQ63 DDR_A_ALERT# AA25 MA_ALERT_L DDR_A_EVENT# DDR_A_RST# AE24 Y24 MA_EVENT_L MA_PAROUT 24 24 DDR_B_CLK0 DDR_B_CLK0# DDR_B_CLK1 DDR_B_CLK1# DDR_B_CS0# DDR_B_CS1# AG30 AC32 AC30 AB29 AB31 AA30 AA29 Y30 AA31 W29 AH29 Y32 W31 AL30 AK30 AK32 AJ30 DDR_B_BA0 DDR_B_BA1 AH31 AG32 DDR_B_BG0 DDR_B_BG1 V31 V29 MB_BG0 MB_DATA19 MB_BG1 MB_DATA20 DDR_B_ACT# V30 MB_ACT_L MB_ADD0 MB_ADD1 MB_DATA0 MB_ADD2 MB_DATA1 MB_ADD3 MB_DATA2 MB_ADD4 MB_DATA3 MB_ADD5 MB_DATA4 MB_ADD6 MB_DATA5 MB_ADD7 MB_DATA6 MB_ADD8 MB_DATA7 MB_ADD9 MB_ADD10 MB_DATA8 MB_ADD11 MB_DATA9 MB_ADD12 MB_DATA10 MB_ADD13_BANK2 MB_DATA11 MB_WE_L_ADD14 MB_DATA12 MB_CAS_L_ADD15 MB_DATA13 MB_RAS_L_ADD16 MB_DATA14 MB_DATA15 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 DDR_B_DQS0 DDR_B_DQS0# DDR_B_DQS1 DDR_B_DQS1# DDR_B_DQS2 DDR_B_DQS2# DDR_B_DQS3 DDR_B_DQS3# DDR_B_DQS4 DDR_B_DQS4# DDR_B_DQS5 DDR_B_DQS5# DDR_B_DQS6 DDR_B_DQS6# DDR_B_DQS7 DDR_B_DQS7# DDR_B_CLK0 DDR_B_CLK0# DDR_B_CLK1 DDR_B_CLK1# DDR_B_CS0# DDR_B_CS1# MB_BANK0 MB_DATA16 MB_BANK1 MB_DATA17 MB_DATA18 MB_DATA21 MB_DATA22 MB_DATA23 C21 C25 E32 K30 AP30 AW31 BB26 BD22 N32 D22 B22 D25 B25 F29 F30 K31 K29 AR29 AR31 AW30 AW29 BC25 BA25 BC22 BA22 N31 N29 MB_DM1 MB_DATA24 MB_DM2 MB_DATA25 MB_DM3 MB_DATA26 MB_DM4 MB_DATA27 MB_DM5 MB_DATA28 MB_DM6 MB_DATA29 MB_DM7 MB_DATA30 RSVD_21 MB_DATA31 MB_DQS_H0 MB_DATA32 MB_DQS_L0 MB_DATA33 MB_DQS_H1 MB_DATA34 MB_DQS_L1 MB_DATA35 MB_DQS_H2 MB_DATA36 MB_DQS_L2 MB_DATA37 MB_DQS_H3 MB_DATA38 MB_DQS_L3 MB_DATA39 AJ31 AM31 AJ29 AM29 24 24 DDR_A_PAR 23 MA_RESET_L FP5 REV 0.90 PART OF 13 DDR_B_CKE0 DDR_B_CKE1 DDR_B_ODT0 DDR_B_ODT1 24 DDR_B_ALERT# 24 24 DDR_B_EVENT# DDR_B_RST# DDR_B_CKE0 DDR_B_CKE1 MB_DQS_L4 MB_DATA40 MB_DQS_H5 MB_DATA41 MB_DQS_L5 MB_DATA42 MB_DQS_H6 MB_DATA43 MB_DQS_L6 MB_DATA44 MB_DQS_H7 MB_DATA45 MB_DQS_L7 MB_DATA46 RSVD_20 MB_DATA47 RSVD_18 MB_CLK_H0 MB_DATA49 MB_CLK_L0 MB_DATA50 MB_CLK_H1 MB_DATA51 MB_CLK_L1 MB_DATA52 MB_CLK_H2 MB_DATA53 MB_CLK_L2 MB_DATA54 MB_CLK_H3 DDR_B_ODT0 DDR_B_ODT1 MB_DATA55 MB_DATA56 MB0_CS_L0 MB_DATA57 MB0_CS_L1 MB_DATA58 MB1_CS_L0 MB_DATA59 MB1_CS_L1 MB_DATA60 DDR_B_DQ8 DDR_B_DQ9 DDR_B_DQ10 DDR_B_DQ11 DDR_B_DQ12 DDR_B_DQ13 DDR_B_DQ14 DDR_B_DQ15 C30 E29 H29 H31 A28 D28 F31 G30 DDR_B_DQ16 DDR_B_DQ17 DDR_B_DQ18 DDR_B_DQ19 DDR_B_DQ20 DDR_B_DQ21 DDR_B_DQ22 DDR_B_DQ23 J29 J31 L29 L31 H30 H32 L30 L32 DDR_B_DQ24 DDR_B_DQ25 DDR_B_DQ26 DDR_B_DQ27 DDR_B_DQ28 DDR_B_DQ29 DDR_B_DQ30 DDR_B_DQ31 AP29 AP32 AT29 AU32 AN30 AP31 AR30 AT31 DDR_B_DQ32 DDR_B_DQ33 DDR_B_DQ34 DDR_B_DQ35 DDR_B_DQ36 DDR_B_DQ37 DDR_B_DQ38 DDR_B_DQ39 AU29 AV30 BB30 BA28 AU30 AU31 AY32 AY29 DDR_B_DQ40 DDR_B_DQ41 DDR_B_DQ42 DDR_B_DQ43 DDR_B_DQ44 DDR_B_DQ45 DDR_B_DQ46 DDR_B_DQ47 BA27 BC27 BA24 BC24 BD28 BB27 BB25 BD25 DDR_B_DQ48 DDR_B_DQ49 DDR_B_DQ50 DDR_B_DQ51 DDR_B_DQ52 DDR_B_DQ53 DDR_B_DQ54 DDR_B_DQ55 BC23 BB22 BC21 BD20 BB23 BA23 BB21 BA21 DDR_B_DQ56 DDR_B_DQ57 DDR_B_DQ58 DDR_B_DQ59 DDR_B_DQ60 DDR_B_DQ61 DDR_B_DQ62 DDR_B_DQ63 24 D C MB0_CKE0 MB0_CKE1 RSVD_17 MB1_CKE0 RSVD_19 MB1_CKE1 RSVD_26 RSVD_29 AL31 AM32 AL29 AM30 D24 A25 D27 C27 C23 B24 C26 B27 MB_CLK_L3 MB_DATA63 U29 T30 V32 U31 DDR_B_DQ0 DDR_B_DQ1 DDR_B_DQ2 DDR_B_DQ3 DDR_B_DQ4 DDR_B_DQ5 DDR_B_DQ6 DDR_B_DQ7 MB_DQS_H4 MB_DATA48 AC31 AD30 AD29 AD31 AE30 AE32 AF29 AF31 B21 D21 B23 D23 A20 C20 A22 C22 MB_DM0 MB_DATA62 24 24 DDR_A_PAR DDR_B_DQ[63 0] DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14_WE# DDR_B_MA15_CAS# DDR_B_MA16_RAS# MB_DATA61 T24 T25 W25 W27 R26 R27 V27 V26 AF24 MEMORY B DDR_B_MA[13 0] MA_CKE0 RSVD_35 DDR_A_ODT0 DDR_A_ODT1 DDR_A_DQ8 DDR_A_DQ9 DDR_A_DQ10 DDR_A_DQ11 DDR_A_DQ12 DDR_A_DQ13 DDR_A_DQ14 DDR_A_DQ15 RSVD_40 24 DDR_A_DQ0 DDR_A_DQ1 DDR_A_DQ2 DDR_A_DQ3 DDR_A_DQ4 DDR_A_DQ5 DDR_A_DQ6 DDR_A_DQ7 G25 F26 L24 L26 L23 F25 K25 K27 MA_DM0 MA_DATA53 DDR_A_CS0# DDR_A_CS1# J21 H21 F23 H23 G20 F20 J22 J23 23 MB0_ODT0 RSVD_16 MB0_ODT1 RSVD_15 MB1_ODT0 RSVD_25 MB1_ODT1 RSVD_24 DDR_B_ALERT# W30 MB_ALERT_L DDR_B_EVENT# DDR_B_RST# AG29 T31 MB_EVENT_L MB_PAROUT M31 N30 P31 R32 M30 M29 P30 P29 AG31 B DDR_B_PAR DDR_B_PAR 24 MB_RESET_L FP5 REV 0.90 PART OF 13 @ FP5_BGA_1140P @ FP5_BGA_1140P EVENT# pull high +1.2V RC1 1K_0402_5% DDR_B_EVENT# 1K_0402_5% DDR_A_EVENT# +1.2V RC2 A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2019/07/24 Deciphered Date 2020/07/24 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title FP5_(2/7)_DDR4 Size Document Number Custom R ev 1.0 FH50Q M/B LA-J621P Date: Monday, November 25, 2019 Sheet of 100 A B C D E Main Func = CPU DISP +1.8VALW UC1C 40 40 APU_DP0_P1 APU_DP0_N1 40 40 APU_DP0_P2 APU_DP0_N2 40 40 APU_DP0_P3 APU_DP0_N3 38 38 EDP 38 38 EDP_TXP1 EDP_TXN1 38 38 EDP_TXP2 EDP_TXN2 38 38 EC_SMB_CK2 EC_SMB_DA2 EC_SMB_CK2 EC_SMB_DA2 RC616 RC617 1 0_0402_5% 0_0402_5% EDP_TXP0 EDP_TXN0 DP_DIGON DP_VARY_BL D8 B8 DP0_TXP1 APU_DP0_P2 APU_DP0_N2 B6 C7 DP0_TXP2 APU_DP0_P3 APU_DP0_N3 C6 D6 DP0_TXP3 EDP_TXP0 EDP_TXN0 E6 D5 DP1_TXP0 EDP_TXP1 EDP_TXN1 E1 C1 DP1_TXP1 EDP_TXP2 EDP_TXN2 F3 E4 DP1_TXP2 DP0_TXN1 DP0_AUXP DP0_AUXN DP0_HPD DP0_TXN2 DP1_AUXP F4 F2 DP1_AUXN DP3: DP2: DP1: eDP DP0: HDMI DP0_TXN3 DP1_TXN0 DP1_TXN1 DP1_HPD DP2_AUXP DP2_AUXN DP2_HPD D9 APU_DP0_CTRL_CLK APU_DP0_CTRL_DATA B9 APU_DP0_HPD C10 DP3_HPD K15 UC66 NC EDP_AUXP 38 EDP_AUXN 38 EDP_HPD 38 A EDP ENVDD_R DP1_TXN3 RSVD_3 F14 F12 RSVD_2 F10 RSVD_4 RC690 RS@ AP14 AN14 TEST6 F13 UC65 NC Y A EMC@ CC5 33P_0402_50V8J EMC@ CC6 33P_0402_50V8J 88 RC80 +1.8VS RC81 +1.8VS APU_PWROK 300_0402_5% 300_0402_5% Close to APU 58,84,88 SVID 88 88 88 +1.8VS 58 THERMTRIP# APU_PROCHOT# RC669 RC670 APU_SVC APU_SVD APU_SVT_R APU_RST# APU_PWROK AW4 AW2 APU_SIC APU_SID APU_ALERT# THERMTRIP# APU_PROCHOT# H14 J14 J15 AP16 L19 F16 H16 J16 1 RC109 RC110 RC111 @ @ @ ENVDD RC4 INVTPWM RC5 4.7K_0402_5% 100K_0402_5% TP@ T4942 APU_TEST41 TP@ T4941 ENBKL_R TEST470 TDO TEST471 AJ21 AK21 APU_TEST470 TP@ APU_TEST471 TP@ RC6130 TDI T4940 T4939 ENVDD_R RC6131 INVTPWM_R RC6132 TCK IO18S5 4.7K_0402_5% 2 4.7K_0402_5% @ 100K_0402_5% 100K_0402_5% @ TRST_L DBREQ_L +0.9VS RESET_L SMU_ZVDD V4 SMU_ZVDDP RC1682 CORETYPE AW11 CORETYPE RC1681 196_0402_1% IO18 PWROK SIC +3VALW 1K_0402_5% @ SID ALERT_L THERMTRIP_L IO33 VDDP_SENSE SVC0 SVD0 SVT0 AN11 APU_VDDP_SEN_H APU_CORESOC_SEN_H K18 APU_CORE_SEN_H APU_VDDP_SEN_H 87 APU_CORESOC_SEN_H APU_CORE_SEN_H 88 VDDCR_SOC_SENSE J19 PROCHOT_L @ APU_TEST31 VDDCR_SENSE 0_0402_5% APU_SVC_R 0_0402_5% APU_SVD_R APU_SVT_R RC3 AR11 TMS 38 +3VS ENBKL W24 1K_0402_5% THERMTRIP# INVTPWM T4949 T4948 TEST41 +3VS @EMC@ CC1202 1U_0402_16V7K TP@ TP@ INVTPWM NL17SZ07EDFT2G_SC70-5 SA0000BIO00 TEST31 TEST16 APU_TEST4 APU_TEST5 G18 H19 F18 F19 TEST15 38 +1.8VALW TEST17 TEST14 ENVDD 0_0402_5% ENVDD APU_TEST14 APU_TEST15 APU_TEST16 APU_TEST17 ENVDD NL17SZ07EDFT2G_SC70-5 SA0000BIO00 TEST5 TEST4 AU2 AU4 AU1 AU3 AV3 AW3 Y A @ DP_STEREOSYNC UC64 NC APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBREQ# 58 DP1_TXP3 APU_SIC APU_SID APU_PROCHOT# APU_RST# APU_PWROK ENBKL INVTPWM_R RC664 ENBKL NL17SZ07EDFT2G_SC70-5 SA0000BIO00 +1.8VALW ENVDD_R DP1_TXN2 Y HDMI J12 H12 K13 DP_STEREOSYNC DP3_AUXN APU_DP0_CTRL_CLK 40 APU_DP0_CTRL_DATA 40 APU_DP0_HPD 40 EDP_AUXP EDP_AUXN EDP_HPD G11 F11 G13 J10 H10 K8 DP3_AUXP ENBKL_R G IO18 ENBKL_R ENVDD_R INVTPWM_R G15 F15 L14 DP_BLON DP0_TXN0 APU_DP0_P1 APU_DP0_N1 EDP_TXP3 EDP_TXN3 EDP_TXP3 EDP_TXN3 DP0_TXP0 HDMI C8 A8 P DISPLAY/SVI2/JTAG/TEST APU_DP0_P0 APU_DP0_N0 APU_DP0_P0 APU_DP0_N0 G 40 40 APU_SID APU_ALERT# APU_SIC APU_PROCHOT# P 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% G 2 2 P 1 1 RC105 RC106 RC107 RC108 +3VS 27,40,58,66 27,40,58,66 EC/THERM IO18 VSS_SENSE_A FP5 REV 0.90 PART OF 13 VSS_SENSE_B J18 APU_VSS_SEN_L AM11 APU_VDDP_SEN_L 88 Leakage prevent from power side APU_VSS_SEN_L 88 APU_VDDP_SEN_L 87 FP5_BGA_1140P 1K_0402_5% APU_SVT_R 1K_0402_5% APU_SVC 1K_0402_5% APU_SVD HDT+ TESTPOINT +1.8VS DP_STEREOSYNC +1.8VALW RC155 +1.8VALW JHDT1 CONN@ APU_TRST# CH2 0.01U_0402_16V7K RH21 33_0402_5% APU_TRST#_R RH38 10K_0402_5% HDT_P11 11 RH39 10K_0402_5% HDT_P13 13 RH40 10K_0402_5% HDT_P15 15 17 19 10 11 12 13 14 15 16 17 18 19 20 APU_TCK APU_TMS APU_TDI APU_TDO 10 APU_PWROK 12 APU_RST# APU_TCK APU_TMS APU_TDI APU_DBREQ# RC154 RH34 RH35 RH36 RH37 1 1 2 2 1K_0402_5% @ 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% +1.8VS APU_TRST# RH26 1K_0402_5% APU_TEST14 APU_TEST15 APU_TEST16 APU_TEST17 14 16 APU_DBREQ#_R RH33 33_0402_5% APU_DBREQ# RC112 RC113 RC114 RC115 2 2 @ @ @ @ 1 1 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 18 20 Follow C5V08 SAMTE_ASP-136446-07-B Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2019/07/24 Deciphered Date 2020/07/24 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title (3/7)_DISP/MISC/HDT Size Document Number Custom A B C D R ev 1.0 FH50Q M/B LA-J621P Date: Monday, November 25, 2019 Sheet E of 100 A B C D E Main Func = CPU +1.8VALW UC1D ACPI/AUDIO/I2C/GPIO/MISC CC7 @ CC100 APU_PCIE_RST#_C APU_PCIE1_RST#_C 150P_0402_50V8J 150P_0402_50V8J RC29 RC704 @ 58 58 33_0402_5% 33_0402_5% EGPIO41/SFI_S5_EGPIO41 AGPIO39/SFI_S5_AGPIO39 APU_PCIE_RST#_R APU_PCIE1_RST#_R EC_RSMRST# BD5 BB6 AT16 PBTN_OUT# SYS_PWRGD_EC SYS_RST# APU_PCIE_WAKE# AR15 AV6 AP10 AV11 SLP_S3# SLP_S5# AV13 AT14 AGPIO10 AR8 AGPIO23 AGPIO12 AT10 AN6 EC_RSMRST# 58 PBTN_OUT# SYS_PWRGD_EC 58 58 SLP_S3# SLP_S5# PCIE_RST1_L/EGPIO27 SW PU/PD SW PU/PD SW PU/PD1.8V_S5 RSMRST_L SW PU/PD SW PU/PD1.8V_S5 PWR_BTN_L/AGPIO0 PWR_GOOD I2C0_SCL/SFI0_I2C_SCL/EGPIO151 I2C0_SDA/SFI0_I2C_SDA/EGPIO152 I2C1_SCL/SFI1_I2C_SCL/EGPIO149 I2C1_SDA/SFI1_I2C_SDA/EGPIO150 SW PU/PD SW PU/PD WAKE_L/AGPIO2 I2C2_SCL/EGPIO113/SCL0 3.3V I2C2_SDA/EGPIO114/SDA0 SW PU/PD SLP_S5_L I2C3_SCL/AGPIO19/SCL1 I2C3_SDA/AGPIO20/SDA1 AC_PRES/AGPIO23 I2C_1_SCL I2C_1_SDA BC20 BA20 SMB_0_SCL SMB_0_SDA AM9 AM10 I2C_3_SCL I2C_3_SDA PSA_I2C_SDA RC6139 RC6140 @ @ 2.2K_0402_5% 2.2K_0402_5% I2C_1_SCL I2C_1_SDA RC6176 RC6177 @ @ 2.2K_0402_5% 2.2K_0402_5% +3VS SMB_0_SCL SMB_0_SDA 23,24 23,24 I2C_3_SCL I2C_3_SDA SMB_0_SCL SMB_0_SDA RC6157 RC6156 2.2K_0402_5% 2.2K_0402_5% I2C_3_SCL I2C_3_SDA RC6159 RC6158 2.2K_0402_5% 2.2K_0402_5% DDR4 +3VALW 63 63 Touch Pad L16 M16 SW PU/PD LLB_L/AGPIO12 +3VS EGPIO42 AGPIO4/SATAE_IFDET AT15 AW10 AGPIO3 AGPIO4 DEVSLP1 AGPIO5/DEVSLP0 AGPIO6/DEVSLP1 +3VALW SATA_ACT_L/AGPIO130 APU_PCIE_WAKE# 56 HDA_SDIN0 Reserve for MBDG/CRB CRB use S0-rail +1.8VALW CC1210 10U_0402_6.3V6M @ 1 +3VS AT2 AT4 AR6 AP6 AGPIO7 RC54 22K_0402_1% SYS_PWRGD_EC AGPIO69 AGPIO86 AGPIO5 27 DEVSLP1 68 PANEL_OD# 38 AGPIO40 68 AZ_BITCLK/TDM_BCLK_MIC AZ_SDIN0/CODEC_GPI AZ_SDIN1/SW_DATA1B/TDM_BCLK_PLAYBACK INTRUDER_ALERT 3.3VS Output AZ_SDIN2/SW_DATA2/TDM_DATA_PLAYBACK AZ_RST_L/SW_DATA1A/SW_DATA3/TDM_DATA_MIC SPKR/AGPIO91 BLINK/AGPIO11 AU14 AU16 AV8 APU_SPKR AW16 BD15 TP_I2C_INT#_APU APU_SPKR AGPIO11 56 AZ_SYNC/TDM_FRM_MIC 3.3VS input 3.3VS input AZ_SDOUT/TDM_FRM_PLAYBACK GENINT1_L/AGPIO89 GENINT2_L/AGPIO90 TP_I2C_INT#_APU SW_MCLK/TDM_BCLK_BT 63 SW_DATA0/TDM_DOUT_BT 3.3VS input 3.3VS input AGPIO7/FCH_ACP_I2S_SDIN_BT AGPIO8/FCH_ACP_I2S_LRCLK_BT FANIN0/AGPIO84 FANOUT0/AGPIO85 AR18 AT18 @ EC_RSMRST# FP5_BGA_1140P CC16 1U_0201_6.3V6M AGPIO40 APU_PCIE_RST#_C APU_PCIE1_RST#_C RC700 RS@ RC701 @ 0_0402_5% 0_0402_5% APU_PCIE_RST#_U APU_PCIE_RST#_U RC30 RS@ 0_0402_5% APU_PCIE_RST# RSV DMIC x2 RSV 1 RC6147 10K_0402_5% @ RC6135 10K_0402_5% @ RC6175 10K_0402_5% @ RC693 10K_0402_5% APU_PCIE_RST# APU_PCIE_RST# 27,51,52,68 @ RC692 10K_0402_5% @ RC6148 10K_0402_5% RC6136 10K_0402_5% @ RC6174 10K_0402_5% UC4 SA0000BIP00 MC74VHC1G08EDFT2G_SC70-5 RC6160 10K_0402_5% @ GPIO Table AGPIO23 AGPIO40 AGPIO9 AGPIO12 AGPIO23 IN2 @ RSV RSV O RSV AGPIO12 P IN1 L CC14 0.1U_0201_10V6K @ 2 DIS Type1 +3VALW G APU_PCIE_RST#_U RSV +3VALW AGPIO9 H CC8 0.22U_0402_16V7K 2 AGPIO40 AGPIO9 AGPIO40 FP5 REV 0.90 PART OF 13 RC28 10K_0402_1% 2 RC6165 10K_0402_1% AR2 AP7 AP1 AP4 AP3 AR4 AR3 AGPIO5 DEVSLP1 PANEL_OD# AU7 AU6 AW13 AW15 10K_0402_5% @ +3VALW SW PU/PD3.3VALW input 3.3VS input 3.3VS input HDA_BIT_CLK HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_RST# HDA_SYNC HDA_SDOUT AP9 AU10 AV15 2 10K_0402_5% @ AGPIO9 RC663 RC6133 @ AN8 AN9 S0A3_GPIO/AGPIO10 AGPIO3 I2C_0_SCL I2C_0_SDA SLP_S3_L PSA_I2C_SCL AW8 AR13 AT13 SYS_RESET_L/AGPIO1 3.3V_S5 ACPI AW12 AU12 PCIE_RST0_L/EGPIO26 I2C_0_SCL I2C_0_SDA AGPIO10 AGPIO5 AGPIO7 AGPIO3 AGPIO11 AGPIO4 Strap Pin MODE +3VALW RC929 2K_0402_5% @ 1 @ RC6146 10K_0402_5% @ RC6138 10K_0402_5% @ RC6171 10K_0402_5% @ RC6169 10K_0402_5% @ RC6134 10K_0402_5% @ RC6173 10K_0402_5% Issued Date Compal Electronics, Inc Compal Secret Data 2019/07/24 Deciphered Date 2020/07/24 Title FP5_(4/7)_GPIO/HDA/STRAP Size Document Number Custom C D Rev 1.0 FH50Q M/B LA-J621P Date: B AGPIO10 AGPIO11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A 2 AGPIO3 AGPIO4 Security Classification 2 @ RC6172 10K_0402_5% AGPIO5 AGPIO7 APU_SPI_CLK_R SYS_RST# RC1703 2K_0402_5% @ @ RC619 10K_0402_5% APU_SPI_CLK_R @ RC6168 10K_0402_5% 10 @ RC6170 10K_0402_5% HDA_SDIN1 HDA_SDIN2 HDA_SDIN0 @ RC6137 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% @ @ @ @ RC6145 10K_0402_5% RC951 10K_0402_5% 1 1 RC695 RC696 RC703 RC47 10K_0402_5% RC622 10K_0402_5% @ +3VALW +3VALW +1.8VALW +1.8VS +3VALW MODE RESET SHORT 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% L USE 100MHZ PCIE CLOCK AS REFERENCE CLOCK 2 2 HDA_RST# HDA_BIT_CLK HDA_SYNC HDA_SDOUT 33_0402_5% 33_0402_5% 33_0402_5% 33_0402_5% 1 1 RC120 RC121 RC122 RC123 2 2 EMC@ EMC@ EMC@ EMC@ SYS_RST# NORMAL RESET (Default) RC116 RC117 RC118 RC119 HDA_RST#_R HDA_BIT_CLK_R HDA_SYNC_R HDA_SDOUT_R CRYSTAL 56 56 56 56 USE 48MHZ CLOCK (Default) APU_SPI_CLK_R H HDA Monday, November 25, 2019 E Sheet of 100 A B C D E Main Func = CPU RC602 33_0402_5% LPC_RST_A# LPC_RST# 58 CC615 150P_0402_50V8J UC1E CLK/LPC/EMMC/SD/SPI/eSPI/UART +3VS RC1695 10K_0402_5% CLKREQ_PCIE#0 RC6149 RC1696 RC1697 10K_0402_5% 10K_0402_5% 10K_0402_5% CLKREQ_PCIE#2 CLKREQ_PEG#4 CLKREQ_PCIE#3 CLKREQ_PCIE#0 M.2 SSD1 68 CLKREQ_PCIE#0 M.2 WLAN LAN DGPU 52 51 27 CLKREQ_PCIE#2 CLKREQ_PCIE#3 CLKREQ_PEG#4 WLAN 48M_X2 48M_X1 RC939 1M_0402_5% 2 +3VALW CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 CLK_REQ1_L/AGPIO115 CLK_REQ2_L/AGPIO116 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131 EC_SCI# CLK_REQ4_L/OSCIN/EGPIO132 68 68 52 52 51 51 LAN DGPU 27 27 CLK_PCIE_P0 CLK_PCIE_N0 CLK_PCIE_P0 CLK_PCIE_N0 CLK_PCIE_P3 CLK_PCIE_N3 CLK_PEG_P4 CLK_PEG_N4 SW PU/PD AK1 AK3 GPP_CLK0P AM2 AM4 GPP_CLK1P AM1 AM3 GPP_CLK2P GPP_CLK0N LPC_PD_L/SD_CMD/AGPIO21 LAD0/SD_DATA0/EGPIO104 GPP_CLK1N M.2 WLAN/BT LAD1/SD_DATA1/EGPIO105 LAD3/SD_DATA3/EGPIO107 SW PU/PD GBE LAN LPCCLK0/EGPIO74 LPC_CLKRUN_L/AGPIO88 GPP_CLK2N CLK_PCIE_P3 CLK_PCIE_N3 AL2 AL4 GPP_CLK3P CLK_PEG_P4 CLK_PEG_N4 AN2 AN4 GPP_CLK4P AN3 AP2 GPP_CLK5P AJ2 AJ4 GPP_CLK6P GPP_CLK3N M.2 M.2 SW PU/PD LPCCLK1/EGPIO75 SW PU/PD LFRAME_L/EGPIO109 WWAN SERIRQ/AGPIO87 WLAN LPC_RST_L/SD_WP_L/AGPIO32 AGPIO68/SD_CD GPP_CLK4N GPP_CLK5N SW PU/PD LPC_PME_L/SD_PWR_CTRL/AGPIO22 PCIE X4 M.2 PCIE DT GPP_CLK6N EVAL GFX SLOT ESPI_RESET_L/KBRST_L/AGPIO129 SPI_DI/ESPI_DATA BB3 X48M_X1 SPI_DO SPI_WP_L/ESPI_DAT2 SPI_HOLD_L/ESPI_DAT3 3 4 SPI_CS1_L/EGPIO118 48M_X2 BA5 SW PU/PD X48M_X2 SPI_CS2_L/ESPI_CS_L/AGPIO30 SPI_CS3_L/AGPIO31 C796 3.9P_0402_50V8C C797 3.9P_0402_50V8C SPI_TPM_CS_L/AGPIO29 AF8 AF9 UART0_RXD/EGPIO136 UART0_CTS_L/UART2_TXD/EGPIO135 32.768KHz CRYSTAL 32K_X1 AW14 RTCCLK UART0_INTR/AGPIO139 AY1 X32K_X1 EGPIO141/UART1_RXD EGPIO143/UART1_TXD EGPIO142/UART1_RTS_L/UART3_RXD EGPIO140/UART1_CTS_L/UART3_TXD 32K_X2 AY4 2 2 10_0402_5% 10_0402_5% 10_0402_5% 10_0402_5% 22_0402_5% GC6_FB_EN3V3 LPC_AD0_R 58 LPC_AD1_R 58 LPC_AD2_R 58 LPC_AD3_R 58 LPC_CLK0_EC GC6_FB_EN3V3 27 +3VS SERIRQ LPC_FRAME# SERIRQ 58 LPC_FRAME# 58 ESPI_ALERT_L RC6181 PE_GPIO1 RC6166 @ EC_SCI# EC_SCI# 10K_0402_5% RC6183 @ 10K_0402_5% RC6180 @ 10K_0402_5% 58 X32K_X2 AGPIO144/UART1_INTR KBRST# ESPI_ALERT_L BB7 BA9 BB10 BA10 BC10 BC9 BA8 BA6 BD8 APU_SPI_CLK APU_SPI_MISO APU_SPI_MOSI APU_SPI_WP# APU_SPI_HOLD# APU_SPI_CS#1 BA16 BB18 BC17 BA18 BD18 UART_0_ARXD_DTXD UART_0_ATXD_DRXD BC18 BA17 BC16 BB19 BB16 PE_GPIO1 NVVDD1_PG GPU_EVENT# PE_GPIO0 KBRST# 58 RC74 EMC@ 10_0402_5% APU_SPI_CLK_R +SPI_VCC 8MB SPI ROM APU_SPI_TPMCS# APU_SPI_MISO UART_0_ARXD_DTXD UART_0_ATXD_DRXD 52 52 2 10K_0402_5% 10K_0402_5% APU_SPI_CS#1 RC639 RC646 APU_SPI_TPMCS# 10K_0402_5% @ 10K_0402_5% 32K_X2 PE_GPIO1 27 NVVDD1_PG 91 GPU_EVENT# 27 PE_GPIO0 27 +SPI_VCC RC1672 0_0603_5% RS@ FP5_BGA_1140P CC686 12P_0402_50V8J 10K_0402_5% +1.8VALW 1 @ RC640 FP5 REV 0.90 PART OF 13 YC3 SJ10000PW00 32.768KHZ_9PF_X1A000141000200 RC914 20M_0402_5% RC1706 APU_SPI_HOLD# RC642 32K_X1 10K_0402_5% 58 APU_SPI_WP# RSVD_77 UART0_TXD/EGPIO138 TP@ RTCCLK 0_0402_5% GC6@ LPC_CLK1 BB11 BC6 RSVD_76 UART0_RTS_L/UART2_RXD/EGPIO137 T115 LPC_RST_A# 48M_OSC SPI_CLK/ESPI_CLK 48M_X1 BD11 BA11 BA13 LPCPD# LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_CLK0 RC6182 TP@ T103 RC101 RC102 RC103 RC104 RC449 BC8 BB8 SPI_ROM_REQ/EGPIO67 ESPI_ALERT_L/LDRQ0_L/EGPIO108 AJ3 GC6_FB_EN LPC_CLK1 SSD SPI_ROM_GNT/AGPIO76 YC2 48MHZ_8PF_7V48000010 SJ10000JP00 BD13 BB14 BB12 BC11 BB15 BC15 BA15 BC13 BB13 BC12 BA12 SLOT 1 10K_0402_5% CLK_REQ6_L/EGPIO121 LAD2/SD_DATA2/EGPIO106 CLK_PCIE_P2 CLK_PCIE_N2 CLK_PCIE_P2 CLK_PCIE_N2 RC6154 SW PU/PD CLK_REQ5_L/EGPIO120 EGPIO70/SD_CLK M.2 SSD1 48MHz CRYSTAL CLKREQ_PCIE#2 CLKREQ_PCIE#3 CLKREQ_PEG#4 AV18 AN19 AP19 AT19 AU19 AW18 AW19 @ CC682 10P_0402_50V8J APU_SPI_CS#1 APU_SPI_MISO APU_SPI_WP# UC7 USB Function +SPI_VCC APU_SPI_HOLD# APU_SPI_CLK_R APU_SPI_MOSI CS# VCC DO(IO1) HOLD#(IO3) WP#(IO2) CLK GND DI(IO0) GD25LB64CSIGR_SOIC_8P SA00008K400 @ APU_SPI_CLK_R @EMC@2 RC680 10_0402_5% +1.8VALW CC635 0.1U_0201_10V6K @EMC@ CC636 10P_0402_50V8J +SPI_VCC RC94 4.7K_0402_5% APU_USBC_SCL RC95 4.7K_0402_5% APU_USBC_SDA APU_SPI_CS#1 APU_SPI_WP# APU_SPI_HOLD# UC1J USB CAMERA 38 38 USB20_P0 USB20_N0 Type-A MB CHG 71 71 USB20_P1 USB20_N1 Type-A MB 72 72 USB20_P2 USB20_N2 Type-C MB 43 43 USB20_P3 USB20_N3 Type-A SUB 73 73 USB20_P4 USB20_N4 USB Hub 52 52 USB20_P5 USB20_N5 USB20_P0 USB20_N0 AE7 AE6 USB_0_DP0 USB20_P1 USB20_N1 AG10 AG9 USB_0_DP1 USBC0_B11/USB_0_RXP0/DP3_TXP3 USB_0_DM1 USBC0_B10/USB_0_RXN0/DP3_TXN3 USB20_P2 USB20_N2 AF12 AF11 USB_0_DP2 USB_0_DM2 USBC0_B3/DP3_TXN1 USB20_P3 USB20_N3 AE10 AE9 USB_0_DP3 USBC0_A11/DP3_TXP0 USB_0_DM3 USBC0_A10/DP3_TXN0 USB20_P4 USB20_N4 AJ12 AJ11 USB_1_DP0 USB_0_TXP1 USB20_P5 USB20_N5 AD9 AD8 USB_1_DP1 USB_0_RXP1 USB_1_DM1 USB_0_RXN1 USBC0_A2/USB_0_TXP0/DP3_TXP2 USB_0_DM0 USBC0_A3/USB_0_TXN0/DP3_TXN2 AD2 AD4 JC1 CS# WP# HOLD# GND VCC SCLK SI/SIO0 SO/SIO1 APU_SPI_CLK_R APU_SPI_MOSI APU_SPI_MISO ACES_91960-0084N_MX25L3206EM2I CONN@ Port AC2 AC4 Controller USBC0_B2/DP3_TXP1 Port USB_1_DM0 USB_0_TXN1 AF4 AF2 AE3 AE1 AG3 AG1 USB3_ATX_DRX_P1 USB3_ATX_DRX_N1 AJ9 AJ8 USB3_ARX_DTX_P1 USB3_ARX_DTX_N1 AG4 AG2 USB3_ATX_DRX_P2 USB3_ATX_DRX_N2 AG7 AG6 USB3_ARX_DTX_P2 USB3_ARX_DTX_N2 AA2 AA4 USB3_ATX_DRX_P3 USB3_ATX_DRX_N3 Y1 Y3 USB3_ARX_DTX_P3 USB3_ARX_DTX_N3 Controller USB_0_TXP2 Port USB_0_TXN2 USB_0_RXP2 APU_USBC_SCL AM6 USBC_I2C_SCL APU_USBC_SDA AM7 USBC_I2C_SDA USB_0_RXN2 USBC1_A2/USB_0_TXP3/DP2_TXP2 Port USBC1_A3/USB_0_TXN3/DP2_TXN2 USBC1_B11/USB_0_RXP3/DP2_TXP3 USBC1_B10/USB_0_RXN3/DP2_TXN3 USBC1_B2/DP2_TXP1 USBC1_B3/DP2_TXN1 AK10 AK9 AL9 AL8 AW7 AT12 USB3_ATX_DRX_P1 USB3_ATX_DRX_N1 71 71 USB3_ARX_DTX_P1 USB3_ARX_DTX_N1 71 71 USB3_ATX_DRX_P2 USB3_ATX_DRX_N2 72 72 USB3_ARX_DTX_P2 USB3_ARX_DTX_N2 72 72 USB3_ATX_DRX_P3 USB3_ATX_DRX_N3 42 42 USB3_ARX_DTX_P3 USB3_ARX_DTX_N3 42 42 Type-A MB CHG Type-A MB Type-C MB AC1 AC3 USB_OC0_L/AGPIO16 USB_OC1_L/AGPIO17 USBC1_A11/DP2_TXP0 USB_OC2_L/AGPIO18 USBC1_A10/DP2_TXN0 AB2 AB4 USB_OC3_L/AGPIO24 AGPIO14/USB_OC4_L AGPIO13/USB_OC5_L USB_1_TXP0 SW PU/PD Port USB_1_TXN0 AH4 AH2 4 USB_1_RXP0 USB_1_RXN0 AK7 AK6 FP5 REV 0.90 PART 10 OF 13 FP5_BGA_1140P @ Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2019/07/24 Deciphered Date 2020/07/24 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title FP5_(5/7)_CLK/USB/SPI/LPC Size Document Number Custom A B C D Rev 1.0 FH50Q M/B LA-J621P Date: Monday, November 25, 2019 E Sheet 10 of 100 +19VB_1.2V BST_1.2V Choke: 5x5x3 Rdc=13mohm(Typ), VTT C PC509 0.033U_0402_16V7K FB +1.2VP PR506 6.19K_0402_1% +1.2VP PR509 0_0402_5% 58 SYSON @ PC518 0.1U_0402_10V7K 14mohm(Max) 0.75*(1+6.19/10)=1.21 PR508 10K_0402_1% L/S AON7506 Rds(on) :typ:13mOhm, max:15.8mOhm Idsm(TA=25)=12A, Idsm(TA=70)=10.5A Note: S3 - sleep ; S5 - power off PC507 10U_0402_6.3V6M VTTREF_1.2V H/S AON7408 Rds(on) :typ:27mOhm, max:34mOhm Idsm(TA=25)=7.5A, Idsm(TA=70)=5.5A VTTREF_1.2V off on on PC506 10U_0402_6.3V6M 20 19 VLDOIN S3 S5 +0.6VSP off off on @ Level L L H 18 PR507 470K_0402_1% +19VB_1.2V 21 FB_1.2V +5VALW Mode S5 S3 S0 VDDQ 1 PR505 2.2_0603_5% VTTREF VDD @ PD501 RB751V-40_SOD323-2 BOOT VDDP 11 EN_0.6VSP PC510 1U_0402_10V6K 12 GND RT8207PGQW_WQFN20_3X3 TON VDD_1.2V VTTSNS CS +5VALW PR504 5.1_0603_5% PAD VTTGND PGND 13 EN_1.2V PR502 26.7K_0402_1% CS_1.2V PC508 1U_0402_10V6K UGATE LGATE 14 PQ502 AON7506_DFN3X3-8-5 15 PGOOD LG_1.2V 17 16 PHASE PU501 @EMI@ PC517 680P_0402_50V7K 2 PC516 22U_0603_6.3V6M PC515 22U_0603_6.3V6M PC514 22U_0603_6.3V6M PC513 22U_0603_6.3V6M PC512 22U_0603_6.3V6M 1 PC511 22U_0603_6.3V6M C @EMI@ PR503 4.7_1206_5% +0.6VSP LX_1.2V D +1.2VP PQ501 AON7408L_DFN8-5 PR501 2.2_0603_5% UG_1.2V PL503 1UH_6.6A_20%_5X5X3_M +1.2VP 0.6Volt +/- 5% TDC 0.7A Peak Current 1A PC505 0.1U_0603_25V7K 1 BST_1.2V_R PC504 10U_0805_25V6K 1 2 @EMI@ PC501 0.1U_0402_25V6 EMI@ PC525 0.1U_0402_25V6 2 PC503 10U_0805_25V6K JUMP_43X79 EMI@ PC502 2200P_0402_50V7K +19VB 10 @ PJ504 D TON_1.2V 530kHz @ 37,58,78,84 SUSP# PR510 0_0402_5% @ PJ501 +1.2VP Switching Frequency: Ipeak=10.91A Iocp~120% OVP: 110%~120% B +5VALW 2 +1.2V JUMP_43X118 @ PC519 0.1U_0402_10V7K B +3VALW @ PJ502 +0.6VSP VIN_2.5V 1 JUMP_43X39 +0.6VS PC524 1U_0201_6.3V6M PC521 4.7U_0402_6.3V6M 2 JUMP_43X39 @ PJ505 @ PJ503 +2.5VP 2 +2.5V JUMP_43X39 PC523 22U_0603_6.3V6M 2 Rup FB_2.5V 1 PR512 21.5K_0402_1% 1M_0402_5% PC522 0.01U_0402_25V7K PR511 +2.5VP Vout=0.8V* (1+(21.5/10)) = 2.52V 0.8% @ 2 0.1U_0402_16V7K PC520 EN_2.5V PR515 0_0402_5% SYSON G9661MF11U_SO8 VDD NC VIN VOUT EN ADJ PGOOD GND GND @ PU502 PR513 A A Rdown 10K_0402_1% Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2018/12/18 2019/12/18 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title 1.2VP/0.6VSP/2.5VP Size Document Number Custom Date: Rev 1.0 FH50Q M/B LA-J621P Sheet Monday, November 25, 2019 86 of 100 EN pin don't floating If have pull down resistor at HW side, pls delete PR2 @ PJ601 +0.9VALWP 2 +0.9VALW JUMP_43X118 BYP NC PAD 16 21 PR610 10_0402_1% 1 @ PR622 0_0402_5% PR609 24.9K_0402_1% (R2) @ PQ601 LSK3541G1ET2L_VMT3 @ PR605 0_0402_5% 58,88 @ PR623 0_0402_5% APU_VDDP_SEN_H ILMT_VDDP VR_ON (R1) FB = 0.6V 1 @ PR604 0_0402_5% C C PR606 13.7K_0402_1% PC615 SY8288RAC_QFN20_3X3 1U_0201_6.3V6M PC612 2.2U_0402_6.3V6M PC611 22U_0603_6.3V6M 12 PC610 22U_0603_6.3V6M 10 +0.9VALWP LDO_VDDP FB_VDDP 17 14 PC609 22U_0603_6.3V6M NC LX_VDDP NC ILMT PL602 1UH_6.6A_20%_5X5X3_M 20 PC608 22U_0603_6.3V6M VCC EN 19 GND D FB @EMI@ PC603 680P_0402_50V7K 2 LDO_VDDP GND @EMI@ PR602 4.7_1206_5% 2SNB_VDDP 15 +3VALW @ PC614 0.22U_0402_10V6K LX 1 PR607 1M_0402_1% 13 LX GND PC602 0.1U_0603_25V7K PC607 22U_0603_6.3V6M 11 ILMT_VDDP IN @ PR603 0_0603_5% 2 0.9_1.8VALW_PWREN LX BST_VDDP PC606 22U_0603_6.3V6M 18 @ PR601 0_0402_5% IN BS PG IN IN PC613 330P_0402_50V7K PC605 10U_0805_25V6K @EMI@ PC604 0.1U_0402_25V6 EMI@ PC601 2200P_0402_50V7K 2 58,87 PU601 +19VB_VDDP 2 EMI@ PC623 0.1U_0402_25V6 1 JUMP_43X79 @ PJ604 D PC622 10U_0805_25V6K +19VB APU_VDDP_SEN_L @ PR621 0_0402_5% VFB=0.6V Vout=0.6V*(1+R1/R2)=0.93V PR1811 100K_0402_5% 2 @0@ PR1815 0_0402_5% PAD 12 PR1813 20.5K_0402_1% 16 21 PR1812 1K_0402_1% PC1807 SY8286RAC_QFN20_3X3 1U_0201_6.3V6M @ 1 (R1) PC1809 2.2U_0402_6.3V6M 1.8VALWP_LDO 10 B +1.8VALWP @ PC1817 22U_0603_6.3V6M NC 17 PL1802 1UH_6.6A_20%_5X5X3_M 2 NC BYP 14 1.8VALWP_FB PC1805 22U_0603_6.3V6M ILMT 1.8VALWP_LX NC 20 EN 19 VCC FB GND @EMI@ PC1806 680P_0402_50V7K FB = 0.6V @ PJ1804 JUMP_43X79 2 1.8VALWP_ILMT 1 1 @ PC1811 0.47U_0402_6.3V6K 2 1.8VALWP_LDO 15 GND 1.8VALWP_SNB PC1804 22U_0603_6.3V6M 13 +3VALW LX PC1814 22U_0603_6.3V6M 1.8VALWP_ILMT PR1808 1M_0402_1% GND @EMI@ PR1807 4.7_1206_5% PC1813 22U_0603_6.3V6M 0.9_1.8VALW_PWREN LX PC1810 0.1U_0603_25V7K 2 58,87 11 LX IN @0@ PR1814 0_0603_5% 1.8VALWP_BST PC1812 22U_0603_6.3V6M 18 @0@ PR1801 0_0402_5% IN PC1803 330P_0402_50V7K BS PG IN IN 2 PC1802 10U_0603_25V6M PC1801 10U_0603_25V6M B @EMI@ PC1808 0.1U_0402_25V6 JUMP_43X79 PU1802 +19VB_1.8VALWP EMI@ PC1815 2200P_0402_50V7K 2 EMI@ PC1816 0.1U_0402_25V6 1 @ PJ1803 +19VB +3VALW +1.8VALWP PR1810 10K_0402_1% @ PR1809 0_0402_5% +1.8VALW 2 (R2) Vout=0.6V* (1+Rup/Rdown) Vout=0.6V*(1+20.5/10) =1.83V (x1.017) 8288RAC A ILMT='0' ILMT=Floating ILMT='1' A Min 8A 12A 16A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2018/12/18 Deciphered Date 2019/12/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title 0.9VALW/1.8VALW Size Document Number Custom Date: R ev 1.0 FH50Q M/B LA-J621P Monday, November 25, 2019 Sheet 87 of 100 RT9610CGQW_WDFN8_2X2 35W_CPU@ PC845 1U_0603_10V6K @EMI@ PR855 4.7_1206_5% LG3_CPU S2 @EMI@ PC817 2200P_0402_50V7K @EMI@ PC816 0.1U_0402_25V6 35W_CPU@ PC848 10U_0805_25V6K 35W_CPU@ PC847 10U_0805_25V6K 1 D1 G1 35W_CPU@ PL806 0.22UH_24A_20%_ 7X7X4_M D2/S1 S2 BST3_CPU ISEN3P_CPU_R 35W_CPU@ PR856 2.7K_0402_1% ISEN3P_CPU 35W_CPU@ PR857 1.1K_0402_1% ISEN3N_CPU ISENA1P_CPU_R PR809 2.7K_0402_1% PC806 0.1U_0402_25V6 SNB_APU_NB ISENA1P_CPU 25W &35W) B MAX 14mohm 3.3mohm 2 PR810 845_0402_1% 1 PC812 0.1U_0402_25V6 ISENA1N_CPU +APU_CORE_SOC TDC 10A (15W & 25W &35W) EDC 13A (15W & 25W &35W) OCP current 24.2A (15W & Load line -2.1mV/A FSW=400kHz DCR 0.98mohm +/-5% TYP H/S Rds(on) :11.7mohm , L/S Rds(on) :2.7mohm , ISENA1N_CPU-1 @EMI@ PC811 @EMI@ PR808 680P_0402_50V7K 4.7_1206_5% 2 S2 PC804 10U_0805_25V6K PC803 10U_0805_25V6K D1 G1 LG1_NB S2 G2 LX1_NB C +APU_CORE 35W_CPU@ PC850 0.1U_0402_25V6 SNB_APU3 @ PL803 0.22UH_24A_20%_ 7X7X4_M +APU_CORE_SOC PQ801 AON6962_DFN5X6D-8-7 D2/S1 S2 PR804 PC805 2.2_0603_5% 0.22U_0603_25V7K BST1_NB BST1_NB1_R VCC_CPU 1 PC838 0.01U_0402_50V7K SET1_CPU SET2_CPU PR837 33K_0402_1% LGATE GND LX3_CPU PR803 0_0603_5% 2UG1_NB_R B +APU_CORE_SOC PR835 124K_0402_1% APU_CORESOC_SEN_H PR836 470_0402_1% 2 PR834 8.2K_0402_1% VCC PGND +19VB_CPU UG1_NB PR833 10_0402_5% 2 PC853 @ 10P_0402_25V8J +5VS EN PR842 1.1K_0402_1% 2 APU_VSS_SEN_L APU_SVT_R PHASE ISEN3N_CPU_R ISEN1P_CPU @ SVD and SVC RC filter put CPU side SVT RC filter put controller side PC855 @ 10P_0402_25V8J UGATE PWM 35W_CPU@ PQ805 AON6962_DFN5X6D-8-7 BOOT @35W_CPU@ PC851 0.1U_0402_25V6 @ PR829 10K_0402_5% PC842 0.1U_0402_25V6 SNB_APU2 35W_CPU@ PU802 PWM3_CPU @EMI@ PC849 680P_0402_50V7K 2 EN: high > 2V, Low < 0.8V Can't be floating 58,87 PR841 2.7K_0402_1% ISEN1N_CPU_R LG1_CPU VR_ON ISEN1P_CPU_R ISEN1N_CPU APU_SVD PC834 33U_25V_NC_6.3X4.5 PC840 10U_0805_25V6K PC839 10U_0805_25V6K 1 @EMI@ PC843 680P_0402_50V7K 2 +3VS +19VB_CPU UG3_CPU_R PC844 0.1U_0402_25V6 @EMI@ PC810 2200P_0402_50V7K 58 PL805 0.22UH_24A_20%_ 7X7X4_M +APU_CORE PQ804 AON6962_DFN5X6D-8-7 D2/S1 35W_CPU@ PR853 0_0603_5% 35W_CPU@ 35W_CPU@ PR860 PC846 2.2_0603_5% 0.22U_0603_25V7K BST3_CPU_R @EMI@ PR840 4.7_1206_5% LX1_CPU S2 PR839 PC841 2.2_0603_5% 0.22U_0603_25V7K BST1_CPU1 BST1_CPU_R Confirm HW side the pull high resistor @EMI@ PC809 0.1U_0402_25V6 1 +19VB_CPU PR819 100K_0402_1% @ PC833 330P_0402_50V7K @ PC854 10P_0402_25V8J PC820 33U_25V_NC_6.3X4.5 @EMI@ PC822 2200P_0402_50V7K 1 +19VB_CPU UG1_CPU_R UG3_CPU +5VS 40 PR838 0_0603_5% D1 41 UG1_CPU S2 42 BST1_NB G2 UG1_NB LX1_NB @ LG1_NB 43 PR812 10_0603_5% 45 44 PC832 0.1U_0402_25V6 BST1_CPU PR830 1.1K_0402_1% 2 46 ISEN2N_CPU PR832 10K_0402_1% APU_SVC PC825 0.1U_0402_25V6 ISEN2N_CPU_R @EMI@ PR824 4.7_1206_5% APU_core TDC 35A (15W & 25W), 56A (35W) EDC 45A (15W & 25W), 70A (35W) OCP current 63A (15W & 25W), 98A (35W) Load line -0.7mV/A FSW=430kHz DCR 0.98mohm +/-5% TYP MAX H/S Rds(on) :11.7mohm , 14mohm L/S Rds(on) :2.7mohm , 3.3mohm +APU_CORE PR826 2.7K_0402_1% 2 G2 39 @EMI@ PC821 0.1U_0402_25V6 S2 UG1_CPU PR828 100K_0402_5% PC830 390P_0402_50V7K PC818 10U_0805_25V6K PC819 10U_0805_25V6K G1 S2 @EMI@ PC826 680P_0402_50V7K 2 LX1_CPU +19VB D1 LG1_CPU 47 PC815 2.2U_0603_10V6K 49 48 PC814 2.2U_0603_10V6K VCC_CPU PGOOD PGOODA 38 37 ISENA2P ISENA1P 36 35 34 PVCC_CPU +5VS PR831 110K_0402_1% LG2_CPU VGATE ISENA1P_CPU ISENA1N_CPU 33 32 FBA 31 VCC EN TONSETA ISENA1N SET2 ISENA2N PWMA2 VSENA BOOTA1 SET1 COMPA OFSA 51 50 EMI@ PL802 NA_2P D ISEN2P_CPU_R2 SNB_APU PR811 2.2_0402_5% PVCC_CPU G1 UGATEA1 LX2_CPU S2 PHASEA1 OFS ISEN2P_CPU 53 52 S2 LGATEA1 SVT 8,58,84 S2 UG2_CPU UGATE2 PWM3_CPU_IC BST2_CPU PWM3 BOOT2 TONSET_CPU ISEN2N_CPU ISEN2P_CPU ISEN2P ISEN2N ISEN1N TONSET ISEN1N_CPU BOOT1 SVD PC829 68P_0402_50V8J PC852 close to IC Pin16 ISEN1P_CPU ISEN1P ISEN3N_CPU_IC ISEN3P_CPU_IC SVC Pull high at HW side @ 10 UGATE1 27 APU_PROCHOT# G2 LG2_CPU PC831 0.1U_0402_25V6 1 @ PC828 0.47U_0402_6.3V6K VREF_CPU ISEN3P PWROK OCP_L 1 PR823 20.5K_0402_1% PH802 100K_0402_1%_B25/50 4250K 2 SET2_CPU 26 1 PC852 0.022U_0402_25V7K 24 SET1_CPU 25 PHASE1 PR822 5.9K_0402_1% 35W_CPU@ PR825 14.3K_0402_1% 1 35W_CPU@ PR821 12.1K_0402_1% 2 PR858 48.7K_0402_1% VCC_CPU PR859 43K_0402_1% 23 0_0402_5% LGATE1 VDDIO FBA_CPU 2APU_SVT 22 PR818 25.5K_0402_1% PC827 0.47U_0402_6.3V6K C 21 APU_SVD 2 35W_CPU@ PR816 7.87K_0402_1% PH801 100K_0402_1%_B25/50 4250K 15W_CPU@ PR825 17.8K_0402_1% APU_SVD APU_SVC APU_SVT_R PR815 15W_CPU@ PR821 8.66K_0402_1% 20 PVCC IMONA 28 APU_SVC V064/SET3 COMPA_CPU 30 19 LGATE2 VCC_CPU 8 18 ISEN3N FB_CPU COMP_CPU PC813 1U_0201_6.3V6M APU_PWROK IMON PR827 100K_0402_1% 11 12 FB 13 15W_CPU@ PR816 16.5K_0402_1% VSEN COMP IMONA_CPU17 SVD_CPU and SVC_CPURC filter put CPU side SVT_CPU RC filter put controller side + +5VALW PHASE2 IBIAS VREF_CPU 16 + PL804 0.22UH_24A_20%_ 7X7X4_M PU801 RT3663BMGQW_WQFN52_6X6 GND RGND IBIAS_CPU 29 IMON_CPU 15 PQ802 AON6962_DFN5X6D-8-7 D2/S1 PWM3_CPU 35W_CPU@ PR847 0_0402_5% +1.8VS LX2_CPU +5VS 2 15W_CPU@ PR848 0_0402_5% ISEN3N_CPU ISEN3P_CPU PR820 PC824 2.2_0603_5% 0.22U_0603_25V7K BST2_CPU1 BST2_CPU_R1 PC808 68P_0402_50V8J 14 CORE SW= 430KHz PR806 60.4K_0402_1% PC807 390P_0402_50V7K EMI@ PL801 NA_2P UG2_CPU_R PR805 10K_0402_1% PR817 0_0603_5% UG2_CPU 35W_CPU@ PR843 0_0402_5% 15W_CPU@ PR844 0_0402_5% +APU_CORE +19VB_CPU 35W_CPU@ PR845 0_0402_5% PC802 0.01U_0402_50V7K @ PC801 330P_0402_50V7K D +19VB_CPU +5VS 2 +5VS PR802 10_0402_5% APU_CORE_SEN_H PR801 10_0402_5% PR807 88.7K_0402_1% APU_VSS_SEN_L 15W_CPU@ PR846 0_0402_5% @ A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2018/12/18 Deciphered Date 2019/12/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title +APU_CORE Size Document Number Rev 1.0 FH50Q M/B LA-J621P Date: Monday, November 25, 2019 Sheet 88 of 100 D D C C Reserve Page B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2018/12/18 2019/12/18 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Reserve Page Size Rev 1.0 FH50Q M/B LA-J621P Date: Document Number Sheet Monday, November 25, 2019 89 of 100 + + + PC9097 330U_D2_2V_Y + @ PC9098 330U_D2_2V_Y + PC9094 330U_D2_2V_Y 1 + PC9021 220U_D7_2VM_R4.5M Under CPU Bot B PC9081 180P_0402_50V8J PC9037 22U_0603_6.3V6M PC9038 22U_0603_6.3V6M PC9102 22U_0603_6.3V6M PC9063 0.22U_0402_16V7K + +APU_CORE Issued Date + PC9082 180P_0402_50V8J Security Classification 2018/12/18 PC9071 0.22U_0402_16V7K PC9070 0.22U_0402_16V7K PC9069 0.22U_0402_16V7K PC9068 0.22U_0402_16V7K PC9012 22U_0603_6.3V6M PC9013 22U_0603_6.3V6M PC9014 22U_0603_6.3V6M PC9015 22U_0603_6.3V6M PC9016 22U_0603_6.3V6M PC9017 22U_0603_6.3V6M PC9018 22U_0603_6.3V6M PC9019 22U_0603_6.3V6M PC9040 22U_0603_6.3V6M PC9041 22U_0603_6.3V6M PC9042 22U_0603_6.3V6M PC9043 22U_0603_6.3V6M PC9044 22U_0603_6.3V6M PC9045 22U_0603_6.3V6M PC9053 22U_0603_6.3V6M PC9103 22U_0603_6.3V6M PC9020 22U_0603_6.3V6M PC9011 22U_0603_6.3V6M PC9039 22U_0603_6.3V6M PC9008 22U_0603_6.3V6M PC9007 22U_0603_6.3V6M PC9006 22U_0603_6.3V6M PC9005 22U_0603_6.3V6M +APU_CORE PC9067 0.22U_0402_16V7K PC9066 0.22U_0402_16V7K PC9065 0.22U_0402_16V7K PC9064 0.22U_0402_16V7K 1 PC9036 22U_0603_6.3V6M PC9101 22U_0603_6.3V6M PC9062 0.22U_0402_16V7K 2 PC9035 22U_0603_6.3V6M PC9049 22U_0603_6.3V6M PC9061 0.22U_0402_16V7K 1 PC9034 22U_0603_6.3V6M PC9047 22U_0603_6.3V6M PC9060 0.22U_0402_16V7K 2 PC9033 22U_0603_6.3V6M PC9051 22U_0603_6.3V6M PC9059 0.22U_0402_16V7K PC9004 22U_0603_6.3V6M +APU_CORE PC9100 330U_D2_2V_Y PC9010 22U_0603_6.3V6M PC9032 22U_0603_6.3V6M PC9050 22U_0603_6.3V6M PC9058 0.22U_0402_16V7K PC9003 22U_0603_6.3V6M PC9099 330U_D2_2V_Y PC9009 22U_0603_6.3V6M PC9031 22U_0603_6.3V6M PC9046 22U_0603_6.3V6M PC9057 0.22U_0402_16V7K PC9002 22U_0603_6.3V6M PC9030 22U_0603_6.3V6M PC9052 22U_0603_6.3V6M PC9056 0.22U_0402_16V7K PC9001 22U_0603_6.3V6M PC9029 22U_0603_6.3V6M 1 PC9048 22U_0603_6.3V6M 2 C PC9096 220U_D7_2VM_R4.5M Under CPU D PC9095 330U_D2_2V_Y Deciphered Date +APU_CORE_SOC +APU_CORE_SOC 2019/12/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC D C APU_CORE_SOC 330uF*2 22uF*19 0.22uF*8 180pF*1 B near CPU 330u is common part SGA00009S00 APU_CORE 330uF*3 220uF*2 22uF*29 0.22uF*8 180pF*1 330u is common part SGA00009S00 A A Compal Secret Data Title Compal Electronics, Inc Size Document Number Custom FH50Q M/B LA-J621P +APU_CORE Cap Date: Monday, November 25, 2019 Sheet 90 of 100 Rev 1.0 @ PCV1 0.1U_0402_25V6 PRV1 0_0402_5% PRV9 3.6K_0402_1% @ PCV5 0.1U_0402_25V6 PRV13 0_0402_5% PRV7 442_0402_1% 2 PCV6 PRV15 0.015U_0402_16V7K 2.4K_0402_1% GPU_DRVON 92 27 1 PWM4_GPU PWM3_GPU PWM2_GPU 2 1 2 PRV29 100K_0402_1% VREF_GPU CH_OC_GPU PRV10 100K_0402_1% REFIN_GPU PWM2 @ PCV8 0.1U_0402_25V6 FDMF3170_REFIN LPC_GPU IMON_GPU 19 17 REFOUT LPC IMON 92 PRV66 20.5K_0402_1% 2 PRV63 PRV57 16.5K_0402_1% 1 113K_0402_1% 22.6K_0402_1% 63.4K_0402_1% 232K_0402_1% R2 NVVDD_VID FDMF3170_REFIN C +5VS +5VCC @0@ PRV54 0_0402_5% R4 O A 92 PRV42 2.2_0603_5% B R3 @0@ PRV70 0_0402_5% FDMF3170_IMON2 GPU_PWM1 92 GPU_PWM2 92 @0@ PRV56 0_0402_5% @ 100K_0402_1% B CSP3_GPU @ PRV30 1K_0402_1% 92 11 PRV71 @ PRV72 PRV73 PRV69 CSP2_GPU 12 NVVDD1_PG @ PUV8 TC7SH08FU_SSOP5~D P 13 10 PWM1 GND CSP1_GPU @0@ PRV146 0_0402_5% FDMF3170_IMON1 R5 PCV25 1U_0402_6.3V6K A C PWMVID 的 RC BOM 請 根 據GPU 據GPU 's conf i g 設定 PRV64 309_0402_1% PRV51 0_0402_5% PCV26 4700P_0402_50V7K EN_GPU 18 VINMON_GPU ADDR/FSW_GPU 21 PGOOD G +5VS 10 20 5VCC PRV53 4.32K_0402_1% +5VS @ PCV9 1U_0402_6.3V6K ADDR VINMON CSP4 PSI CSNSUM_GPU 14 R1 PRV61 100K_0402_1% +3VS DAC EN CSPSUM_GPU 32 CSP3 VID @ PRV52 0_0402_5% DAC_GPU EAP_GPU 24 SCL 33 PRV50 0_0402_5% 27 B CSP2 UP9512QQKI_WQFN32_4X4 PWM3 NVVDD1_PG CSP1 SDA PWM4 31 TSENSE REFIN 30 PSI_GPU 22 COMP_GPU EN_GPU NVVDD_PSI @ PRV46 0_0402_5% 29 16 15 PRV44 6.19K_0402_1% +3VS NVVDD1_EN 28 VGA_I2CC_SCL_PWR VGA_I2CC_SCL_PWR PQV01B DMN53D0LDW-7 2N SOT363-6 VGA_I2CC_SDA_PWR CSPSUM CSNSUM @ PRV19 1K_0402_1% +5VCC PCV18 4.7U_0402_6.3V6M 27,37 TSENSE_GPU 27 VGA_I2CC_SDA_PWR 27 NVVDD1_FBRTN PRV39 10K_0402_1% TSENSE_GPU FBRTN VID_GPU 27 FB 26 @0@ PRV145 0_0402_5% +5VCC REFADJ_GPU 92 PRV35 10_0402_1% +3VALW COMP 25 NVVDD1_FBRTN @0@ PRV34 0_0402_5% 1 PUV1 23 PRV31 1K_0402_1% PQV01A DMN53D0LDW-7 2N SOT363-6 NVVDD1_VSS_SENSE @ PCV11 0.1U_0402_25V6 2 PRV40 PCV14 @ 0.1U_0402_25V6 VOUT_S PRV14 2K_0402_1% EAP @ @ PRV25 0_0402_5% C 29 @ PCV7 0.1U_0402_25V6 REFADJ PRV22 10_0402_1% +NVVDD1 PRV18 0_0402_5% PRV21 @0@ PRV20 0_0402_5% 10K_0402_1% NVVDD1_VCC_SENSE 0_0402_5% 29 PCV3 1U_0402_6.3V6K CH_OC VREF PRV12 0_0402_5% PRV4 3.4K_0402_1% 1 PRV16 0_0402_5% D +5VCC PRV2 4.99K_0402_1% PCV4 0.1U_0402_25V6 @ PRV141 0_0402_5% @ PRV142 0_0402_5% VGA_I2CC_SCL_PWR PRV6 4.3K_0402_1% PWM1_GPU PRV11 10K_0402_1% VGA_I2CC_SDA_PWR +5VCC PRV8 91K_0402_1% PRV140 10K_0402_1% D PRV139 10K_0402_1% +3VS N17P-G1N VVDD1 TDC 59A Peak Current 124A OCP 200A Fsw=300kHz @ PCV13 0.1U_0402_25V6 NVVDD_B+ PCV2 0.1U_0402_25V6 PRV3 34K_0402_1% A NVVDD1_FBRTN Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_VGA_UP9512Q Size Rev 1.0 FH50Q M/B LA-J621P Date: Document Number Monday, November 25, 2019 Sheet 91 of 100 GPU_B+ EMI@ PLV11 HCB2012KF-121T50_0805 +19VB PRV74 EMI@ PLV12 HCB2012KF-121T50_0805 NVVDD_B+ PRV75 0.005_1206_1% 0.005_1206_1% +5VS A A 36 CSSP_B+ 36 CSSN_B+ CSSP_NVVDD 36 36 CSSN_NVVDD NCP303150@ PRV77 0_0402_5% @0@ PRV84 91 FDMF3170_IMON1 PWM1_FDMF3170 14 EN1_FDMF3170 15 0_0402_5% FDMF3170_IMON1 18 FDMF3170_REFIN1 19 LX1_FDMF3170 PCV249 33U_25V_M PCV39 10U_0805_25VAK PCV35 10U_0805_25VAK PCV34 10U_0805_25VAK PCV33 10U_0805_25VAK PCV32 10U_0805_25VAK 13 VIN 10 N/C VIN1 BOOT PGND2 PWM SW +NVVDD1 PLV2 S COIL 0.22UH 20% MMD-10DZIR22MER1L 50A B GPU_PWM1 PUV2 QD9619AQR1 PGND DISB# 10X10X4 Isat:90A DCR:0.55mΩ (+/-5%) EMI@ PRV154 4.7_1206_5% IMON REFIN GL @0@ PRV81 0_0402_5% 91 PHASE1_FDMF3170 AGND TP 91 12 VCC 21 GPU_DRVON PHASE + GPU1_SNB1 20 PVCC EMI@ PCV255 680P_0402_50V7K 2 PCV37 2.2U_0402_6.3V6M @0@ PRV79 0_0402_5% B PGND1 2 PRV78 2_0402_5% NC PCV40 0.1U_0603_25V7K VCC1_FDMF3170 11 16 VOS1_FDMF3170 FAULT +NVVDD1 PCV27 2.2U_0402_6.3V6M PRV85 0_0402_5% 17 +5VS EMI@ PCV31 2200P_0402_50V7K BST1_FDMF3170 PRV80 2.2_0603_1% TMON1_FDMF3170 EMI@ PCV30 0.1U_0402_25V6 PRV82 0_0402_5% TSENSE_GPU ZCD_EN 91 NVVDD_B+ PRV76 30K_0402_5% 2 +5VS NCP303150@ PRV87 0_0402_5% @0@ PRV91 91 FDMF3170_REFIN219 0_0402_5% LX2_FDMF3170 PCV52 10U_0805_25VAK PCV51 10U_0805_25VAK PCV50 10U_0805_25VAK 13 BOOT VIN 10 N/C VIN1 SW +NVVDD1 PLV3 S COIL 0.22UH 20% MMD-10DZIR22MER1L 50A PWM DISB# EMI@ PRV93 4.7_1206_5% IMON REFIN FDMF3170_REFIN PUV3 QD9619AQR1 D FDMF3170_IMON2 EN2_FDMF3170 15 0_0402_5% FDMF3170_IMON2 18 PGND2 10X10X4 Isat:90A DCR:0.55mΩ (+/-5%) GPU1_SNB2 91 14 PGND EMI@ PCV60 680P_0402_50V7K D 2 @0@ PRV94 PWM2_FDMF3170 11 @0@ PRV89 0_0402_5% PHASE2_FDMF3170 PGND1 GPU_PWM2 20 12 AGND PHASE PCV57 0.1U_0603_25V7K C VCC TP PCV54 2.2U_0402_6.3V6M PVCC 21 91 GL VCC2_FDMF3170 NC 17 16 PRV86 2_0402_5% VOS2_FDMF3170 FAULT +NVVDD1 PCV44 2.2U_0402_6.3V6M PRV95 0_0402_5% ZCD_EN +5VS PCV49 10U_0805_25VAK BST2_FDMF3170 PRV90 2.2_0603_1% C EMI@ PCV48 2200P_0402_50V7K TMON2_FDMF3170 EMI@ PCV47 0.1U_0402_25V6 PRV92 0_0402_5% NVVDD_B+ PRV88 30K_0402_5% Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_+NVVDD1 Size Rev 1.0 FH50Q M/B LA-J621P Date: Document Number Monday, November 25, 2019 Sheet 92 of 100 2 Security Classification Issued Date 2016/01/06 PCV282 10U_0402_6.3V6M PCV287 10U_0402_6.3V6M PCV250 10U_0402_6.3V6M PCV275 10U_0402_6.3V6M PCV281 10U_0402_6.3V6M PCV284 10U_0402_6.3V6M PCV277 10U_0402_6.3V6M PCV229 10U_0402_6.3V6M PCV228 10U_0402_6.3V6M PCV230 10U_0402_6.3V6M PCV231 10U_0402_6.3V6M PCV232 10U_0402_6.3V6M PCV233 10U_0402_6.3V6M PCV234 10U_0402_6.3V6M Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PCV256 22U_0603_6.3V6M PCV257 22U_0603_6.3V6M PCV252 22U_0603_6.3V6M PCV253 22U_0603_6.3V6M 1 Compal Secret Data Size Date: PCV361 22U_0603_6.3V6M PCV360 22U_0603_6.3V6M PCV359 22U_0603_6.3V6M PCV358 22U_0603_6.3V6M PCV248 22U_0603_6.3V6M PCV247 22U_0603_6.3V6M PCV246 22U_0603_6.3V6M PCV245 22U_0603_6.3V6M PCV244 22U_0603_6.3V6M PCV243 22U_0603_6.3V6M 2 PCV224 10U_0402_6.3V6M PCV223 10U_0402_6.3V6M PCV222 10U_0402_6.3V6M PCV221 10U_0402_6.3V6M PCV220 10U_0402_6.3V6M PCV219 10U_0402_6.3V6M PCV218 10U_0402_6.3V6M PCV217 10U_0402_6.3V6M PCV216 10U_0402_6.3V6M PCV254 22U_0603_6.3V6M 1 PCV279 10U_0402_6.3V6M PCV227 10U_0402_6.3V6M 2 PCV215 10U_0402_6.3V6M +NVVDD1 PCV236 10U_0402_6.3V6M PCV226 10U_0402_6.3V6M 1 PCV276 10U_0402_6.3V6M PCV237 10U_0402_6.3V6M PCV280 10U_0402_6.3V6M 2 PCV235 10U_0402_6.3V6M PCV225 10U_0402_6.3V6M 1 PCV148 1U_0201_6.3VAM PCV154 1U_0201_6.3VAM PCV147 1U_0201_6.3VAM PCV153 1U_0201_6.3VAM 2 PCV272 560U_D2_2VM_R4.5M + PCV283 10U_0402_6.3V6M PCV146 1U_0201_6.3VAM PCV152 1U_0201_6.3VAM 2 PCV165 1U_0201_6.3VAM PCV145 1U_0201_6.3VAM PCV151 1U_0201_6.3VAM + PCV139 560U_D2_2VM_R4.5M PCV164 1U_0201_6.3VAM PCV144 1U_0201_6.3VAM PCV150 1U_0201_6.3VAM 2 PCV138 560U_D2_2VM_R4.5M + PCV163 1U_0201_6.3VAM PCV143 1U_0201_6.3VAM PCV149 1U_0201_6.3VAM 2 PCV162 1U_0201_6.3VAM PCV142 1U_0201_6.3VAM PCV258 1U_0201_6.3VAM + PCV137 560U_D2_2VM_R4.5M PCV158 1U_0201_6.3VAM PCV141 1U_0201_6.3VAM PCV161 1U_0201_6.3VAM 2 PCV136 560U_D2_2VM_R4.5M + PCV157 1U_0201_6.3VAM 1 PCV140 1U_0201_6.3VAM 2 PCV160 1U_0201_6.3VAM 1 PCV251 1U_0201_6.3VAM 2 PCV159 1U_0201_6.3VAM 1 PCV156 1U_0201_6.3VAM PCV155 1U_0201_6.3VAM N18P-G0 +NVVDD 560uF X 22uF_0603 X 15 10uF_0402X 34 1uF_0201 X 28 D D +NVVDD1 +NVVDD1 C C B B A A Title Compal Electronics, Inc Document Number PWR_VGA DECOUPLING FH50Q M/B LA-J621P Monday, November 25, 2019 Sheet 93 of 100 Rev 1.0 Micron & Hynix & Samesung VRAM Vboot=Vref*R2/(R1+R2+80) 1 PCW5 10U_0805_25VAK EMI@ PCW19 0.1U_0402_25V6 LG1_+1.35VS_VGAP 18 PVCC_+1.35VS_VGAP @ PCW12 22U_0603_6.3V6M + PCW11 22U_0603_6.3V6M + PCW10 330U_D1_2VY_R9M PCW9 330U_D1_2VY_R9M + @EMI@ PCW16 680P_0402_50V7K PCW14 0.22U_0603_25V7K PCW23 330U_D1_2VY_R9M SW1_+1.35VS_VGAP 19 +1.35VSDGPU D1_1 D1_2 D2/S1_1 D2/S1_2 G2 LG1_+1.35VS_VGAP 20 PLW1 0.47UH_MHT-MHDZIR47MEM1-RT_30A_20% @EMI@ PRW8 4.7_1206_5% BOOT1 UG1_+1.35VS_VGAP EN_+1.35VS_VGAP PSI_+1.35VS_VGAP BOOT1_+1.35VS_VGAP EN UGATE1 PHASE1 30 FB_VDDQ_SENSE @0@ PRW20 0_0402_5% 1 PCW17 2.2U_0402_6.3V6M BOOT2 UGATE2 14 PGOOD 13 VSNS GND 11 21 16 PHASE2 +5VALW 1.35VSDGPU_PG PCW27 0.1U_0402_25V6 PRW17 36.5K_0402_1% PRW19 100_0402_1% 17 LGATE2 RGND C PRW11 2.2_0603_5% 15 TON Inside@ PRW25 42.2K_0402_1% REFADJ_+1.35VS_VGAP +1.35VSDGPU PVCC OCSET/SS 10 VREF 1OCset_+1.35VS_VGAP 12 RGND LGATE1 TON_+1.35VS_VGAP 0.1U_0402_25V6 REFADJ REFIN PCW18 1TON_+1.35VS_VGAP_R Inside@ PCW22 2200P_0402_50V7K Inside@ PRW24 25.5K_0402_1% REFADJ 0_0402_5% @ PRW14 PRW13 383K_0402_1% REFIN_+1.35VS_VGAP REF2 VID_+1.35VS_VGAP PSI VID REFIN_+1.35VS_VGAP Vsense_+1.35VS_VGAP B+_+1.35VS_VGAP PRW12 2.2_0402_1% Inside@ PCW21 2200P_0402_50V7K RBOOT Inside@ PRW23 3.92K_0402_1% REFADJ_+1.35VS_VGAP_R PUW1 RT8816BGQW_WQFN20_3X3 REFADJ_+1.35VS_VGAP S2 SW1_+1.35VS_VGAP-1 10 D PRW28 10K_0402_1% @ Inside@ PCW20 0.1U_0402_25V6 Inside@ PRW22 4.7K_0402_1% VREF_+1.35VS_VGAP 27 VRAM_VDD_CTL G1 2 @0@ PRW9 0_0402_5% VID_+1.35VS_VGAP_R @ PCW15 0.1U_0402_16V7K Outside@ PQW2A DMN53D0LDW-7 2N SOT363-6 Outside@ PRW5 68.1K_0402_1% 1 Outside@ PQW2B DMN53D0LDW-7 2N SOT363-6 Outside@ PRW27 0_0402_5% D1_3 PQW1 AOE6930_DFN5X6E8-10 SNB1_+1.35VS_VGAP Inside@ PRW26 0_0402_5% VID_+1.35VS_VGAP_R VREF_+1.35VS_VGAP REF1 PRW4 2.2_0603_5% BOOT1_+1 35VS_VGAP_R Outside@ PCW8 0.033U_0402_16V7K +3VALW C B D2/S1_3 S1/D2 PRW6 10K_0402_1% Outside@ PRW21 10K_0402_1% 13X8X4 Isat:55A DCR:1.3mΩ (+/-5%) 2 FBVDDQ_PSI @ PRW3 0_0402_5% Outside@ PCW7 0.1U_0402_25V6 27 N18P-G0 +1.35VSDGPU TDC 14A Peak Current 15A OCP current 31A fsw=400kHz SW1_+1.35VS_VGAP PRW10 31.6K_0402_1% REFIN_+1.35VS_VGAP GPU_B+ UG1_+1.35VS_VGAP Outside@ PRW2 10K_0402_1% Outside@ PRW7 30.9K_0402_1% PCW4 10U_0805_25VAK MOSFET: DFN 5X6E H/S Rds(on): 5.2mohm(Typ), 7mohm(Max) L/S Rds(on): 0.8mohm(Typ), 1.05mohm(Max) PCW3 10U_0805_25VAK PCW6 0.1U_0402_25V6 +3VALW VREF_+1.35VS_VGAP Rref2 EMI@ PCW1 2200P_0402_50V7K 1.35VSDGPU_EN EMI@ PCW2 0.1U_0402_25V6 27,37 PRW1 1K_0402_1% When,VRAM_VDD_CTL=Low Vboot=2*(30.9K//68.1K)/(10K+(30.9K//68.1K)+80) =1.356V (x1.08) Rref1 EMI@ PLW11 FBMA-L11-201209-800LMA50T B+_+1.35VS_VGAP When,VRAM_VDD_CTL=High Vboot=2*30.9K/(10K+30.9K+80) =1.508V (x1.11) D PCW13 22U_0603_6.3V6M PRW18 10K_0402_1% +3VS 1.35VSDGPU_PG 27 B PRW17=36.5K ohm, Rocset for 31.4A Micron & Hynix & Samesung VRAM When,VRAM_VDD_CTL=High Vboot=1.515V (x1.122) When,VRAM_VDD_CTL=Low Vboot=1.363V (x1.091) A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/02/01 Deciphered Date 2017/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_+VRAM Size Rev 1.0 FH50Q M/B LA-J621P Date: Document Number Monday, November 25, 2019 Sheet 94 of 100 A B C D E 1 PR1010 0_0402_5% 1VSDGPU_EN_R Current limit = 4.7A(min) +3VALW 2 Choke 1uH SH00000YG00 (Common Part) (Size:3.8 x 3.8 x 1.9 mm) (DCR:20m~25m) Choke: SH00000YG00 Size:4x4x2 (Common Part) Rdc=27± 20% Taiyo Rdc=20mohm(Typ), 25mohm(Max) Cyntec Rdc=27± 20% 3L Rdc=30± 20% Tai-Tech Rdc=32± 20% Chilisin Rdc=36mohm(Typ), Xmohm(Max) Maglayers PR1012 20K_0402_1% Rdown VFB=0.6V Vout=0.6V* (1+Rup/Rdown) =0.6V* (1+13.7/20) Vout=1.011V EMI@ PC1008 680P_0402_50V7K FB=0.6V Note:Iload(max)=3A FB_1.0VSDGPUP PR1011 13.7K_0402_1% +1.0VSDGPUP @ PC1011 22U_0603_6.3V6M EMI@ PR1007 4.7_0603_5% 22U_0603_6.3V6M SY8003ADFC_DFN8_2X2 Rup NC PL1002 1UH_2.8A_30%_4X4X2_F LX_1.0VSDGPUP PC1010 22U_0603_6.3V6M PGND LX PC1013 EN IN PG PC1009 22U_0603_6.3V6M PC1012 68P_0402_50V8J VIN_1.0VSDGPUP PGND SGND @ PJ1001 JUMP_43X79 2 FB +3VALW @ PC1014 0.1U_0402_16V7K PU1002 1VSDGPU_PG 27 PR1008 1M_0402_5% PR1009 10K_0402_5% 27 1 1VSDGPU_EN +1.0VSDGPUP @ PJ1003 JUMP_43X79 2 +1.0VSDGPU 3 4 Compal Secret Data Security Classification Issued Date 2016/11/03 2017/06/14 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_1.0VSDGPU Size Document Number Custom B C D Rev 1.0 FH50Q M/B LA-J621P Date: A Compal Electronics, Inc Monday, November 25, 2019 Sheet E 95 of 100 D D C C Reserve Page B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2017/11/23 2017/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Reserve Page Size Rev 1.0 FH50Q M/B LA-J621P Date: Document Number Monday, November 25, 2019 Sheet 96 of 100 D D C C Reserve Page B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2017/11/23 2017/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Reserve Page Size Rev 1.0 FH50Q M/B LA-J621P Date: Document Number Monday, November 25, 2019 Sheet 97 of 100 Version change list (P.I.R List) Item D Fixed Issue Reason for change Page of for PWR Rev PG# 01 Design Update Solution Change 1.0 84 PQ301 change from 2N7002KW (SB000009Q80) to L2N7002SWT1G (SB00001GE00) Modify List 2019/09/18 Date Phase C 02 03 Design Update Design Update Solution Change Solution Change 1.0 1.0 94 84 86 2019/09/26 2019/10/01 C C 04 05 Design Update Design Update Design Update Solution Change SDLE measure result SDLE measure result 1.0 1.0 1.0 82 98 90 88 2019/10/01 2019/10/07 2019/10/14 C C C 06 Design Update Solution Change 1.0 2019/10/15 C 07 Design Update Thermal team request 1.0 91 92 84 83 Add location PRW28, 10K_0402_1% (SD034100280)at net 'VRAM_VDD_CTL' and pull down PR312 change from 10_1206_5% (SD011100A80) to 10_0805_5% (SD002100A80) PC318 change from 100p_0603_50V (SE024101J80) to 100p_0402_50V (SE071101J80) PC301 change from 1000p_0603_50V (SE025102K80) to 1000p_0402_50V (SE074102K80) PC506,PC507 change from 10u_0603_6.3V (SE000005T80) to 10u_0402_6.3V (SE00000UD00) PC101 change from 100p_0402_50V (SE071101J80) to 100p_0201_50V (SE00000SE00) PR609 change from 24.3K_0402_1% (SD00000AT80) to 24.9K_0402_1% (SD034249280) Add location PC9101,PC9102,PC9103, 22U_0603_6.3V (SE00000M000)at net '+APU_CORE' and '+APU_CORE_SOC' PR806 change from 52.3K_0402_1% (SD034523280) to 60.4K_0402_1% (SD034604280) PC807 change from 270p_0402_50V (SE074271K80) to 390p_0402_50V (SE074391K80) PC830 change from 330p_0402_50V (SE074331K80) to 390p_0402_50V (SE074391K80) Change from Ohm (0_0402_5%, SD028000080) to R-short as below location: PRV20,PRV34,PRV54,PRV56,PRV70,PRV145,PRV146,PRV79,PRV81,PRV84,PRV89,PRV91,PRV94,PRW9,PRW20, PR315,PR317.PR321,PR334, total 19 pcs PR210 change from 16.9K_0402_1% (SD034169280) to 21K_0402_1% (SD034210280) 2019/10/15 PreMP D 08 09 C C 10 11 12 13 14 15 16 B B 17 18 19 20 21 22 23 24 A A Compal Electronics, Inc Compal Secret Data Security Classification 2018/12/18 Issued Date Deciphered Date 2019/12/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_PIR1 Size Document Custom Re v 1.0 FH50Q M/B LA-J621P Date: Number Monday, November 25, 2019 Sheet 98 of 100 Version change list (P.I.R List) Item Fixed Issue Reason for change Page of for PWR Rev PG# Modify List Date Phase 01 02 D D 03 04 05 06 07 08 09 C C 10 11 12 13 14 15 16 B B 17 18 19 20 21 22 23 24 A A Compal Electronics, Inc Compal Secret Data Security Classification 2018/12/18 Issued Date Deciphered Date 2019/12/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_PIR2 Size Document Custom Re v 1.0 FH50Q M/B LA-J621P Date: Number Monday, November 25, 2019 Sheet 99 of 100 A B C D Version change list (P.I.R List) Item Page Title E Page of for HW Date Issue Description Solution Description Phase Rev 10/03 Change source Change SA00004BV00 to SA0000BIO00 for UC64,UC65,UC66 PVT 1.0 10/03 Change source Change SA00000OH00 to SA0000BIP00 for UC4 PVT 1.0 10/03 Change source Change SA00003R000 to SA0000BJI00 for UV2,UV10,UV11 Change RV9 from 100K_0402 to 10K_0402 PVT 37 10/03 Change source Change SA00003R000 to SA0000BJI00 for UV46 Change SE082221J80 to SE074221K80 for CG335 PVT 1.0 42 10/03 Change source Change SE082221J80 to SE074221K80 PVT 1.0 52 10/03 Size reduce Change CM79,CM80 from 10U_0603 to 10U_0402 PVT 1.0 56 10/03 Size reduce Change SE071101J80 to SE00000SE00 for CA26 (0402 -> 0201) PVT 1.0 58 10/03 Size reduce Change SE071101J80 to SE00000SE00 for C1265,C1266,C1279 (0402 -> 0201) PVT 1.0 68 10/03 Size reduce Change source Change SE071101J80 to SE00000SE00 for CM17 (0402 -> 0201) Change SA00000OH00 to SA0000BIP00 for UM5 PVT 1.0 10 78 10/03 Change source Change SE082221J80 to SE074221K80 11 68 PCIE SSD 10/04 12 40 HDMI 10/14 13 66 IEC Themal Sensor 10/23 1 27 for CS129,CS130 for CG336 PVT 1.0 Change UM5,RM135 to @ Change UM28 to pop PVT 1.0 Change footprint,add"-npm" on R756,R765,L2513,L2514,L2515 PVT 1.0 Change RF25 from TMSIEC@ to always pop PVT 1.0 SSD1_PCIE_RST# path change Change footprint for colay 蓋 綠漆 THERMAL1_ALERT# need always PU 1.0 3 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2019/07/24 Deciphered Date 2020/07/24 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title HW PIR Size Document Number Custom A B C D R ev 1.0 FH50Q M/B LA-J621P Date: Monday, November 25, 2019 Sheet E 100 of 100 ... JDIMM1 01 01 00 00b 50h 101 0 00 00b A0h 101 0 00 01b A1h JDIMM2 01 01 00 01b 51h 101 0 00 10b A2h 101 0 00 11b A3h PTP (Synaptics) 00 10 1 100 b 2Ch 01 01 100 0b 58h 01 01 100 1b 59h PTP (ELAN) 00 01 1111b 15h 00 11... RV34) SD028 100 3 80 X76_H4G@ 100 K _04 02_5% SD028 100 3 80 RV28 X76_H4G@ 100 K _02 01_5% SD043 100 3 80 RV26 X76_S4G@ 100 K _04 02_5% RV27 SD028 100 3 80 X76_S4G@ 100 K _04 02_5% SD028 100 3 80 RV36 X76_S4G@ 100 K _02 01_5%... 00 01 00 11b 13h APU Temp (TSI) 01 00 1 100 b 4Ch 100 1 100 0b 98h 100 1 100 1b 99h GPU Temp 100 1 1110b 9Eh Thermal Sensor G781-1 100 1 101 0b 9Ah 100 1 101 1b 9Bh Thermal Sensor IEC 62368-1 100 1 00 00b 90h