Giáo trình Thiết kế logic số - Phần 2 bao gồm 4 phụ lục, cung cấp cho người học những kiến thức về: Thống kê các hàm, thủ tục, kiểu dữ liệu của VHDL trong các thư viện chuẩn IEEE; thực hành thiết kế VHDL; mạch phát triển ứng dụng FPGA; thực hành thiết kế mạch số trên FPGA. Mời các bạn cùng tham khảo.
PHỤ LỤC 313 Phụ lục 1: THỐNG KÊ CÁC HÀM, THỦ TỤC, KIỂU DỮ LIỆU CỦA VHDL TRONG CÁC THƢ VIỆN CHUẨN IEEE Các kiểu liệu hỗ trợ thư viện chuẩn IEEE Tên kiểu BIT BITVECTOR STD_ULOGIC STD_LOGIC STD_ULOGIC_VE CTOR STD_LOGIC_VEC TOR X01 X01Z UX01 UX01Z UNSIGNED SIGNED SMALL_INT CONV_INTEGER CONV_INTEGER SIGNED UNSIGNED SIGNED UNSIGNED Giải thích Thư viện IEEE.STD_LOGIC_1164 STD_ULOGIC STD_LOGIC_VECTOR mức logic chuẩn gồm X, 0, 1, L, H, Z, W, - , U Giống STD_ULOGIC nhƣng đƣợc định nghĩa cách thức giá trị hợp với Chuỗi STD_ULOGIC Chuỗi STD_LOGIC Kiểu STD_LOGIC với giá trị (0, 1, X) Kiểu STD_LOGIC với giá trị (0, 1, X, Z) Kiểu STD_LOGIC với giá trị (0, 1, U, X) Kiểu STD_LOGIC với giá trị (0, 1, U, X, Z) Thư viện IEEE.STD_LOGIC_ARITH Chuỗi STD_LOGICđƣợc xem nhƣ số không dấu Chuỗi STD_LOGIC đƣợc xem nhƣ số có dấu Kiểu INTEGER với giá trị 0, Thư viện IEEE.STD_LOGIC_UNSIGNED STD_LOGIC_VECTOR INTEGER Thư viện IEEE.STD_LOGIC_SIGNED STD_LOGIC_VECTOR INTEGER Thư viện IEEE.NUMERIC_BIT Chuỗi BIT đƣợc xem nhƣ số có dấu Chuỗi BIT đƣợc xem nhƣ số không dấu Thư viện IEEE.NUMERIC_STD Chuỗi STD_LOGICđƣợc xem nhƣ số có dấu Chuỗi STD_LOGIC đƣợc xem nhƣ số không dấu 314 Các hàm thông dụng hỗ trợ thư viện chuẩn IEEE Tên hàm (Đối biến) Giá trị trả Ghi Thư viện IEEE.STD_LOGIC_1164 AND( l : std_ulogic; r : std_ulogic ) UX01 NAND( l : std_ulogic; r : std_ulogic ) UX01 OR( l : std_ulogic; r : std_ulogic ) UX01 NOR( l : std_ulogic; r : std_ulogic ) UX01 XOR( l : std_ulogic; r : std_ulogic ) UX01 XNOR( l : std_ulogic; r : std_ulogic ) UX01 NOT( l : std_ulogic; r : std_ulogic ) UX01 AND( l, r : std_logic_vector ) std_logic_vector NAND( l, r : std_logic_vector) std_logic_vector OR( l, r : std_logic_vector) std_logic_vector NOR( l, r : std_logic_vector ) std_logic_vector XOR( l, r : std_logic_vector) std_logic_vector XNOR( l, r : std_logic_vector) std_logic_vector NOT(( l, r : std_ulogic_vector) std_logic_vector AND( l, r : std_ulogic_vector ) std_ulogic_vector NAND( l, r : std_ulogic_vector) std_ulogic_vector OR( l, r : std_ulogic_vector) std_ulogic_vector NOR( l, r : std_ulogic_vector ) std_ulogic_vector XOR( l, r : std_ulogic_vector) std_ulogic_vector XNOR( l, r : std_ulogic_vector) std_ulogic_vector NOT(( l, r : std_ulogic_vector) std_ulogic_vector rising_edge (SIGNAL s : std_ulogic) BOOLEAN falling_edge (SIGNAL s : std_ulogic) BOOLEAN Is_X ( s : std_ulogic_vector) BOOLEAN Is_X ( s : std_ulogic_vector) BOOLEAN Is_X ( s : std_ulogic) BOOLEAN Thư viện IEEE.STD_LOGIC_ARITH 315 +, - (L, R: SIGNED, SIGNED) +, - (L, R: UNSIGNED, UNSIGNED) +, - (L, R: UNSIGNED, SIGNED) +, - (L: SIGNED, R: INTEGER) +, - (L: UNSIGNED, R: INTEGER) +, - (L: STD_ULOGIC, R: SIGNED) +, - (L : STD_ULOGIC, R: UNSIGNED) +, - (L: SIGNED, R: UNSIGNED) +, - (L: INTEGER, R: SIGNED, UNSIGNED) +, - (L: STD_ULOGIC, R: SIGNED, UNSIGNED) * (L, R: SIGNED, SIGNED) * (L, R: UNSIGNED, UNSIGNED) * (L, R: UNSIGNED, SIGNED) * (L: SIGNED, UNSIGNED, R: SIGNED, UNSIGNED) =, = (L: SIGNED, UNSIGNED, R: SIGNED, UNSIGNED) =, = (L: INTEGER, R: SIGNED, UNSIGNED) SHL(ARG: SIGNED; COUNT: UNSIGNED) SHL(ARG: UNSIGNED; COUNT: UNSIGNED) SHR(ARG: SIGNED; COUNT: UNSIGNED) SHR(ARG: UNSIGNED; COUNT: UNSIGNED) SIGNED UNSIGNED SIGNED SIGNED UNSIGNED SIGNED UNSIGNED STD_LOGIC_VECTOR STD_LOGIC_VECTOR STD_LOGIC_VECTOR SIGNED UNSIGNED SIGNED STD_LOGIC_VECTOR BOOLEAN BOOLEAN SIGNED UNSIGNED SIGNED UNSIGNED Thư viện IEEE.STD_LOGIC_UNSIGNED +, - (L: STD_LOGIC_VECTOR, R: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) +, - (L: STD_LOGIC_VECTOR, R: INTEGER) STD_LOGIC_VECTOR +, - (L: STD_LOGIC_VECTOR, R: STD_LOGIC) STD_LOGIC_VECTOR * (L: STD_LOGIC_VECTOR, R: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) =, = (L: STD_LOGIC_VECTOR, R: BOOLEAN INTEGER) =, = (L: STD_LOGIC_VECTOR, R: BOOLEAN 316 STD_LOGIC_VECTOR) SHL(ARG: STD_LOGIC_VECTOR; COUNT: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) SHR(ARG: STD_LOGIC_VECTOR; COUNT: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) Thư viện IEEE.STD_LOGIC_SIGNED +, - (L: STD_LOGIC_VECTOR, R: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) +, - (L: STD_LOGIC_VECTOR, R: INTEGER) STD_LOGIC_VECTOR +, - (L: STD_LOGIC_VECTOR, R: STD_LOGIC) STD_LOGIC_VECTOR * (L: STD_LOGIC_VECTOR, R: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) =, = (L: STD_LOGIC_VECTOR, R: BOOLEAN STD_LOGIC_VECTOR) =, = (L: STD_LOGIC_VECTOR, R: BOOLEAN INTEGER) SHL(ARG: STD_LOGIC_VECTOR; COUNT: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) SHR(ARG: STD_LOGIC_VECTOR; COUNT: STD_LOGIC_VECTOR STD_LOGIC_VECTOR) Thư viện IEEEE.NUMERIC_BIT +, - (L, R: UNSIGNED) UNSIGNED +, - (L, R: SIGNED) SIGNED +, - (L: NATURAL, R: SIGNED) SIGNED +, - (L: NATURAL, R: UNSIGNED) UNSIGNED +, - (L: INTEGER, R: SIGNED) SIGNED *, /, mod, rem (L, R: UNSIGNED) UNSIGNED *, /, mod, rem (L, R: SIGNED) SIGNED *, /, mod, rem (L: NATURAL, R: UNSIGNED) UNSIGNED *, /, mod, rem (L: INTEGER, R: SIGNED) SIGNED =, = (L: UNSIGNED, R: UNSIGNED) BOOLEAN =, = (L: SIGNED, R: SIGNED) BOOLEAN =, = (L: INTEGER, R: SIGNED) BOOLEAN =, = (L: NATURAL, R: UNSIGNED) BOOLEAN 317 UNSIGNED sll, sla, srl, sra, ror, rol INTEGER UNSIGNED SIGNED sll, sla, srl, sra, ror, rol INTEGER SIGNED SHIFT_LEFT(L: UNSIGNED, R: NATURAL) UNSIGNED SHIFT_LEFT(L: SIGNED, R: NATURAL) SIGNED SHIFT_RIGHT(L: UNSIGNED, R: NATURAL) UNSIGNED SHIFT_RIGHT(L: SIGNED, R: NATURAL) SIGNED ROTATE_RIGHT(L: UNSIGNED, R: UNSIGNED NATURAL) ROTATE_RIGHT(L: SIGNED, R: NATURAL) SIGNED RESIZE(L: UNSIGNED, R: NATURAL) UNSIGNED RESIZE(L: SIGNED, R: NATURAL) SIGNED Thư viện IEEEE.NUMERIC_STD +, - (L, R: UNSIGNED) UNSIGNED +, - (L, R: SIGNED) SIGNED +, - (L: NATURAL, R: SIGNED) SIGNED +, - (L: NATURAL, R: UNSIGNED) UNSIGNED +, - (L: INTEGER, R: SIGNED) SIGNED *, /, mod, rem (L, R: UNSIGNED) UNSIGNED *, /, mod, rem (L, R: SIGNED) SIGNED *, /, mod, rem (L: NATURAL, R: UNSIGNED) UNSIGNED *, /, mod, rem (L: INTEGER, R: SIGNED) SIGNED =, = (L: UNSIGNED, R: UNSIGNED) BOOLEAN =, = (L: SIGNED, R: SIGNED) BOOLEAN =, = (L: INTEGER, R: SIGNED) BOOLEAN =, = (L: NATURAL, R: UNSIGNED) BOOLEAN UNSIGNED sll, sla, srl, sra, ror, rol INTEGER UNSIGNED SIGNED sll, sla, srl, sra, ror, rol INTEGER SIGNED SHIFT_LEFT(L: UNSIGNED, R: NATURAL) UNSIGNED SHIFT_LEFT(L: SIGNED, R: NATURAL) SIGNED SHIFT_RIGHT(L: UNSIGNED, R: NATURAL) UNSIGNED SHIFT_RIGHT(L: SIGNED, R: NATURAL) SIGNED ROTATE_RIGHT(L: UNSIGNED, R: UNSIGNED NATURAL) ROTATE_RIGHT(L: SIGNED, R: NATURAL) SIGNED 318 RESIZE(L: UNSIGNED, R: NATURAL) RESIZE(L: SIGNED, R: NATURAL) UNSIGNED SIGNED Các hàm phục vụ cho q trình mơ kiểm tra thiết kế Tên hàm (Đối biến) Giá trị trả Thư viện IEEE.STD_LOGIC_TEXTIO READ(l : inout LINE, R: out std_ulogic ) std_ulogic R READ(l : inout LINE, R: out std_ulogic, Good: std_ulogic R Boolean ) READ(l : inout LINE, R: out std_ulogic_vector ) std_ulogic_vector R READ(l : inout LINE, R: out std_ulogic_vector, std_ulogic_vector Good: Boolean) R WRITE(l : inout LINE, R: in std_ulogic_vector ) LINE WRITE(l : inout LINE, R: in std_ulogic_vector, LINE Good: Boolean) READ(l : inout LINE, R: out std_logic_vector) std_logic R READ(l : inout LINE, R: out std_logic_vector, std_logic R Good: Boolean) WRITE(l : inout LINE, R: in std_logic_vector, LINE Good: Boolean) HREAD(l : inout LINE, R: out std_ulogic_vector) std_logic R HREAD(l : inout LINE, R: out std_ulogic_vector, std_logic R Good: Boolean) HWRITE(l : inout LINE, R: in std_ulogic_vector, LINE Good: Boolean) HREAD(l : inout LINE, R: out std_logic_vector) std_logic R HREAD(l : inout LINE, R: out std_logic_vector, std_logic R Good: Boolean) HWRITE(l : inout LINE, R: in std_logic_vector, LINE Good: Boolean) OREAD(l : inout LINE, R: out std_ulogic_vector) std_logic R OREAD(l : inout LINE, R: out std_ulogic_vector, std_logic R Good: Boolean) Ghi 319 OWRITE(l : inout LINE, R: in std_ulogic_vector, Good: Boolean) OREAD(l : inout LINE, R: out std_logic_vector) OREAD(l : inout LINE, R: out std_logic_vector, Good: Boolean) OWRITE(l : inout LINE, R: in std_logic_vector, Good: Boolean) Thư viện STD.ENV STOP (STATUS: INTEGER) FINISH (STATUS: INTEGER) RESOLUTION_LIMIT () LINE std_logic R std_logic R LINE PROCEDURE UNSIGNED Delay_length (Bƣớc thời gian sở q trình mơ phỏng) Thư viện IEEE.STD_TEXTIO READLINE (file f: TEXT; L: out LINE) String LINE READ(L:inout LINE; VALUE: out bit; GOOD : BIT VALUE out BOOLEAN) READ(L:inout LINE; VALUE: out bit) BIT VALUE READ(L:inout LINE; VALUE: out bit_vector; bit_vector GOOD : out BOOLEAN) VALUE READ(L:inout LINE; VALUE: out bit_vector) bit_vector VALUE READ(L:inout LINE; VALUE: out BOOLEAN; BOOLEAN GOOD : out BOOLEAN) VALUE READ(L:inout LINE; VALUE: out BOOLEAN) BOOLEAN VALUE READ(L:inout LINE; VALUE: out Charater; Charater GOOD : out BOOLEAN) VALUE READ(L:inout LINE; VALUE: out Charater) Charater VALUE READ(L:inout LINE; VALUE: out INTEGER; INTEGER GOOD : out BOOLEAN) VALUE READ(L:inout LINE; VALUE: out INTEGER) INTEGER 320 READ(L:inout LINE; VALUE: out REAL; GOOD : out BOOLEAN) READ(L:inout LINE; VALUE: out REAL) READ(L:inout LINE; VALUE: out STRING; GOOD : out BOOLEAN) READ(L:inout LINE; VALUE: out STRING) READ(L:inout LINE; VALUE: out TIME; GOOD : out BOOLEAN) READ(L:inout LINE; VALUE: out TIME) SREAD (L : inout LINE; VALUE : out STRING; STRLEN : out NATURAL); OREAD(L:inout LINE; VALUE: out bit_vector; GOOD : out BOOLEAN) OREAD(L:inout LINE; VALUE: out bit_vector) VALUE REAL VALUE REAL VALUE STRING VALUE STRING VALUE TIME VALUE TIME VALUE STRING VALUE bit_vector VALUE bit_vector VALUE trong trong trong trong HREAD(l : inout LINE, R: out bit_vector) Bit_vector R HREAD(l : inout LINE, R: out bit_vector, Good: Bit_vector R Boolean) WRITELINE (file f : TEXT; L : inout LINE) Ghi LINE file WRITE(L : inout LINE; VALUE : in bit) WRITE(L : inout LINE; VALUE : in bit_vector) WRITE(L : inout LINE; VALUE : in BOOLEAN) WRITE(L : inout LINE; VALUE : in CHARACTER) WRITE(L : inout LINE; VALUE : in INTEGER) WRITE(L : inout LINE; VALUE : in REAL) WRITE(L : inout LINE; VALUE : in TIME) SWRITE(L : inout LINE; VALUE : in STRING) OWRITE(l : inout LINE, R: in BIT_VECTOR) 321 HWRITE (l : inout LINE, R: in BIT_VECTOR) Các hàm biến đổi kiểu liệu dùng VHDL Tên hàm (Đối biến) Giá trị trả Thư viện IEEE.STD_LOGIC_1164 TO_BIT(Arg: STD_ULOGIC) BIT TO_BITVECTOR (Arg: STD_LOGIC_VECTOR) BIT_VECTOR BIT_VECTOR TO_BITVECTOR (Arg:STD_ULOGIC_VECTOR) TO_STD_ULOGIC (Arg: BIT) STD_ULOGIC TO_STD_LOGICVECTOR (Arg: BIT_VECTOR) STD_LOGIC_VEC TOR TO_STD_LOGICVECTOR (Arg: STD_LOGIC_VEC STD_ULOGIC_VECTOR) TOR TO_STD_ULOGICVECTOR (Arg: STD_ULOGIC_VE BIT_VECTOR) CTOR TO_STD_ULOGICVECTOR(Arg: STD_ULOGIC_VE STD_LOGIC_VECTOR); CTOR TO_X01(Arg: STD_LOGIC_VECTOR) STD_LOGIC_VEC TOR TO_X01 (Arg: STD_ULOGIC_VECTOR) STD_ULOGIC_VE CTOR TO_X01 (Arg: STD_ULOGIC) X01 TO_X01(Arg: BIT_VECTOR) STD_LOGIC_VEC TOR TO_X01 (Arg: BIT_VECTOR) STD_ULOGIC_VE CTOR TO_X01 (Arg: BIT) X01 TO_X01Z(Arg: STD_LOGIC_VECTOR) STD_LOGIC_VEC TOR TO_X01Z(Arg: STD_ULOGIC_VECTOR) STD_ULOGIC_VE CTOR TO_X01Z(Arg: STD_ULOGIC) X01Z Ghi 322 entity numeric_led is Port ( CLK : in STD_LOGIC; nRESET : in STD_LOGIC; ANOD : out STD_LOGIC_VECTOR (3 downto 0); SEG7 : out STD_LOGIC_VECTOR (7 downto 0) ); end numeric_led; architecture Behavioral of numeric_led is component counter10 IS PORT( clk : in std_logic; reset : in std_logic; clock_enable : in std_logic; count_out : out std_logic_vector(3 DOWNTO 0) ); END component; component clk_div20 IS GENERIC(baudDivide : std_logic_vector(19 downto 0) := x"00000"); PORT( clk_in : in std_logic; clk_out : inout Std_logic ); END component; component scan_digit is Port ( CLK : in STD_LOGIC; ANOD : out STD_LOGIC_VECTOR(3 downto 0); RESET : in STD_LOGIC); end component; component bcd_adder is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); b : in STD_LOGIC_VECTOR (3 downto 0); s1 : out STD_LOGIC_VECTOR (3 downto 0); s2 : out STD_LOGIC_VECTOR (3 downto 0)); end component; component BCD_7seg is Port ( nbcd : in STD_LOGIC_VECTOR (3 downto 0); 402 seg : out STD_LOGIC_VECTOR (7 downto 0)); end component; signal reset, cnt1_enable : std_logic; signal clk0, clk1 : std_logic; signal nbcd0, nbcd1 : std_logic_vector(3 downto 0); signal nbcd2, nbcd3 : std_logic_vector(3 downto 0); signal nbcd : STD_LOGIC_VECTOR(3 downto 0); signal anod_sig, nanod : std_logic_vector(3 downto 0); begin reset