A B C D BLOCK DIAGRAM Model Name : 888M3 PCB No : LA-1121 Revision : 1.0 Mobile Tualatin or Coppermine-T (uFCBGA/uFCPGA) E THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC Thermal Sensor MAX1617MEE CK TITAN ICS9250-38 PAGE12 PAGE PAGE 4,5,6 CPU VID & All reference voltage PAGE PSB CRT & TV-Out CONN PAGE 16 AGP 4X CONN Almador-M GMCH-M AGP Bus Interface BANK 2,3,4,5 625 BGA PAGE 15 SO-DIMM * Memory Bus PAGE 13,14 PAGE 8,9,10,11 IEEE 1394 HUB Interface USB USB & BlueTooth PAGE 27 TI TSB43AB22 PAGE 22 SmartMedia with SD TC6371AF HDD Connector ATA 66/100 PAGE 29 LAN PAGE 20 FAN on controller & TEMP sensing circuit RTL8100-L PAGE 21 Audio CD-DJ OZ163 Rev.C CD-ROM Connector PAGE 20 421 BGA PAGE 30 PAGE 35 ICH3-M PCI BUS PAGE 17,18,19 Mini PCI Socket DC/DC Interface RTC Battery PAGE 28 PAGE 37 LPC CardBus TI PCI1420 PAGE 23 Super I/O LPC47N227 PAGE 25 Slot 0/1 BATTERY Charger PAGE 24 Embedded Controller PAGE 41 NS PC87591 AC'97 CODEC CS4299 PAGE 33 POWER Interface PAGE 31 PAGE 40,42,43,44 BIOS & I/O PORT 1 PAGE 34 Parallel PAGE 26 FIR PAGE 26 FDD PAGE 20 Audio Jack Scan KB PAGE 15 Audio Amplifier PAGE 32 PAGE 32 Title Compal Electronics, inc SCHEMATIC, M/B LA-1121 Size Document Number Custom Rev 1C 401191 (FOR ATL02 / ACL00) Date: A B C D 星星星, 星星星 27, 2001 Sheet E of 87 A B C D E THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC Voltage Rails PIR Power Plane Description S1 S3 S5 VIN Adapter power supply (19V) N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A +VCC_H_CORE Core voltage for CPU ON OFF OFF +VTT 1.2V switched power rail for CPU AGTL Bus ON OFF OFF +1.5V 1.5V power rail ON ON OFF +1.5VS AGP 4X ON OFF OFF +1.8V 1.8V power rail ON ON OFF +1.8VS 1.8V switched power rail ON OFF OFF +2.5V 2.5V power rail ON ON OFF +3VALW 3.3V always on power rail ON ON ON* +3V 3.3V power rail ON ON OFF +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5V 5V power rail ON ON OFF +5VS 5V switched power rail ON OFF OFF +12VALW 12V always on power rail ON ON ON* +12VS 12V switched power rail ON OFF OFF RTCVCC RTC power ON ON ON REV 0.2 Page 5/8 29 Modification toshiba SM+SD function 5/8 32 Modification audio volume control function 5/8 42 ADD system thermal protection 5/14 33 DEL R244 ,Add D44 Page Description REV 0.3 Date 5/23 U8 Vcc plane modifty to +5VALW 5/23 18 DEL R90,R89,R281 5/23 32 R448 change gnd to +5VCD, R479 change +5VCD to gnd 5/23 37 U2.4 link to U20.8 5/23 30 Add R519 5/23 U9.AF19 add R517 link to +1.5VS 5/23 25 Modifty LPC_RST# timing Add U55,D45,R518 5/31 27 JP15.8 connector to U29.57 5/31 25 ADD R520, Add net name BT_DET# to U29.57 5/31 34 Modifty net name ANT_SW to WL_OFF#, ADD R221 5/31 28 Modifty net name RFOFF# to WL_OFF# 5/31 35 DEL R19 Date Page 7/3 16 Description Del L23,R14,R12,R10,R6,R8 7/3 27 ADD C720,C721,C722,C723,C724,C725 7/3 29 IDSEL0 change to PCI_AD26, INTA#/INTB# change to PIRQC#/PIRQD# 7/10 24 Add U58,U59,R531,R532,R533,R534,C718,C719 Interrupts PIRQA Device AGP 4X CONN IDSEL# 7/17 29 Del SD function IEEE 1394 AD16 PIRQA 7/18 29 Change IDSEL to PCI_AD22 CardBus AD20 PIRQA/PIRQB 7/23 21 DEL C15 LAN AD17 PIRQB Mini-PCI AD18 1/4 PIRQC/PIRQD AD22 SD/SM REV 0.5 Date PIRQC/PIRQD Page EC SM Bus2 address Description 8/13 15 Add R544 reserve for sus_stat# and stp_agp# 8/13 29 8/13 35 Add R545 pull-up signal SM_LED to SMC_VCC,Add@ in U62,C729,R486 Change R543 pull-up form SMC_VCC to +5VS 8/13 29 Add R546,R547 signal PCIRST#,CBRST# 8/13 37 Del U2,Q4,R330 8/16 10 Add Signal TV_out_DDC2CCLK,TV_out_DDC2DATA ,VCH_I2CCLK,VCH_I2CDATA,AGP_DDCCLK,AGP_DDCDATA EC SM Bus1 address Device Address Device Address Smart Battery 0001 011X b MAX1617MEE 1001 110X b 8/16 10 Add R551.R552 DEL R225,R235 EEPROM(24C16/02) 1010 000X b OZ163 0011 0100 b 8/16 15 Add RP38,RP39 1011 000Xb Smart Battery 0001 011X b 8/16 16 Add R553,R554,R555 Docking 0011 011X b 8/17 34 Del R29, Add R557, R558 DOT Board XXXX XXXXb 8/17 20 Add R556 (24C04) REV 1.0 ICH3-M SM Bus address Device Address Clock Generator ( ICS9238-50) 1101 0000 SDRAM Select ( 74HC4052 ) 1010 0000 CPU Voltage VID select ( F3565 ) 0110 111Xb REV 0.4 External PCI Devices Description Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF REQ#/GNT# Date Date Page Description 8/31 Q6 RESERVE Date Page Description 9/6 12 Add D47 and R562 REV 1.A Title Compal Electronics, inc SCHEMATIC, M/B LA-1121 Size Document Number Custom Rev 1C 401191 (FOR ATL02 / ACL00) Date: A B C D 星星星, 星星星 27, 2001 Sheet E of 87 A B C D E +VCC_H_CORE H_REQ#[0 4] H_ADS# +1.5VS A#3 A#4 A#5 A#6 A#7 A#8 A#9 A#10 A#11 A#12 A#13 A#14 A#15 A#16 A#17 A#18 A#19 A#20 A#21 A#22 A#23 A#24 A#25 A#26 A#27 A#28 A#29 A#30 A#31 A#32 A#33 A#34 A#35 R1 L3 T1 U1 L1 T4 AA3 REQ#0 REQ#1 REQ#2 REQ#3 REQ#4 RP# ADS# W2 AB3 P3 C14 AF23 AF4 AERR# AP#0 AP#1 BERR# BINIT# IERR# BREQ0# NC NC NC BPRI# BNR# LOCK# HIT# HITM# DEFER# H_REQ#[0 4] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 K1 J1 G2 K3 J2 H3 G1 A3 J3 H1 D3 F3 G3 C2 B5 B11 C6 B9 B7 C8 A8 A10 B3 A13 A9 C3 C12 C10 A6 A15 A14 B13 A12 R331 1.5K R87 10 8 H_BPRI# H_BNR# H_LOCK# A7 C4 C22 AD23 R2 L2 V3 8 H_HIT# H_HITM# H_DEFER# AA2 U2 T3 TUALATIN VCC Address Lines Mobile Tualatin Data Signals Request Signals Error Interface Arbitration Signals Snoop Signals VSS VCC VCC_80 VCC_79 VCC_78 VCC_77 VCC_76 VCC_75 VCC_74 VCC_73 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_D#[0 63] D#0 D#1 D#2 D#3 D#4 D#5 D#6 D#7 D#8 D#9 D#10 D#11 D#12 D#13 D#14 D#15 D#16 D#17 D#18 D#19 D#20 D#21 D#22 D#23 D#24 D#25 D#26 D#27 D#28 D#29 D#30 D#31 D#32 D#33 D#34 D#35 D#36 D#37 D#38 D#39 D#40 D#41 D#42 D#43 D#44 D#45 D#46 D#47 D#48 D#49 D#50 D#51 D#52 D#53 D#54 D#55 D#56 D#57 D#58 D#59 D#60 D#61 D#62 D#63 A16 B17 A17 D23 B19 C20 C16 A20 A22 A19 A23 A24 C18 D24 B24 A18 E23 B21 B23 E26 C24 F24 D25 E24 B25 G24 H24 F26 L24 H25 C26 K24 G26 K25 J24 K26 F25 N26 J26 M24 U26 P25 L26 R24 R26 M25 V25 T24 M26 P24 AA26 T26 U24 Y25 W26 V26 AB25 T25 Y24 W24 Y26 AB24 AA24 V24 H_D#[0 63] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 P6 M6 AC5 AA5 AB6 W5 Y6 U5 U9A H_A#[3 31] VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 H_A#[3 31] E16 VSS_0 R4 VSS_1 E25 VSS_2 G25 VSS_3 J25 VSS_4 L25 VSS_5 N25 VSS_6 R25 VSS_7 U25 VSS_8 W25 VSS_9 AA25 VSS_10 AC25 VSS_11 AF25 VSS_12 AE26 VSS_13 C23 VSS_14 F23 VSS_15 H23 VSS_16 K23 VSS_17 M23 VSS_18 P23 VSS_19 T23 VSS_20 V23 VSS_21 Y23 VSS_22 AB23 VSS_23 AE23 VSS_24 B22 VSS_25 D21 VSS_26 F21 VSS_27 E22 VSS_28 H21 VSS_29 G22 VSS_30 K21 VSS_31 J22 VSS_32 M21 VSS_33 L22 VSS_34 P21 VSS_35 N22 VSS_36 T21 VSS_37 R22 VSS_38 V21 VSS_39 U22 VSS_40 Y21 VSS_41 W22 VSS_42 AB21 VSS_43 AA22 VSS_44 AC22 VSS_45 AE21 VSS_46 B20 VSS_47 D19 VSS_48 AB19 VSS_49 AA20 VSS_50 AC20 VSS_51 AE19 VSS_52 B18 VSS_53 D17 VSS_54 F17 VSS_55 E18 VSS_56 AB17 VSS_57 D22 F22 E21 H22 G21 K22 J21 M22 L21 P22 N21 T22 R21 V22 U21 Y22 W21 AB22 AA21 AC21 D20 F20 E19 AB20 AA19 AC19 D18 F18 E17 AB18 AA17 AC17 D16 F16 E15 AB16 AA15 AC15 D14 F14 E13 AB14 AA13 AC13 D12 F12 E11 AB12 AA11 AC11 D10 F10 E9 AB10 AA9 AC9 D8 F8 E7 AB8 AA7 AC7 D6 F6 E5 H6 G5 K6 J5 N5 T6 V6 +VCC_H_CORE 4 Title Compal Electronics, inc SCHEMATIC, M/B LA-1121 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC 星星星, 星星星 27, 2001 Date: Rev 1C 401191 (FOR ATL02 / ACL00) A B C D Sheet E of 87 B C +VTT +1.8VS +1.5VS 1 H_TRDY# 17 H_A20M# 17 17 H_IGNNE# H_SMI# H_A20M# H_IGNNE# 17 H_STPCLK# 17,43 H_DPSLP# 17 H_INTR 17 H_NMI 17 H_INIT# H_INTR H_NMI H_RESET# W3 Y1 H_DBSY# H_DRDY# 17 17 H_PICD0 H_PICD1 R55 150 10,12 12 H_BSEL0 H_BSEL1 R280 110_1% 2 @0 2 @0 Analog AF13 AF14 THERMDA THERMDC AE12 AF10 AF16 SELFSB0 SELFSB1 EDGECTRLP Mobile Tualatin AD19 AD17 AF20 12 CLK_CPU_APIC C39 @33_0402 R482 1.5K ITP_TRST# +1.5VS +VS_CMOSREF PICD0 PICD1 PICCLK APIC AF22 AE20 AD22 AD21 RP2# RP3# BPM0# BPM1# Debug Break Point AD10 AD7 AD11 AF7 AF15 AF19 AE22 TCK TDI TDO TMS TRST# PREQ# PRDY# AF12 AD5 AE16 CMOSREF_1 CMOSREF_0 RTTIMPDEP R517 200 R68 56.2_1% L5 17,19 PM_CPUPERF# VREF_1 VREF_2 VREF_3 VREF_4 VREF_5 VREF_6 VREF_7 VREF_8 AF21 AB26 H26 A21 AF9 A4 N1 AA1 TESTLO VCC PLL1 PLL2 NC NC NC NC Y4 R5 N3 N2 P1 P5 E1 F1 TESTLO1 CLK0 CLK0# TESTLO AC1 AD1 M1 CLK_HCLK CLK_HCLK# TESTLO2 NC NCHCTRLP TESTHI NC NC NC TESTHI NC Test Access PORT NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 ( ITP ) VCCT VID VTTPWRGOOD NC GHI# Note : GHI# Pull-Up internally TESTLO1 TESTLO2 8P4R_1K +V_AGTLREF +VCC_H_CORE +VTT L30 4.7UH C520 33UF_16V_D2 CLK_HCLK 12 CLK_HCLK# 12 AF18 AD16 AF11 AE8 N24 AE10 E2 R76 14_1% TESTHI1 TESTHI2 P4 AD4 A5 D1 AD13 B1 P26 A11 E3 CPUVTT_PWRGD D26 TUALATIN +VTT +VTT +VTT R41 @10PF DEP#0 DEP#1 DEP#2 DEP#3 DEP#4 DEP#5 DEP#6 DEP#7 VSS_142 VSS_141 VSS_140 VSS_139 VSS_138 VSS_137 VSS_136 VSS_135 VSS_134 VSS_133 VSS_132 VSS_131 VSS_130 R62 150 R53 1 R64 DBSY# DRDY# H_THERMDA H_THERMDC VTT Ref +VTT RP23 TESTHI1 TESTHI2 AE24 AD25 AE25 AC24 AF24 AD26 AC26 AD24 + +1.5VS Data Signals A20M# FERR# FLUSH# IGNNE# SMI# PWRGOOD STPCLK# DPSLP# Compatibility INTR/LINT0 NMI/LINT1 INIT# RESET# F19 E20 C25 A25 AE1 AD2 AB2 Y2 V2 T2 P2 M2 K2 8 +1.5VS AC3 AF6 AF5 AD9 AD3 AB4 AE4 AF8 AD15 AE14 AE6 B15 C1 NC AF17 NC N4 NC GND RS#0 RS#1 RS#2 RSP# Request TRDY# Signals B26 VSS M4 VSS AF26 VSS H_PWRGD H_RS#0 H_RS#1 H_RS#2 VID0 VID1 VID2 VID3 VID4 17 8 AB1 AC2 AE2 AF3 R3 H_FERR# R336 1.5K Y3 V1 U3 M5 W1 A26 VCCT_1 G23 VCCT_2 J23 VCCT_3 L23 VCCT_4 N23 VCCT_5 R23 VCCT_6 U23 VCCT_7 W23 VCCT_8 AA23 VCCT_9 C21 VCCT_10 C19 VCCT_11 AD20 VCCT_12 C17 VCCT_13 AD18 VCCT_14 C15 VCCT_15 C13 VCCT_16 AD14 VCCT_17 C11 VCCT_18 AD12 VCCT_19 C9 VCCT_20 C7 VCCT_21 AD8 VCCT_22 C5 VCCT_23 AD6 VCCT_24 AC23 VCCT_25 AA4 VCCT_26 E4 VCCT_27 G4 VCCT_28 J4 VCCT_29 L4 VCCT_30 AC4 VCCT_31 V4 VCCT_32 AE3 VCCT_33 AF2 VCCT_34 AF1 VCCT_35 AE18 VCCT_36 D5 VCCT_37 E6 VCCT_38 17 R335 3K R325 1.5K R61 56.2_1% Place H_RESET# R3