compal la 5751p r03 schematics

A B C D E 1 Compal Confidential Schematics Document 2 NIWE1 Arrandale with Intel IBEX PEAK-M core logic REV:0.3 4 Issued Date Compal Electronics,Ltd Compal Secret Data Security Classification 2008/03/25 Deciphered Date 2008/04/ Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Cover Sheet Size Document Number Custom Rev 0.3 LA-5751 Date: Thursday, October 29, 2009 Sheet E of 51 A B C D Compal confidential POWER BD: POWER BTN NOVO BTN POWER MANAGE BTN File Name : ZZZ1 Intel Arrandale (UMA/DIS) VRAM 64*16 DDR3*4 14W_PCB_LA5751P ZZZ page23 PCI-E X16 HYN@ Clock Generator E CARD READER BD: ENE UB6250/52 HP JACK MIC JACK CAP SENSOR BD: VOLUME UP VOLUME DOWN MUTE AUDIO ENHANCE BUTTON & LED RTM890N page12 X76_H512 Socket-rPGA989 37.5mm*37.5mm NVidia N11M-GE1 page19~23 level shift IC ASM1442 HDMI CONN DDR3-SO-DIMM X2 BANK 0, 1, 2, page5~9 100MHz 2.7GT/s page25 page24 FDI *8 DMI *4 Dual Channel DDR3-800(1.5V) DDR3-1066(1.5V) page 10,11 UP TO 8G CRT Connector 2Channel Speaker page33 page26 Intel Ibex Peak M LVDS Connector page27 PCI Express Mini card Slot Audio Codec AZALIA Analog MIC_Int page33 CONEXTAN CX20671 page33 FCBGA 951 25mm*25mm 6*PCI-E BUS CMOS Camera 14*USB2.0 page28 page27 PCI Express Mini card Slot BlueTooth CONN 6*SATA serial page 13~18 page37 page28 USB CONN X1(Right) SPI ROM BIOS page13 page37 LPC BUS USB PORT X1(Left) SIM Card page28 EC RTL8103EL/8111DL 10/100/1G LAN New Card X1 ENE KB926D page28 page34 page29 WWAN page28 Int.KBD RJ45 CONN page30 page35 EMC1403 Thermal Sensor SPI ROM page36 EC page31 ENE UB6250/52 HP X 1+ MS/MS MIC_Ext X1 pro/SD/SD pro/mmc/XD page38 ESATA HDD AND USB CONN page37 SATA HDD CONN SATA ODD CONN page32 page35 Compal Secret Data Security Classification 2008/03/24 Issued Date 2008/04/ Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B Card Reader/Audio Jack SB CONN page32 Touch Pad A page37 USB(WWAN) C D Title Compal Electronics, Inc MB Block Diagram Size Document Number Custom Date: Rev 0.3 LA-5751 Thursday, October 29, 2009 Sheet E of 51 A B C D E DDR3 Voltage Rails SMBUS Control Table SOURCE RAM M2 +5VS power plane +5VALW +1.5V +B +3VALW State +3VS SMB_EC_CK1 +1.5VS SMB_EC_DA1 +VCCP SMB_EC_CK2 +CPU_CORE SMB_EC_DA2 +VGA_CORE SMBCLK +1.8VS SMBDATA +0.75VS SML0CLK +1.05VS SML0DATA SML1CLK SML1DATA S0 O O O O S3 O O O X S5 S4/AC O O X X O X X X X X X X S5 S4/ Battery only S5 S4/AC & Battery don't exist @ FUNCTION Structure 45@ BT@ 3G@ CAP@ CMOS@ ESATA@ HDMI@ UMA_HDMI@ X76@ 100@ GIGA@ UMA@ DIS@ Description 45 BOM Blue Tooth function 3G function (WWAN) CAP Sensor function CMOS CAMERA function E-SATA function HDMI function (UMA or DIS) HDMI function (UMA only) X76 BOM 10/100 LAN function GIGA LAN function UMA only (Arrandale) DIS only (Arrandale) KB926 +3VALW KB926 +3VALW PCH +3VALW PCH +3VALW PCH +3VALW N10x Thermal Sensor N10x Cap sensor board X X X X X X X X X X X WLAN CLK CHIP WWAN BATT KE926 SODIMM V X X X X X X X V X X X X X X X +3VALW +3VALW Arrandale(dGPU) V X X V X X X X X X X X X X X X V X X X V X +3VS +3VS +3VALW X V I2C / SMBUS ADDRESSING DEVICE HEX ADDRESS DDR SO-DIMM A0 10100000 DDR SO-DIMM A4 10100100 CLOCK GENERATOR (EXT.) D2 11010010 NON-USE PCIE PORT LIST PORT USB PORT LIST DEVICE PORT 10 11 12 13 WLAN LAN 3G NEW CARD SKU X X +3VS +3VS PCH V +3VS +3VALW V NEW CARD DEVICE RIGHT SIDE LEFT SIDE CMOS LEFT SIDE RIGHT SIDE CARD READER WIRELESS NEW CARD BT 3G DIS@ DIS only Arrandale(iGPU) UMA@ UMA only Compal Secret Data Security Classification 2008/03/24 Issued Date 2008/04/ Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc MB Notes List Size B Date: Document Number Rev 0.3 LA-5751 Thursday, October 29, 2009 Sheet E of 51 A B VGA and DDR3 Voltage Rails C (N11x GPIO) GPIO I/O ACTIVE GPIO0 N/A N/A GPIO1 IN - Hot plug detect for IFP link C GPIO2 OUT H Panel Back-Light brightness(PWM capable) GPIO3 OUT H Panel Power Enable GPIO4 OUT H Panel Back-Light On/Off (PWM) GPIO5 OUT - GPU VID0 GPIO6 OUT - GPU VID1 GPIO7 OUT N/A GPIO8 I/O N/A GPIO9 OUT N/A GPIO10 OUT N/A GPIO11 I/O - GPIO12 IN N/A GPIO13 OUT N/A GPIO14 OUT - GPIO15 IN N/A GPIO16 OUT N/A GPIO17 IN - GPIO18 IN N/A GPIO19 IN N/A D E Performance Mode P0 TDP at Tj = 102 C* (DDR3) Function Description Products GPU (4) Mem (1,5) NVCLK /MCLK (W) (W) (MHz) (V) (A) (W) 2.16 TBD TBD 12.9 12.26 N11M-GE1 64bit 14.02 512MB DDR3 FBVDD (1.5V) NVVDD FBVDDQ PCI Express I/O and (GPU+Mem) (1.05V) PLLVDD (1.5V) (6) (1.8V) I/O and PLLVDD (1.05V) Other (3.3V) (A) (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W) 0.66 0.99 1.3 1.95 530 0.56 84 0.15 140 0.15 38 0.13 Device ID N11M-GE1/LP1 (40nm) 0x0A7D GPIO5 GPIO6 GPU_VID0 GPU_VID1 0 0.8V Deep P12 1 0.85V P8 1.03V P0 VGA_CORE P-State Reserve 10K pull low Reserve 10K pull low PAD Power Sequence The ramp time for any rail must be more than 40us (+3VS) VDD33 PEX_VDD can ramp up any time (1.05VS)PEX_VDD tNVVDD 3 (+VGA_CORE) NVVDD tNV-IFPAB_IOVDD (1.8VS)IFPAB_IOVDD tNV-FBVDDQ (1.5VS) FBVDDQ 4 Compal Secret Data Security Classification 2009/03/16 Issued Date 2010/03/15 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc VGA Notes List Size B Date: Document Number Rev 0.3 LA-5751 Thursday, October 29, 2009 Sheet E of 51 DDR3 Compensation Signals SM_RCOMP0 R567 R566 R565 SM_RCOMP1 SM_RCOMP2 D 2 100_0402_1% 24.9_0402_1% 130_0402_1% Layout Note:Please these resistors near Processor Layout rule：10mil width trace length < 0.5", spacing 20mil D JCPU1B AT23 COMP3 2COMP2 AT24 COMP2 49.9_0402_1% R548 2COMP1 G16 COMP1 R557 2COMP0 AT26 COMP0 AH24 SKTOCC# 49.9_0402_1% TP_SKTOCC# 49.9_0402_1% H_PECI 0_0402_5% H_PECI_ISO R569 +VCCP H_CATERR# R163 R564 AK14 AT15 CATERR# THERMAL +VCCP PECI 68_0402_5% H_PROCHOT# H_PROCHOT# H_THERMTRIP# H_THERMTRIP# AN26 AK15 PROCHOT# THERMTRIP# A16 B16 CLK_CPU_BCLK CLK_CPU_BCLK# BCLK_ITP BCLK_ITP# AR30 AT30 CLK_CPU_ITP CLK_CPU_ITP# PEG_CLK PEG_CLK# E16 D16 CLK_EXP CLK_EXP# DPLL_REF_SSCLK DPLL_REF_SSCLK# A18 A17 BCLK BCLK# CLOCKS 2COMP3 R558 F6 SM_DRAMRST# AL1 AM1 AN1 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 PM_EXT_TS#[0] PM_EXT_TS#[1] AN15 AP15 PM_EXTTS#0 PM_EXTTS#1 PRDY# PREQ# AT28 AP27 XDP_PRDY# XDP_PREQ# TCK TMS TRST# AN28 AP28 AT27 XDP_TCK XDP_TMS XDP_TRST# TDI TDO TDI_M TDO_M AT29 AR27 AR29 AP29 XDP_TDI XDP_TDO R555 DBR# AN25 XDP_DBRESET# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23 XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_BPM#6 XDP_BPM#7 SM_DRAMRST# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] DDR3 MISC R560 20_0402_1% MISC 20_0402_1% 68_0402_5% H_CPUPWRGD PM_DRAM_PWRGD RESET_OBS# AL15 PM_SYNC R190 VCCPWRGOOD_1 0_0402_5% AN14 VCCPWRGOOD_1 R139 VCCPWRGOOD_0 0_0402_5% AN27 VCCPWRGOOD_0 R191 VDDPWRGOOD_R 0_0402_5% AK13 SM_DRAMPWROK AM15 VTTPWRGOOD AM26 TAPPWRGOOD AL14 RSTIN# VTT_POK R185 BUF_PLT_RST# R183 560_0402_5% PLT_RST#_R 1.5K_0402_5% +VCCP PM_EXTTS#0 PAD PAD R561 R562 PM_EXTTS#1 CLK_EXP CLK_EXP# pins unused by Clarksfield on the rPGA989 Package R563 0_0402_5% T19 PM_EXTTS#1_R PAD 2 10K_0402_5% 10K_0402_5% XDP_PREQ# R136 @ 51_0402_1% XDP_TMS R138 @ 51_0402_1% XDP_TDI R556 @ 51_0402_1% XDP_TDO R134 XDP_TCK R57 XDP_TRST# R133 XDP_DBRESET# R137 51_0402_5% @ 51_0402_1% 51_0402_5% @ 1K_0402_5% C +3VS CHECK INTEL DOCUMENT #385422 Debug Port Design Guide Rev1.3 0_0402_5% FROM POWER VTT POWER GOOD SIGNAL AP26 H_PM_SYNC_R 0_0402_5% R187 2 R184 1K_0402_1% VCCP_POK H_CPURST#_R R135 PWR MANAGEMENT +VCCP H_PM_SYNC JTAG & BPM C CLK_CPU_BCLK CLK_CPU_BCLK# T17 T18 R186 750_0402_1% IC,AUB_CFD_rPGA,R1P0 ME@ B +1.5V For Intel S3 Power Reduction For Intel S3 Power Reduction +1.5V DDR3 CONNECTER DRAMRST# DRAMRST# Q27 2N7002_SOT23 PCH GPIO CONTROL DRAMRST_CNTRL_PCH R281 DRAMRST_CNTRL_EC R282 2 750_0402_1% @ R192 3K_0402_1% R300 +5VALW @ S 100K_0402_5% 0.01U_0402_16V7K C338 D R283 0_0402_5% S3_0.75V_EN DRAMRST_CNTRL_R 0_0402_5% EC GPIO CONTROL R610 10K_0402_5% SM_DRAMRST# S VDDPWRGOOD_R D 1.5K_0402_1% MC74VHC1G08DFT2G SC70 5P R194 A @ 0_0402_5% P R195 DRAM_PWRGD A R301 1K_0402_1% U8 Y B G VCCP_POK @ R193 1.1K_0402_1% +3VALW G B S3_0.75V_EN A VCCP_POK G Q42 2N7002_SOT23 Compal Secret Data Security Classification Classification Issued Date 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Arrandale(1/5)-Thermal/XDP Size Document Number Custom Date: Rev 0.3 LA-5751 Friday, October 30, 2009 Sheet of 51 Layout rule：trace length < 0.5" JCPU1A DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 B24 D23 B23 A22 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 D24 G24 F23 H23 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 D25 F24 E23 G23 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] C FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 E22 D21 D19 D18 G21 E19 F21 G18 FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 D22 C21 D20 C18 G22 E20 F20 G19 FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] FDI_FSYNC0 FDI_FSYNC1 FDI_FSYNC0 FDI_FSYNC1 F17 E17 FDI_FSYNC[0] FDI_FSYNC[1] FDI_INT FDI_INT C17 FDI_INT FDI_LSYNC0 FDI_LSYNC1 FDI_LSYNC0 FDI_LSYNC1 F18 D17 Intel(R) FDI JCPU1E FDI_LSYNC[0] FDI_LSYNC[1] EXP_ICOMPI R544 49.9_0402_1% EXP_RBIAS R545 750_0402_1% PCIE_CRX_GTX_N[0 15] PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS B26 A26 B27 A25 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 PCIE_CRX_GTX_P15 PCIE_CRX_GTX_P14 PCIE_CRX_GTX_P13 PCIE_CRX_GTX_P12 PCIE_CRX_GTX_P11 PCIE_CRX_GTX_P10 PCIE_CRX_GTX_P9 PCIE_CRX_GTX_P8 PCIE_CRX_GTX_P7 PCIE_CRX_GTX_P6 PCIE_CRX_GTX_P5 PCIE_CRX_GTX_P4 PCIE_CRX_GTX_P3 PCIE_CRX_GTX_P2 PCIE_CRX_GTX_P1 PCIE_CRX_GTX_P0 PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 PCIE_CTX_GRX_C_N15 PCIE_CTX_GRX_C_N14 PCIE_CTX_GRX_C_N13 PCIE_CTX_GRX_C_N12 PCIE_CTX_GRX_C_N11 PCIE_CTX_GRX_C_N10 PCIE_CTX_GRX_C_N9 PCIE_CTX_GRX_C_N8 PCIE_CTX_GRX_C_N7 PCIE_CTX_GRX_C_N6 PCIE_CTX_GRX_C_N5 PCIE_CTX_GRX_C_N4 PCIE_CTX_GRX_C_N3 PCIE_CTX_GRX_C_N2 PCIE_CTX_GRX_C_N1 PCIE_CTX_GRX_C_N0 C527 C540 C529 C542 C531 C544 C533 C546 C535 C562 C564 C555 C557 C561 C548 C559 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K PCIE_CTX_GRX_N15 PCIE_CTX_GRX_N14 PCIE_CTX_GRX_N13 PCIE_CTX_GRX_N12 PCIE_CTX_GRX_N11 PCIE_CTX_GRX_N10 PCIE_CTX_GRX_N9 PCIE_CTX_GRX_N8 PCIE_CTX_GRX_N7 PCIE_CTX_GRX_N6 PCIE_CTX_GRX_N5 PCIE_CTX_GRX_N4 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_N2 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_N0 PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25 PCIE_CTX_GRX_C_P15 PCIE_CTX_GRX_C_P14 PCIE_CTX_GRX_C_P13 PCIE_CTX_GRX_C_P12 PCIE_CTX_GRX_C_P11 PCIE_CTX_GRX_C_P10 PCIE_CTX_GRX_C_P9 PCIE_CTX_GRX_C_P8 PCIE_CTX_GRX_C_P7 PCIE_CTX_GRX_C_P6 PCIE_CTX_GRX_C_P5 PCIE_CTX_GRX_C_P4 PCIE_CTX_GRX_C_P3 PCIE_CTX_GRX_C_P2 PCIE_CTX_GRX_C_P1 PCIE_CTX_GRX_C_P0 C528 C541 C530 C543 C532 C545 C534 C547 C536 C563 C565 C556 C558 C560 C549 C550 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K PCIE_CTX_GRX_P15 PCIE_CTX_GRX_P14 PCIE_CTX_GRX_P13 PCIE_CTX_GRX_P12 PCIE_CTX_GRX_P11 PCIE_CTX_GRX_P10 PCIE_CTX_GRX_P9 PCIE_CTX_GRX_P8 PCIE_CTX_GRX_P7 PCIE_CTX_GRX_P6 PCIE_CTX_GRX_P5 PCIE_CTX_GRX_P4 PCIE_CTX_GRX_P3 PCIE_CTX_GRX_P2 PCIE_CTX_GRX_P1 PCIE_CTX_GRX_P0 PCIE_CRX_GTX_N15 PCIE_CRX_GTX_N14 PCIE_CRX_GTX_N13 PCIE_CRX_GTX_N12 PCIE_CRX_GTX_N11 PCIE_CRX_GTX_N10 PCIE_CRX_GTX_N9 PCIE_CRX_GTX_N8 PCIE_CRX_GTX_N7 PCIE_CRX_GTX_N6 PCIE_CRX_GTX_N5 PCIE_CRX_GTX_N4 PCIE_CRX_GTX_N3 PCIE_CRX_GTX_N2 PCIE_CRX_GTX_N1 PCIE_CRX_GTX_N0 PCIE_CRX_GTX_P[0 15] AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30 CFG0 CFG3 CFG4 PCIE Lane Numbers Reversed CFG3-PCI Express Static Lane Reversal @ R59 PCIE_CTX_GRX_N[0 15] R547 0_0402_5% @ @ PCIE_CTX_GRX_P[0 15] CFG Straps for PROCESSOR R536 DIS@ 1K_0402_5% FDI_INT R534 DIS@ 1K_0402_5% FDI_LSYNC0 R533 DIS@ 1K_0402_5% FDI_LSYNC1 R535 DIS@ 1K_0402_5% R58 @ 3.01K_0402_1% PCI-Express Configuration Select 1: Single PEG CFG0 0: Bifurcation enabled Not applicable for Clarksfield Processor CFG[1:0] FDI_FSYNC1 R546 0_0402_5% H_RSVD17_R H_RSVD18_R AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16 CFG3 RSVD15 RSVD16 A20 B20 RSVD17 RSVD18 U9 T9 RSVD19 RSVD20 AC9 AB9 RSVD21 RSVD22 RSVD32 RSVD33 AJ13 AJ12 RSVD34 RSVD35 AH25 AK26 RSVD36 RSVD_NCTF_37 AL26 AR2 RSVD38 RSVD39 AJ26 AJ27 RSVD_NCTF_40 RSVD_NCTF_41 AP1 AT2 RSVD_NCTF_42 RSVD_NCTF_43 AT3 AR1 RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57 RSVD58 AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32 RSVD_TP_59 RSVD_TP_60 KEY RSVD62 RSVD63 RSVD64 RSVD65 E15 F15 A2 D15 C15 AJ15 AH15 RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75 AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 RSVD_NCTF_23 RSVD_NCTF_24 J29 J28 RSVD26 RSVD27 A34 A33 RSVD_NCTF_28 RSVD_NCTF_29 C35 B35 RSVD_NCTF_30 RSVD_NCTF_31 VSS 11=1*16 PEG 10=2*8 PEG R61 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86 B19 A19 C1 A3 IC,AUB_CFD_rPGA,R1P0 ME@ DIS@ 1K_0402_5% CFG7 CFG0 R532 1 3.01K_0402_1% FOR ES1 SAMPLE ONLY DIS@ B FDI_FSYNC0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 SA_DIMM_VREF SB_DIMM_VREF RSVD11 RSVD12 RSVD13 RSVD14 RESERVED A24 C23 B22 A21 PCI EXPRESS GRAPHICS DMI_CRX_PTX_N0 DMI_CRX_PTX_N1 DMI_CRX_PTX_N2 DMI_CRX_PTX_N3 DMI D D C R189 0_0402_5% RSVD64_R @ RSVD65_R @ R188 0_0402_5% 1 B AP34 IC,AUB_CFD_rPGA,R1P0 ME@ 3.01K_0402_1% CFG3-PCI Express Static Lane Reversal 1: Normal Operation CFG3 0: Lane Numbers Reversed 15 -> 0, 14 ->1, CFG4 R60 @ 3.01K_0402_1% CFG4-Display Port Presence 1: Disabled; No Physical Display Port attached to Embedded Display Port CFG4 0: Enabled; An external Display Port device is connected to the Embedded Display Port A A Compal Secret Data Security Classification Issued Date 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Arrandale(2/5)-DMI/PEG/FDI Size Document Number Custom Date: Rev 0.3 LA-5751 Friday, October 30, 2009 Sheet of 51 JCPU1D JCPU1C DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 C B A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AC3 AB2 U7 SA_BS[0] SA_BS[1] SA_BS[2] DDR_A_CAS# DDR_A_RAS# DDR_A_WE# AE1 AB3 AE9 SA_CAS# SA_RAS# SA_WE# DDR SYSTEM MEMORY A DDR_A_D[0 63] DDR_B_D[0 63] SA_CK[0] SA_CK#[0] SA_CKE[0] AA6 AA7 P7 M_CLK_DDR0 M_CLK_DDR#0 DDR_CKE0_DIMMA SA_CK[1] SA_CK#[1] SA_CKE[1] Y6 Y5 P6 M_CLK_DDR1 M_CLK_DDR#1 DDR_CKE1_DIMMA SA_CS#[0] SA_CS#[1] AE2 AE8 DDR_CS0_DIMMA# DDR_CS1_DIMMA# SA_ODT[0] SA_ODT[1] AD8 AF9 M_ODT0 M_ODT1 SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] B9 D7 H7 M7 AG6 AM7 AN10 AN13 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] C9 F8 J9 N9 AH7 AK9 AP11 AT13 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] C8 F9 H9 M9 AH8 AK10 AN11 AR13 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_DM[0 7] DDR_A_DQS#[0 7] DDR_A_DQS[0 7] DDR_A_MA[0 15] DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AB1 W5 R7 SB_BS[0] SB_BS[1] SB_BS[2] DDR_B_CAS# DDR_B_RAS# DDR_B_WE# AC5 Y7 AC6 SB_CAS# SB_RAS# SB_WE# SB_CK[0] SB_CK#[0] SB_CKE[0] W8 W9 M3 M_CLK_DDR2 M_CLK_DDR#2 DDR_CKE2_DIMMB SB_CK[1] SB_CK#[1] SB_CKE[1] V7 V6 M2 M_CLK_DDR3 M_CLK_DDR#3 DDR_CKE3_DIMMB SB_CS#[0] SB_CS#[1] AB8 AD6 DDR_CS2_DIMMB# DDR_CS3_DIMMB# SB_ODT[0] SB_ODT[1] AC7 AD1 M_ODT2 M_ODT3 SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] D4 E1 H3 K1 AH1 AL2 AR4 AT8 DDR_B_DM[0 7] DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 D C DDR SYSTEM MEMORY - B D SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] D5 F4 J4 L4 AH2 AL4 AR5 AR8 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] C5 E3 H4 M5 AG2 AL5 AP5 AR7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_DQS#[0 7] DDR_B_DQS[0 7] DDR_B_MA[0 15] B IC,AUB_CFD_rPGA,R1P0 ME@ IC,AUB_CFD_rPGA,R1P0 ME@ A A Compal Secret Data Security Classification Issued Date 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Arrandale(3/5)-DDR III Size Document Number Custom Date: Rev 0.3 LA-5751 Friday, October 30, 2009 Sheet of 51 R132 GFX_IMON 1K_0402_5% DIS@ +CPU_CORE AS NO CONNECT +GFX_CORE JCPU1F JCPU1G UMA@ C159 UMA@ C591 UMA@ 2 C592 UMA@ R559 0_0402_5% DIS@ +VCCP AR25 GFX_VR_EN AT25 AM24 GFX_IMON R141 P10 N10 L10 K10 VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68 J22 J20 J18 H21 H20 H19 @ + 2 2 VCCPLL1 VCCPLL2 VCCPLL3 L26 L27 M26 0_0402_5% PROC_DPRSLPVR G15 VTT_SELECT 1.1V IC,AUB_CFD_rPGA,R1P0 ME@ +1.5V +1.5V_DDR3 J3 2 Modify for cost revew 09/16/2009 C 2 2 2 B For Intel S3 Power Reduction @ VTT_SELECT +1.8VS 1 R56 C170 4.7U_0603_6.3V6K 1.8V C169 10U_0805_6.3V6M POWER H_VID[0 6] 0.6A C168 2.2U_0603_6.3V4Z CPU VIDS GFXVR_EN GFXVR_DPRSLPVR GFXVR_IMON C213 10U_0805_6.3V6M UMA@ C212 10U_0805_6.3V6M 4.7K_0402_5% +VCCP C218 10U_0805_6.3V6M VTT_SELECT H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 PM_DPRSLPVR_R C273 10U_0805_6.3V6M C149 1U_0603_10V4Z AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34 GFX_VR_EN +VCCP C167 1U_0603_10V4Z VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] PROC_DPRSLPVR PSI# VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58 PEG & DMI AN33 C240 10U_0805_6.3V6M PSI# C272 10U_0805_6.3V6M C215 10U_0805_6.3V6M 1K_0402_5% R140 C257 1U_0603_10V4Z VTT0_59 VTT0_60 VTT0_61 VTT0_62 C214 10U_0805_6.3V6M R608 0_0402_5% C255 1U_0603_10V4Z AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1 C258 22U_0805_6.3V6M VTT1_45 VTT1_46 VTT1_47 3A VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 +VCCP K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25 UMA@ GFX_VR_EN GFX_DPRSLPVR GFX_IMON C252 22U_0805_6.3V6M DESIGN GUIDE REV1.1 D GFXVR_VID_0 GFXVR_VID_1 GFXVR_VID_2 GFXVR_VID_3 GFXVR_VID_4 GFXVR_VID_5 GFXVR_VID_6 C268 220U_B2_2.5VM_R35 J24 J23 H25 FDI C211 10U_0805_6.3V6M C210 10U_0805_6.3V6M C209 10U_0805_6.3V6M C208 10U_0805_6.3V6M AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15 AM22 AP22 AN22 AP23 AM23 AP24 AN24 +1.5V_DDR3 +VCCP VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6] (~15MW) MAYBE WASTED C253 1U_0603_10V4Z VAXG_SENSE VSSAXG_SENSE C256 1U_0603_10V4Z 15A VCC_AXG_SENSE VSS_AXG_SENSE C254 1U_0603_10V4Z SENSE LINES C189 GRAPHICS VIDs C207 10U_0805_6.3V6M 2 C190 @ 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 10U_0805_6.3V6M C274 10U_0805_6.3V6M C217 10U_0805_6.3V6M C219 10U_0805_6.3V6M 2 - 1.5V RAILS C191 @ AR22 AT22 DDR3 1 C160 @ VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 GRAPHICS + C200 10U_0805_6.3V6M @ 2 C554 330U_D2_2.5VY_R9M 1 C182 10U_0805_6.3V6M @ C181 10U_0805_6.3V6M 1 C216 10U_0805_6.3V6M 2 C270 10U_0805_6.3V6M 1 C198 10U_0805_6.3V6M C199 10U_0805_6.3V6M C271 10U_0805_6.3V6M IMVP_IMON VCCSENSE VSSSENSE SI4800BDY-T1-E3_SO8 R268 20K_0402_5% VTT_SENSE @ PAD T15 1.5V_DDR3_GATE VCCSENSE VSSSENSE R552 R551 S +1.5V_DDR3 2 2 SUSP R233 220_0402_5% D S Q19 BSS138_NL_SOT23-3 G @ A C325 0.1U_0603_25V7K For Intel S3 Power Reduction +CPU_CORE Compal Secret Data Security Classification 100_0402_1% 100_0402_1% Issued Date 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC IC,AUB_CFD_rPGA,R1P0 ME@ R267 0_0402_5% Q23 2N7002_SOT23 SUSP D G Close to CPU C286 0.1U_0402_10V6K 0_0402_5% VCCSENSE VSSSENSE 0_0402_5% @ C287 0.1U_0402_10V6K 2 S S S G C288 0.1U_0402_10V6K VTT_SENSE VSS_SENSE_VTT B15 A15 R554 R553 D D D D C289 0.1U_0402_10V6K VCC_SENSE VSS_SENSE AJ34 VCC_SENSE AJ35 VSS_SENSE U11 +5VALW AN35 C269 0.1U_0402_10V6K ISENSE JUMP_43X118 +1.5V_DDR3 +1.5V @ H_VTTVID1 = High, 1.05V FOR Auburndale 12 H_VTTVID1 = Low, 1.1V FOR Clarksfiel JUMP_43X118 J2 2 1 CPU A VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 C161 @ AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16 +VCCP CPU CORE SUPPLY B VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 C201 10U_0805_6.3V6M C AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 SENSE LINES D +VCCP 18A 1.1V RAIL POWER 48A BUT A SMALL AMOUNT OF POWER 10U_0805_6.3V6M POWER 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M Title Compal Electronics, Inc Arrandale(4/5)-PWR Size Document Number Custom Date: Rev 0.3 LA-5751 Friday, October 30, 2009 Sheet of 51 CPU CORE +CPU_CORE JCPU1H 2 C571 22U_0805_6.3V6M C572 22U_0805_6.3V6M C577 22U_0805_6.3V6M C583 22U_0805_6.3V6M C578 22U_0805_6.3V6M C584 22U_0805_6.3V6M C573 22U_0805_6.3V6M C574 22U_0805_6.3V6M C579 22U_0805_6.3V6M Inside cavity D 2 + + 2 2 C129 22U_0805_6.3V6M + C87 22U_0805_6.3V6M C90 22U_0805_6.3V6M + C91 22U_0805_6.3V6M between Inductor and socket C164 470U_D2T_2VM 2 C92 470U_D2T_2VM 1 C75 470U_D2T_2VM 2 C76 470U_D2T_2VM 1 C194 10U_0805_6.3V6M 2 C165 10U_0805_6.3V6M 1 C197 10U_0805_6.3V6M 2 C148 10U_0805_6.3V6M 1 C89 10U_0805_6.3V6M 2 C166 10U_0805_6.3V6M 1 C180 10U_0805_6.3V6M 2 C193 10U_0805_6.3V6M 1 C196 10U_0805_6.3V6M 2 C88 10U_0805_6.3V6M 1 C179 10U_0805_6.3V6M C162 10U_0805_6.3V6M C192 10U_0805_6.3V6M IC,AUB_CFD_rPGA,R1P0 ME@ Under cavity VSS 470uF 4.5mohm C NCTF VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 C580 22U_0805_6.3V6M K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9 C163 10U_0805_6.3V6M AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30 C585 22U_0805_6.3V6M VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 C195 10U_0805_6.3V6M B VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 C147 10U_0805_6.3V6M C JCPU1I C568 22U_0805_6.3V6M D AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 AT35 AT1 AR34 B34 B2 B1 A35 VSS_NCTF1_R VSS_NCTF2_R VSS_NCTF3_R VSS_NCTF4_R VSS_NCTF5_R VSS_NCTF6_R VSS_NCTF7_R B IC,AUB_CFD_rPGA,R1P0 ME@ A A Compal Secret Data Security Classification Issued Date 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Arrandale(5/5)-GND/Bypass Size Document Number Custom Date: Rev 0.3 LA-5751 Thursday, October 29, 2009 Sheet of 51 +1.5V 3A@1.5V DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27 C DDR_CKE0_DIMMA DDR_CKE0_DIMMA DDR_A_BS2 DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#0 DDR_A_BS0 DDR_A_MA10 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_A_WE# DDR_A_CAS# DDR_CS1_DIMMA# DDR_A_MA13 DDR_CS1_DIMMA# B DDR_A_D34 DDR_A_D35 DDR_CKE1_DIMMA DDR_CKE1_DIMMA C DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 M_CLK_DDR1 M_CLK_DDR#1 DDR_A_BS1 DDR_A_RAS# M_CLK_DDR1 M_CLK_DDR#1 DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMA# M_ODT0 M_ODT1 DDR_CS0_DIMMA# M_ODT0 M_ODT1 DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39 +VREF_DQ_DIMMA Layout Note: Place near DIMM B +1.5V 2 2 2 + C569 220U_B2_2.5VM_R35 6*0603 10uf (PER CONNECTOR) DDR_A_DM6 VTT(0.75V) = DDR_A_D54 DDR_A_D55 3*0805 10uf 4*0402 1uf VREF = DDR_A_D60 DDR_A_D61 1*0402 0.1uf DDR_A_DQS#7 DDR_A_DQS7 2 2 1U_0603_10V4Z C301 PM_EXTTS#1_R SMB_DATA_S3 SMB_CLK_S3 1U_0603_10V4Z PM_EXTTS#1_R SMB_DATA_S3 SMB_CLK_S3 1*0402 2.2uf 1U_0603_10V4Z 1*0402 0.1uf DDR_A_D62 DDR_A_D63 +0.75VS 1*0402 2.2uf VDDSPD (3.3V)= A +0.75VS 0.65A@0.75V FOX_AS0A626-U4SN-7F ME@ Compal Secret Data Security Classification Issued Date 2008/10/31 Deciphered Date 2009/10/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC C316 0.1U_0402_10V6K C317 0.1U_0402_10V6K C315 0.1U_0402_10V6K C314 0.1U_0402_10V6K C308 @ 10U_0603_6.3V6M 3*330uf / 12m ohm (TOTAL FOR SO-DIMMs) DDR_A_D52 DDR_A_D53 10U_0603_6.3V6M @ C570 VDDQ(1.5V) = DDR_A_D46 DDR_A_D47 C309 DDR_A_DQS#5 DDR_A_DQS5 10U_0603_6.3V6M DDR_A_D44 DDR_A_D45 C300 DDR_A_D30 DDR_A_D31 10U_0603_6.3V6M DDR_A_DQS#3 DDR_A_DQS3 C606 206 DDR_A_D28 DDR_A_D29 C310 G2 DDR_A_D22 DDR_A_D23 1U_0603_10V4Z G1 DDR_A_DM2 C607 205 For Arranale only +VREF_DQ_DIMMA supply from a external 1.5V voltage divide circuit 07/17/2009 DDR_A_D20 DDR_A_D21 1U_0603_10V4Z R571 10K_0402_5% C617 0.1U_0402_10V6K C608 2.2U_0603_6.3V4Z +3VS A C605 DDR_A_D58 DDR_A_D59 R570 10K_0402_5% DRAMRST# DDR_A_D14 DDR_A_D15 10U_0603_6.3V6M DDR_A_DM7 DDR_A_DM1 DRAMRST# C581 DDR_A_D56 DDR_A_D57 D C586 DDR_A_D50 DDR_A_D51 +VREF_DQ_DIMMA R305 1K_0402_1% DDR_A_D12 DDR_A_D13 10U_0603_6.3V6M DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D6 DDR_A_D7 C588 DDR_A_D48 DDR_A_D49 DDR_A_DQS#0 DDR_A_DQS0 10U_0603_6.3V6M DDR_A_D42 DDR_A_D43 DDR_A_MA[0 15] C589 DDR_A_DM5 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 R297 1K_0402_1% DDR_A_DQS#[0 7] 10U_0603_6.3V6M DDR_A_D40 DDR_A_D41 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 DDR_A_DQS[0 7] DDR_A_D4 DDR_A_D5 C355 2.2U_0603_6.3V4Z DDR_A_DQS#4 DDR_A_DQS4 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 C346 0.1U_0402_10V6K DDR_A_D32 DDR_A_D33 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 DDR_A_DM0 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 C347 2.2U_0603_6.3V4Z D C303 0.1U_0402_10V6K 1 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 +1.5V DDR_A_DM[0 7] JDIMM1 DDR_A_D0 DDR_A_D1 DDR_A_D[0 63] DDR3 SO-DIMM A +VREF_DQ_DIMMA +1.5V +VREF_DQ_DIMMA Title Compal Electronics, Inc DDRIII-SODIMM SLOT1 Size Document Number Custom Date: Rev 0.3 LA-5751 Friday, October 30, 2009 Sheet 10 of 51 ON/OFF switchSW1 @ Power Button Power Bottom Board Conn 4pin Cap Sensor Board Conn 6pin ENE SB3534 SMT1-05_4P TOP Side +3VALW J5 JP3 SHORT PADS Bottom Side R272 100K_0402_5% D14 ON/OFFBTN# ON/OFF# 51_ON# PM_BTN# ON/OFF# NOVO_BTN# ON/OFFBTN# PM_BTN# 51_ON# E&T_6905-E04N-00R DAN202UT106_SC70-3 JP1 R3 R2 R1 I2C_INT ESB_DAT ESB_CLK RST# 1 1 10 0_0402_5% I2C_INT_R 0_0402_5% 0_0402_5% +3VS ME@ G Q28 2N7002_SOT23-3 EC_ON EC_ON S @ C1 33P_0402_50V8J 2 1 @ C2 33P_0402_50V8J ACES_85201-08051 ME@ +3VS R302 10K_0402_5% R603 100K_0402_1% PM_BTN# NOVO# 51_ON# D13 NOVO# 2 NOVO_BTN# 51_ON# D20 PJSOT24C 3P C/A SOT-23 @ D19 PJSOT24C 3P C/A SOT-23 @ R296 100K_0402_5% PM_BTN# 3 ON/OFFBTN# NOVO_BTN# +3VALW D +5VS GND GND DAN202UT106_SC70-3 EMI REQUEST 1ST = SCA00000E00 2ST = SCA00000R00 Card Reader/Audio Jack SB CONN JP8 +3VALW PLUG_IN HP_OUTR HP_OUTL PLUG_IN HP_OUTR HP_OUTL MIC_JD EXT_MIC_L EXT_MIC_R MIC_JD EXT_MIC_L EXT_MIC_R USB20_P5 USB20_N5 USB20_P5 USB20_N5 10 11 12 10 11 12 GND GND 13 14 ACES_85201-1205N ME@ Issued Date Compal Electronics,Ltd Compal Secret Data Security Classification 2008/03/25 Deciphered Date 2008/04/ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Audio Jack & SW connector Size Document Number Custom Date: Friday, October 30, 2009 Rev 0.3 LA-5751 Sheet 38 of 51 A B C +5VALW TO +5VS D +3VALW TO +3VS E +1.5V to +1.5VS B+ R202 470_0603_5% @ C134 10U_0805_10V4Z C135 1U_0603_10V4Z B+ D +1.8VS 1 2 100K_0402_5% R312 SUSP +1.5V +VCCP D R88 0_0402_5% Q9 2N7002_SOT23 G +0.75VS S @ Q33 C144 0.1U_0603_25V7K D R313 0_0402_5% SUSP G 2N7002_SOT23S S C278 0.1U_0603_25V7K Q20 2N7002_SOT23 S 5VS_GATE2 R228 15VS_GATE_R 10K_0402_5% D G SUSP S R89 47K_0402_5% SUSP G Q6 2N7002_SOT23 @ R314 470_0603_5% @ D B+ D SUSP G Q16 2N7002_SOT23 @ 3 S R229 20K_0402_5% R87 470_0603_5% @ SI4800BDY-T1-E3_SO8 C276 1U_0603_10V4Z C277 10U_0805_10V4Z 1 1 1 S S S G 2 D D D D C279 10U_0805_10V4Z U4 D S D S D S C127 D G 10U_0805_10V4Z SI4800BDY-T1-E3_SO8 U10 +1.5VS U16 D S D 1 S D S C389 C362 C363 G 10U_0805_10V4Z D 10U_0805_10V4Z 1U_0603_10V4Z 2 SI4800BDY-T1-E3_SO8 +3VS +3VALW +5VS +1.5V +5VALW @ SUSP G Q34 2N7002_SOT23 @ 1.5VS_GATE 1 C373 C361 0.1U_0603_25V7K DIS@ 2 0.1U_0603_25V7K +1.05VS S S D SUSP G Q15 2N7002_SOT23 @ R143 470_0603_5% @ D SUSP G Q40 2N7002_SOT23 S D SYSON# G Q35 2N7002_SOT23 @ R568 22_0603_5% R174 470_0603_5% @ 1 S 3 S D SUSP G Q10 2N7002_SOT23 @ D R342 470_0603_5% @ R142 470_0603_5% @ 2 2 SUSP G Q11 2N7002_SOT23 @ For Intel S3 Power Reduction RTCVREF +5VALW @ R5 100K_0402_5% SYSON SYSON IN 3 IN GND SUSP# OUT SYSON# Q2 DTC124EKAT146_SC59-3 @ OUT Q1 DTC124EKAT146_SC59-3 GND @ R6 100K_0402_5% SUSP R4 100K_0402_5% SUSP 1 +5VALW 4 Compal Electronics, Inc Compal Secret Data Security Classification 2006/08/18 Issued Date Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title DC Interface Size Document Number Custom Date: Rev 0.3 LA-5751 Thursday, October 29, 2009 Sheet E 39 of 51 B C D ACIN PR142 1K_1206_5% 2 VIN PQ26 TP0610K-T1-E3_SOT23-3 PR38 1K_1206_5% PR31 1K_1206_5% PR143 100K_0402_1% PD13 RLS4148_LL34-2 VIN VS ACOFF PQ11 3 51ON-1 1 PD12 LL4148_LL34-2 1 BATT+ 2 IN GND PC91 10U_0603_6.3V6M + +RTCBATT @ MAXEL_ML1220T10 +CHGRTC RB751V-40_SOD323-2 RTC Battery 2CHGRTCIN PC90 1U_0805_25V6K Compal Electronics, Inc Compal Secret Data Security Classification Issued Date 2009/01/06 Deciphered Date 2010/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A +5VALW PQ25 DTC115EUA_SC70-3 JRTC PR123 200_0603_5% OUT PACIN PD8 PR136 47K_0402_5% 2 3.3V VS - PU8 G920AT24U_SOT89-3 PR125 PR124 560_0603_5% 560_0603_5% 2RTCVREF-1 2 G PC16 0.1U_0603_25V7K 51ON-3 RTCVREF +CHGRTC PQ3 SSM3K7002F_SC59-3 1 RTCVREF D PC4 0.22U_0603_25V7K 2 PR16 22K_0402_1% PR17 10K_0402_5% S 51ON-2 PR15 100K_0402_1% 51_ON# PR140 68_1206_5% PR141 PQ4 68_1206_5% TP0610K-T1-E3_SOT23-3 PR122 200_0603_5% CHGRTCP PD2 LL4148_LL34-2 PC98 0.1U_0603_25V7K - PR24 499K_0402_1% + O PU10B LM393DG_SO8 1 P G ACON VIN PD10 RB715F_SOT323-3 PC11 1000P_0402_50V7K PR137 100K_0402_1% MAINPWON PC99 0.01U_0402_25V7K VS 3.3V RTCVREF PR25 2.2M_0402_5% VL PC12 0.01U_0402_25V7K PACIN PR22 499K_0402_1% 2 PD9 LLZ4V3B_LL34-2 PR20 10K_0402_5% 2 B+ PQ12 PR23 205K_0402_1% PR21 10K_0805_5% PACIN O PU10A LM393DG_SO8 DTC115EUA_SC70-3 DTC115EUA_SC70-3 ACIN PR19 10K_0402_5% - PR18 10K_0402_1% 2 + P PC13 0.1U_0402_16V7K PR135 20K_0402_1% VINDE-3 G PR27 22K_0402_1% VINDE-1 2 PR134 84.5K_0402_1% PC14 1000P_0603_50V7K PC97 0.01U_0402_25V7K PRG++ VINDE-2 VIN PR26 1M_0402_1% 2 1 Vin Detector Min typ Max L >H 17.430V 17.901V 18.384V H >L 16.976V 17.262V 17.728V 2 PC5 1000P_0402_50V7K PC6 100P_0402_50V8J PC7 0.1U_0603_25V7K 2 @ 4602-Q04C-09R 4P P2.5 JDCIN PC10 100P_0402_50V8J 1 PL2 SMB3025500YA_2P 2 PF1 7A_24VDC_429007.WRML APDIN1 PC9 1000P_0402_50V7K APDIN PC8 0.1U_0603_25V7K PR138 100K_0402_1% DC030006J00 BATT ONLY Precharge detector Min typ Max L >H 7.196V 7.349V 7.505V H >L 6.138V 6.214V 6.056V Precharge detector Min typ Max L >H 14.991V 15.381V 15.782V H >L 13.860V 14.247V 14.621V VIN PR39 100K_0402_1% A B C Title DCIN & DETECTOR Size Document Number Custom Date: Rev 0.1 Friday, October 30, 2009 D Sheet 40 of 51 A B C D 1 VMB VS PH1 100K_0402_1%_TSM0B104F4251RZ PR84 47K_0402_1% TM-2 TM-1 + O - 1 D S PQ20 SSM3K7002FU_SC70-3 G PU4A LM393DG_SO8 VL PR85 100K_0402_1% PR86 100K_0402_1% + - O G A/D BATT_TEMP P 2 TM-3 PR5 10K_0402_5% +3VALW PC64 1000P_0402_50V7K 1 PR6 6.49K_0402_1% PC63 0.22U_0603_25V7K EC_SMB_DA1 PR88 15.4K_0402_1% TM_REF1 EC_SMB_CK1 MAINPWON PR87 13.7K_0402_1% PR83 47K_0402_1% 1 PC109 0.01U_0402_25V7K VL 2 PC110 1000P_0402_50V7K TYCO_1775789-1 @ PR3 100_0402_1% 1 EC_SMCA EC_SMDA VL BATT+ PL3 SMB3025500YA_2P P PR4 100_0402_1% 2 GND GND G PF2 12A_65V_451012MRL JBATT PC62 0.01U_0402_25V7K VMB2 PH1 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 56 degree C PU4B LM393DG_SO8 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2009/01/06 Deciphered Date 2010/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title BATTERY CONN / OTP Size Date: Document Number Rev 0.1 Thursday, October 29, 2009 D Sheet 41 of 51 B+ P3 P2 PR152 0.02_1206_1% CHG_B+ PJ11 @ JUMP_43X118 PR28 47K_0402_1% 2 1 20 VCOMP CSIP 19 ICM PHASE 18 ACLIM VDDP 15 11 VADJ LGATE 14 GND PGND 13 PR157 2.2_0402_5% BST_CHG PC120 0.1U_0603_25V7K BST_CHGA PD14 RB751V-40TE17_SOD323-2 6251_VDDP DL_CHG 26251_VDD PR163 4.7_0402_5% PC122 4.7U_0805_6.3V6K BATT_OVP + - 4 PR11 @ 105K_0402_1% 2 PR12 100K_0402_1% A PQ38 DTC115EUA_SC70-3 FSTCHG SUSP# PD1 RB715F_SOT323-3 FSTCHG 2007/6/22 Issued Date 2 PR177 @ 0_0402_5% BATT_SEL_EC PQ1A @ 2N7002KDW-2N_SOT363-6 PQ1B @ 2N7002KDW-2N_SOT363-6 A Compal Electronics, Inc Compal Secret Data Security Classification SUSP# 2008/6/22 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PR10 @ 499K_0402_1% - P + PU1A @ LM358DT_SO8 G 6251_DCIN PR139 @ 10K_0402_1% PU1B @ LM358DT_SO8 P PR14 10_0603_5% G PR13 100K_0402_1% P3 TP0610K-T1-E3_SOT23-3 Per cell=3.5V PR176 0_0402_5% BATT-OVP=0.1112*VMB LI-3S :13.5V BATT-OVP=1.5012V VS PQ2 CELLS VCHLIM need over 95mV IREF=0.254V~3.048V PR9 @ 340K_0402_1% DIS CP mode Vaclim=2.39*{(31.6K//514K)/((31.6K//514K)+(21K//514K))}=1.425V Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05) where Vaclim=1.425V, Iinput=4A IREF=1.016*Icharge PR168 PR178 @ 100K_0402_1% @ 100K_0402_1% VS PC100 @0.01U_0402_25V7K CC=0.25A~3A 6251_VDD 3.2935V VMB2 4.35V B 6251_VDD PR1 31.6K_0402_1% 1.882V BATT+ PR171 15.4K_0402_1% 4.2V CHGVADJ C PC105 10U_1206_25V6M BOOT 10 12 UMA CP mode Vaclim=2.39*{(2.26K//514K)/((2.26K//514K)+(21K//514K))}=0.239V Iinput=(1/0.02)((0.05*Vaclim)/2.39+0.05) where Vaclim=0.239V, Iinput=2.75A 0V PC103 10U_1206_25V6M CHLIM 16 CHGVADJ 4V CHG PC106 10U_1206_25V6M DH_CHG 17 Vcell PQ5 2N7002KW_SOT323-3 PR151 0.02_1206_1% PR154 4.7_1206_5% UGATE ISL6251AHAZ-T_QSOP24 B PACIN G S VREF PR2 31.6K_0402_1% Connect to EC A/D Pin CHGVADJ=(Vcell-4)/0.10627 PL5 10U_LF919AS-100M-P3_4.5A_20% CSIN VIN D ICOMP PC121 0.1U_0603_25V7K CSOP PR162 200K_0402_1% 2 21 PQ29 SIS412DN-T1-GE3 _PAK1212-8 CSOP CELLS CSON PC124 0.047U_0402_16V7K PR160 20_0402_5% PR159 PC123 20_0402_5% 0.1U_0402_16V7K PR158 2.2_0402_5% LX_CHG 22 CSON PR161 20_0402_5% PC118 680P_0603_50V7K PR167 100K_0402_1% EN PD3 RB715F_SOT323-3 PC101 @0.01U_0402_25V7K IREF 2 PC1 0.1U_0402_16V7K PR172 21K_0402_1% 6251_VREF 23 PQ31 SI7716ADN-T1-GE3 _PAK1212-8 ACOFF PR174 100_0402_1% 6251_VREF ADP_I PR173 154K_0402_1% ACOFF PC130 @ 100P_0402_50V8J ACSET ACPRN 1 ACOFF VIN PQ32 DTC115EUA_SC70-3 0.01U_0402_25V7K 6.81K_0402_1% 2 1 ACON PQ10 DTC115EUA_SC70-3 PR175 24 PC3 G 6800P_0402_25V7K DCIN S PC131 VDD PQ9 D 2N7002KW_SOT323-3 PC2 0.01U_0402_25V7K PACIN CELLS C PR37 3K_0402_1% 6251_EN PC125 0.1U_0603_25V7K 6251_DCIN 2 S 2 G PR8 PR29 150K_0402_1% PQ8 D 2N7002KW_SOT323-3 PC132 0.1U_0402_16V7K PU11 FSTCHG PACIN D PR7 10K_0402_1% 100K_0402_1% PQ28 DTC115EUA_SC70-3 PR155 10K_0402_1% PC128 2.2U_0603_6.3V6K 1 PD15 RB751V-40TE17_SOD323-2 6251_VDD 2 PC111 2200P_0402_50V7K CSIN CSIP PC113 4.7U_1206_25V6K 2 PQ34 FDS6675BZ_SO8 1 PC107 0.1U_0603_25V7K PR30 200K_0402_1% PQ7 PC114 4.7U_1206_25V6K 2 2 PC112 4.7U_1206_25V6K 2 4 PR145 47K_0402_5% DTA144EUA_SC70-3 D VIN PQ6 FDS6675BZ_SO8 PC15 470P_0603_50V8J PQ27 FDS6675BZ_SO8 Title Size Date: CHARGER Document Number Rev 0.1 Thursday, October 29, 2009 Sheet 42 of 51 ISL6237_B+ PHASE2 PHASE1 16 LG3 23 LGATE2 LGATE1 18 LG5 PGND 22 30 OUT2 OUT1 10 FB1 11 BYP SKIP 29 NC POK2 28 EN_LDO POK1 13 EN1 ILIM1 12 ILM1 ILIM2 31 ILIM2 32 VL @ REF LDOREFIN PC102 0.22U_0603_25V7K PD11 3/5V_EN1 14 3/5V_EN2 27 EN2 GND PC42 0.22U_0603_25V7K PC37 0.1U_0402_25V6 PC36 2200P_0402_50V7K FB5 5V_SKIP 21 PU2 ISL6237IRZ-T_QFN32_5X5 + PC117 150U_B2_6.3VM_R45M C VL 2VREF_ISL6237 PR34 301K_0402_1% PR147 301K_0402_1% B 13/5V_TON PR50 0_0402_5% PR150 @ 0_0402_5% PR149 0_0402_5% PR51 @ 0_0402_5% PR43 0_0402_5% PJ10 +3VALWP 2 1 +3VALW @ JUMP_43X118 2VREF_ISL6237 2 PC28 1U_0603_10V6K 13/5V_NC 0_0402_5% PR33 @ 47K_0402_1% MAINPWON 2VREF_ISL6237 PR32 PC108 0.047U_0402_16V7K RB751V-40_SOD323-2 PC104 0.047U_0402_16V7K PR146 PD4 806K_0603_1% VL B LLZ5V1B_LL34-2 EN_LDO TON PR44 100K_0402_1% 2 1 EN_LDO-1 PR144 200K_0402_1% 2 NC 20 PD5 PC25 10U_1206_25V6M PQ33 SI7716ADN-T1-GE3_PAK1212-8 RB751V-40_SOD323-2 VS PC119 680P_0402_50V7K REFIN2 2VREF_ISL6237 PC22 0.1U_0603_25V7K 25 SW5 SW3 PR156 4.7_1206_5% 1BST5A-1 PR36 @ 61.9K_0402_1% BST5A2 PR40 2.2_0603_5% +5VALWP HG5 17 15V_SNB 15 BOOT1 PC43 0.1U_0603_25V7K FB3 UGATE1 19 PQ13 SIS412DN-T1-GE3_PAK1212-8 PL6 4.7UH_PCMC063T-4R7MN_5.5A_20% BOOT2 LDO VCC UGATE2 24 PC40 1U_0603_10V6K PVCC 2 VIN 26 4.7U_0805_6.3V6K PC23 PC41 3/5V_VCC 1U_0603_10V6K 3/5V_VIN UG3 BST3A PR42 2.2_0603_5% D PR35 0_0402_5% 2 TP PQ30 SI7716ADN-T1-GE3_PAK1212-8 PR148 10K_0402_1% C VL PC115 680P_0402_50V7K 2 BST3A-1 13V_SNB 2 + PR153 4.7_1206_5% PR52 0_0402_5% 33 PL4 4.7UH_PCMC063T-4R7MN_5.5A_20% +3VALWP PC27 0.1U_0603_25V7K PQ14 SIS412DN-T1-GE3_PAK1212-8 5 PC39 2200P_0402_50V7K PC26 10U_1206_25V6M PR41 0_0402_5% PC38 0.1U_0402_25V6 PC21 330P_0402_50V7K PJ4 @ JUMP_43X118 2 1 PC116 150U_B2_6.3VM_R45M ISL6237_B+ B+ D @ PJ12 +5VALWP 2 1 +5VALW @ JUMP_43X118 A A 2009/01/06 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/01/06 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title 3VALW/5VALW Size Document Number Custom Date: Rev 0.1 Thursday, October 29, 2009 Sheet 43 of 51 PJ20 1.5V_IN PU14 TPS51117RGYR_QFN14_3.5x3.5 PC183 4.7U_0805_6.3V6K PC174 2200P_0402_50V7K PC173 0.1U_0402_25V6 PC175 10U_1206_25V6M PC169 10U_1206_25V6M + 1 PR241 4.7_1206_5% +1.5VP PC177 10U_0603_6.3V6M LG_1.5V 15 PC179 @0.1U_0402_16V7K DRVL PGND PGOOD PR243 @ 100K_0402_1% PC181 @ 47P_0402_50V8J 2 PC178 4.7U_0603_6.3V6K GND +5VALW B+ D PC172 220U_B2_2.5VM_R15M V5DRV 10 PR245 7.15K_0402_1% 1.5V_SNB SW_1.5V 1 1.5V_TRIP 11 VFB 12 PC180 680P_0402_50V7K LL TRIP PQ48 SI4686DY-T1-E3_SO8 PL13 1UH_PCMB103E-1R0MS_20A_20% TPCA8028-H_SOP-ADVANCE8-5 1.5V_FB UG_1.5V PQ49 V5FILT 13 VOUT DRVH 3 1.5V_V5FILT VBST TON TP PR242 100_0603_1% +5VALW EN_PSV PC184 @0.1U_0402_16V7K 2BST_1.5V-1 PC182 0.1U_0603_25V7K BST_1.5V PR249 2.2_0603_5% 14 1.5V_EN SYSON PR248 0_0402_5% 2 @ JUMP_43X79 PR247 240K_0402_1% 1.5V_TON D 1.5V_PGOOD PR244 31.6K_0402_1% C C PR246 30.1K_0402_1% VCCP_IN VCCP_TON B+ @ DRVL LG_VCCP PU9 @ TPS51117RGYR_QFN14_3.5x3.5 PC92 4.7U_0805_6.3V6K @ + @ 1 B @ PC135 @ 680P_0402_50V7K PQ40 SI7716ADN-T1-GE3_PAK1212-8 @ 1.05V_PGOOD PR129 13.7K_0402_1% @ @1 PR181 @ 4.7_1206_5% +5VALW PC137 10U_0603_6.3V6M 10 +1.05VSP PC136 220U_B2_2.5VM_R15M V5DRV VCCP_TRIP PR128 @ 23.7K_0402_1% VBST TP PR126 100K_0402_1% SW_VCCP 11 PGOOD PC94 @ 47P_0402_50V8J 12 VFB LL TRIP 5 UG_VCCP VCCP_FB 13 V5FILT DRVH VOUT PGND VCCP_V5FILT EN_PSV TON PL9 @ 2.2UH_PCMC063T-2R2MN_8A_20% 14 15 1 @ VCCP_SNB +3VS GND PC96 0.22U_0402_6.3V6K @ PC93 4.7U_0603_6.3V6K @ B 0.1U_0603_25V7K PR127 100_0603_1% 1@ +5VALW @ VCCP_EN SUSP# PR131 @ PC95 2.2_0603_5% @ BST_VCCP1 2BST_VCCP-1 PR132 @ 100K_0402_1% @ PC138 0.1U_0402_25V6 PC140 10U_1206_25V6M PQ41 SIS412DN-T1-GE3_PAK1212-8 @ PR133 240K_0402_1% 2 @ JUMP_43X79 PC141 2200P_0402_50V7K PJ16 @ PR130 31.6K_0402_1% @ PJ17 @ JUMP_43X79 1 +1.5V PJ21 GND NC VREF NC VOUT NC TP +1.5VP +3VALW 1 +1.5V @ JUMP_43X118 PC151 1U_0402_6.3V6K PJ14 +1.05VSP 2 PJ19 1 +1.05VS +0.75VSP @ JUMP_43X118 1 +0.75VS @ JUMP_43X79 G2992F1U_SO8 +0.75VSP S PQ46 SSM3K7002FU_SC70-3 PC176 0.1U_0402_16V7K PC149 10U_0603_6.3V6M 2009/01/06 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 1 PR240 1K_0402_1% PC147 @ 0.1U_0402_16V7K SUSP D 0.75V_REF PR190 0_0402_5% 20.75V_EN G S3_0.75V_EN VCNTL PR250 0_0402_5% @ A VIN 1 PR239 1K_0402_1% PC146 4.7U_0805_6.3V6K 1 PU13 0.75V_IN 2010/01/06 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title 1.5V/VCCP/0.75V Size Date: Document Number Rev 0.1 Friday, October 30, 2009 Sheet 44 of 51 A PJ3 2 VGA_IN +3VS UG_VGA @ PR47 10K_0402_5% 2 PC185 2200P_0402_50V7K BST_VGA PR48 2.2_0603_5% BST_VGA-1 PC49 0.1U_0603_25V7K +5VALW PC186 0.1U_0402_25V6 PC35 10U_1206_25V6M PC24 10U_1206_25V6M @ JUMP_43X79 D PR49 0_0603_5% D B+ 15 BOOT 13 2 PC20 10U_0603_6.3V6M PC18 10U_0603_6.3V6M + PC19 10U_0603_6.3V6M PC133 330U_D2_2.5VY_R9M 10 + C PR69 42.2K_0402_1% VGA_FB PC55 FSET_VGA9 0.01U_0402_25V7K 1VGA_COMP-1 PR68 22.1K_0402_1% PC17 330U_D2_2.5VY_R9M VO Rds=4.0mΩ PQ36 SI4634DY-T1-E3_SO8 2 PR63 3.6K_0402_1% VGA_FB-1 PR179 1.82K_0402_1% PR71 0_0402_5% +VGASENSE PJ2 +VGA_COREP PR180 5.36K_0402_1% 1 +VGA_CORE @ JUMP_43X118 PR67 6.04K_0402_1% 22P_0402_50V8J PC54 6800P_0402_25V7K PQ37A 2N7002KDW-2N_SOT363-6 PJ13 2 PQ37B 2N7002KDW-2N_SOT363-6 PC129 0.01UF_0402_25V7K PJ606 +1.8VSP B 2 +1.8VS @ JUMP_43X39 1 @ JUMP_43X118 2 1GVID0-1 PR170 10K_0402_1% PR72 10K_0402_5% ISEN_VGA +VGA_COREP @ VFB=0.6V GPU_VID0 B PR169 22.6K_0402_1% GVID1-2 PC127 0.01UF_0402_25V7K 2 PR165 10K_0402_5% 11 1 GPU_VID1 1GVID1-1 PR166 10K_0402_1% PC134 N11M-GE1/LP1 PR620=22.6k GPIO5 GPIO6 GPU_VID0 GPU_VID1 VGA_CORE 0.8V 0 0.85V 1 0.9V FSET FB COMP VGA_COMP C N11M-GE1/LP1 ISEN EN PC51 1U_0402_6.3V6K 12 PQ39 SI4634DY-T1-E3_SO8 PGND PC50 2.2U_0603_6.3V6K 2VGA_EN_2 PR62 2.2K_0402_5% VGA_EN PL7 0.88UH_PCMB103E-R88MS_20A_20% SW_VGA TPCA8030-H_SOP-ADV8-5 PR70 100_0402_5% LG PC52 2.2U_0603_6.3V6K LG_VGA PR164 4.7_1206_5% VCC +VGA_PVCC 1VGA_SNB PU3 ISL6268CAZ-T_SSOP16 14 16 UG PVCC 4 PC126 680P_0402_50V7K VGA_VCC VIN PHASE GND PGOOD PQ35 PR46 4.7_0603_5% VGA_VCC PU6 VIN VCNTL GND NC VREF NC VOUT NC TP 2 A LDO_1.8V_REF A G2992F1U_SO8 +1.8VSP PC78 10U_0603_6.3V6M PQ22 SSM3K7002FU_SC70-3 S 2009/01/06 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification PC77 0.1U_0402_16V7K PR105 1.24K_0402_1% PC76 0.1U_0402_16V7K PC79 1U_0402_6.3V6K 1 D SUSP PR103 100K_0402_1% 2LDO_1.8V_EN G +5VS PR104 1K_0402_1% PC75 4.7U_0805_6.3V6K LDO_1.8V_IN PJ8 @ JUMP_43X39 1 +3VS 2010/01/06 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title VGA_CORE/1.8VS/1.1VS Size Date: Document Number Rev 0.1 Thursday, October 29, 2009 Sheet 45 of 51 D D PJ9 VTT_B+ +5VS SW_VTT PR112 2.2_0603_5% VTT_BOOT-1 PGND 12 ISEN 11 TPCA8030-H_SOP-ADV8-5 PL8 0.56UH_MMD-10CZ-R56M-M1_19A_20% + VTT_SNB PC80 1000P_0603_50V7K + @ PC139 330U_D2E_2.5VM PR107 4.7_1206_5% PR110 10_0402_5% PC82 0.01U_0402_25V7K @ 2 PQ21 TPCA8028-H_SOP-ADVANCE8-5 3 VO 10 Rds=4.0mΩ PQ23 TPCA8028-H_SOP-ADVANCE8-5 PR109 3K_0402_1% VFB=0.6V 1 H_VTTVID1= Low, 1.1V H_VTTVID1= High, 1.05V C VTT_COMP-1 PR121 35.7K_0402_1% VTT_ISEN +1.1V_VCCPP PC74 330U_D2E_2.5VM BOOT LG 13 PC81 2.2U_0603_6.3V6K LG_VTT PC89 6800P_0402_25V7K PC88 22P_0402_50V8J VTT_COMP VTT_SELECT FB PC87 @ 0.1U_0402_16V7K FSET EN COMP VTT_FSET PR113 42.2K_0402_1% VTT_EN-1 PR117 0_0402_5% PC86 2.2U_0603_6.3V6K PR118 22.1K_0402_1% VTT_FB @ 1.05V_PGOOD C B UG PU7 ISL6268CAZ-T_SSOP16 VCC 14 SUSP# PQ24 PR108 4.7_0603_5% VTT_VCC 1 PR106 0_0603_5% VTT_PVCC PVCC VTT_VCC VIN PHASE PGOOD GND PR116 0_0402_5% PC84 0.1U_0603_25V7K +5VALW VTT_BOOT1 UG_VTT 1.1VS_PGOOD VCCP_POK PR114 0_0402_5% 15 PC187 2200P_0402_50V7K PC85 10U_1206_25V6M PC188 0.1U_0402_25V6 PC83 10U_1206_25V6M @ JUMP_43X118 16 PR115 1K_0402_5% 2 B+ PR120 1.58K_0402_1% VTT_FB-1 PR111 0_0402_5% B VTT_SENSE PR119 1.96K_0402_1% PJ15 +1.1V_VCCPP 2 1 +VCCP @ JUMP_43X118 PJ7 2 1 @ JUMP_43X118 PJ1 +1.1V_VCCPP 2 1 +1.05VS @ JUMP_43X118 A A Compal Electronics, Inc Compal Secret Data Security Classification 2009/01/06 Issued Date Deciphered Date 2010/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title +1.1VS_VTT Size Document Number Custom Date: Rev 0.1 Thursday, October 29, 2009 Sheet 46 of 51 D D B+ PJ5 2 VSS_AXG_SENSE ISUM+ 14 15 UG_GFX PL12 0.56UH_MMD-10CZ-R56M-M1_19A_20% @ 62881_VID0 + 2 PH4 10KB_0603_5%_ERTJ1VR103J @ @ @ PR90 11K_0402_1% @ @ PC65 0.1U_0402_16V7K @ @ 0_0402_5% 2 2 2 2 1 1 1 1 @ @ @ @ @ @ @ @ PC70 0.068U_0402_10V6K PR93 @ 3.01K_0402_1% PR94 82.5_0402_1% 2ISUM-3 GFXVR_VID_0 GFXVR_VID_1 GFXVR_VID_2 GFXVR_VID_3 GFXVR_VID_4 GFXVR_VID_5 GFXVR_VID_6 GFXVR_EN PR237 GFXVR_DPRSLPVR PR89 @ 100_0402_1% PC68 @ 0.01U_0402_25V7K ISUM+ 2 PR228 PR229 PR231 PR232 PR233 PR234 PR235 PR236 2ISUM-4 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% B @ PC69 @ 180P_0402_50V8J @ GFXVR_CLKEN# 1 2ISUM-2 PR227 @ 2.61K_0402_1% PC60 @ @ 680P_0402_50V7K 330U_D2_2.5VY_R9M GFX_SN @ + PR81 0_0402_5% PC158 ISUM-1 62881_VID1 @ PR82 3.65K_0402_1% 2 @ PC66 2.2U_0603_6.3V6K PR80 2.2_1206_5% PR225 +5VALW 0_0603_5% 20 @ 19 62881_VCCP 21 1 18 LG_GFX VID2 22 VID3 23 VID4 24 VID5 25 VID6 26 +GFX_COREP PC67 17 330U_D2_2.5VY_R9M 16 LX_GFX 11 10 13 BOOT IMON VIN VDD RTN @ SI4686DY-T1-E3_SO8 GFXVR_PWRGD 62881_VID2 B @ 62881_VID3 @ VID1 62881_VID4 @ VID0 CLK_EN# PR98 8.06K_0402_1% PR238 10K_0402_1% @ 2 @ PR100 17.8K_0402_1% 1GFX_FB-2 2 PC73 150P_0402_50V8J PC170 22P_0402_50V8J VCCP PGOOD @ @ LGATE RBIAS +GFX_COREP PR97 1.91K_0402_1% @ VW 62881_VID5 PC71 100P_0402_50V8J VSSP 62881_VID6 @ @ @ PQ47 PC162 0.22U_0603_16V7K 162881_RBIAS PHASE COMP VR_ON PR230 47K_0402_1% 2BST_GFX1 @ UGATE DPRSLPVR PC171 1000P_0402_50V7K 62881_VW @ PR92 2.2_0603_5% PU5 ISL62881HRZ-T_QFN28_4X4 FB 27 PR99 825K_0402_1% 2GFX_FB-1 62881_COMP C BST_GFX @ VSEN 62881_VR_ON PR226 10K_0402_1% 2@ 62881_FB ISUM+ @ @ ISUM PC72 330P_0402_50V7K @ 62881_DPRSLPVR 28 29 @ PC167 330P_0402_50V7K AGND PR102 +GFX_COREP 10_0402_5% 2 VCC_AXG_SENSE 1 PC166 1000P_0402_50V7K VSS_AXG_SENSE @ 12 62881_VIN @ ISUM- C @ PR224 @ 0_0402_5% @ PQ19 TPCA8028_PSO8 PC165 1U_0603_10V6K @ @ @ @ @ PR101 10_0402_5% GFXVR_IMON PC163 0.22U_0402_6.3V6K 1_0603_5% 62881_VDD PR91 22.6K_0402_1% PR96 1 PC164 0.22U_0603_25V7K PR95 0_0603_5% +5VALW 1 PC161 0.1U_0402_25V6 2 PC160 2200P_0402_50V7K GFX_B+ 1 PC59 10U_1206_25V6M @ JUMP_43X118 PC61 10U_1206_25V6M ISUM- @ PJ18 +GFX_COREP 2 1 +GFX_CORE @ JUMP_43X118 PJ6 A 2 A 1 @ JUMP_43X118 (15A,600mils ,Via NO.= 30) Compal Secret Data Security Classification Issued Date 2009/01/06 Deciphered Date 2010/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title GFX_CORE Size Date: Compal Electronics, Inc Document Number Rev 0.1 Friday, October 30, 2009 Sheet 47 of 51 H H +3VS VGATE CLK_EN# PR199 PR200 PR209 G VR_ON PR76 1K_0402_5% PR77 1.91K_0402_1% 0_0402_5% 0_0402_5% 0_0402_5% G CPU_B+ B+ 10U_0603_6.3V6M VID0 BOOT_CPU1-1 2.2_0603_5% PC144 0.22U_0603_10V7K +5VS PD6 1SS355_SOD323-2 UGATE_CPU1 PQ15 TPCA8030-H_SOP-ADV8-5 @ TPCA8030-H_SOP-ADV8-5 CPU_CSP1 PC148 100U_25V_M PC168 100U_25V_M PC31 10U_1206_25V6M 1 PC30 10U_1206_25V6M 2 CPU_CSN2 PR64 69.8K_0402_1% PH3 100K_0402_1%_TSM0B104F4251RZ 2CPU_SN-1 PR188 28.7K_0402_1% PC159 0.033U_0402_16V7K C TPCA8028-H_SOP-ADVANCE8-5 PC143 680P_0402_50V7K TPCA8028-H_SOP-ADVANCE8-5 3 CPU_CSP1-1 PR185 4.7_1206_5% PQ45 PR186 17.8K_0402_1% PQ44 PC29 10U_1206_25V6M PR182 17.8K_0402_1% CPU_CSP2 PL11 0.36UH_PCMC104T-R36MN1R17_30A_20% D PQ16 PC34 10U_1206_25V6M BOOT_CPU1 PR187 UGATE_CPU1 21 CPU_CSN1 PHASE_CPU1 22 PC32 10U_1206_25V6M 23 H_VID0 H_VID1 H_VID2 H_VID4 H_VID3 H_VID5 PSI# H_VID6 1CPU_SNB2 2 CPU_B+ PC33 10U_1206_25V6M LGATE_CPU1 PC45 2200P_0402_50V7K 24 PR215 PROC_DPRSLPVR PR214 PSI# PR213 H_VID6 PR208 H_VID5 PR207 H_VID4 PR206 H_VID3 PR205 H_VID2 PR196 H_VID1 PR195 H_VID0 PR194 PROC_DPRSLPVR E +VCCP IMVP_IMON PC47 2200P_0402_50V7K PC48 0.1U_0402_25V6 +5VS PR222 69.8K_0402_1% PH2 100K_0402_1%_TSM0B104F4251RZ 2CPU_SN-2 PR183 28.7K_0402_1% PC56 0.033U_0402_16V7K 3 1 PC53 +CPU_CORE 25 20 VID1 19 VID3 VID2 18 17 VID4 16 VID5 15 VID6 14 13 PSI# DRVH1 26 PC142 680P_0402_50V7K TPCA8028-H_SOP-ADVANCE8-5 PC46 0.1U_0402_25V6 VBST1 LGATE_CPU2 TPCA8028-H_SOP-ADVANCE8-5 CPU_IMON 0_0402_5% 2CPU_DPRSLPVR 0_0402_5% CPU_PSI# 0_0402_5% VID6 0_0402_5% VID5 0_0402_5% VID4 0_0402_5% VID3 0_0402_5% VID2 0_0402_5% VID1 0_0402_5% VID0 0_0402_5% 12 DPRSLPVR LL1 IMON DRVL1 VSNS 27 BOOT_CPU2-1 2.2_0603_5% PC145 0.22U_0603_10V7K 1CPU_SNB1 GNDSNS 28 PHASE_CPU2 CPU_CSP2-1 PR184 4.7_1206_5% V5IN PGND BOOT_CPU2 PR189 + F CSN1 UGATE_CPU2 29 DRVL2 PU12 TPS51621RHAR_QFN40_6X6 @ CSN2 30 PL10 0.36UH_PCMC104T-R36MN1R17_30A_20% TPCA8030-H_SOP-ADV8-5 PQ42 LL2 VR_TT# 1 CSP2 THERM CPU_TRIPSEL CPU_OSRSEL 32 31 CPU_PGOOD 33 OSRSEL TRIPSEL CPU_CLK_EN# 34 PGOOD CLK_EN# CPU_VR_ON 35 VR_ON CPU_TONSEL VBST2 CSP1 +5VS 2 2 2 CPU_ISLEW1 36 38 CPU_DROOP 39 37 ISLEW V5FILT TONSEL DRVH2 GND 11 68_0402_5% PQ43 PD7 1SS355_SOD323-2 + PQ17 TPCA8030-H_SOP-ADV8-5 +5VS @ +VCCP H_PROCHOT# PR216 20K_0402_1% PR217 PR53 PR45 12.4K_0402_1% PR212 0_0402_5% VSSSENSE B 10 DROOP CPU_VREF 40 41 VREF GND CPU_THERM 2CPU_VR_TT# 0_0402_5% CPU_VSNS PR65 0_0402_5% PR66 0_0402_5% VCCSENSE @ PC44 0.22U_0402_6.3V6K 2 VSSSENSE C PR198 D UGATE_CPU2 PR197 0_0402_5% CPU_CSN2-1 33P_0402_50V8J CPU_CSN1-1 33P_0402_50V8J CPU_CSP1-2 33P_0402_50V8J CPU_GNDSNS PR79 0_0402_5% CPU_CSP1 PR219 PC153 100P_0402_50V8J 470_0402_1% PC157 PC155 PC154 PC152 MODE PR78 CPU_CSN2 PR221 CPU_CSN1 PR220 PC156 100P_0402_50V8J 470_0402_1% 470_0402_1% CPU_CSP2-2 33P_0402_50V8J 0_0402_5% 470_0402_1% PR210 CPU_CSP2 PR223 @ PQ18 @ PR74 2CPU_MODE1 0_0402_5% PR73 E 0_0402_5% PC57 0.22U_0603_10V7K 249K_0402_1% F @ 0_0402_5% PC150 2.2U_0603_6.3V6K PC58 68P_0402_50V8J PR218 5.11K_0402_1% +3VS CPU_VREF PR75 @ 1K_0402_5% +5VS PL1 HCB4532KF-800T90_1812 H_VID0 1PR61 @ 1K_0402_5% H_VID0 1PR191 1K_0402_5% H_VID1 1PR60 @ 1K_0402_5% H_VID1 1PR192 1K_0402_5% H_VID2 1PR59 1K_0402_5% H_VID2 1PR193 @ 1K_0402_5% H_VID3 1PR58 1K_0402_5% H_VID3 1PR201 @ 1K_0402_5% H_VID4 1PR57 1K_0402_5% H_VID4 1PR202 @ 1K_0402_5% H_VID5 1PR56 @ 1K_0402_5% H_VID5 1PR203 1K_0402_5% H_VID6 1PR55 @ 1K_0402_5% H_VID6 1PR204 1K_0402_5% PROC_DPRSLPVR 1PR54 PROC_DPRSLPVR 1PR211 @ 1K_0402_5% 10K_0402_5% B Clarkfield: VID(0-5):001101 Auburndale: VID(0-5):001110 A A Compal Secret Data Security Classification 2009/01/06 Issued Date Deciphered Date 2010/01/06 Title CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Date: Compal Electronics, Inc Document Number Thursday, October 29, 2009 Rev 0.1 Sheet 48 of 51 Version change list (P.I.R List) Item D Page of for PWR Reason for change PG# Modify List Date Phase D C C 10 B B 11 12 13 14 15 16 A 20081022 17 2009/01/06 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2009/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Title PIR (PWR) Size Document Number Custom Rev 0.1 Date: Thursday, October 29, 2009 Sheet 49 of 51 D C B A NO DATE PAGE MODIFICATION LIST PURPOSE EVT TO DVT P15 Add C638~C645 For UMA HDMI P05 Add test point for BCLK_ITP,BCLK_ITP#,PRDY# For XDP connector P32,P28 Change J6 size & unstuff ODD power control components Disable ODD power control circuit Change J4 size P17 Stuff C262 For UMA CRT P34 Change R291,R294 from +3VALW to +3VS P38 Add R603 pull high to +3VS For PM_BTN# P38 Change JP1 from pin to pin , For LED color changed Change JP8 from 14 pin to 12 pin , unstuff R322 Remove CLK_48M_CR P29,P34 Change EN_WOL to EN_WOL# For identify clearly P34 EC pin26-> EC_FAN_PWM , pin75->PCH_TEMP_ALERT , EC GPIO arrangement pin34->PROCHOT# , pin66->NOVO# 10 P31 Change JP12 pin define For EC FAN control 11 P16 Change U5 pin3,pin5 POWER , GND reversed 12 P15 Add U28 for ICH_POK & VGATE Reserved P12 Unstuff R278,stuff R269 and change U14 to SA00003HQ00 For low power CLK GEN 13 P13 Change U3 from 2MBytes to 4MBytes For 4MBytes SPI ROM for PCH 14 P29 Correct Q17 to P/N:SB000007600 For +3V_LAN power 15 16 P16 Add C646 for BUF_PLT_RST# Reserved for BUF_PLT_RST# overshoot problem P36 Change U9 from 2MBytes to 256KBytes For 256KBytes SPI ROM for EC 17 P03 UMA_HDMI@ , HDMI@ , BT@ , 3G@ , ESATA@ , CMOS@ New BOM structure 18 19 P08 Add R608 For PSI# pull down P37 Delete D18 20 P16 Unstuff R210,R212 Set Boot BIOS Strap to SPI 21 22 P22 Change & stuff R475 to 30K,R51 to 15K For N11M-GE1 QS sample Unstuff R474,R50 P25 23 Unstuff R246 Level shift default setting 24 P39 Change C373 to DIS@ for DIS power sequence P15,P16,P17 Change R436 from 1K to 10K Check list Rev2.0 update 25 Change C447 from 0.1u to 1u Delete R514 Unstuff C493,C494 Reserve R609 27 28 P34 P36 29 30 31 32 33 34 35 36 P14 P38 P13,P34 P12 P13,P20 P36 P37 P27,P32,P37 Add R607 Change LED1,LED3,LED4 to white color LED2 to orang\white color and orage connect to +3VALW Change exp-card from PCIE port to port Unstuff SW1 Change X1,X2 footprint Change C348 to 22p,C349 to 22p Add C647~C650 12p, stuff C370->22p, R331->33 Delete JP6 Change C430,C615 footprint to B2 type Change Q4,Q24,Q32,Q37 footprint to AO3413 D C B Reserved for KB926 SPI STRAP PIN SW BIOS request A For Crystal matching Reserved for RF team SPI ROM socket Title HW PIR Size B Date: Compal Electronics, Inc Document Number LA-5751 Thursday, October 29, 2009 Rev 0.3 Sheet 50 of 51 D C NO DATE PAGE MODIFICATION LIST PURPOSE EVT TO DVT 37 P34 Change C320 to 0805 type 38 P08 Unstuff C268 For CPU VDDQ (DDR3 1.5V rails) Change C252,C258 from 10u to 22u 39 P34 Change ODD_power_on# from U13 pin28 to pin 76 EC GPIO arrangement Add EC_TACH on U13 pin28 to JP12 40 P31 Change U20 to EMC1403, add C651 Change thermal sensor solution to EMC1403 41 P05 Add Q42,R610 Reserve for +0.75V enable option 42 P34,P35 Add C652,C653,C654 Reserve for NUM_LED#,CAPS_LED# ESD request 43 P34 Add R611,R612,R613 For EC_FAN_PWM, EC_TACH D NO DATE PAGE MODIFICATION LIST PURPOSE DVT TO PVT P34 Reseve R614,R615 EC_ID to identify KB926 D or E P34 Stuff R607 KB926 SPI STRAP PIN P33 Stuff C632~C635 EMI request P16 Stuff C646 For PLT_RST# singnal quality P37 Add R616 100K, change R304 to 100K, C353 to 0.1u For +3VS_BT power on rising time P37 Changed R304 pin1 from +5VS to +5VALW For +3VS_BT power on leakage P5 Stuff R283, C338 0.01u For S3 power reduction P31 Add U29 Colay EMC2103/EMC1403 thermal sensor C B B A A Title Compal Electronics, Inc HW PIR Size B Date: Document Number LA-5751 Thursday, October 29, 2009 Rev 0.3 Sheet 51 of 51 ... CLKOUT_PCIE0P PCIECLKRQ0# / GPIO73 WLAN WLAN_CLKREQ1# +3VS B LAN CLK_PCIE_LAN# CLK_PCIE_LAN CLKREQ_LAN# +3VS 3G 0_0402_5% CLK_PCIE_WLAN1#_R 0_0402_5% CLK_PCIE_WLAN1_R R454 10K_0402_5%... CLKREQB PERSTB 46 RSET ISOLATEB 26 28 LANWAKEB ISOLATEB LAN_XTALI LAN_XTALO 41 42 CKTAL1 CKTAL2 FB12 SROUT12 EVDD12 DVDD12 DVDD12 DVDD12 AVDD12 +3VS R204 1K_0402_5% ISOLATEB R205 15K_0402_5% MDIP0... Port attached to Embedded Display Port CFG4 0: Enabled; An external Display Port device is connected to the Embedded Display Port A A Compal Secret Data Security Classification Issued Date 2008/10/31