compal la 733 r4c schematics

A B C D E 1 2 Hurricane 1.6 N32N LA-733 REV 4A SCHEMATIC DOCUMENT uPGA2 COPPERMINE with Geyserville 3 4 Compal Electronics, inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE B USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC Date: A B C D SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet E of 47 A B Compal confidential Model Name : N32N Board Name : LA-733 HP Model Name : Hurricane 1.6 C Revision History Date:06/28/2000 Date:12/20/2000 Date:02/02/2001 Date:03/05/2001 Rev#: Rev#: Rev#: Rev#: D E 2.0 description: MP-test for H1.5 3.0 description: C1-test for H1.6 4.0 description: C2-test for H1.6 4A description: C3-test for H1.6 1 SPR CONN Gerserville Tech page 33 page Coppermine (uPGA2) CPU HCLK_CPU page 3,4,5 HA#(3 31) Y1 HD#(0 63) 14.318MHZ Clock Generator Buffer PCLK_MTXC CRT CONN page 24 440ZXM 14M_3V MD(0 63) Dot-Matrix, Button Board, FDD, Touch-PAD CONN.page 32 14M_5V PCLK_DOCK PCLK_PCM +3V +3VS AD(0 31) CLK_SDRAM(0 3) 144Pin S.O.Dimm Socket page 11,12 CardBus TI1420 Solt1/2 ESS ES1988 page 15,16 page 31 page 10 DCLKO AGP Bus page 23 Mini PCI Socket DCLKWR page 7,8,9 14M_3V MA(0 13) VGA Board CONN HCLK_CPU IDE (HDD/CR-ROM) PCLK_PIIX4 +3V PCI BUS Audio CD-DJ OZ163 PIIX4M page 20 page 21,22 CLK_48MHZ 14M_3V page 13,14 page 17 page 28 EQ & Speaker AMP +3V / +3VS (5VS Tolerant) USB Port and Port SA(0 15) SD(0 15) PCLK_SIO ISA BUS page 18,19 Super IO 37N869 page 27 PIO 14M_5V RESET CKT page 32 page 28 FIR FDD SMBus page 25 SUS_ON page 34 page 28 KBD page 26 page 29 PS/2 page 29 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B Power CKT DC/DC MAX1632 MAX1711 SM Bus Battery Charge Title B Date: D Compal Electronics, inc SCHEMATIC, M/B LA-733 Size page 35 C page 34,36,37,38 page 29 BIOS A page 39 page 30 page 25,26 Touch Pad CONN SIO page 28 Screw Hole DC-DC Interface & RTC KeyBoard 87570 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet E of 47 HCLK AA10 AC9 A6 INIT# FLUSH# RESET# AA18 AB21 Y20 PICCLK PICD0 PICD1 COPPERMINE SOCKET V20 T21 U21 R21 V18 P21 P20 U19 AA3 T1 PC Compatibility Signals Debug & Test Signals Thermal Diode Error Signals APIC 21 C360 15PF T4 U4 C6 R1 TESTHI TESTLO1 TESTLO2 1K R89 CPURST# +3V R248 1 R95 1K 56.2_1% 10K C281 1UF U25 Change value by Charles at 6/22 SMC 5,20,25,26,32,33,38 SMD 5,20,25,26,32,33,38 ATF# 26 NE1617DS Change value by Charles at 6/22 16 15 14 13 12 11 10 R255 1K +VCPU_IO R275 R262 10K +3V +VCPU_IO RP25 TDI TDO @1K R82 TCK @1K R273 TMS TRST# 1K PREQ# IERR# FLUSH# SLP# RP2 8P4R-1.5K TCK TDI TMS 8P4R-1K Signal name +3VS GT_A20M# @150 R80 @150 R277 THERMDC NC STBY SMBCLK NC SMBDATA ALERT ADD0 NC C279 2200PF R256 +3V 1K NC VCC DXP DXN NC ADD1 GND GND 2 THERMDA BNR# BPRI# BREQ0# HLOCK# R85 1.5K GT_IGNNE# PWRGD_CPU GT_SMI# TCK TDO TDI TMS TRST# PREQ# +VCPU_IO 1.5K R92 +VCPU_IO FERR_CPU# R282 33 BNR# BPRI# BREQ0# LOCK# THERMDC THERMDA DEFER# HIT# HITM# IERR# DEP0# DEP1# DEP2# DEP3# DEP4# DEP5# DEP6# DEP7# DBSY# DRDY# Arbitration Phase Signals +VCPU_IO R77 HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55 HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63 AD20 H4 AA17 G4 AD19 AD17 Y5 N5 TESTHI TESTLO1 TESTLO2 RTTIMPEDP TESTP1 TESTP2 TESTP3 TESTP4 1 2 RSVD AB19 BCLK R64 1K Snoop Phase Signals D10 D11 C7 C8 B9 A9 C10 B11 C12 B13 A14 B12 E12 B16 A13 D13 D15 D12 B14 E14 C13 A19 B17 A18 C17 D17 C18 B19 D18 B20 A20 B21 D19 C21 E18 C20 F19 D20 D21 H18 F18 J18 F21 E20 H19 E21 J20 H21 L18 G20 P18 G21 K18 K21 M18 L21 R19 K19 T20 J21 L20 M19 U18 R18 FLUSH# CPURST# CPURST# Execution Control Signals D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15# D16# D17# D18# D19# D20# D21# D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# R109 10K 1 STPCLK# SLP# GT_CPUINIT# L2 M2 Debug Break Point LINT0/INTR LINT1/NMI M3 R2 Response Phase Signals AC11 AB12 7,10 HCLK PLL1 PLL2 Request Phase Request GT_STPCLK# HCLK AA16 H-PBGA 495 Ball GT_INTR GT_NMI SLP# Data Phase Signals Coppermine AB18 AC19 EDGCTRLP Default Mode Software Debug Mode TDI 1K PULL-DOWN 150 PULL-UP TO +CPU_IO TCK 1K PULL-DOWN 1K PULL-UP TO +CPU_IO TMS 1K PULL-DOWN 1K PULL-UP TO +CPU_IO TRST# 1K PULL-DOWN X X 150 PULL-UP TO +CPU_IO TDO FERR# 13 Q10 2SC2412K BPM1# BPM0# BP3# BP2# 110_1% W19 W21 Y21 AA21 RTTIMPEDP R249 1 RS0# RS1# RS2# RSP# TRDY# Geyserville AA15 THERMDA AB16 THERMDC U1 AA2 W1 Y1 U2 BSEL1 AB10 SMI# V5 PWRGOOD AC13 IGNNE# AC12 FERR# AD10 A20M# ADS# 56.2_1% Data Phase Signals Address Lines R75 BSEL0 1.5K R250 CMOS Test Inputs W20 PRDY# AB20 PREQ# AA14 TRST# AD14 TMS AD13 TDI AC15 TDO AA11 TCK HTRDY# HTRDY# AB2 01UF +VCPU_IO R276 DBSY# DRDY# Add CAP by Charles at 6/22 C552 AERR# AP0# AP1# BERR# BINIT# IERR# RS#[0 2] RS#0 RS#1 RS#2 REQ0# REQ1# REQ2# REQ3# REQ4# RP# + AA1 AB1 Y2 E6 V21 AD9 RS#[0 2] T2 V4 V2 W3 W5 W2 TESTLO2 Analog DEFER# HIT# HITM# HADS# A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16# A17# A18# A19# A20# A21# A22# A23# A24# A25# A26# A27# A28# A29# A30# A31# A32# A33# A34# A35# GHI# BSEL0 BSEL1 HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 L3 K3 J2 L4 L1 K5 K1 J1 J3 K4 G1 H1 E4 F1 F4 F2 E1 C4 D3 D1 E2 D5 D4 C3 C1 B3 A3 B2 C2 A4 A5 B4 C5 U3 V1 Y4 HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18 HA19 HA20 HA21 HA22 HA23 HA24 HA25 HA26 HA27 HA28 HA29 HA30 HA31 EDGECTRLP U7A HD[0 63] HREQ#[0 4] HA[3 31] HD[0 63] HREQ#[0 4] HA[3 31] AA12 AB15 TESTLO1 TESTHI RTTIMPEDP +VCPU_IO L7 LQG21N4R7K10 C107 10UF_10V_1206 LO/HI# CPU_LO/HI# EDGCTRLP BSEL1 BSEL0 R104 +VCPU_IO 1K Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE B USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC Date: Compal Electronics, inc SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet of 47 A B C D E +VCPU_IO R81 1K_1% VGTLREF VGTLREF 2 A15 A16 A17 C14 D8 D14 D16 E15 G2 G5 G18 H3 H5 1 2 1000PF 2 C324 1 VCLKREF C104 2 1UF +VCPU_IO C66 C282 1UF + C89 220U_TPB_4V 1 C68 2 2 2 C67 1000PF.01UF 1UF C288 C287 C91 1000PF.01UF 1000PF.01UF 1UF 1 C338 C344 1 Change value by Charles at 6/24 +VCPU_IO 1000PF.01UF 1UF 1UF C555 C284 + 1UF 150UF_TPC_4V C553 C554 C64 1000PF.01UF 1UF C63 C59 C60 M6 M17 N6 N17 P1 P6 P17 R6 R17 T6 T17 U6 U17 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 W6 W7 W8 W9 W10 W11 W12 W13 VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT 1UF C61 C62 1 Change value by Charles at 6/24 2 C79 1UF 2 2 C292 C364 C349 C350 C299 10UF_10V_1206 10UF_10V_120610UF_10V_1206 10UF_10V_1206 10UF_10V_1206 10UF_10V_1206 10UF_10V_1206 C354 1000PF 1 2 1 +VCC_CORE C309 C58 VCMOSREF R93 2K_1% 220UF_TPB_4V 220UF_TPB_4V +VCPU_IO C94 + H-PBGA 495 Ball AD8 AD7 AD6 AC8 AC7 AC6 AB8 AB7 AB6 AA8 AA7 AA6 Y8 Y7 Y6 W17 W16 W15 W14 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 H6 H17 K6 K17 L6 L17 J6 J17 10UF_10V_1206 C109 + 10UF_10V_1206 1 C103 + 2 220UF_TPB_4V C366 + 1 C98 + Coppermine VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT VCCT 150UF_TPB_6.3V 150UF_TPB_6.3V +VCC_CORE 1UF Change value by Charles at 6/24 VCLKREF C329, C315, C357, C94, C98, C109 Change from TPC to TPB for cost down C357 + C291 R96 2K_1% C341 1UF C334 1000PF 1 2 C328 1UF 01UF +VCLK C315 + C319 1UF C70 R278 2K_1% 2 150UF_TPB_6.3V C329 + C313 1000PF VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC J5 M4 M5 P3 P4 AA5 AA19 AC3 AC17 AC20 AD15 2 H8 H10 H12 H14 H16 J7 J9 J11 J13 J15 K8 K10 K12 K14 K16 L7 L9 L11 L13 L15 M8 M10 M12 M14 M16 N7 N9 N11 N13 N15 P8 P10 P12 P14 P16 R7 R9 R11 R13 R15 T8 T10 T12 T14 T16 U7 U9 U11 U13 U15 1 +VCC_CORE 1 C305 1UF 2 1UF 2 1UF 1UF C108 1UF C339 1 1 C100 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 C343 C65 1000PF 01UF +VCC_CORE C93 1UF VCMOSREF 1 C85 1UF C327 1UF C333 1000PF C304 1UF 1 2 C303 1UF 1 2 C302 1UF C73 R279 1K_1% +VCC_CORE C312 1000PF C57 1000PF 01UF +VCPU_IO NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 AA9 AD18 P2 CLKREF VREF VREF VREF VREF VREF VREF VREF VREF +VCC_CORE CMOSREF CMOSREF 1UF U7B C318 01UF C75 1UF C69 1 1UF C84 E5 E16 E17 F5 F17 U5 Y17 Y18 1UF C92 C332 1UF C326 1UF C317 1000PF 2 C311 1UF 1 C310 01UF C316 1UF C325 1UF 1 C331 01UF 2 C56 R79 2K_1% VCLKREF VGTLREF +VCC_CORE VCMOSREF COPPERMINE SOCKET +VCC_CORE 10UF_10V_1206 C298 1 C300 10UF_10V_1206 C361 10UF_10V_1206 +VCC_CORE 2 Change value by Charles at 12/20 Change by Charles at 9/2 Compal Electronics, inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE B USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC Date: A B C D SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet E of 47 B VID[0 4] C D U7C VID[0 4] 36 E A2 A7 A8 A12 A21 B1 B5 B6 B7 B8 B10 B15 B18 C9 C11 C15 C16 C19 D2 D6 D7 D9 E3 E7 E8 E9 E10 E11 E13 E19 F3 F6 F7 F8 F9 F10 F11 F12 F13 A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AD21 AD16 AD5 AD4 AD3 AD2 AD1 AC21 AC18 AC16 AC14 AC10 AC5 AC4 AC2 AC1 AB17 AB14 AB13 AB11 AB9 AB5 AB4 AB3 AA20 AA13 AA4 Y19 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y3 W18 W4 CPU_VID2 CPU_VID1 CPU_VID0 CPU_VID3 CPU_VID4 2 3,20,25,26,32,33,38 SMD 12,13 SDAP4 +3V 2 L@8P4R-4.7K VID4 L@4.7K Add by Charles at 3/27 to reserved for LA733L I-0 I-1 I-2 I-3 I-4 L@8P4R-0 R69 L@0 CPU_VID4 10 ASEL WP Non_Mux_Out Mux_Sel 17 16 15 14 13 12 11 VID0 VID1 VID2 VID3 VID4 Y-0 Y-1 Y-2 Y-3 Y-4 Level GND LN_.1UF 19 18 R59 LN_0 R265 LN_0 D LN_FM3560 VR_HI/LO# H-PBGA 495 Ball VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VID0 VID1 VID2 VID3 20 Coppermine F14 F15 F16 F20 G3 G19 H2 H7 H9 H11 H13 H15 H20 J4 J8 J10 J12 J14 J16 J19 K2 K7 K9 K11 K13 K15 K20 L5 L8 L10 L12 L14 L16 L19 M7 M9 M11 M13 M15 M20 N2 N3 N4 V19 V3 U20 U16 U14 U12 U10 U8 T19 T18 T15 T13 T11 T9 T7 T5 T3 R20 R16 R14 R12 R10 R8 R5 R4 R3 P19 P15 P13 P11 P9 P7 P5 N20 N19 N18 N16 N14 N12 N10 N8 VCC3 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 R58 LN_0 SCL SDA Override# RP1 R461 C286 U27 R57 @0 3,20,25,26,32,33,38 SMC 12,13 SCKP4 RP65 COPPERMINE SOCKET Q5 G S LN_SI2302DS +3V R68 LN_0 R67 @0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ADDRESS: ASEL = LOW => 6E/6F VID4 VID3 VID2 VID1 VID0 1 +VCC_CORE 1.3V 1 1.35V 1 1.5V 0 1.55V 0 1.6V 0 1 1.65V 0 1 1.70V 0 1 1.75V 0 0 1.80V 0 1 1.85V Compal Electronics, inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE B USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC Date: A B C D SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet E of 47 A B 26,36,37 VR_ON 36,37 V_GATE V_GATE R447 LN_1K Add by Charles at 3/21 for ATE testing CRESET# CRESET# R298 10 14.3M_GCL STPCLK# SUSSTAT1# CPU_STP# 14 G_LO/HI# 15 29 43 VR_ON VGATE IGN_VGATE# 28 44 VR100/50# PLL30/60# 41 CRESET# 26 25 45 Y5 23 19 13 @0 Add by Charles at 2/16 @14.318MHZ Y6 38 37 36 G_STPCLK# G_SUSSTAT1# G_CPU_STP# 11 47 RESERVED 46 GHI# 10 CPUPWRGD VRPWRGD 32 PWRGD_CPU G_VR_POK VRCHGNG# VR_HI/LO# LP_TRANS# 12 33 34 VRCHGNG# VR_HI/LO# GT_A20M# GT_IGNNE# GT_STPCLK# GT_SUSTAT1# R115 GT_CPU_STP# LN_0 GT_STPCLK# GT_SUSTAT1# GT_CPU_STP# 10 PWRGD_CPU G_VR_POK 29 VRCHGNG# 13 VR_HI/LO# CPU_LO/HI# 35 39 40 RESERVED RESERVED RESERVED R123 LN_10K Change by Charles at 2/10 D19 CPU_STP# VRCHGNG# GT_CPU_STP# CPU_LO/HI# D @RB717F 2 G S STB# DIN DOUT GT_NMI GT_INTR GT_CPUINIT# GT_A20M# GT_IGNNE# GT_SMI# Change by Charles at 2/16 Q12 LN_SI2302DS Add by Charles at 1/18 18 31 42 27 C378 LN_15PF 2 +3V 48 CLK_IN CLK_OUT CLKEN#L LN_14.318MHZ C379 LN_15PF GT_NMI GT_INTR GT_CPUINIT# R111 @0 R106 GT_SMI# @0 G_NMI G_INTR G_INIT# G_A20M# G_IGNNE# G_SMI# 13 GT_LO/HI# NMI INTR INIT# A20M# IGNNE# SMI# 13 PIIX4_STPCLK# 13 SUS_STAT# 13 CPU_STP# 20 16 22 24 21 17 NMI INTR CPUINIT# A20M# R294 IGNNE# @0 SMI# R292 @0 STPCLK# SUSTAT1# CPU_STP# R108 GT_CPU_STP# GT_LO/HI# @0 PIIX4_NMI PIIX4_INTR PIIX4_INIT# PIIX4_A20M# PIIX4_IGNNE# PIIX4_SMI# E 30 13 13 13 13 13 13 D U10 LN_AMI11686-001 GND GND GND GND GND VCC3 VCC3 R117 LN_1K R121 LN_1K C C367 LN_.01UF without Geyserville, GHI#(CPU_LO/HI#) can OPEN C385 2 LN_.1UF +VCPU_IO RP24 GT_NMI GT_INTR GT_IGNNE# GT_A20M# 8P4R-1.5K A20M# R295 GT_A20M# IGNNE# R293 GT_IGNNE# Change by Charles at 2/16 R100 R87 R86 R88 CPU_LO/HI# L@1.5K GT_CPUINIT# 1K GT_STPCLK# 680 GT_SMI# 330 +3V R296 VR_HI/LO# LN_10K +3VS R304 G_VR_POK LN_10K +VCLK R289 1.5K PWRGD_CPU +3VS R300 4.7K GT_CPU_STP# 10K GT_SUSTAT1# RP27 CPU_STP# INTR SMI# CPUINIT# 10 11 12 13 14 15 16 NMI SUSTAT1# Add by Charles at 3/22 L@16P8R-0 R448 L@0 R122 L@0 V_GATE STPCLK# GT_CPU_STP# GT_INTR GT_SMI# GT_CPUINIT# Change by Charles at 2/10 GT_NMI GT_SUSTAT1# G_VR_POK +3V +3VS VR_POK 37 L@RB751V R99 RP18 CPUINIT# NMI INTR SMI# LN_8P4R-4.7K U13 13,14 PIIX4_SLP# C161 @.1UF 2 VGA_SUS_STAT# 23 +3V @7SH08 R175 +3VS +3V R301 R103 STPCLK# LN_4.7K VRCHGNG# 10K R119 R113 R291 CRESET# 1K GT_LO/HI# 10K SUSTAT1# LN_10K THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B VR_POK +3V GT_SUSTAT1# A GT_STPCLK# for without Geyserville Add by Charles at 1/18 D20 C D Title Compal Electronics, inc SCHEMATIC, M/B LA-733 Size B Date: Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet E of 47 A B 443ZXM-100_ A C B23 K21 H24 H26 CPURST# ADS# BNR# BPRI# DBSY# DEFER# DRDY# HIT# HITM# HLOCK# HTRDY# BREQ0# L23 J26 K23 L24 L22 K22 H25 B26 DBSY# DEFER# DRDY# HIT# HITM# HLOCK# HTRDY# BREQ0# K26 L26 L25 RS#0 RS#1 RS#2 J22 J23 K24 K25 J25 HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 N23 HCLKIN M25 M26 TESTIN# CRESET# C120 10UF_10V_1206 2 RS#0 RS#1 RS#2 RS#[0 2] HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 HREQ#[0 4] R329 = @10K (no load) 2/16 HCLK R150 R329 +3V CRESET# 33 13,16,31 PCIRST# A3 PCIRST# C148 MAB#0 MAB#1 MAB#2 MAB#3 MAB#4 MAB#5 MAB#6 MAB#7 MAB#8 MAB#9 MAB10 MAB#11 MAB#12 MAB#13 AD16 AC16 AD17 AB17 AE18 AD19 AB18 AB19 AF20 AC20 AB20 AE21 AD21 AF22 CSA#0 CSA#1 CSA#2 CSA#3 CSA#4 CSA#5 CKE2/CSA#6 CKE3/CSA#7 AB14 AF15 AE15 AC15 AD15 AE16 AE24 AD23 CSB#0 CSB#1 CSB#2 CSB#3 CSB#4 CSB#5 CKE4/CSB#6 CKE5/CSB#7 AE25 AD24 AD26 AC24 AC26 AB23 AC23 AF24 DQMA0 DQMA1 DQMA2 DQMA3 DQMA4 DQMA5 DQMA6 DQMA7 AD13 AC13 AC25 AB26 AE14 AC14 AA22 AA24 DQMB1 DQMB5 AE13 AD14 CKE0/FENA CKE1/GCKE AC22 AF23 SRAS_A# SRAS_B# SCAS_A# SCAS_B# AF16 AA17 AF12 AB13 WE_A# WE_B# AE12 AC12 11 CKE[2 5] CKE[2 5] MMA0 MMA1 MMA2 MMA3 MMA4 MMA5 MMA6 MMA7 MMA8 MMA9 MMA10 MMA11 MMA12 MMA13 RAS0#_BX RAS1#_BX RAS2#_BX RAS3#_BX R1931 R1781 R1941 R1951 2 2 R186 1 R185 CKE4_BX CKE5_BX 47 47 47 47 RRAS#2 RRAS#3 RRAS#4 RRAS#5 11 11 11 11 33 CKE4 11 CKE5 11 33 PLACE THE RESISTOR ON THE 443ZX RCAS#0 RCAS#1 RCAS#2 RCAS#3 RCAS#4 RCAS#5 RCAS#6 RCAS#7 RCAS#[0 7] 11 33 33 R1971 R1961 CKE2_BX CKE3_BX CKE2 11 CKE3 11 SRASA# 12 SCASA# 12 PLACE THE TERMINATOR ON THE STUB TO CPU @10K TESTIN# CRESET# 3,10 HCLK 492 BGA AF17 AB16 AE17 AC17 AF18 AE19 AF19 AC18 AC19 AE20 AD20 AF21 AC21 AF25 Add by Charles at 5/20 AE22 AE23 P22 CRESVA CRESVB CRESVC DCLKO DCLKWR DCLKRD RMWEA# 12 R168 AB21 AD25 AB22 W=5mils DCLKO_R W=5mils A1 A14 A26 C5 C9 C18 C22 E3 E12 E15 E24 F6 F8 F19 F21 H6 H21 J3 J24 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 15PF DCLKRW 10 18 W=5mils DCLKO 10 1000PF 1UF 1UF 2 2 01UF MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 C163 R170 + 01UF 82443ZXM-100 U31A 443ZXM-A C155 C156 C159 C158 C157 C154 1 +3V 1000PF V21 Y21 F7 F9 F18 F20 G6 G21 J6 J21 AA7 AA9 AA18 AA20 CPURST# HADS# BNR# BPRI# C146 10UF_10V_1206 1000PF 1UF 1UF 2 2 01UF VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 HOST INTERFACE G25 H22 G23 H23 G24 F26 G26 G22 F22 F23 F24 F25 E23 E26 E25 D25 D26 B25 C26 A25 C25 A24 D24 C23 B24 C24 A23 E22 D23 DRAM INTERFACE C135 + 01UF +3V HA[3 31] HA3 HA4 HA5 HA6 HA7 HA8 HA9 HA10 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18 HA19 HA20 HA21 HA22 HA23 HA24 HA25 HA26 HA27 HA28 HA29 HA30 HA31 C132 C131 C130 C134 1 C137 1000PF E MMA[0 13] 12 HA[3 31] +3V D 22PF place closely to 443zx Add by Charles at 5/20 1 33 C162 15PF AB22 leave to be NC 2/16 4 Compal Electronics, inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE B USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC Date: A B C D SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet E of 47 A B C D E 443ZXM-100_ B R129 TO DOCKING GNT#0 31 31 GNT#1 17 GNT#4 15 GNT#3 R128 13,29 RSMRST# 10K 13,14,23,27,31 CLKRUN# 10 PCLK_BX REFVCC5 W=5mils D7 place closely to 443zx +3V 1 1K R143 C128 C393 1UF PIPE# SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 M3 K1 M2 M1 N2 P2 P4 P3 R1 PIPE# SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 RBF# M4 RBF# 23 ST0 ST1 ST2 L4 L2 L1 ST0 23 ST1 23 ST2 23 AC2 T5 N3 AD_STBA 23 AD_STBB 23 SBSTB 23 1UF 2 1 PIPE# 23 1 C147 C416 1UF 1UF 1000PF W=10mils R162 18 R166 1 C412 C387 1UF 1UF 1000PF 18 W=5mils GCLKO 23 ** Trace lengths of GCLKOUT & GCLKIN must be matched Stub to teebshould be 1" MAX C160 22PF R165 R158 GIRDY# R161 GDEVSEL#1 R338 GSTOP# R340 AD_STBA R156 AD_STBB R335 GFRAME# R145 GREQ# R328 GGNT# R332 SBSTB R149 RBF# R331 PIPE# 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K 8.2K R337 100K GTRDY# SBA[0 7] W=20mils SBA[0 7] 23 +3V 1000PF C145 01UF C139 01UF 2 C152 C143 01UF 1 Add by Charles at 5/20 AGPREFV C403 01UF C153 2 1 C149 1000PF GREQ# 23 GGNT# 23 W=5mils C536 C384 1UF +3V P1 AE1 V6 Y6 GCLKOUT N4 C150 01UF C535 1UF R152 3.48K_1% C537 R154 1UF 2.32K_1% Change value by Charles at 2/16 +3V 15PF 2 GCLKOUT GCLKIN P5 N5 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS +5V L5 L3 AGPREFV 10 RB751V GREQ# GGNT# GADSTB-A GADSTB-B SB-STB R308 GREQ# GGNT# +3VS GFRAME# 23 GDEVSEL# 23 GIRDY# 23 GTRDY# 23 GSTOP# 23 GPAR 23 23 23 23 23 PGNT0#/IOGNT# PGNT1# PGNT2# PGNT3# PGNT4# BXPWROK CLKRUN# REFVCC5 PCLKIN C151 E7 D7 E10 E8 E9 AF3 AC4 C2 B2 W3 W5 V5 W4 Y1 Y2 C167 01UF GNT#0 GNT#1 GNT#2 GNT#3 GNT#4 GT_SUSTAT1# GC/BE#0 GC/BE#1 GC/BE#2 GC/BE#3 10K 1 +3VS PREQ0#/IOREQ# PREQ1# PREQ2# PERQ3# PERQ4# SUSTAT# A6 C7 F10 D8 D10 AD4 REQ#0 REQ#1 REQ#2 REQ#3 REQ#4 PCI ARB & PWR MGT TO DOCKING 31 REQ#1 13 REQ#2 15 REQ#3 PHOLD# PHLDA# WSC# GFRAME# GDEVSEL# GIRDY# GTRDY# GSTOP# GPAR AB2 Y4 V4 U2 B6 D6 AE3 13,14 PHLD# 13,14 PHLDA# VDD_AGP VDD_AGP VDD_AGP VDD_AGP FRAME# DEVSEL# IRDY# TRDY# STOP# PAR SERR# PLOCK# VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD E2 F3 E1 F5 F4 G5 F1 F2 FRAME#_BX DEVSEL#_BX IRDY#_BX TRDY#_BX GC/BE#0 GC/BE#1 GC/BE#2 GC/BE#3 C166 1000PF 2 2 C/BE#0 C/BE#1 C/BE#2 C/BE#3 C138 01UF +3V 0 0 J4 G3 E4 C4 C141 1000PF 1R314 1R322 1R313 1R130 13,14,31 FRAME# 13,14,31 DEVSEL# 13,14,31 IRDY# 13,14,31 TRDY# 13,14,31 STOP# 13,14,31 PAR 13,14,31 SERR# 14 PLOCK# C/BE#0 C/BE#1 C/BE#2 C/BE#3 492 BGA 2 PCI INTERFACE +3VS 82443ZXM-100 +3V 10P8R_10K 443BX as possible 31 ** Place as close to REQ#0 GAD[0 31] 23 GAD[0 31] REQ#0 REQ#1 REQ#2 REQ#3 GAD0 GAD1 GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8 GAD9 GAD10 GAD11 GAD12 GAD13 GAD14 GAD15 GAD16 GAD17 GAD18 GAD19 GAD20 GAD21 GAD22 GAD23 GAD24 GAD25 GAD26 GAD27 GAD28 GAD29 GAD30 GAD31 U31B 443ZXM-A GAD0 AB5 GAD1 AE2 GAD2 AD3 GAD3 AD2 GAD4 AD1 GAD5 AC3 GAD6 AC1 GAD7 AB4 GAD8 AB1 GAD9 AA5 GAD10 AA3 GAD11 AA4 GAD12 AA2 GAD13 AA1 GAD14 Y5 GAD15 Y3 GAD16 W1 GAD17 V2 GAD18 W2 GAD19 U5 GAD20 V1 GAD21 U4 GAD22 U3 GAD23 U1 GAD24 T3 GAD25 T4 GAD26 T2 GAD27 T1 GAD28 U6 GAD29 R3 GAD30 R4 GAD31 R2 10 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 N1 M5 L12 L15 M11 M13 M14 M16 M22 N12 N13 N14 N15 P12 P13 P14 P15 P26 T12 T15 R5 R11 R13 R14 R16 R22 V3 V24 W6 W21 K6 K2 K4 K3 K5 J1 J2 H2 H1 J5 H3 H5 H4 G1 G2 G4 D1 D3 D2 C1 A2 C3 B3 D4 E5 A4 D5 B4 B5 A5 E6 C6 AGP INTERFACE RP4 GNT#0 GNT#1 GNT#2 GNT#3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AD[0 31] 13,31 AD[0 31] +3V L11 L13 L14 L16 M12 M15 N11 N16 P11 P16 R12 R15 T11 T13 T14 T16 N26 +3VS C/BE#[0 3] 13,31 C/BE#[0 3] +3V ** Place as close to 443BX as possible GPAR U30C 74LVC08 13 PX4_REQ1# REQ#1 10 REQ#3 4 +3VS POWER Compal Electronics, inc U30D 74LVC08 13 PX4_REQ2# 12 REQ#0 13 REQ#4 11 REQ#4 17 +3VS POWER Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE B USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC Date: A B C D SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet E of 47 A B C D E 443ZXM-100_ C 1 1 C123 C144 01UF 1UF 1UF C133 C170 01UF C171 1000PF CAP closeed to 443BX HD[0 63] HD[0 63] +VCPU_IO +VCPU_IO R476 1K_1% C538 1UF VGTLREF_BX 1 MECC0 MECC1 MECC2 MECC3 MECC4 MECC5 MECC6 MECC7 492 BGA AE11 AA10 AA23 AA26 AF11 AD12 AA25 Y22 82443ZXM-100 +3V MECC0 MECC1 MECC2 MECC3 MECC4 MECC5 MECC6 MECC7 HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 C122 1UF R477 2K_1% C142 1UF Add by Charles at 5/3 Add by Charles at 5/3 C533 4.7UF_10V_0805 C541 01UF 2 C532 4.7UF_10V_0805 1 2 C540 01UF C539 01UF 1 M23 E16 M24 F17 GTLREFA GTLREFB VTTA VTTB W=40mils AB25 VSS N24 VSS AA6 VSS AA8 VSS AA19 VSS AA21 VSS AB3 VSS AB12 VSS AB15 VSS AB24 VSS AD5 VSS AD9 VSS AD18 VSS AD22 VSS AF1 VSS AF13 VSS AF26 VSS MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 MEMORY DATA BUS AF4 AE4 AF5 AD6 AE6 AB7 AC7 AF7 AB8 AB9 AC9 AE9 AB10 AC10 AF10 AD11 Y24 Y25 W23 W24 W26 W25 V26 U24 U23 T22 T23 T26 R24 R25 P23 N25 AC5 AE5 AB6 AC6 AF6 AD7 AE7 AC8 AD8 AF8 AE8 AF9 AD10 AE10 AB11 AC11 Y23 Y26 W22 V22 V23 V25 U22 U25 U26 T24 T25 U21 R23 R26 P24 P25 U31C 443ZXM-A B22 HD0 D22 HD1 E21 HD2 A22 HD3 D21 HD4 C21 HD5 A21 HD6 C20 HD7 B21 HD8 E20 HD9 A20 HD10 E19 HD11 B20 HD12 E18 HD13 D20 HD14 D19 HD15 D18 HD16 C19 HD17 B19 HD18 A18 HD19 A19 HD20 B18 HD21 C17 HD22 E17 HD23 D17 HD24 B17 HD25 C16 HD26 A17 HD27 C15 HD28 B16 HD29 D16 HD30 A16 HD31 B15 HD32 A15 HD33 D14 HD34 D15 HD35 B13 HD36 C14 HD37 E14 HD38 D13 HD39 A13 HD40 D12 HD41 B12 HD42 B14 HD43 C13 HD44 E13 HD45 D11 HD46 A12 HD47 B11 HD48 A11 HD49 B7 HD50 C12 HD51 C8 HD52 B10 HD53 A10 HD54 A9 HD55 A7 HD56 E11 HD57 D9 HD58 C11 HD59 C10 HD60 B8 HD61 A8 HD62 B9 HD63 12 MECC[0 7] MECC[0 7] MMD0 MMD1 MMD2 MMD3 MMD4 MMD5 MMD6 MMD7 MMD8 MMD9 MMD10 MMD11 MMD12 MMD13 MMD14 MMD15 MMD16 MMD17 MMD18 MMD19 MMD20 MMD21 MMD22 MMD23 MMD24 MMD25 MMD26 MMD27 MMD28 MMD29 MMD30 MMD31 MMD32 MMD33 MMD34 MMD35 MMD36 MMD37 MMD38 MMD39 MMD40 MMD41 MMD42 MMD43 MMD44 MMD45 MMD46 MMD47 MMD48 MMD49 MMD50 MMD51 MMD52 MMD53 MMD54 MMD55 MMD56 MMD57 MMD58 MMD59 MMD60 MMD61 MMD62 MMD63 HOST DATA BUS 12 MMD[0 63] MMD[0 63] VDD VDD VDD VDD VDD B1 N22 AF14 AF2 AE26 +3V ** Place as close to Add by Charles at 5/3 443BX as possible 4 Compal Electronics, inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE B USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC Date: A B C D SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet E of 47 A B C D E CLOCK GENERATOR & BUFFER +3VPCI L29 HB1M2012-121JT C376 01UF C372 4.7UF_10V_0805 1 C381 1UF L30 1 C114 1UF C382 4.7UF_10V_0805 C118 01UF 2 4.7UF_10V_0805 VDDPCI VDDPCI VDD VDD VDD CPUCLK0 24 CPUCLK1 23 25 VDDCPU PCICLK1 PCICLK2 PCICLK3 PCICLK4 10 PCICLK5 11 PCICLKF XIN C370 1000PF XIN Y1 XOUT 14.318MHZ Y2 2 10K GT_CPU_STP# 13 PCI_STP# SUSA# D5 RB751V 14.3M_SIO 27 R114@22 14.3M_VGA 23 14.3M_GCL XOUT R118 Add by Charles at 2/16 R116 22 HCLK 3,7 33 R120 PCLK_BX 15 R124 PCLK_MINI 31 33 2 33 PCLK_AUD 17 R136 33 PCLK_SIO 27 R112 33 PCLK_PIIX4 13 R127 15 CPU_STP# 48M 16 19 PCI_STP# 17 PWRDWN# 15 SEL100/66# GND GND GND GND GND GND 12 14 20 22 28 Change value by Charles for EA at 5/26 PCLK_PCM 15 R126 18 PWRDWN# 13,25 SUSA# C112 10PF C113 10PF R125 @14.318MHZ R107 2M +3VS 14MOSC 13 Add by Charles at 1/4 48M 13 Change value by Charles at 5/21 C116 01UF C369 14.3M 26 13 21 27 1 L28 HB1M2012-121JT U11 CLK_CPUIO +VCLK R110 22 C383 1000PF 2 HB1M2012-121JT +3VS R105 22 R101 22 VCLK_+3VS Reserved by Charles at 6/24 +3VS C121 @33PF W48C111-17 R132 @0 13 FSQ0 +3VS R131 FQS : 66MHZ 10K : 100MHZ 3 BUF_IN 12 CLK_SMD SDACLK 14 SDATA 12 CLK_SMC SCKCLK 15 C420 1000PF C414 01UF VDD VDD VDD VDD VDD VDD VDDIIC 1 C421 01UF U32 24 28 10 19 13 C415 1UF 1 C417 1UF 2 C168 4.7UF_10V_0805 +3V VCLK_SDRAM L33 HB1M2012-121JT C418 1000PF DCLKO Add by Charles at C169 5/20 12 R187 33 SUSA# D11 20 +3V R345 10K CLK_SDRAM1 For EA requirment at 6/26 CLK_SDRAM2 CLK_SDRAM3 CLK_SDRAM4 22 CLK_SDRAM5 23 SCLCOK R349 10 R347 10 R346 10 R348 CLK_SDRAM2 11 CLK_SDRAM3 11 CLK_SDRAM4 11 CLK_SDRAM5 11 10 OE 22PF RB751V CLK_SDRAM0 CLK_SDRAM6 26 CLK_SDRAM7 27 CLK_SDRAM8 11 17 12 21 25 16 GND GND GND GND GND GND VSSIC R354 DCLKRW 22 18 CLK_SDRAM9 C419 15PF_5% W40S11-02 Compal Electronics, inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE B USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC Date: A B C D SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet E 10 of 47 A B C D E DOCKING 100 PIN 25,29 KBD_DATA 25,29 KBD_CLK 25,29 EXT_CLK 25,29 EXT_DATA 31 LAN_TX+ 31 LAN_TX31 LAN_RX+ 31 LAN_RX28 DCD1# 28 DSR1# 28 TXD1 28 RXD1 LPD1 LPD3 LPD5 LPD7 27,28 LPTSTB# 27,28 LPTAFD# 27,28 LPTERR# 27,28 LPTINIT# 27,28 LPTSLCTIN# 23,24 COMPS 23,24 TV_GND 23,24 R 23,24 G 23,24 B 23,24 CRTGND 19 INTSPKOFF# 19,32 LINE_OUT_PLUG 19 INTMICOFF# 19,32 LINEOUT_L 19,32 LINEOUT_R 17 DOCK_LIN_L 17 DOCK_LIN_R 19 DOCK_MIC 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 101 101 102 102 103 103 104 104 1 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 LPD[0 7] 27,28 LPD[0 7] JP26 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 VIN SMD 3,5,20,25,26,32,38 SMC 3,5,20,25,26,32,38 SUSPBTN# 26,32 DTR1# 28 CTS1# 28 RTS1# 28 RI1# 28 ON/OFFBTN# 29 LPD0 LPD2 LPD4 LPD6 LPTSLCT 27,28 LPTPE 27,28 LPTBUSY 27,28 LPTACK# 27,28 +5VS VSYNC 23,24 HSYNC 23,24 M_SEN# 23,24,25 DDC_MD2 23 DDC_CLK 23,24 DDC_DATA 23,24 +5VALW Modify by Charles at 2/16 OVCUR#0 13,28 OVCUR#1 13,28 USB0_D+ 28 USB0_D- 28 CONA# USBP1_D+ 28 USBP1_D- 28 CONA# 26 DOCKING 100 3 4 Compal Electronics, inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC Date: A B C D SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet E 33 of 47 A B C D E B+ PD1 B+ P6 +12VALWP RB751V PR1 10_1206 PD2 RB751V 28 PR131 RUN/ON3 21 PT1 PR130 B+ P7 P8 10UH_SDT-1205P-100-120 PQ3 SI4800 P9 PC21 0.1UF_0805_25V PC20 4.7UF_1210_25V TIME/ON5 PR5 26,28,30 SUSP# 0.015_2512 PC19 4.7UF_1210_25V PQ4 FDS6690S PR4 0.015_2512 1W PD5 @BYS10-45 MAX1632 PR3 22_1206 10UH_SPC-1207P-100 CSH3 CSL3 FB3 SKIP# SHDN# PD4 EC11FS2 D D D D 10 23 PC18 @1000PF PL3 LX3 DL3 1 P5 PU1 0.1UF_0805_25V 18 16 17 19 20 14 13 12 15 11 26 24 12OUT VDD BST5 DH5 LX5 DL5 PGND CSH5 CSL5 FB5 SEQ REF SYNC RST# PC14 D D D D DH3 PC12 470PF_0805_100V PC11 1UF_0805_25V S S S G BST3 27 VL 25 PC6 4.7UF_1206_16V GND 4 PR129 PC7 0.1UF_0805_25V PC4 4.7UF_C_35V 22 PC13 0.1UF_0805_25V 4.7UF_1210_25V 25V V+ + S S S G PD35 @BYS10-45 PC10 4.7UF_1210_25V PC9 S S S G 0.1UF_0805_25V PQ1 FDS6690S PC2 2.2UF_1206_25V 25V PL1 1UH_BLM3216 PQ2 SI4800 D D D D D D D D PC8 2 S S S G VL 8 PC5 0.1UF_0805_25V PC1 4.7UF_1206_25V @0 +3VALWP 1 PR132 10K PZD1 @RLZ4.3B + + + PC25 47UF_D_6.3V + PC26 47UF_D_6.3V PR123 @1M PR6 100K 2 PD7 RB051L-40 PC23 @1000PF PC166 47UF_D_6.3V + PR124 @1M PR125 PC28 + 47UF_D_6.3V PC29 1 +5VALWP PC27 47UF_D_6.3V PZD2 @RLZ6.2C PD8 RB051L-40 2 PC24 47UF_D_6.3V +5VP VREF PZD3 PC30 PR7 47K 5% RLZ3.6B PC31 1000PF 50V PR8 120K 5% 4.7UF_1206_10V PR126 0.047UF 16V +5VP 3 4 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE Title SECRET INFORMATION THIS SHEET MAY NOT BE TRANS FERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR Size THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY B THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS, INC Date: A B C D Compal Electronics, inc SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet E 34 of 47 A B ADAPTER CURRENT 2.9A C D E PR163 @0 P2 P1 B+ PQ5 VIN PR12 10K PR9 0.02_2512 PQ7 D D D D S S S G PR11 200K SI4835 S S S G D D D D PC33 @100P 1W PQ6 S S S G D D D D P3 PQ13 SI4435 SI4435 PC40 PR18 150K PC41 PC42 4.7UF_1210_25V PC43 0.1UF_0805_25V 4.7UF_1210_25V PR27 0.02_2512 1W 22UH_SPC-1207P-220 P4 PC37 PC102 4.7UF_1210_25V + PD13 EA60QC04 PC38 PC39 4.7UF_1210_25V4.7UF_1210_25V 33UF_EC_25V VIN 4.7UF_1210_25V PR22 47K 1 FDS4435 VMB PL4 D D D D S S S G PACIN 36,38 PQ9 2N7002 PD11 1SS355 PR205 PR26 47K Modify by CT at 2/25 4.7 OVP# 38 B+ PU10 PQ14 DTC115EK 100K 25 ACOFF -INC2 +INC2 24 OUTC2 GND 23 +INE2 CS 22 -INE2 VCC(o) 21 OUT 20 VH 19 VCC 18 PR165 10K PR184 PR185 @0 PC140 2200PF 2 PC142 4700PF_0805_50V 30.1K_1% PR170 10K_1% FB2 VREF FB1 -INE1 RT 17 +INE1 -INE3 16 OUTC1 FB3 15 11 OUTD CTL 14 12 -INC1 +INC1 13 10K PC148 2200PF_0805_50V PR171 PR172 PC149 0.1UF 10K PR177 10K 10K_1% 25 TRICKLE PQ107 26 FSTCHG TRICKLE 25 PC165 0.1UF_0805_25V 68K PR176 PD40 1SS355 PC146 10 PC164 0.1UF_0805_25V PQ100 Add by CT at 5/3 PR175 PR183 16.9K 1% 1.2K_0.5% 0.1UF PR173 24.9K_1% PR174 PC141 PR169 PD41 1SS355 PR168 100K 324K_1% 1500PF MB3878 P1 PR178 69.8K_0.5% PR179 150K_0.5% PD18 RLS4148 CC: 2.87A LI-ION FAST CC: 2A NI-MH FAST CC: 0.273A LI-ION TRICKLE CC: 0.265A NI-MH TRICKLE PR180 VS CHGRTCP 215K_0.5% PC56 0.1UF 100K 1 1 PC147 100K 3 LI/NIMH# 25,38 PC51 10UF_1206_10V PC52 1UF_0805_25V PC54 0.22UF_1206_25V PZD6 RLZ16B 100K PR62 22K DTC115EK 2 PQ102 0.1UF PZD5 RLZ5.1B 200_0805 RTCVREF 29,32 51ON# PR61 150K PC55 0.1UF_0805_25V 2 PR60 100K PR59 10K +5VP 2 1 PZD4 RLZ6.2C +5VP PR58 47_1206 PR45 PU6 S-81235SG 38 NIMH/LI# PR181 CHGRTCP PQ24 TP0610T 1 PQ101 2N7002 VMB PD16 RB751V CV:LI-ION 13.241V NI-MH 16.202V PR191 47K 2N7002 2N7002 4 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANS FERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R& D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS, INC A B C D Compal Electronics, inc Title SCHEMATIC, M/B LA-733 Size B Date: Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet E 35 of 47 A B C D E +5VALWP VREF S D D +5VALWP PD38 + - PU7A LM393 PC137 1000PF PR94 300K_0.5% G D D PQ45 2SC2411K PQ46 2SA1036K PD30 RB051L-40 2 PC72 0.047UF SI3443DV 1 PR93 100K PQ99 47K +5VALWP PR92 200K_0.5% PR157 1 RB751V PC136 0.1UF_0805_25VPR158 2.2K Change value by Charles at 2/2 100K PL9 2.2UH_SPC1002 6,26,36 VR_ON PQ30 DTC115EK PR96 5.1K PQ31 DTC115EK 100K PR99 @1M_1% VREF 100K CPU_IOP PC138 @1000PF 25V + 100K PC139 47UF_D_6.3V PR98 @1M PR159 5.6M PR100 200K_1% +5VS + - PR154 PR162 10K 10K JOPEN2 +2.5VP VR_POK PD3 PR160 100K_1% 2 +VCLK +VCPU_IO +5VALW +3VALW 80mil 2MM V_GATE 6,36 PR101 200K_1% PU7B LM393 +3VS RB751V JOPEN1 CPU_IOP PR102 220K 2MM JOPEN4 PC76 0.047UF_1206_16V +5VALWP RB751V PD27 3MM JOPEN3 +3VALWP 3MM CPU_COREP +VCC_CORE 3 CUT POWER PLANE JOPEN5 +12VALWP +12VALW 2MM 4 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANS FERRED FROM THE Title CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY Size THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS, B INC Date: A B C D Compal Electronics, inc SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet E 37 of 47 A B C D E +5VALWP PR127 100K PF1 7A PCN1 VMB LI/NIMH# 25,35 LI/NIMH# +5VALWP PD31 B/I PR128 1K_1% TS 3 2 SLD SLC PR63 6.49K_1% PC100 PR64 1K +5VALWP @BAS40-04 PD20 @BAS40-04 Add by CT at 2/25 PR186 @470 BATT CONN 1000PF PR67 1K PC101 0.01UF 25 BATT_TEMP +5VALWP PR187 @10K +5VALWP PR69 PC150 @100PF PC152 @0.1UF PD22 @BAS40-04 - + PC153 @10UF_1206_10V PR189 @100K INVPWR G D D PR188 @11K_1% PQ108 @SI3443DV + 200 1 3,5,20,25,26,32,33 SMD +5VALWP PC151 @47UF_D_6.3V 200 PD23 VREF @BAS40-04 PR190 +5VALWP PR71 S D D PU11 @MAX4490 3,5,20,25,26,32,33 SMC 0_0805 VIN PT2 2 DC JACK PC62 0.01UF_0805_25V JBT0385-100805-4 PC61 1000PF PC63 1000PF LI/NIMH# PC64 0.01UF_0805_25V PR227 PC190 @2.2K_0805 @0.47UF_0805 PR229 @0 1 VMB Change by James for NIMH battrey issue PD24 BYS10-45 PR228 @0 PQ115 @2N7002 PC189 @1UF_0805 P1 P1 PD25 @1SS355 35 OVP# PR73 @39K PC163 0.1UF_25V_0805 PR80 1M_1% PR81 10K PR79 100K_1% PR89 32.4K_1% 22K LM393 + + PU4B LM393 - PACIN 35,36 PR87 @100K - PC66 @1UF_1206 PC67 @1000P LI-ION OVP 14.55V NI-MH OVP 17.55V PR74 @1M_1% PR76 @1M PR83 @100K_1% PR86 PQ25 @2N7002 PU4A PR72 @1.2M_1% PR75 PR82 @324K_1% ACIN 25,30 VREF VIN PQ116 @2N7002 VMB PR211 22 PR88 10K PD45 PC191 @1SS355@1000PF PR230 @470 PCN2 PR85 @1M PQ26 NIMH/LI# PC65 @1UF_0805_16VPR84 NIMH/LI# 35 @2N7002 25V RTCVREF PC69 0.22UF_0805_16V PD26 RLZ5.1B PR90 10K PC68 1000PF PR91 100K THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE Title SECRET INFORMATION THIS SHEET MAY NOT BE TRANS FERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R &D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR Size THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY B THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRON ICS, INC Date: A B C D Compal Electronics, inc SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Wednesday, August 29, 2001 Sheet E 38 of 47 A D E For HDD H7 HOLE_HDD_D3 H13 H11 H8 HOLE_HDD_D3.5 HOLE_HDD_D3.5 HOLE_HDD_D3.5 3mm +0mm -0.05mm, With ring 8mm PTH 3mm+/- 0.05mm, With ring 8mm, NPTH 4.5mm, NPTH 5.2mm, with ring 8mm PTH Hole Hole Hole Hole : : : : C HOLEA HOLEB HOLEC HOLED B For Tooling 1 FD19 FMARK FD11 FMARK FD4 FMARK FD8 FMARK 1 For Boss SMC37N869 FD6 FMARK FD13 FMARK FD2 FMARK FD10 FMARK FD18 FMARK FD22 FMARK 1 1 FD5 FMARK FD7 FMARK FD14 FMARK FD3 FMARK 1 FD15 FMARK NS87570 FD9 FMARK 440ZXM 1 H14 H16 H10 H15 HOLED HOLED HOLED HOLED 1 1 H18 H19 HOLEC HOLEC_1 TI1420 PIIX4M H1 HOLEB FD21 FD20 FMARK FMARK FD1 FMARK 1 H3 H12 HOLEA HOLEA 1 1 H5 H2 H9 H17 HOLEA HOLEA HOLEA HOLEA 1 H4 H6 HOLEA HOLEA FD16 FMARK 1 FD17 FD12 FMARK FMARK 1 ESS 1988 OZ163 3 4 Compal Electronics, inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE B USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC Date: A B C D SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet E 39 of 47 P.I.R (1) LIST D Revision History Date: 2000/01/14 D REV#: 0.2 Description: A1-TEST TO A2-TEST PAGE - R388, RP2, R71, R59 delete placement, U38 pin 18 connect to ground, Q2 changed value to SI2302DS PAGE - R346, R350, R347 delete placement and Y3 and Y4 both pin direct connection U9 pin 25 L27, C371, C373 delete placement and U9 pin and 30 direct connection +3V power PAGE - R336, R357, R345, R112 delete placement and RP56 pin 16 change connection signal from "VGA_SUS_STAT#" to "SUSTAT1#", RP56 pin signal short to "VGA_SUS_STAT#" signal, Q59 (SI2302DS), R452 (10K) add for Intel's Geyserville issue PAGE - "VR_HI/LO#" signal add R443 (10K) pullhigh to +3V power, "GT_SUSTAT1#" signal add R444 (10K) pullhigh to +3V power, R353 and R107 delete placement, "SUSTAT1#" siganl add R445 (10K) pullhigh to +3V power PAGE - R119 delete placement and RP19 pin change signal from "IGNNE#" to "CPUINIT#", "PWRGD_CPU" signal of R356 serial D45 (RB751V) to "VR_POK" signal PAGE - U9 pin 29 change signal from "VR_POK" to "V_GATE", U9 pin 32 change signal from "V_GOOD" to "VR_POK" C PAGE - R175 and R177 delete placement, R189 change connection signal from "RRAS#4" to "RRAS#2", R176 change connection signal from "RRAS#5" to RRAS#3", R190 change connection signal from "RRAS#2" to "RRAS#4", R191 change connection signal from "RRAS#3" to "RRAS#5" PAGE - R192 pin change connection U34 pin AC22, R184 pin change connection U34 pin AF23 C PAGE - R83 and R338 delete placement, U34 pin M24 and pin F17 change power source from "+VCC_CORE" to "+VCPU_IO" 10 PAGE 10 - Signal "PCLK_SIO" add R427 (22) connection to U10 pin 11 11 PAGE 11 - JP23 pin 61 change signal to "CLK_SDRAM3", JP23 pin 74 change signal to "CLK_SDRAM2", JP23 pin 69 change signal to "RRAS#3", JP23 pin 71 change signal to "RRAS#2", JP23 pin 62 change signal to "CKE3", JP23 pin 68 change signal to "CKE2" 12 PAGE 13 - U11 pin P16 change signal to "LID#" 13 PAGE 15 - U37 pin 148 used a 2N7002 to gatting leakage by "SYS_ALW" signal B 14 PAGE 17 - R398, R403, C494, R44, U42 delete placement, C465, C466, C467 change power source from +8VS to +5VS and serial L44 (HB1M2012-601JT) to AVDD power, U3 pin 39 add R44 (10K) pullhigh to +3VS power, R1, R2, R3 changed value to 20K, R16, R17, R18 changed value to 24K 15 PAGE 18 - R8, R7, R425, R426 change value to 22K, C22, C23, C503, C500 change value to 470PF, C6, C10, C510, C508 change value to 8200PF, C1, C4, C515, C514 change value to 4700PF, C2, C3, C513, C509 change value to 150PF, C7, C11, C507, C502 change value to 68PF 16 PAGE 19 - Audio AMP changed to TDA8552, JP1 pin add bais CKT (R429, R430, R428, C517), C9 delete placement and U43 pin connect signal "MICIN", Gatting internal MIC CKT changed to new one 17 PAGE 20 - R258, R263, R267 delete placement, U32 pin 93 connect signal "SIORDY", U32 pin 12 connect signal "IRQ_15", U32 pin 12 connect signal "SDDREQ", Q39 change value to 2N7002 and gate by "CD_PLAY_ON#", Q32, Q31 change value to 2N7002, U30 changed value to SI4800, R455 (100K), Q60(2N7002) add part to control U30 18 PAGE 21 - JP11 pin 44 change to no connection, JP11pin 21 serial R431 (82), JP11 pin 27 serial R432 (82), JP15 pin 27 serial R258 (82), JP15 pin 22 serial R267 (82) 19 PAGE 22 - R322 and R160 both changed value to 5.6K B 20 PAGE 24 - C109 pin change connection to L9 pin 2, JP6 pin change connection to C109 pin and signal "TV_GND" 21 PAGE 25 - U24 pin 94 changed to no connection 22 PAGE 26 - U25 pin and pin5 changed to no connection, U25 pin connect signal "CD_PLAY", U25 pin 16 change connection signal "CD_PLAY_ON#" 23 PAGE 27 - Super I/O change to SMC37N869 CKT 24 PAGE 28 - R278 and R207 delete placement 25 PAGE 29 - U35 pin change connection signal "VR_POK", U39 pin 13 add pullhigh R448(10K) to +3V power 26 PAGE 30 - U18, U15, U17, U16 changed value to SI4800, Q11 changed value to SI3861, C202, C204, C203, C183, C184, C196 changed value to 4.7UF, C210, C208, C294, R264, C182, C185, C299, R270, C309, C209, C207, C278, R255, C199, C195, C297, R265 delete placement 27 PAGE 30 - R266, Q35, R47, Q1, C198, C190, R211, R209, Q14, Q16, C197, C194, C218, C215, R213, R212, Q17, Q18, C217, C216 delete placement 28 PAGE 32 - Delete battery status LED CKT, signal "DRV0#" add level-shift CKT, JP12 changed pin difinition, JP9 pin 21 and pin 22 change to no connection, JP9 pin 13 and pin 15 connect to "AGND", JP9 pin 14 change connection to signal "INT_MIC", JP9 pin 12 change connection to signal "HDDLED#" and add JP29 to support headphone board 29 PAGE 33 - JP25 delete placement, JP26 pin 15, pin 17, pin 21, pin 23 direct connection to JP22 in page 31 29 PAGE 17 - AVDD power supply change by MOS A A Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE B USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC Date: Compal Electronics, inc SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet 40 of 47 P.I.R (2) LIST 02/25/2000 Revision History Date: 2000/02/14 REV#: 0.3 Description: Issue A2C008 : Can't mute completely (Page 20) A2-TEST TO B-TEST - add resistor divider R1(20K-serial), R16 (24K-to AGND) on INT_CD_L - add resistor divider R3(20K-serial), R18 (24K-to AGND) on INT_CD_R D - add C503 (1UF_0603) to decouple the small signal of INT_CD_R PAGE - U10 (GCL_AMI11686-001) pin 32 and R304 (10K) changed connection net to "G_VR_POK", R304 changed pull-high power source from +3V to +3VS PAGE 10 - R127 changed value from 22 to 10 Ohm, C121 (33PF) change to reserved in PCB - add R426,R427 (both @10K) on INT_CD_L small signal voltage divider to be 2.5V (reserved) - add R428,R429 (both @10K) on INT_CD_R small signal voltage divider to be 2.5V (reserved) PAGE 17 - R44 changed value form 33 to 10 Ohm, C38 changed value from 22 to 15PF - add R436,R437 (both @10K) on LEFT_EQ and RIGHT_EQ for noise improvement (reserved) PAGE 17 - Audio has one clean power source changed to two, one (+5VAMP) for AMP and EQ, other (AVDD) for CODEC - add R432,R433 (@24K,@20K) on CDROM_L for noise improvement (reserved) PAGE 18 - R8, R215, U1 and U21 changed power source from +5VCD to +5VAMP - add R434,R435 (@24K,@20K) on CDROM_R for noise improvement (reserved) PAGE 19 - U2 changed power source from +5VCD to +5VAMP Correct CD-ROM CD_AGND pin assignment (page 21) PAGE 19 - Q6 pin add a serial resistor (2.2K) to connect JP1 pin and - change JP16 pin4 connection from CD_AGND to GND PAGE 20 - Q42, Q43 and Q32 swap pin and 3, U33 (OZ163) pin 56 change 1K pull-down ground to 10K pull-high +5VCD of R366 No load D20(level shift gate for VR_POK) for Geyservelli inside (page 6) 10 PAGE 25 -U41 (87570) add "FIR_PRE#" signal at pin 84, RP56 (8P4R_10K) add "FIR_PRE#" signal at pin and "BT_PRE#" signal at pin Add amplify mute AMP_MUTE for reservation only (page 17,19) 11 PAGE 26 - "PLAYBTN#", "REVBTN#", FRDBTN#, STOPBTN#, "DJ_ON/OFF#", VOL_UP#, VOL_DW# and "CONA#" signals add RP55 pull-high array - add Q54 (@FDV301), R430(@100K), R431(@10K) 12 PAGE 27 - R205 change value from 33 to 10 ohm, C176 change value from 10 to 15PF - AMP_MUTE was inverse from the output of ESS1988 pin63 13 PAGE 27 - U15 pin 81 changed to connect to "DTRA#" signal, pin 80 changed to connect to "CTSA#" signal, pin 79 changed to connect to "RTSA#" signal, pin 78 changed to connect to "DSRA#" signal, pin 77 changed to connect to "TXDA", pin 76 changed connect to "RXDA" signal, pin 83 changed to connect to "DCDA#" signal 14 PAGE 29 - U8 pin 11 changed to connect to "FIR_PRE#" signal - AMP_MUTE was connected to TDA8552TS pin5 Add M_SEN# for CRT monitor detection (page24,25) - add D45(DAN217), R425(100K), C371(68PF) - M_SEN# was coming from JP11 pin11 15 PAGE 29 - U8 (MAX708) pin changed to connect to "G_VR_POK" signal, R283 changed value from 240K to 113K and pin changed to connect to +3VS power, , U8 (MAX708) pin serial a resistor (2.2M) to R283 pin 16 PAGE 29 - U26F (74LVC14) pin 13 add one +5V RC delay CKT C D - add C502 (1UF_0603) to decouple the small signal of INT_CD_L PAGE - Q12 (GCL_SI2302DS) swap pin 1, - M_SEN# was going to EC pin83 Exchange IR module pin11 and pin13 (page 28) 17 PAGE 32 - JP12 pin 17 changed power source from +5VS to +5VALW, JP12 pin 17 changed signal from NC to "DOT_PRES#", JP9 pin 25 changed signal from "ON/OFFBTN#" to "ON/OFF" (Old components' references) 18 PAGE 33 - JP26 pin 80 and 82 changed power source from +5V to +5VALW - pin11 will be GND Add CP8,9,10,11,12,13 (@8P4C_22PF) on keyboard signals for reserve(page 29) C Change MAX708 to be MAX6342 for cost improvement (page 29) Delete three beads HB1M1608-121JT on Mini-PCI connector pin28,19,123 (pass through) (page 31) 10 MD_BITCLK improvement for EMI (page 17,31) 02/18/2000 - add R423(22 ohm) serial on MD_BITCLK(nearby ESS1988) SpeedStep Workarond for CPU_STP# timming (page 6) - add R424(10 ohm), C501(15PF) AC termination on MD_BITCLK (nearby Mini-PCI CN) - add D19 (@RB717), pin1 connect CPU_STP#, pin2 connectVRCHGNG#, pin3 connectGCL_CPUSTP# 11 Internal PS2 signals add two decouple CAPs for EMI improvement Remove CPU_LO/HI# pull high (CPU had internal pull high) (page 6) - C499(@22PF) on PS2_CLK - no load R100 (@GCL_1.5K) 13 Switch Board change pin definition for Inverter Power (page 32) - add R298 (@GCL_0) serial on the trace 14.3M_GCL - JP10 pin3,4,5,6 change from +5VS to be INVPWR - U11 pin26 add a serial R114 (@22) on 14.3M_GCL Remove North Bridge TESTIN# pull high (according to updated RDDP) (page 7) - JP10 pin21,22 change from NC to be +5VS 02/29/2000 - no load R329 (@10K) Modify the references of some components for easy layout No connection DCLKRD input of the North Bridge (arrording to RDDP) (page 6) - R433 R1 => R433=20K,R1=0 ohm - let U31 pin AB22 to be NC - R432 R16 => R432=24K,R16=@24k Change AGPREF to meet RDDP (page 8) - R435 R3 => R435=20K,R3=0 ohm - R152 change value from 1K_1% to be 3.48K_1% - R434 R18 => R434=24K,R18=@24K - R154 change value from 2K_1% to be 2.32K_1% Scheme correct (page 6) Redundance ECC serial resistors remove (page 12) - D19 pin3 change net from GCL_CPUSTP# to CPU_CPU_STP# - no load RP47 (@16P8R-10) - D20 pin1 add a output module VR_POK for external connection Improve PIIX4 32KHz crystal RC value for more reliable (page 13) B - C500(@22PF) on PS2_DATA 12 Dot-Matrix connector change from 30 pins 0.5 pitch to 24 pins 1.0 pitch (page 32) Reserve 14.318MHz from Clock generator to Geyserville control logic (page 6,10) A2H001 & A2C045 (CD-ROM copy compare fail & low performance) - R172 change value from 1M to be 22M - IRQ14 damping R306 change from 82 ohm to 33 ohm - C164,C165 change value from 22PF to be 12PF - IRQ15 damping R333 change from 82 ohm to 33 ohm MIC circuit improve (page 19) - add a serial R53 (2.2K) on Q6 pin3 - connect JP24 pin2,3 together - PIORDY pull high R311 change from 1K ohm to 10K ohm - no load U22,C8,C239,C240,R234 - change R23 from 27K to be ohm - SIORDY damping R378 change from 82 ohm to ohm - change R29 from 10K to be ohm - change C20 from 1UF to be ohm - SIORDY pull high R341 change from 1K ohm to 10K ohm - change R32 from 2K to be 2.2K - add Q1 (2S2411EK) just like Q56 but only pin3 connect to R32 pin1 - PDDREQ damping R320 change from 82 ohm to 33 ohm 10 For layout space improve (page 20) - CD_DREQ damping R380 change from 82 ohm to 33 ohm - C429 change value from 10UF_10V_1206 to be 1UF_0603 03/01/2000 - R359 change from 10K to be 100K Add MUTE function for amplify (page 17,19,26) 11 CD_AGND improvement (page 21) - add "MUTE" signal on U3 pin63 - add R356 (0_0603 ohm) between CD_AGND & GND (at the middle of the trace) - add "EC_MUTE" signal on U39 pin5 - add R288 (0_0603 ohm) between CD_AGND & GND (close CD-ROM module) - add U47 (NC7ST32-SC70) to "OR" "MUTE & "EC_MUTE" 12 Modify BlueTooth connector definition (U47 pin1 = "MUTE", pin2 = "EC_MUTE" , pin4 connect to U2(Amplify) pin5) - pin : NC -> BT_DET - pin : GND -> BT_ON# - add C504(0.1UF) for U47 power decoupling - pin : NC -> BT_WAKE_UP - pin : NC -> BT_PRE# - add R438(0 ohm) serial on "EC_MUTE" for reserve only - pin : NC -> BT_USB1_D+ - pin 10 : BT_PRE# -> GND - pin : NC -> BT_USB_D- - pin 12: BT_WAKE_UP -> TO_USB1_D+ - pin 13 : NC -> BT_RST# - pin 14 : NC -> TO_USB1_D- - no load R36 to be @0 ohm (original pull down on U2 pin5 Add some CAPs for noise cross reference (help for EMI & signal quality) - for PCI BUS on +3VS,+5VS : C505,C508 (0.1UF) ; on +3VS,+3V : C510,C511 (0.1UF) ; - pin 16 : BT_ON# -> GND A B - PIORDY damping R309 change from 82 ohm to 33 ohm on +3VS,+3VALW : C513 (0.1UF) on +3V,+3VALW : C515 (0.1UF) - pin 18 : BT_RST# -> NC - for CD-ROM IDE BUS on +3V,+5VS : C512 (0.1UF) ; on +3VS,+3V : C514 (0.1UF) ; on +5VS,+5VCD : C516 (0.1UF) - pin 20 : BT_DET -> NC - for HDD IDE BUS on +3VS,+3V : C506 (0.1UF) ; on +5VS,+3V : C509 (0.1UF) - add R317,R324,R318,R325 (0 ohm) & R316,R323,R319,R326 (@0) A - for AGP BUS on +3V,+3VS : C507 (0.1UF) for USB1 signals switching (BlueTooth or non-BlueTooth) 03/08/2000 Improve EQ quality (page 18) Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC SCHEMATIC, M/B LA-733 Size Document Number Rev 4C 401138 Date: Compal Electronics, inc Tuesday, August 21, 2001 Sheet 41 of 47 - R31,R231 change from 120K to 12K - R28,R233 change from 1M to 180K - R27,R223 change from 120K to 20K - R24,R226 change from 1M to 270K - R213,R12 change from 120K to 16K - R13,R217 change from 1M to 240K - R218,R214 change from 120K to 24K - R11,R221 change from 1M to 330K - C7,C10,C229,C234 change from 68PF to 0.22UF - R227,R232 change from 120K to 1.5K - R25,R229 change from 1M to 24K - C21,C22,C235,C237 change from 470PF to 3300PF - C6,C9,C228,C230 change from 8200PF to 330PF - C1,C4,C222,C223 change from 4700PF to 5600PF - C2,C3,C224,C227 change from 150PF to 180PF P.I.R (3) LIST D Revision History Date: 2000/03/23 D REV#: 0.4 Description: 03/23/2000 03/30/2000 MODEM can't work was caused by the mal-reset of MD_RST# (page 31) Correct ON/OFF button signal for PIIX4 (page 13) - D9 pin1 change connection from ON/OFFBTN# to ON/OFF - add R462 @0 for MD_RST# Correct DM_ON signal for OZ163 direct CD-PLAY function (page 20) - change D26 pin1 from CD_PLAY_ON# to DM_ON - add R463 for PCIRST# (default) CMOS data lost (caused by +5VALW undershoot too big while unplug the AC) (page 34) Correct Bluetooth power supply (page 24) - change PD8 from BYS10-45 to RB051L40 (the same as PD30) - JP20 pin15,17,19 change connection from +3VS to +3VALW IRQ8 need to pullhigh (because BIOS change the programming method) (page 13) - JP20 pin18,20 change connection from N.C to +5VALW for USB hub on Bluetooth module Add a option resistor for G_VR_POK for 733L while Geyservilli ASIC was no load (page 6) - add R448 L@0, pin1 connect V_GATE, pin2 connect G_VR_POK - load R167 1K 04/05/2000 Speed up the +3V discharge time (page 30) For Factory ATE testing (page 6) C B1-TEST TO B2-TEST - R371 change from 470 ohm to 33 ohm - change R117,R121 from LN_0 to LN_1K C - add R447 LN_1K on U10 pin43 Improvement for Issue A2C008 (page 20) - change R432,R434 from 24K to 33K - add C517,C518 1UF_0603 serial in front of the EQ for LEFT_EQ & RIGHT_EQ respectively Improve the reserved "MUTE" function (page 19) - add R445 100K - add D46,D48,D49 RB751V - add R444 @0 - add C526 @.1UF - add U48 @NC7ST32 - no load R43,R33 to be @100K - no load R235 to be @10K 03/28/2000 B Reserve Pull high for VID[0 4] (page 5) B - add RP65 @8P4R-4.7K & R461 @4.7K Improve PCI signal quality (add damping resistors) - for miniPCI : add RP60,RP61,RP62,RP63,RP64,Rp66 16P8R-33 ohm (page 31) - for miniPCI : R453,R454 33 ohm & R450R452,R449,R451 10 ohm (page 31) - for PCI1420 : R458,R459,R460 10 ohm (page 15) - for ESS1988 : R455,R456,R451 10 ohm (page 17) Add pad junction for TV_GND for EMI request (page 24) - add JOPEN6 2MM for TV_GND 03/30/2000 FIR module change from HP3600 to VISHAY TFDS6101E (page 28) - change R286 from LN_2.2_1206 to @LN_3.3_1206 (change to be on load) - change R97 from LN_560 to LN_0_0805 - delete R287 (original @0) A A - change R102 from original LN_0 to 100K - change C111 from LN_220PF to LN_0.1UF - delete C368 (original LN_0.47UF_16V_0805) - change U9 from LN_HSDL_3600 to LN_TFDS6101E Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE B USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC - add R446 LN_3.3_1206 - add C525 LN_100PF Date: Compal Electronics, inc SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet 42 of 47 P.I.R (4) LIST D Revision History Date: 2000/04/20 D REV#: 0.5 Description: 04/20/2000 05/03/2000 Correct MOS switch (74HCT4066) for switching headphone or Int speaker (page 18) 17 Add more damping capicator in +VCPU_IO and VGTLREF_BX (page 9) - Add Q55 and Q54(2N7002) to use "HPS" signal to switching L-R channel - add C541, C539, C540 (.01UF) - Add R466 (10K) and R465 (10K) pullhigh +5VCD - add C538 (1UF) - Add one MOS switch (74HCT4066) to switching L-R channel - add R476 (1K) - Add R464 (@0) and R464 (@0) only for reserved, that can bypass MOS switch - add R477 (2K) Add MOS to gatting MIC signal (page 19) - change value C532, C533 (4.7UF) - Add Q58(SI2304DS) and Q59(2N7002) to disconnect MIC signal - change value C122, C142 (1UF) - Add R470(100K) pullhigh resistor 18 Add more damping capicator in +3V (page 23) - Add R471(10K) pulldown resistor - add C534 (10UF) 19 Modify and reserved for FAN control function (page 30) - Add R473(@10K) pulldown resistor C B2-TEST TO B3-TEST - Load R444(0), C526(.1UF) and U48(NC7ST32) for control "MUTE_AUD" signal - add C542 (@10UF) - No load R29(0) - direct to connect Q29 pin 2, U4 pin7 and C274 pin Add JOPEN for EMI (page 24) C - remove R52 (0) and the resistor reserved for connect "EN_DFAN" signal and Q29 pin Add pullhigh resistor for "BIOSCS#" signal (page 25) - add R472 (10K) Add a diod to reserved for S/W (page 13) - add D50 (@RB751V) Add capicator on JP22 (RJ11) for EMI request (page 31) - add C529 and C529 (1000PF_2KV_1206) Add capicator on JP10 "+5VCD" power pin for EMI request (page 32) - add C530(0.1UF) Change EQ RC value (page 18) Add damping capicator C532 and C533 (1UF) on U31 power pin VTTA(M24) and VTTB(F17) for WIN98 Multi-task will be halt (page 9) B - add C532, C533(1UF) B 10 Diconnect MIC Jack (JP24) pin and pin for EXT MIC can't record voice (page 19) 11 Add capicator and change value for TV-OUT quility (page 24) - add C531(27PF) - change C106 and C105 value (330PF) 12 Add CKT for gatting ME-OFF reset (page 25) - add Q56 and Q57(2N7002) - add R468 (10K) - add R469 (100K) - add R474 (0) 13 Add resistor reserved for FAN control function (page 30) - add R475(@0) 14 Add +5VALW power pin at LCD status board connector (JP13) pin 15 and 34 (page 32) 15 Add ATE and function testing point A A 16 Change RC value for beep sound is very loud (page 19) - change value R266(10K_1%) - change value C285(.22UF) - "PCM_SPK#" signal change to connect U26 pin and C306 pin change to connect U26 pin Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE B USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC Date: Compal Electronics, inc SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet 43 of 47 P.I.R (5) LIST D Revision History Date: 2000/06/15 D REV#: 1.0 Description: B3-TEST TO C-TEST 05/20/2000 Fix high pitch noise issue (page 18) - Add C543 and C544 (0.01UF) Fix PO-PO sound noise when power on (page 19) - Add Q62, Q63, Q64, Q65 (SI2304DS) - Add Q61(2N7002) - Add R480(100K) Fix USB power leakage (page 28) - Add Q60(SI2306DS) - Add R478(100K) Fix CD-direct play will into sleep mode after second (page 20) C - Delete R362 (10K) C - Add R364 (10K) Fix 733 and 733C can't identify M/B (page 25) - Add R479 (@10K) For EMI change (page 32) - Add C545, C546, C547, C548, C549, C550, C551 (220PF) BOM change for EMI - C121 (@33PF > 33PF) and R127 (10 > 15 Ohm) for "48M" (page 10) - C148 (@15PF > 15PF) and R150 (@10 > 33 Ohm) for "HCLK" (page 7) - C163 (@22PF > 22PF) for "DCLKO" (page 7) - C160 (@22PF > 22PF) for "GCLKO" (page 8) - C169 (@10PF > 22PF) and R187 (@33 > 33 Ohm) for "DCLKO" (page 10) - C444, C445, C460, C458 (@15PF > 22PF) for SDRAM_CLK (page 11) - R384, R385, R382, R383 (@33 > 33 Ohm) for SDRAM_CLK (page 11) Change value for FIR setting (page 28) B B - R98 (0 > 10K) - R102 (100K > @10K) Delete double pullup in "CDLED#" signal (The signal already had R189 pullup in page 21) (page 26) - R350 (100K > @100K) 10 Fix unplug AC-IN in SPR then system shut down (page 29) - Q51 (2N7002 > @2N7002) 11 Fix "GCLKO" signal waveform quility on the EA report (page 8) - R162 (10 > 22) 12 Fix "PCLK_MINI" signal waveform quility on the EA report (page 10) - R120 (33 > 15) 06/08/2000 13 Fix IR noise (page 28) - C110 (10UF_10V_1206 > @10UF_10V_1206) A A 06/15/2000 14 Fix "CLK_SDRAM2"~"CLK_SDRAM5" signal waveform quility on the EA report (page 10) - R346, R347, R348, R349 ( 22 > 15 Ohm ) Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE B USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC Date: Compal Electronics, inc SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet 44 of 47 P.I.R (6) LIST D Revision History Date: 2000/06/26 D REV#: 2.0 Description: C-TEST TO MP-TEST 05/20/2000 11/03/2000 ( Modify for N32N-733B ) Fix winstone99 will be hang issue (page 4) - Add C553(1UF), C554(1000PF) and C555(.01UF) for "CPU_IO" power - Change C427,C428 from "10PF" to "BN_10PF" - Change value C338, C288, C67, C63, C61 and C324 from 0.1UF to 1000PF for "CPU_IO" power - Change C115 from "10UF_10V_1206" to "BN_10UF_10V_1206" - Change value C344, C287, C68, C64 and C60 from 0.1UF to 0.01UF for "CPU_IO" power - Change C111,C430,C432,C435 from ".1UF" to "BN_.1UF" - Change value C62, C59 and C66 from 0.1UF to 1UF for "CPU_IO" power - Change C525 from "100PF" to "BN_100PF" - Change D25 from "1N4148" to "BN_1N4148" Fix noise sound when plug-in headphone (page 17) - Add Q66(2N7002) - Change D26,D27,D28,D29,D30 from "RB751V" to "BN_RB751V" - Add R481(33) - Change U33 from "OZ163" to "BN_OZ163" - Change U9 from "TFDU6101E" to "BN_TFDU6101E" Fix T.P mouse move cause audio noise (page 17) - Change JP13 from "HEADER24" to "BN_HEADER24" - Delete L17, L13 and L3 (0_0805) C - Change JP26 from "DOCKING 100" to "BN_DOCKING 100" Fix U2 pin floting problem (page 19) C - Change Q33,Q34,Q44 from "2N7002" to "BN_2N7002" - Add R482 (100K) Fix +5VCD discharge slowly problem (page 20) - Change R391 value from 470 to 33 Ohm Fix EA problem (page 10) - Change value R346, R347, R348 and R349 from 22 to 10 Ohm for memory clock - Delete C121 (33PF) for 48M clock 11/03/2000 ( Modify for N32N-733B ) BOM modified for N32N-733B (page 20,28,32,33) - Change RP49 from "8P4R-10K" to "BN_8P4R-10K" - Change RP48 from "10P8R_10K" to "BN_10P8R_10K" - Change RP51,RP53 from "10P8R_4.7K" to "BN_10P8R_4.7K" - Change RP52 from "@16P8R_33" to "B@16P8R_33" B - Change RP54,RP50 from "@16P8R_0" to "B@16P8R_0" B - Change R361 from "1M" to "BN_1M" - Change R359,R394 from "100K" to "BN_100K" - Change R361 from "1M" to "BN_1M" - Change R360,R363,R364,R366,R367,R368,R98 from "10K" to "BN_10K" - Change R102 from "@10K" to "B@10K" - Change R355 from "1K" to "BN_1K" - Change R375 from "5.6K" to "BN_5.6K" - Change R374 from "47K" to "BN_47K" - Change R97 from "0_0805" to "BN_0_0805" - Change R446 from "3.3_1206" to "BN_3.3_1206" - Change R369 from "33" to "BN_33" - Change R370 from "@33" to "B@33" - Change R379,R376,R377 from "@0" to "B@0" - Change L41 from "HB1M2012-601JT" to "BN_HB1M2012-601JT" A A - Change X2 from "8MHZ" to "BN_8MHZ" Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE B USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC Date: Compal Electronics, inc SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet 45 of 47 P.I.R (7) LIST D Revision History Date: 2000/12/20 D REV#: 3.0 Description: C2-TEST for H1.6/MP-TEST for H1.5 12/20/2000 Fix C0-step after CPU (page 4) - Change U7 P1 pin power source from "+VCPU_IO" to "+VCC_CORE" Mini-PCI add signal for 802.11b combo module (page 31) - Add R483(10) for "REQ#0" signal on pin 21 of Mini-PCI connector (JP25) - Add R485(100) for "S_AD26" signal for IDSEL on pin 43 of Mini-PCI connector (JP25) - Add R484(10) for "GNT#0" signal on pin 22 of Mini-PCI connector (JP25) - Add R486(10) for "PME#" signal for 802.11b device on pin 36 of Mini PCI connector (JP25) Fix Microphone feedback sound issue - Add new signal (AUTO_GAIN_CONTROL) output from U3 (ESS1988) pin 49 (Page 17) that connect U44 pin (Page 26) Capacitor change value to met Intel 1GHz CPU requirement (page 4) C C - C299, C300 change value from 1UF to 10UF - C292, C354 change value from 0.1UF to 10UF - C309, C350, C364, C361 change value from 0.01UF to 10UF - C298, C349 change value from 1000PF to 10UF 12/26/2000 Power Change List For Hurricane 1.6 Use MAX1711 instead of AD3421 (Control PWM IC) and AD3410 (Driver) in CPU-CORE circuitry (page 36) One MOSFET (FDS7764A) is reserved for 21.1A peak current in 1GHz Intel CPU (page 36) PU14 is added for 2.5V CLK_VCC (The Linear regulator is included in AD3421 for original LA733 design) (page 36) Date: 2000/02/02 B REV#: 4.0 Description: MP-TEST 02/02/2001 B Fix 1GHz CPU voltage transient issue (page 4) - C555, C319, C326 and C303 change value from 0.01UF to 0.1UF - C554 and C325 change value from 1000PF to 0.1UF Del R97 (0 ohm_0805) because of PCB trace connected (page 28) 02/02/2001 Power Change List For Hurricane 1.6 PR92 change value from 174K to 200K for "CPU_IO" voltage down from 1.58V to 1.5V (page 37) PR215 change value from 150K to 215K for current limit protection (page 36) Add PR226 (2.2 Ohm) for EMI requirement (page 36) Add PC184, PC185, PC186, PC187 and PC188 pcs capaciator those value all are 0.1UF_0805_25V for EMI requirement (page 36) Add one circuit for EMI requirement (page 38) - Add PQ116 (2N7002) - Add PC190 (0.47UF_0805) and PC191 (1000PF) A A - Add PD45 (ISSS355) - Add PR230 (470 Ohm) - Reserved PR229 (0 Ohm), PR228 (0 Ohm) and PR227 (2.2K_0805) - Reserved PQ115 (2N7002) Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE B USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC - Reserved PC189 (1UF_0805) Date: Compal Electronics, inc SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet 46 of 47 P.I.R (8) LIST D Revision History Date: 2001/03/05 D REV#: 4A Description: C3-TEST for H1.6/MP-TEST for H1.5 03/05/2001 Modify the Res.'s value to meet U36 NM24C16 2nd source's SPEC (Page 26) - R397,R398,R399 change value from 100K ohm to 1K ohm Modify the FIR related C.K.T to fix the nun-work issue (Page 28) - Cut the connection between C115.2,C111.2,C525.2,U9.8 and GND signal - Connect C115.2,C111.2,C525.2,U9.8 to JOPEN11.1 - Connect JOPEN11.2 to JOPEN10.1 - Connect JOPEN10.2 to GND signal near C98 side Make a table to show the H1.5/H1.6 ID selection (Page 25) - Remove R416(10K ohm),R479(10K ohm) and add R420(10K ohm) when selected for H1.6 Celeron - Remove R416(10K ohm),R420(10K ohm) and add R479(10K ohm) when selected for H1.6 PIII C C - Remove R479(10K ohm) and add R420(10K ohm),R416(10K ohm) when selected for H1.5 PIII - Remove R420(10K ohm) and add R479(10K ohm),R416(10K ohm) when selected for H1.5 Celeron Add three resistors for EMI solution (Page 17) - Add L17,L13,L3 (0 ohm 0805) to fix the EMI issue 03/09/2001 Add R488 10K ohm Res for platform ID (Page 25) - C3-test (REV:4A) M/B lose it It will be put into REV:4B M/B and rework on REV:4A 03/19/2001 Return the making table for showing the H1.5/H1.6 ID selection action (Page 25) - Add R416(10K ohm),R479(10K ohm) and remove R420(10K ohm) when selected for H1.6 Celeron - Add R416(10K ohm),R420(10K ohm) and remove R479(10K ohm) when selected for H1.6 PIII - Remove R479(10K ohm) and add R420(10K ohm),R416(10K ohm) when selected for H1.5 PIII B - Remove R420(10K ohm) and add R479(10K ohm),R416(10K ohm) when selected for H1.5 Celeron B Cancel R488 10K ohm Res rework for platform ID (Page 25) - C3-test cancel the R488(10K ohm) rework for platform ID selection action but still reserve that to connect GND on REV:4B PCB for future Change PR181 from 22uF_6.3V Tan Cap to 22uF_10V Ceramic Cap for ME (Page 36) 03/21/2001 Add CAP to fix FIR issue (Page 28) - Add C556(22U_10V_1206) to close C111 ASAP on REV:4B PCB Put C556 to close C111 on REV:4A PCB by rework this time A A Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS,INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERRED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS,INC NEITHER THIS SHEET NOR THE INFORMATION CONTAINS MAY BE B USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS,INC Date: Compal Electronics, inc SCHEMATIC, M/B LA-733 Document Number Rev 4C 401138 Tuesday, August 21, 2001 Sheet 47 of 47 www.s-manuals.com ... ENDIM1 ENDIM2 PHDRST SHDRST FLASH# HDDPW# SHDPW# G4 Y15 T14 W14 U13 V13 Y13 T12 T19 G5 F2 F3 F4 GPO0 GPO1 /LA1 7 GPO2 /LA1 8 GPO3 /LA1 9 GPO4 /LA2 0 GPO5 /LA2 1 GPO6 /LA2 2 GPO7 /LA2 3 GPO8 GPO27 GPO28 GPO29... MMD[0 63] MA[0 13] RRAS#[2 5] Title CKE[2 5] Compal Electronics, inc SCHEMATIC, M/B LA- 733 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL... EN_CDPLAY# U35 + GPIO[1]/VOL_UP GPIO[0]/VOL_DN GPIO_1 GPIO_0 MODE0 MODE1 56 57 PAVMODE 38 CSN INCN UDN 41 42 43 R393 100K SCLK OSCI OSCO R363 +5VCD 10 CIOCS16# 26,32 CD_PLAY_ON# CD_PLAY_ON# EN_CDPLAY#