B A C E D Model Name : File Name : 1 Compal Confidential 2 ULC UMA M/B LA-A994P Schematics Document Intel Bay Trail M VC Project Code : ZSO50 2014/02/05 MV Rev 1.0 3 4 DAX DAZ14Z00200 Issued Date Description PCB 14Z LA-A994P REV0 M/B Compal Electronics, Inc Compal Secret Data Security Classification ZSO50 BayTrail-M Part Number 2012/12/01 Deciphered Date 2013/07/10 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Cover Page Document Number Rev 0.1 LA-A994P Friday, February 21, 2014 Sheet E of 43 B A C E D 204pin DDRIII-SO-DIMM X1 Memory BUS(DDR3) Single Channel page15 BANK 0, 1, 1.35V DDR3L 1333MHz Digital Display Interfaces (DDI) USB2.0 Port LVDS Conn page17 Port LVDS Translater RTS2132R page16 Port HDMI Conn USB3.0 page18 VALLEYVIEW-M VGA USB2.0 Conn page24 SOC VGA Conn page19 Port Port USB3.0 Conn.X1 page24 GPP2 Card Reader RTS5239 page23 GPP1 MINI Card (WLAN/BT) page21 Debug port Touch Screen GPP0 page23 Port USB2.0 Conn WLAN BT Combo page24 page21 page24 page6~13 page23 SPI page23 Port HD Audio(AZ) 10/100 LAN Controller RTL8166-CG Transformer RJ45 page17 Port FCBGA 1170 Pin Port Card Reader Conn USB Camera page25 PCIE Port USB HUB FE1.1s(STT) LPC SATA III ODD Conn HDD Conn page22 BIOS (8M) SATA I Port1 Audio ALC3227 page20 page22 ENE KBC9012 FAN/LED page26 page28 Int.KBD Sub-borad Int Speaker Conn page20 Combo Jacks page20 Touch Pad page27 page27 USB/B page24 PWR BTN/B page28 4 TP BTN/B Issued Date Compal Electronics, Inc Compal Secret Data Security Classification page27 2012/12/01 Deciphered Date 2013/07/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Block Diagrams Size Document Number Custom Rev 0.1 LA-A994P Date: Sheet Friday, February 21, 2014 E of 43 B A C Voltage Rails Power Plane E D BOARD ID Table Description S0 S3 S4/S5 VIN 19V Adapter power supply ON ON ON BATT+ 12V Battery power supply ON ON ON B+ AC or battery power rail for power circuit (19V/12V) ON ON ON +VSB +VSBP to +VSB always on power rail for sequence control ON ON ON +RTCVCC RTC Battery Power ON ON ON +1.0VALW +1.0v Always power rail ON ON ON +1.2VALW +1.2v Always power rail ON ON ON +1.8VALW +1.8v Always power rail ON ON ON +3VALW +3.3v Always power rail ON ON ON +5VALW +5.0v Always power rail ON ON ON +1.35V +1.35V power rail for DDR3L ON ON OFF +SOC_VCC Core voltage for SOC ON OFF OFF +SOC_VNN GFX voltage for SOC ON OFF OFF +0.675VS +0.675V power rail for DDR3L Terminator ON OFF OFF +1.0VS +1.0v system power rail ON OFF OFF +1.05VS +1.05v system power rail ON OFF OFF +1.35VS +1.35v system power rail ON OFF OFF +1.5VS +1.5v system power rail ON OFF OFF +1.8VS +1.8v system power rail ON OFF OFF +3VS +3.3v system power rail ON OFF OFF +5VS +5.0v system power rail ON OFF OFF Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF USOC1 Board ID DB SI PV MV PCB Revision 0.1 0.2 0.3 1.0 USOC1 217@ 186@ B3 1.86G B3 2.17G SA00007E920 SA00007EO10 USOC1 USOC1 CR1@ PR1@ BOM Option Table BTO Item BOM Structure Unpop @ Connector CONN@ XDP (Debug Port) XDP@ EMI requirement EMI@ EMI requirement unpop @EMI@ ESD requirement ESD@ ESD requirement unpop @ESD@ 8161 LAN controller 8161@ 8166 LAN controller 8166@ LVDS LVDS@ LVDS LDO mode LVDSLDO@ LVDS SWR mode LVDSSWR@ Translator RTS2132S 2132S@ Translator RTS2132R 2132R@ Short Pad RS@ Clean CMOS CMOS@ Jump JP@ CeleronR N2815 Dual 7.5W 2C PentiumR N3520 Quad 7.5W 4C USOC1 USOC1 SA00007EO30 CR3@ CeleronR N2815 Dual 7.5W 2C SA00007EO60 SA00007E940 PR3@ PentiumR N3520 Quad 7.5W 4C SA00007E950 3 EC SM Bus1 address Device Address Smart Battery 0001 011X b EC SM Bus2 address Device Address SOC SM Bus address Device ChannelA Address DIMM0 A0 1010 000X 43 level BOM table JDIMM1(SPD) 43 Level 4319P6BOL01 Description SMT MB AA231 V1UE3 HDMI BOM Structure 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/12/01 Deciphered Date 2013/07/10 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Notes List Document Number Rev 0.1 LA-A994P Monday, February 24, 2014 Sheet E of 43 G3->S0 S0->S3 S3->S0 S0->S5 D +3VLP +3VLP EC_ON EC_ON 1.53ms +3VALW 1.58ms +3VALW +5VALW +5VALW SPOK SPOK 7.28ms +1.0VALW 8.23ms +1.0VALW +1.8VALW +1.8VALW ON/OFF ON/OFF 95.38ms EC_RSMRST# 101ms EC_RSMRST# PBTN_OUT# 101ms PBTN_OUT# C D ACIN ACIN 102ms EC_SLP_S4# 102ms EC_SLP_S3# EC_SLP_S4# EC_SLP_S3# 222ms SYSON 204ms C SYSON 0.6ms +1.35V 3.29ms +1.35V 3.29ms DDR_PWROK 1.71ms 33.68ms DDR_PWROK 21ms 22.32ms 36.20ms VR_ON VR_ON 2.49ms 2.50ms 8.85ms +SOC_VCC 2.50ms +SOC_VCC 11.5ms +SOC_VNN 2.50ms 10.55ms +SOC_VNN 9.81ms 0.28ms 279us VGATE VGATE 42.56ms 263ms 11.71ms SUSP# 5.57ms 31.28us +1.0VS 2.18ms 1.30ms 1.52ms 1.84ms +1.05VS 1.83ms 8ms +1.35VS +1.0VS 1.29ms 1.56ms +1.05VS SUSP# 31.12us 2.56ms 8.12ms 2.79ms 10.71ms +1.5VS 10.71ms 2.11ms 16.63ms +1.8VS 15.34ms +3VS 3.77ms 3.77ms 15.31ms +3VS B +1.5VS 2.08ms 16.59ms +1.8VS +1.35VS 2.8ms B 4.41ms 4.41ms 20.48ms +5VS 20.27ms 19.61ms +0.675VS +5VS 12.77ms 12.83ms 19.60ms +0.675VS 49.87ms 49.83ms 148.3ms KBRST# 144ms KBRST# 110ms 110ms 11.71ms MC_CORE_PWROK PMC_CORE_PWROK 110ms 110ms 11.71ms DR_CORE_PWROK DDR_CORE_PWROK 116ms 116ms 8.8ms 584ms SUSP# PMC_PLTRST# PMC_PLTRST# 2.38ms NOTE: T1 and T2 are recommended time for all the VR rails unless specified otherwise The VR ramp up time T2 and subsequent rail delay T3 are put in place to avoid inrush current which may be caused by multiple loads turning on simultaneously or fast charging of VR output decoupling A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Platform devices other than SOC sequencing are not explicitly shown as they are not limited by the SOC sequencing requirement 2012/12/01 Deciphered Date 2013/07/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size C Date: Power Sequence Document Number Rev 0.1 LA-A994P Sheet Friday, February 21, 2014 of 43 B+ AC Adapter +SOC_VNN Page 37 Charger PU301 D +SOC_VCC PU801 PWM ISL95833HRTZ 19V BQ24725ARGRR Page 32 CHG_B+ +0.675VS PU501 PWM RT8207MZQW +1.35V D Page 34 U37 MOSFET DMN3030LSS +VBATT +1.35VS Page 28 BATTERY 8V~12V PU604 Regulator SY8206DQNC +1.0VALW Page 35 U36 MOSFET AO4304L +1.0VS Page 28 +3VALW PU401 Regulator SY8208BQNC C C Page 33 U35 MOSFET DMN3030LSS +3VS Page 28 PU601 Regulator SY8032ABC +1.05VS Page 35 PU701 Regulator SY8032ABC +1.2VALW Page 36 B B PU703 Regulator SY8033BDBC +1.8VALW Page 36 U38 MOSFET DMN3030LSS PU402 Regulator SY8208CQNC +1.8VS Page 28 +5VALW PU702 LDO APL5930KAI Page 33 U33 MOSFET DMN3030LSS +1.5VS Page 36 +5VS Page 28 A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/12/01 Deciphered Date 2013/07/10 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Power Map Document Number Rev 0.1 LA-A994P Friday, February 21, 2014 Sheet of 43 D D USOC1B USOC1A 15 15 DDR_A_MA[0 15] DDR_A_DM[0 7] C DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 K45 H47 L41 H44 H50 G53 H49 D50 G52 E52 K48 E51 F47 J51 B49 B50 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 G36 B36 F38 B42 P51 V42 Y50 Y52 15 15 15 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# M45 M44 H51 15 15 15 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 K47 K44 D52 15 DDR_A_CS0# P44 15 DDR_A_CS2# P45 15 DDR_A_CKE0 15 DDR_A_CKE2 C47 D48 F44 E46 15 DDR_A_ODT0 T41 15 DDR_A_ODT2 P42 15 15 DDR_A_CLK0 DDR_A_CLK0# M50 M48 15 15 DDR_A_CLK2 DDR_A_CLK2# P50 P48 DDR_A_RST# P41 15 AF44 +DDR_SOC_VREF 100K_0402_5% 100K_0402_5% B 38 R960 R961 DDR_TERMN0 DDR_TERMN1 AD42 AB42 DDR_PWROK DDR_CORE_PWROK 23.2_0402_1% 29.4_0402_1% 162_0402_1% 1 AF42 AH42 R962 R963 R964 DDR_RCOMP0 DDR_RCOMP1 DDR_RCOMP2 AD44 AF45 AD45 Follow CRB v1.15 AF40 AF41 AD40 AD41 DDR_CORE_PWROK DRAM0_MA_0 DRAM0_MA_1 DRAM0_MA_2 DRAM0_MA_3 DRAM0_MA_4 DRAM0_MA_5 DRAM0_MA_6 DRAM0_MA_7 DRAM0_MA_8 DRAM0_MA_9 DRAM0_MA_10 DRAM0_MA_11 DRAM0_MA_12 DRAM0_MA_13 DRAM0_MA_14 DRAM0_MA_15 DRAM0_DQ_0 DRAM0_DQ_1 DRAM0_DQ_2 DRAM0_DQ_3 DRAM0_DQ_4 DRAM0_DQ_5 DRAM0_DQ_6 DRAM0_DQ_7 DRAM0_DQ_8 DRAM0_DQ_9 DRAM0_DQ_10 DRAM0_DQ_11 DRAM0_DQ_12 DRAM0_DQ_13 DRAM0_DQ_14 DRAM0_DQ_15 DRAM0_DQ_16 DRAM0_DQ_17 DRAM0_DQ_18 DRAM0_DQ_19 DRAM0_DQ_20 DRAM0_DQ_21 DRAM0_DQ_22 DRAM0_DQ_23 DRAM0_DQ_24 DRAM0_DQ_25 DRAM0_DQ_26 DRAM0_DQ_27 DRAM0_DQ_28 DRAM0_DQ_29 DRAM0_DQ_30 DRAM0_DQ_31 DRAM0_DQ_32 DRAM0_DQ_33 DRAM0_DQ_34 DRAM0_DQ_35 DRAM0_DQ_36 DRAM0_DQ_37 DRAM0_DQ_38 DRAM0_DQ_39 DRAM0_DQ_40 DRAM0_DQ_41 DRAM0_DQ_42 DRAM0_DQ_43 DRAM0_DQ_44 DRAM0_DQ_45 DRAM0_DQ_46 DRAM0_DQ_47 DRAM0_DQ_48 DRAM0_DQ_49 DRAM0_DQ_50 DRAM0_DQ_51 DRAM0_DQ_52 DRAM0_DQ_53 DRAM0_DQ_54 DRAM0_DQ_55 DRAM0_DQ_56 DRAM0_DQ_57 DRAM0_DQ_58 DRAM0_DQ_59 DRAM0_DQ_60 DRAM0_DQ_61 DRAM0_DQ_62 DRAM0_DQ_63 DRAM0_DM_0 DRAM0_DM_1 DRAM0_DM_2 DRAM0_DM_3 DRAM0_DM_4 DRAM0_DM_5 DRAM0_DM_6 DRAM0_DM_7 DRAM0_RAS# DRAM0_CAS# DRAM0_WE# DRAM0_BS_0 DRAM0_BS_1 DRAM0_BS_2 DRAM0_CS_0# DRAM0_CS_2# DRAM0_CKE_0 RESERVED_D48 DRAM0_CKE_2 RESERVED_E46 DRAM0_ODT_0 DRAM0_ODT_2 DRAM0_CKP_0 DRAM0_CKN_0 DRAM0_CKP_2 DRAM0_CKN_2 DRAM0_DRAMRST# DRAM_VREF 0.675V DRAM0_DQSP_0 DRAM0_DQSN_0 DRAM0_DQSP_1 DRAM0_DQSN_1 DRAM0_DQSP_2 DRAM0_DQSN_2 DRAM0_DQSP_3 DRAM0_DQSN_3 DRAM0_DQSP_4 DRAM0_DQSN_4 DRAM0_DQSP_5 DRAM0_DQSN_5 DRAM0_DQSP_6 DRAM0_DQSN_6 DRAM0_DQSP_7 DRAM0_DQSN_7 ICLK_DRAM_TERMN_AF42 ICLK_DRAM_TERMN_AH42 DRAM_VDD_S4_PWROK DRAM_CORE_PWROK DRAM_RCOMP_0 DRAM_RCOMP_1 DRAM_RCOMP_2 RESERVED_AF40 RESERVED_AF41 RESERVED_AD40 RESERVED_AD41 M36 J36 P40 M40 P36 N36 K40 K42 B32 C32 C36 A37 C33 A33 C37 B38 F36 G38 F42 J42 G40 C38 G44 D42 A41 C41 A45 B46 C40 B40 B48 B47 K52 K51 T52 T51 L51 L53 R51 R53 T47 T45 Y40 V41 T48 T50 Y42 AB40 V45 V47 AD48 AD50 V48 V50 AB44 Y45 V52 W51 AC53 AC51 W53 Y51 AD52 AD51 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 J38 K38 C35 B34 D40 F40 B44 C43 N53 M52 T42 T44 Y47 Y48 AB52 AA51 DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7 DDR_A_D[0 63] AY45 BB47 AW41 BB44 BB50 BC53 BB49 BF50 BC52 BE52 AY48 BE51 BD47 BA51 BH49 BH50 BD38 BH36 BC36 BH42 AT51 AM42 AK50 AK52 AV45 AV44 BB51 AY47 AY44 BF52 AT44 AT45 BG47 BE46 BD44 BF48 AP41 AT42 AV50 AV48 AT50 AT48 AT41 DRAM1_DM_0 DRAM1_DM_1 DRAM1_DM_2 DRAM1_DM_3 DRAM1_DM_4 DRAM1_DM_5 DRAM1_DM_6 DRAM1_DM_7 DRAM1_RAS# DRAM1_CAS# DRAM1_WE# DRAM1_BS_0 DRAM1_BS_1 DRAM1_BS_2 DRAM1_CS_0# DRAM1_CS_2# DRAM1_CKE_0 RESERVED_BE46 DRAM1_CKE_2 RESERVED_BF48 DRAM1_ODT_0 DRAM1_ODT_2 DRAM1_CKP_0 DRAM1_CKN_0 DRAM1_CKP_2 DRAM1_CKN_2 DRAM1_DRAMRST# 15 15 BG38 BC40 BA42 BD42 BC38 BD36 BF42 BC44 BH32 BG32 BG36 BJ37 BG33 BJ33 BG37 BH38 AU36 AT36 AV40 AT40 BA36 AV36 AY42 AY40 BJ41 BG41 BJ45 BH46 BG40 BH40 BH48 BH47 AY52 AY51 AP52 AP51 AW51 AW53 AR51 AR53 AP47 AP45 AK40 AM41 AP48 AP50 AK42 AH40 AM45 AM47 AF48 AF50 AM48 AM50 AH44 AK45 AM52 AL51 AG53 AG51 AL53 AK51 AF52 AF51 C BF40 BD40 BG35 BH34 BA38 AY38 BH44 BG43 AU53 AV52 AP42 AP44 AK47 AK48 AH52 AJ51 B OF 13 FH8065301546401_FCBGA131170 FH8065301546401_FCBGA131170 C1159 @ESD@ 0.01U_0402_16V7K DRAM1_DQ_0 DRAM1_DQ_1 DRAM1_DQ_2 DRAM1_DQ_3 DRAM1_DQ_4 DRAM1_DQ_5 DRAM1_DQ_6 DRAM1_DQ_7 DRAM1_DQ_8 DRAM1_DQ_9 DRAM1_DQ_10 DRAM1_DQ_11 DRAM1_DQ_12 DRAM1_DQ_13 DRAM1_DQ_14 DRAM1_DQ_15 DRAM1_DQ_16 DRAM1_DQ_17 DRAM1_DQ_18 DRAM1_DQ_19 DRAM1_DQ_20 DRAM1_DQ_21 DRAM1_DQ_22 DRAM1_DQ_23 DRAM1_DQ_24 DRAM1_DQ_25 DRAM1_DQ_26 DRAM1_DQ_27 DRAM1_DQ_28 DRAM1_DQ_29 DRAM1_DQ_30 DRAM1_DQ_31 DRAM1_DQ_32 DRAM1_DQ_33 DRAM1_DQ_34 DRAM1_DQ_35 DRAM1_DQ_36 DRAM1_DQ_37 DRAM1_DQ_38 DRAM1_DQ_39 DRAM1_DQ_40 DRAM1_DQ_41 DRAM1_DQ_42 DRAM1_DQ_43 DRAM1_DQ_44 DRAM1_DQ_45 DRAM1_DQ_46 DRAM1_DQ_47 DRAM1_DQ_48 DRAM1_DQ_49 DRAM1_DQ_50 DRAM1_DQ_51 DRAM1_DQ_52 DRAM1_DQ_53 DRAM1_DQ_54 DRAM1_DQ_55 DRAM1_DQ_56 DRAM1_DQ_57 DRAM1_DQ_58 DRAM1_DQ_59 DRAM1_DQ_60 DRAM1_DQ_61 DRAM1_DQ_62 DRAM1_DQ_63 DRAM1_MA_0 DRAM1_MA_1 DRAM1_MA_2 DRAM1_MA_3 DRAM1_MA_4 DRAM1_MA_5 DRAM1_MA_6 DRAM1_MA_7 DRAM1_MA_8 DRAM1_MA_9 DRAM1_MA_10 DRAM1_MA_11 DRAM1_MA_12 DRAM1_MA_13 DRAM1_MA_14 DRAM1_MA_15 DRAM1_DQSP_0 DRAM1_DQSN_0 DRAM1_DQSP_1 DRAM1_DQSN_1 DRAM1_DQSP_2 DRAM1_DQSN_2 DRAM1_DQSP_3 DRAM1_DQSN_3 DRAM1_DQSP_4 DRAM1_DQSN_4 DRAM1_DQSP_5 DRAM1_DQSN_5 DRAM1_DQSP_6 DRAM1_DQSN_6 DRAM1_DQSP_7 DRAM1_DQSN_7 DDR_A_DQS[0 7] DDR_A_DQS#[0 7] OF 13 15 0705:for ESD request Close To SOC Pin +1.35V +DDR_SOC_VREF R965 4.7K_0402_1% 1 R966 4.7K_0402_1% C1132 1U_0402_16V7K A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/12 Deciphered Date 2014/04/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size C Date: VLV-M SOC Memory DDR3L Document Number Rev 0.1 LA-A994P Friday, February 21, 2014 Sheet of 43 2 C @ R970 10K_0402_5% T186 T187 GPIO_NC12 3.3V 3.3V VGA_DDCCLK VGA_DDCDATA RESERVED_T7 RESERVED_T9 RESERVED_AB13 RESERVED_AB12 RESERVED_Y12 RESERVED_Y13 RESERVED_V10 RESERVED_V9 RESERVED_T12 RESERVED_T10 RESERVED_V14 RESERVED_V13 RESERVED_T14 RESERVED_T13 RESERVED_T6 RESERVED_T4 RESERVED_P14 R971 10K_0402_5% GPIO_NC13 GPIO_NC14 RESERVED_T2 RESERVED_T3 RESERVED_AB3 RESERVED_AB2 RESERVED_Y3 RESERVED_Y2 RESERVED_W3 RESERVED_W1 RESERVED_V2 RESERVED_V3 RESERVED_R3 RESERVED_R1 RESERVED_AD6 RESERVED_AD4 RESERVED_AB9 RESERVED_AB7 RESERVED_Y4 RESERVED_Y6 RESERVED_V4 RESERVED_V6 GPIO_S0_NC_13 GPIO_S0_NC14 RESERVED_AB14 GPIO_S0_NC_12 RESERVED_C30 VGA_HSYNC VGA_VSYNC Follow CRB v1.15 OF 10 GPIO_S0_NC_15 GPIO_S0_NC_16 GPIO_S0_NC_17 GPIO_S0_NC_18 GPIO_S0_NC_19 GPIO_S0_NC_20 GPIO_S0_NC_21 GPIO_S0_NC_22 GPIO_S0_NC_23 GPIO_S0_NC_24 GPIO_S0_NC_25 GPIO_S0_NC_26 A P G 26 @ AH14 AH13 AF14 AF13 SH000001G00 R973 47NH_LQG15HS47NJ02D_0.2A_5% CRT_R EMICRT@ BA3CRT_L_R R974 47NH_LQG15HS47NJ02D_0.2A_5% CRT_B EMICRT@ AY2CRT_L_B EMICRT@ R986 47NH_LQG15HS47NJ02D_0.2A_5% CRT_G BA1CRT_L_G AW1 CRT_IREF R969 CRT@ 357_0402_1% AY3 BD2 CRT_HSYNC BF2 CRT_VSYNC CRT_HSYNC CRT_VSYNC BC1 CRT_DDC_CLK BC2 CRT_DDC_DATA CRT_DDC_CLK 19 CRT_DDC_DATA 19 CRT_R CRT_B CRT_G 19 19 19 DDI1_ENVDD Y A ENVDD 17 C NL17SZ07DFT2G_SC70-5 SA00004BV00 +1.8VS +1.8VALW R1045 0_0402_5% @ U62 NC CRT 19 19 CRT@ RP43 150_0804_8P4R_1% DDI1_PWM @ U64 NC Y A INVT_PWM 16 NL17SZ07DFT2G_SC70-5 SA00004BV00 B 0918 add CRT F34 M32 D28 J28 K34 D34 F32 F28 K28 J34 N32 D32 DDI1_ENBKL DDI1_ENVDD DDI1_PWM RP45 0504 100K_0804_8P4R_5% +3VS RP50 INVT_PWM ENVDD ENBKL FH8065301546401_FCBGA131170 GPIO_S0_NC[13]: Multiplexed with Hardware 1 R1043 0_0402_5% @ Follow CRB v1.15 0ohm till to GND CRT_B CRT_G CRT_R ENBKL NL17SZ07DFT2G_SC70-5 SA00004BV00 +1.8VS +1.8VALW Control by RTS2132R T7 T9 AB13 AB12 Y12 Y13 V10 V9 T12 T10 V14 V13 T14 T13 T6 T4 P14 R1044 +1.8VS T2 T3 AB3 AB2 Y3 Y2 W3 W1 V2 V3 R3 R1 AD6 AD4 AB9 AB7 Y4 Y6 V4 V6 A29 C29 AB14 B30 C30 3.3V 3.3V 16 0_0402_5% B VGA_RED VGA_BLUE VGA_GREEN VGA_IREF VGA_IRTN Y A 2.2K_0402_5% +1.8VS N30 DDI1_ENVDD J30 DDI1_ENBKL M30 DDI1_PWM AH3 AH2 NC RESERVED_AH14 RESERVED_AH13 RESERVED_AF14 RESERVED_AF13 R967 P VSS_AH3 VSS_AH2 DDI0_RCOMP_P DDI0_RCOMP_N RESERVED_AM14 RESERVED_AM13 VSS_AM3 VSS_AM2 EDP_HPD# P30 DDI1_ENABLE G30 DDI1_ENBKL G DDI1_VDDEN DDI1_BKLTEN DDI1_BKLTCTL K30 16 16 1.8V 1.8V 1.8V DDI0_VDDEN DDI0_BKLTEN DDI0_BKLTCTL EDP_AUXP EDP_AUXN DDI1_DDCDATA DDI1_DDCCLK AK3 AK2 U61 DDI1_HPD 1.8V 1.8V Follow CRB v1.15 0ohm till to GND AK12 AK13 AM14 AM13 AM3 AM2 1.8V 1.8V 1.8V D eDP Panel R1042 R968 DDI0_RCOMPP 402_0402_1% DDI0_RCOMPN 1.8V DDI0_DDCDATA DDI0_DDCCLK @ 0_0402_5% B28 C27 B26 DDI0_HPD R1041 0_0402_5% @ 16 16 P C26 C28 EDP_TXP0 EDP_TXN0 HDMI_DDCDATA HDMI_DDCCLK DDI1_AUXP DDI1_AUXN AG3 AG1 AF3 AF2 AD3 AD2 AC3 AC1 HDMI_HPD# 18 18 1.0V 1.0V DDI0_AUXP DDI0_AUXN DDI1_TXP_0 DDI1_TXN_0 DDI1_TXP_1 DDI1_TXN_1 DDI1_TXP_2 DDI1_TXN_2 DDI1_TXP_3 DDI1_TXN_3 18 D27 1.0V AL3 AL1 1.0V HDMI DDI0_TXP_0 DDI0_TXN_0 DDI0_TXP_1 DDI0_TXN_1 DDI0_TXP_2 DDI0_TXN_2 DDI0_TXP_3 DDI0_TXN_3 R1040 D AV3 AV2 AT2 AT3 AR3 AR1 AP3 AP2 HDMI_TX2+ HDMI_TX2HDMI_TX1+ HDMI_TX1HDMI_TX0+ HDMI_TX0HDMI_CLK+ HDMI_CLK- 0_0402_5% 18 18 18 18 18 18 18 18 +1.8VS +1.8VALW USOC1C G 0504 Straps Pin:MDSI_DDCDATA A 4.7K_0804_8P4R_5% Compal Electronics, Inc Compal Secret Data Security Classification 2013/04/12 Issued Date Deciphered Date 2014/04/12 Title VLV-M SOC Display THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 0.1 LA-A994P Date: Friday, February 21, 2014 Sheet of 43 USOC1D 22 22 ODD 22 22 AU16 AV16 BD10 BF10 SATA_PTX_DRX_P1 SATA_PTX_DRX_N1 AY16 BA16 SATA_PRX_DTX_P1 SATA_PRX_DTX_N1 Follow CRB V1.15 0ohm till to GND 22 Follow CRB v1.15 BB10 BC10 SOC_SCI# SOC_SCI# ODD_DA# BA12 AY14 SATA_LED#_SOC AY12 ODD_DA# R972 SATA_RCOMPP 402_0402_1% SATA_RCOMPN AU18 AT18 AT22 C 22 ODD_PLUG# 22 ODD_PWR ODD_PLUG# AV20 AU22 AV22 AT20 AY24 AU26 AT26 AU20 ODD_PWR +1.8VS R955 R956 R957 1K_0402_5% 10K_0402_5% 10K_0402_5% @ ODD_DA# ODD_PLUG# ODD_PWR AV26 BA24 AY18 17 TS_GPIO_CPU TS_GPIO_CPU BA18 AY20 BD20 BA20 BD18 BC18 AY26 AT28 BD26 AU28 BA26 BC24 AV28 BF22 BD22 B BF26 SATA_RXP_0 SATA_RXN_0 PCIE_RXP_0 PCIE_RXN_0 AY7 AY6 AT14 AT13 PCIE_TXP_1 PCIE_TXN_1 SATA_TXP_1 SATA_TXN_1 SATA_RXP_1 SATA_RXN_1 PCIE_RXP_1 PCIE_RXN_1 VSS_BB10 VSS_BC10 PCIE_TXP_2 PCIE_TXN_2 AT7 PCIE_PTX_DRX_P2 AT6 PCIE_PTX_DRX_N2 BB7 BB5 VSS_BB7 VSS_BB5 PCIE_CLKREQ_0# / GPIO_S0_SC_3 PCIE_CLKREQ_1# / GPIO_S0_SC_4 PCIE_CLKREQ_2# / GPIO_S0_SC_5 PCIE_CLKREQ_3# / GPIO_S0_SC_6 SD3_WP / GPIO_S0_SC_7 PCIE_RCOMP_P PCIE_RCOMP_N 21 21 PCIE_PTX_C_DRX_P2 PCIE_PTX_C_DRX_N2 23 23 C1133 C1134 PCIE_PRX_DTX_P3 PCIE_PRX_DTX_N3 BG3 BD7 BG5 BE3 BD5 PCIE_CLKREQ_0# WLAN_CLKREQ# CR_CLKREQ# LAN_CLKREQ# AP14 AP13 PCIE_RCOMPP PCIE_RCOMPN Card Reader 23 23 PCIE_PTX_C_DRX_P3 PCIE_PTX_C_DRX_N3 Follow CRB V1.15 0ohm till to GND WLAN 23 23 PCIE LAN 23 23 8411 Pin 36 O/D RP51 10K_0804_8P4R_5% WLAN_CLKREQ# 21 CR_CLKREQ# 23 LAN_CLKREQ# 23 C For EMI HDA_BITCLK_AUDIO C1001 @RF@ 22P_0402_50V8J T214 R975 402_0402_1% 49.9_0402_1% BF20 HDA_RCOMP BG22 HDA_RST# BH20 HDA_SYNC BJ21 HDA_BIT_CLK BG20 HDA_SDOUT BG19 HDA_SDIN0 HDA_SDIN0 BG21 T189 BH18 T190 BG18 T191 BF28 BA30 BD28 BC30 HDA_SYNC HDA_SDOUT HDA_BIT_CLK HDA_RST# GPIO_S0_SC_63: BIOS/EFI Boot Strap (BBS) BIOS Boot Selection = LPC = SPI 09/13a H_PROCHOT# GPIO_S0_SC_65: Security Flash Descriptors = Override = Normal Operation (Internal PU) 26,34,35 R978 10K_0402_5% R977 10K_0402_5% GPIO_S0_SC_63 B +1.8VS +1.8VS Internal PD 2K HDA_SYNC_AUDIO 20 HDA_SDOUT_AUDIO 20 HDA_BITCLK_AUDIO 20 HDA_RST_AUDIO# 20 20 R979 33.2_0402_1% +1.0VS C24 +1.8VS 33_0804_8P4R_5% GPIO_S0_SC_65 AK9 AK7 PROCHOT# R976 GPIO_S0_SC_63 P34 N34 FH8065301546401_FCBGA131170 GPIO_S0_SC_65 @ESD@ C1002 10P_0402_50V8J EC programing : "High"for Flash BIOS D S R980 10K_0402_5% Pull High 10k at LED Page +1.8VS LAN_CLKREQ# WLAN_CLKREQ# CR_CLKREQ# PCIE_CLKREQ_0# RP46 HDA_LPE_RCOMP HDA_RST# / LPE_I2S0_CLK / GPIO_S0_SC_8 HDA_SYNC / LPE_I2S0_FRM / GPIO_S0_SC_9 HDA_CLK / LPE_I2S0_DATAOUT / GPIO_S0_SC_10 HDA_SDO / LPE_I2S0_DATAIN / GPIO_S0_SC_11 HDA_SDI0 / LPE_I2S1_CLK / GPIO_S0_SC_12 HDA_SDI1 / LPE_I2S1_FRM / GPIO_S0_SC_13 SD3_CLK / GPIO_S0_SC_33 HDA_DOCKRST# / LPE_I2S1_DATAOUT / GPIO_S0_SC_14 HDA_DOCKEN# / LPE_I2S1_DATAIN / GPIO_S0_SC_15 SD3_D0 / GPIO_S0_SC_34 SD3_D1 / GPIO_S0_SC_35 LPE_I2S2_CLK / SATA_DEVSLP_1 / GPIO_S0_SC_62 SD3_D2 / GPIO_S0_SC_36 LPE_I2S2_FRM / GPIO_S0_SC_63 SD3_D3 / GPIO_S0_SC_37 LPE_I2S2_DATAIN / GPIO_S0_SC_64 SD3_CD# / GPIO_S0_SC_38 LPE_I2S2_DATAOUT / GPIO_S0_SC_65 SD3_CMD / GPIO_S0_SC_39 SD3_1P8EN / GPIO_S0_SC_40 SD3_PWREN# / GPIO_S0_SC_41 RESERVED_P34 RESERVED_N34 SD3_RCOMP RESERVED_AK9 RESERVED_AK7 OF 10 1U_0402_16V7K 1U_0402_16V7K 21 21 PCIE_PRX_DTX_P1 PCIE_PRX_DTX_N1 PCIE_PRX_DTX_P2 PCIE_PRX_DTX_N2 AV10 AV9 RESERVED_AV10 RESERVED_AV9 SD2_CLK / GPIO_S0_SC_27 SD2_D0 / GPIO_S0_SC_28 SD2_D1 / GPIO_S0_SC_29 SD2_D2 / GPIO_S0_SC_30 SD2_D3_CD# / GPIO_S0_SC_31 SD2_CMD / GPIO_S0_SC_32 CC6 CC7 PCIE_PTX_C_DRX_P1 PCIE_PTX_C_DRX_N1 BB4 BB3 RESERVED_BB4 RESERVED_BB3 MMC1_RCOMP 1 AP9 PCIE_PRX_DTX_P3 AP7 PCIE_PRX_DTX_N3 MMC1_CLK / GPIO_S0_SC_16 MMC1_CMD / GPIO_S0_SC_25 MMC1_RST# / SATA_DEVSLP_0 / GPIO_S0_SC_26 1U_0402_16V7K 1U_0402_16V7K AP6 PCIE_PTX_DRX_P3 AP4 PCIE_PTX_DRX_N3 PCIE_RXP_3 PCIE_RXN_3 MMC1_D0 / GPIO_S0_SC_17 MMC1_D1 / GPIO_S0_SC_18 MMC1_D2 / GPIO_S0_SC_19 MMC1_D3 / GPIO_S0_SC_20 MMC1_D4 / GPIO_S0_SC_21 MMC1_D5 / GPIO_S0_SC_22 MMC1_D6 / GPIO_S0_SC_23 MMC1_D7 / GPIO_S0_SC_24 C1135 C1000 AP12 PCIE_PRX_DTX_P2 AP10 PCIE_PRX_DTX_N2 PCIE_TXP_3 PCIE_TXN_3 SATA_RCOMP_P SATA_RCOMP_N 1U_0402_16V7K 1U_0402_16V7K AT10 PCIE_PRX_DTX_P1 AT9 PCIE_PRX_DTX_N1 PCIE_RXP_2 PCIE_RXN_2 SATA_GP0 / GPIO_S0_SC_0 SATA_GP1 / SATA_DEVSLP_0 / GPIO_S0_SC_1 SATA_LED# / GPIO_S0_SC_2 D AV6 PCIE_PTX_DRX_P1 AV4 PCIE_PTX_DRX_N1 SATA_PRX_DTX_P0 SATA_PRX_DTX_N0 PCIE_TXP_0 PCIE_TXN_0 22 22 SATA_TXP_0 SATA_TXN_0 SATA_PTX_DRX_P0 SATA_PTX_DRX_N0 D 22 22 HDD BF6 BG7 TXE_DBG G Q62 MESS138W-G_SOT323-3 26 A SOC_SATALED# S 28 D G A SATA_LED#_SOC Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Q63 MESS138W-G_SOT323-3 2013/04/12 Deciphered Date 2014/04/12 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: VLV-M SOC SATA/PCI-E/HDA Document Number Rev 0.1 LA-A994P Friday, February 21, 2014 Sheet of 43 +3VALW_EC +3VALW_EC +1.8VALW +3VALW EC_SLP_S4# 26,38 26 EC_SLP_S4# EC_KBRST# EC_KBRST# A 3 D40 PMC_ACIN 2 NL17SZ07DFT2G_SC70-5 SA00004BV00 D PLT_RST Buffer SOC_KBRST# Y NL17SZ07DFT2G_SC70-5 SA00004BV00 R1036 10K_0402_5% R983 2.2K_0402_5% U58 NC P R3 4.7K_0402_5% R5 4.7K_0402_5% Y A +1.8VALW 1 1 2 +3VALW_EC R2 4.7K_0402_5% U57 NC PMC_SLP_S4# 21,23,26,27 NL17SZ07DFT2G_SC70-5 SA00004BV00 Change To 10pF for Vendor Suggest 0701 D +1.8VALW 3.3V PLT_RST_BUF# G @ G Y A P NC 2 2 1 PMC_PLTRST# 0705:for ESD request R982 4.7K_0402_5% R1032 1.8V C1004 10P_0402_25V8K R1033 @ U53 0_0402_5% 0_0402_5% GND XTAL_25M_OUT 1 C1174 @ESD@ 0.01U_0402_16V7K PLT_RST_BUF# +3VS @ R1038 GND R1039 C1003 10P_0402_25V8K 0_0402_5% 1 0_0402_5% R981 1M_0402_5% Y7 25MHZ_10PF_7V25000014 P +1.8VS +1.8VALW XTAL_25M_IN G ACIN 26,34 36 RB751V40_SC76-2 +3VALW_EC AM4 AM6 NL17SZ07DFT2G_SC70-5 SA00004BV00 10K_0804_8P4R_5% 0705:for ESD change to 0.1uF PCIE_CLKN_0 PCIE_CLKP_0 PMC_SUSPWRDNACK / GPIO_S5_11 PMC_SUSCLK_0 / GPIO_S5_12 PMC_SLP_S0IX# / GPIO_S5_13 PMC_SLP_S4# PMC_SLP_S3# GPIO_S5_14 PMC_ACPRESENT PMC_WAKE_PCIE_0# / GPIO_S5_15 PMC_BATLOW# PMC_PWRBTN# / GPIO_S5_16 PMC_RSTBTN# PMC_PLTRST# GPIO_S5_17 PMC_SUS_STAT# / GPIO_S5_18 PCIE_CLKN_1 PCIE_CLKP_1 PCIE_CLKN_2 PCIE_CLKP_2 PCIE_CLKN_3 PCIE_CLKP_3 RESERVED_AM9 RESERVED_AM10 D26 G24 F18 F22 D22 J20 D20 F26 K26 J26 BG9 F20 J24 G18 T192 32.768k output PMC_SUSCLK PMC_SLP_S4# PMC_SLP_S3# GPIO_S5_14 PMC_ACIN PMC_PCIE_WAKE# PMC_BATLOW# PMC_PWRBTN# PMC_RSTBTN# PDG v1.2 update EC_RSMRST# +3VALW_EC 100K_0402_5% C1155 @ESD@ 1U_0402_16V7K R1083 RS@ 0_0402_5% GPIO_S5_17 R990 XDP_RSTBTN# PMC_PLTRST# T205 0705:for ESD request 14 14 26 EC_SCI# EC_SCI# R8 4.7K_0402_5% U66 AU32 AT32 OF 13 R996 20K_0402_1% 2 R997 20K_0402_1% SOC_SPI_CS0# SOC_SPI_MISO SOC_SPI_MOSI +BIOS_SPI SPI_CS0# SPI_MISO SPI_WP# 2 1 EC_SERIRQ 4.7K_0402_5% CMOS@ CLRP1 SHORT PADS EC_SERIRQ R9 +1.8VALW 26,27 C1009 18P_0402_50V8J P NL17SZ07DFT2G_SC70-5 SA00004BV00 +3VALW_EC Need Change footprint : pin / wrong 26 SJ10000EC00 +1.8VALW EC_SMI# EC_SMI# R7 4.7K_0402_5% U65 NC Y A C1010 18P_0402_50V8J +RTCBATT +RTCBATT 20mil 0.01U_0402_16V7K @ESD@ U56 SA00006ZV00 CS# VCC DO(IO1) HOLD#(IO3) WP#(IO2) CLK GND DI(IO0) R1000 SPI_HOLD# SPI_CLK SPI_MOSI +RTCVCC 0705:for ESD request 0_0402_5% A 1U_0402_16V7K JRTC1 CONN@ LOTES_AAA-BAT-054-K01 SP07000H700 Compal Electronics, Inc Compal Secret Data Security Classification Issued Date 2013/04/12 Deciphered Date 2014/04/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC SPI_CLK R1002 @EMI@ 33_0402_5% D32 BAV70W-7-F_SOT323-3 3.3K_0402_5% Reserve for EMI(Near SPI ROM) C1014 @EMI@ 10P_0402_50V8J + 20mil C1158 SOC_SMI# NL17SZ07DFT2G_SC70-5 SA00004BV00 +3VLP +1.8VALW R998 RS@ B W25Q64DWSSIG_SO8 5 DDR_CORE_PWROK SPI ROM ( 8MByte ) 1.8V 3.3K_0402_5% 3.3K_0402_5% VCCB EO B4 32.768KHZ_12.5PF_Q13FC135000040 Y8 Clear CMOS RTC_RST close to RAM door +BIOS_SPI C1013 R999 R1001 A R446 1K_0402_5% +RTCBATT_R 22_0804_8P4R_5% 22_0402_5% R1016 SPI_CLK SOC_SPI_CLK EMI@ A VCCA GND A4 10M_0402_5% Check Intel 1 RP48 R994 RTC_TEST# RTC_RST# C1012 1U_0402_6.3V6K SOC_SERIRQ SOC_LID_OUT# Y +3VALW_EC SPI_CS0# SPI_MISO SPI_MOSI EC_LID_OUT# EC_LID_OUT# R4 4.7K_0402_5% U59 NC G2129TL1U_SC70-6 SA00007CX00 C1011 1U_0402_6.3V6K 51_0804_8P4R_5% XDP@ 2 XDP_H_TDI XDP_H_TMS XDP_H_TCK XDP_H_TRST# SOC_SERIRQ ILB_RTC_X1 ILB_RTC_X2 XDP_H_PRDY# U67 10 +RTCVCC NL17SZ07DFT2G_SC70-5 SA00004BV00 26 AV32 BA28 AY28 AY30 +1.8VALW GPIO_RCOMP SIO_SPI_CS# / GPIO_S0_SC_66 SIO_SPI_MISO / GPIO_S0_SC_67 SIO_SPI_MOSI / GPIO_S0_SC_68 SIO_SPI_CLK / GPIO_S0_SC_69 Close To SOC