Compal LA 9063p rev 1 0 схема

A B C D E 1 Compal Confidential 2 VIWZ1/VIWZ2 DIS M/B Schematics Document Intel Ivy Bridge Processor with DDRIII + Panther Point PCH nVIDIA N14P-GV2 2012-12-26 3 LA-9063P REV:1.0 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2012/12/26 2012/07/11 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Cover Page Rev 1.0 LA-9603P Date: A B C D Wednesday, January 09, 2013 Sheet E of 62 A B C D U4 Compal confidential HM76@ E U4 HM70@ ZZZ VIWZ1 LA9063 File Name : VIWZ1/VIWZ2 PCH-HM76 PCH-HM70 SA00005FH70 LS9061P PWR/B LS9062P USB/B DA_PCB SA00005MQ80 DA8000XJ000 Page23-32 ZZZ6 15@ LA9063 nVIDIA N14P-GV2 14@ VIWZ2 DA_PCB VRAM 128Mb*16 DDR3*4 1GB Intel Ivy Bridge PCI-E x8 VRAM 256Mb*16 DDR3*4 2GB 100MHz 2.7GT/s Page34 CRT Connector Page33 Page45 BANK 0, 1, 2, Page12-13 Up to 8GB Dual Channel DDR3 1066MHz(1.5V) DDR3 1333MHz(1.5V) DDR3 1600MHz(1.5V) DMI *4 Page5-11 HDMI Connector LVDS Connector DDR3 SO-DIMM *2 Socket-rPGA988B 37.5mm*37.5mm Page35 LS9065P PWR/B LS9062P USB/B LS9063P ODD/B LS9064P LED/B DA8000XJ100 FDI *8 Intel Panther Point LVDS AZALIA channel speaker Audio Codec Realtek Int Digital MIC array Page41 (Combine with webcam) ALC259-VC2 HM70 / HM76 eDP Page41 FCBGA 989 25mm*25mm USB 3.0 USB2.0 USB3.0 *1(Left) include USB2.0*1 Page41 Combo Jack*1 USB2.0 *14 Page43 Camera Conn.Page33 PCI-E x1 *6 BlueTooth Conn Page40 SATA *6 Page14-22 SPIROM BIOS Page14 Card Reader Reltek LPC BUS Realtek Page42 EC RTL8111F(GLAN) RTL8105E-VD(10/100) Page44 RTS5178 for SDR50 SDXC/MMC ENE KB9012 Page37 USB2.0 *2(Right) Page38 RJ-45 Connector Touch Pad Page43 Mini PCIE Half size Slot *1 Mini PCIE Full size Slot *1 PCI-E(WLAN) Thermal Sensor EMC1403 WLAN Page 43 Int KBD Page43 SSD Page36 SATA HDD Page40 Page39 Page36 SATA ODD Issued Date Page40 Compal Electronics, Inc Compal Secret Data Security Classification 2012/12/26 2012/07/11 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Block Diagram Rev 1.0 LA-9603P Date: A B C D Wednesday, January 09, 2013 Sheet E of 62 A B C D SIGNAL Voltage Rails SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS HIGH HIGH HIGH HIGH ON ON ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF STATE Full ON +5VS +1.5VS +V1.05S_VCCP +5VALW +1.5V +VCC_CORE +VGA_CORE +B +3VALW BOARD ID Table +1.8VS +0.75VS Board ID Board ID / SKU ID Table for AD channel PCB Revision +1.05VS S0 O O O O O O X S5 S4/AC O O X X O S5 S4/AC & Battery don't exist X O S3 S5 S4/ Battery only X X X X X X USB 2.0 Device 0001 011X b USB Charger 1010 111X b UHCI0 EHCI1 USB3.0 UHCI1 EC SM Bus2 address Device Smart Battery LA-9061P 1.0 LA-9061P 0.3 LA-9061P 0.2 LA-9061P 0.1 LA-9063P 0.2 LA-9063P 0.2 15_TS UHCI2 Address Thermal Sensor EMC1403 EHCI1 1001_101xb UHCI3 PCH SM Bus address UHCI4 Device Address DDR DIMM0 1001 000Xb DDR DIMM2 1001 010Xb Vcc Ra/Rc/Re Board ID 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V USB Port Table Address EC SM Bus1 address EHCI2 UHCI5 UHCI6 Device Address 1001 111Xb (0x9E) SMBUS Control Table SOURCE SMB_EC_CK1 SMB_EC_DA1 SMB_EC_CK2 SMB_EC_DA2 SMBCLK SMBDATA SML0CLK SML0DATA SML1CLK SML1DATA KB9012 +3VALW KB9012 +3VALW PCH +3VALW PCH +3VALW PCH +3VALW VGA X BATT WLAN KB9012 SODIMM WWAN PCH TP V X X X X X X X X X X X X +3VS V X X X X +3VS V +3VS V X X +3VS X X X X X X X X V X +3VS V X X +3VS V X X +3VS +3VALW BOM Structure OPT@ OPTNOGCLK@ GV2@ GC6@ 10 11 12 13 USB Port (Left Side) USB3.0 Touch Screen Blue Tooth Camera USB Port (Right Side USB-BD) USB Port (Right Side USB-BD) Mini Card(WLAN) Card Reader N14P-GV2 V V V Select V 2012/12/26 2012/07/11 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B C Z-series Z-series Z-series Z-series Re-flash Reserved Reserved Reserved Phase MP PVT DVT EVT EVT DVT PVT MP BOM Structure GV2@ OPT@ UMA@ GV2@ GC6@ OPTNOGCLK@ OPTGCLK@ GCLK@ NOGCLK@ GCLK244@ GCLK304@ CR@ woofer@ Gastube@ RESET@ HDMI@ BT@ ME@ 45@ 8105@ GIGA@ DS3@ NODS3@ AOAC@ NOAOAC@ CMOS@ 14@ 15@ @ CHG@ NOCHG@ KBL@ TS@ HM76@ HM70@ RTS5178@ RTS5170@ TS_14@ TS_15@ Title Notes List Size Document Number Custom D Rev 1.0 LA-9603P Date: A Porject Compal Electronics, Inc Compal Secret Data Security Classification Issued Date V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BTO Item GPU:N14P-GV2 OPTIMUS part integrate Graphic part GPU:N14P-GV2 Strap GPU:N14P-GV2 GC6 function OPTIMUS no support GCLK OPTIMUS support GCLK Support Green CLK not Support Green CLK Support Green CLK 244 Support Green CLK 304 Cardreader Support HP Woofer Gastube EC RESET function HDMI BlueTooth Connector 45 LEVEL 10/100 LAN GIGA LAN Deep Sleep S3 Not Support Deep Sleep S3 ISCT ISCT not support Camera For Z490 (14") For Z590 (15") Unpop USB Charger not USBCharger Keyboard Back Light Touch Screen HM76 by PCH HM70 by PCH Cardreader RTS5178 Cardreader RTS5170 for 14" Touch Screen for 15" Touch Screen External USB Port GPU BOM Structure Table Thermal Sensor V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V BOM Structure Table Port NV-GPU SM Bus address Internal thermal sensor +VCC_GFXCORE_AXG State Clock +3VS power plane E Wednesday, January 09, 2013 Sheet E of 62 Hot plug detect for IFP link C VGA and GDDR3 Voltage Rails D ACTIVE (N13x GPIO) Performance Mode P0 TDP at Tj = 102 C* (GDDR3) GPIO I/O GPIO0 I H GC6_FB_CLAMP GPIO1 OUT - MEM_VDD_CTL GPIO2 OUT H Panel Back-Light brightness(PWM capable) GPIO3 OUT H Panel Power Enable GPIO4 OUT H Panel Back-Light On/Off (PWM) GPIO5 OUT - RESERVED GPU (4) Mem (1,5) NVCLK /MCLK Products (W) (W) (MHz) (V) (A) (W) (A) N13P-GL 64bit 1GB GDDR3 TBD TBD TBD TBD TBD TBD TBD Function Description OUT L GC6_FB_REQ GPIO7 OUT - 3DVision GPIO8 I/O L Thermal Catastrophic Over Temperature GPIO9 OUT L Thermal Alert GPIO10 OUT - Memory VREF Control GPIO11 OUT - PWM_VID GPIO12 IN GPIO13 OUT - GPIO14 OUT N/A GPIO15 IN GPIO16 OUT N/A GPIO17 IN N/A GPIO18 IN GPIO19 IN PCI Express I/O and (1.05V) PLLVDD (6) (1.8V) I/O and PLLVDD (1.05V) Other (W) (A) (W) (mA) (W) (mA) (W) (mA) (W) (mA) (W) TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD (3.3V) D Physical Strapping pin ROM_SCLK GPIO6 FBVDDQ (GPU+Mem) (1.35V) FBVDD (1.35V) NVVDD Logical Strapping Bit3 Logical Strapping Bit1 +3VS_VGA PCI_DEVID[4] Logical Strapping Bit2 SUB_VENDOR ROM_SI +3VS_VGA RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0] ROM_SO +3VS_VGA FB[1] FB[0] SMB_ALT_ADDR VGA_DEVICE STRAP0 +3VS_VGA USER[3] USER[2] USER[1] STRAP1 +3VS_VGA STRAP2 +3VS_VGA PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0] STRAP3 +3VS_VGA SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED STRAP4 +3VS_VGA PCIE_SPEED_ CHANGE_GEN3 PCIE_MAX_SPEED DP_PLL_VDD33V Power Rail Logical Strapping Bit0 SLOT_CLK_CFG/PCI_DEVID[5] USER[0] 3GIO_PAD_CFG_ADR[3] 3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1] RESERVED PEX_PLL_EN_TERM 3GIO_PAD_CFG_ADR[0] C B C AC Power Detect Input (10K pull low) PSI N/A +3VS_VGA B +VGA_CORE tNVVDD >0 +1.5VS_VGA tFBVDDQ >0 +1.05VS_VGA tPEX_VDD >0 all power rail ramp up time should be larger than 40us Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ A A Tpower-off 2.4V 1phase > PSI < 0.8V HW pull high PR826 0_0402_5% @ NVVDD_PWM_VID 2 PR823 0_0402_5% 1 @ PC871 2700P_0402_50V7K 20120919 Change PQ810 gnd net name to gnd from GPU_FBRTN U2_UGATE1 PR801 0_0402_5% @ 20120926 Add PC871 for reserve +VGA_CORE Under VGA Core +VGA_CORE Near VGA Core Issued Date Deciphered Date 2012/07/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C PC826 4.7U_0805_6.3V6K PC839 4.7U_0805_6.3V6K PC838 4.7U_0805_6.3V6K 2 PC824 47U_0805_4V PC868 22U_0805_6.3V6M @ PC863 22U_0805_6.3V6M Compal Electronics, Inc VGA_COREP Size Document Number Rev 0.1 LA-9601P Date: A PC837 4.7U_0805_6.3V6K 1 Compal Secret Data 2008/09/15 PC855 22U_0805_6.3V6M PC828 22U_0805_6.3V6M @ Security Classification PC836 4.7U_0805_6.3V6K 1 PC821 4.7U_0603_6.3V6M PC835 4.7U_0603_6.3V6M PC820 4.7U_0603_6.3V6M PC834 4.7U_0603_6.3V6M PC822 4.7U_0603_6.3V6M PC819 4.7U_0603_6.3V6M PC833 4.7U_0603_6.3V6M PC849 0.1U_0402_10V7K PC818 4.7U_0603_6.3V6M PC832 4.7U_0603_6.3V6M PC817 4.7U_0603_6.3V6M PC816 4.7U_0603_6.3V6M PC845 0.1U_0402_10V7K PR835 0_0402_5% PC831 4.7U_0603_6.3V6M 2 PC843 0.1U_0402_10V7K 1 GPU_HOT# PC830 4.7U_0603_6.3V6M 2 1 100K_0402_1% PC852 PR825 +3VS_VGA 1U_0603_25V7K PR830 2.2_0603_5% 2 PC848 0.1U_0402_10V7K 1 PR831 0_0402_5% +5VS PC829 4.7U_0603_6.3V6M 2 DGPU_PWROK 1U_0402_6.3V6K PC814 PR820 470K_0402_1% PH801 470K_0402_5%_TSM0B474J4702RE PR840 PR833 9.09K_0402_1% 10K_0402_1% +3VS_VGA PC815 4.7U_0603_6.3V6M GPU_VREF Wednesday, January 09, 2013 D Sheet 54 of 62 PC902 1U_0402_16V7K PR904 PR955 CSCOMP 1K_0402_1% DROOP PC937 LG2 [56] PR930 0_0402_5% 6132P_VCCP 1000P_0402_50V7K 3P: 806 2P: 1K A +5VS SW1A [56] SW2 [56] HG1 [56] PR931 BST1_1 2.2_0603_5% PC922 0.22U_0603_25V7K PR928 0_0402_5% CSP2A SW1 [56] 3P: 73.2K 2P: 41.2K PR934 41.2K_0402_1% Option for phase CPU PR935 0_0402_5% CSP3 PC924 1U_0402_16V7K B TSENSE SWN2 [56] 20120723 unmount PR915 and PR946 3P: 2P: 1200p CSSUM PC934 1000P_0402_50V7K CSP1 PC931 1500p0.047U_0402_16V7K CSREF PC936 1000P_0402_50V7K PR952 2NTC_PH201 PR953 75K_0402_1% 165K_0402_1% PH903 20120514 PR9452 6.98K_0402_1% SWN1 [56] PR961 @ 6.98K_0402_1% CSREF PR946 1 PR960 @ 6.98K_0402_1% PC932 1000P_0402_50V7K PR941 6.98K_0402_1% CSP2 CSREF [56] 3Phase: @ 2Phase: install 6132_PWM 2Phase: @ 1Phase: install Option for phase GFX +5VS LG1 [56] BST1 TSENSE CSCOMP PUT COLSE TO VCORE Phase Inductor PC919 0.22U_0603_25V7K PC920 2.2U_0603_10V7K PC927 0.047U_0402_16V7K CSREF PR921 PC918 BSTA1_11 2.2_0603_5% 0.22U_0603_25V7K LG1A [56] PR924 BST2_1 2.2_0603_5% HG2 [56] BST2 3P: 21K 2P: 12.4K 3P: 3.65K 2P: 9.53K 3P: 23.7K 2P: 24.9K HG1A [56] CSP1 CSP2 CSP3 3P: 2200p 2P: 3300p 24.9K_0402_1% 3P: 348 2P: 1.21K 806_0402_1% 2 PC933 PR950 8.06K_0402_1% 1 BSTA1 C +5VS PR943 PC929 1COMP_CPU1 6.04K_0402_1% 1500P_0402_50V7K 3P: 6.04K 2P: 4.32K PR948 0.033U_0402_16V7K PR944 PC930 2FB_CPU3 10_0402_1% 0.033U_0402_16V7K PR947 FB_CPU2 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 22P_0402_50V8J PR942 PC928 2FB_CPU1 49.9_0402_1% 560P_0402_50V7K TRBST# PC926 1 PR940 1K_0402_1% 3P: 330p 2P: 1000p PUT COLSE TO V_GT HOT SPOT PAD VSNA VSPA DIFFA TRBSTA# FBA COMPA IOUTA ILIMA DROOPA CSCOMPA CSSUMA CSREFA CSP2A CSP1A TSNSA B 20120514 Change PC928 to 560P_0402_50V7K SE074561K80 from 680P_0402_50V7K SE074681K80 2P: 36K 1P: 26.1K 6132_PWMA PC923 1000P_0402_50V7K VSP 3P: 22p 2P: 10p 1 PR938 @ 0_0402_5% [9] VCCSENSE VSN 1U_0402_16V7K PR936 @ 0_0402_5% [16] VGATE [9] VSSSENSE 100K_0402_1%_TSM0B104F4251RZ @ PR918 26.1K_0402_1% TRBST# FB_CPU COMP_CPU IMON ILIM_CPU DROOP [42] VR_HOT# PH904 1U_0402_16V7K 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PR933 10K_0402_5% IMVP_IMON PR939 12.4K_0402_1% PR932 @ 75_0402_1% SWN1A [56] CSREFA [56] TRBST# FB COMP IOUT ILIM DROOP CSCOMP CSSUM CSREF CSP3 CSP2 CSP1 TSNS DRVEN PWM 1 +V1.05S_VCCP 6.98K_0402_1% PC914 VCC PWMA VDDBP BSTA VRDYA HGA EN SWA SDIO LGA ALERT# BST2 SCLK HG2 VBOOT NCP6132AMNR2G_QFN60_7X7 SW2 ROSC LG2 VRMP PVCC VRHOT# PGND VRDY LG1 VSN SW1 VSP HG1 DIFF BST1 PC935 2 2.2U_0603_10V7K PR920 2VR_ON_CPU [42] VR_ON 0_0402_5% VR_SVID_DAT1 VR_SVID_ALRT# PR927 PR925 VR_SVID_CLK VBOOT @ PR926 0_0402_5% 95.3K_0402_1% 10K_0402_1% 2VR_SVID_DAT1 ROSC_CPU 10 VRMP CPU_B+ 11 VR_HOT# 12 PR929 1K_0402_1% VGATE 13 14 PC921 +3VS 15 DIFF_CPU [9] VR_SVID_DAT [9] VR_SVID_ALRT# [9] VR_SVID_CLK 6132_VCC 0.01U_0402_25V7K 1 PR913 TSENSEA PU901 1U_0402_16V7K PR923 54.9_0402_1% PR922 130_0402_1% 1U_0402_16V7K PC917 CSP1A PC910 0.047U_0402_16V7K PC911 1000P_0402_50V7K 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 PR919 2_0603_5% PC915 +5VS C SWN1A PH902 100K_0402_1%_TSM0B104F4251RZ DIFFA TRBSTA# FBA COMPA IMONA ILIMA DROOPA PC912 1000P_0402_50V7K PR912 71.5K_0603_1% 2P: 21.5K 1P: 15.8K +V1.05S_VCCP PC916 CSREFA 1 PR954 @ 0_0402_5% [10] VSS_AXG_SENSE CSREFA 1000P_0402_50V7K 2P: 1.65K 1P: 1K PR937 @ 0_0402_5% [10] VCC_AXG_SENSE 2200P_0402_50V7K PC906 DROOPA 6.04K_0402_1% 1K_0402_1% 20120731 Change PR937,PR954,PR926,PR936,PR938 footprint to R0402_0ohm-NEW 20120514 Change PR921 to 71.5K_0603_1% SD014715280 from 63.4K_0603_1% SD014634280 PR910 10P_0402_50V8J PC909 COMPA1 2 1K_0402_1% PR915 1 CSCOMPA PR909 PR906 220K_0402_5%_TSM0B224J4702RE NTC_PH203 200K_0402_1% 680P_0402_50V7K PR907 165K_0402_1% D FBA2 PC908 PR915,PR946=200K(setting 113 degreeC) PR915,PR946=8.25K(setting 93 degreeC) PUT COLSE TO GT Inductor PH901 2 10_0402_1% PC907 PR908 4700P_0402_25V7K 24.9K_0402_1% 2P: 24K 1P: 24.9K 10.7K_0402_1%~N PC905 CSP2A CSP1A TSENSEA 1.21K_0402_1% 1PR914 15.8K_0402_1% CSCOMPA FBA1 PR902 PC903 680P_0402_50V7K PR903 CSSUMA 10_0402_1% TRBSTA# 1 PC901 PR905 75K_0402_1% FBA3 PC904 PR901 1200P_0402_50V7K D 1000P_0402_50V7K 20120514 Change PH901,PH904 to SL200000L00 220K_0402_5%_TSM0B224J4702RE from SL200000500 220K_0402_5%_ERTJ0EV224J 200K_0402_1% @ PR949 143K_0603_1% SWN1 PR951 143K_0603_1% SWN2 PUT COLSE TO VCORE HOT SPOT 20120514 Change PR949,PR951 to 143K_0603_1% SD014143380 from 130K_0603_1% SD014130380 Change PC936 to 1000P_0402_50V7K SE074102K80 from 680P_0402_50V7K SE074681K80 220K_0402_5%_TSM0B224J4702RE A [42] IMVP_IMON Compal Secret Data Security Classification Issued Date 2009/12/01 2012/07/11 Deciphered Date Title Compal Electronics, Inc PWR-CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: C38-G series Chief River Schematic Sheet Wednesday, January 09, 2013 55 of 62 Rev 0.1 4 PC944 0.1U_0402_25V6 2 @ PR957 4.7_1206_5% CSREF [55] [55] LG2 SWN1 [55] TPCA8057-H_PPAK56-8-5 V2N_CPU PR959 10_0402_1% SNUB_CPU2 PR958 10_0402_1% CSREF SWN2 [55] @ PC948 TPCA8057-H_PPAK56-8-5 D PQ904 V1N_CPU2 +VCC_CORE PL903 0.36UH_PCMB104T-R36MH1R105_30A_20% [55] SW2 1SNUB_CPU1 TPCA8065-H_PPAK56-8-5 PC943 10U_0805_25V6K @ PR956 4.7_1206_5% PQ903 PC942 10U_0805_25V6K [55] HG2 PC954 + PQ902 CPU_B+ 1 100U_25V_M PC953 100U_25V_M +VCC_CORE + 5 [55] SW1 [55] LG1 PL901 FBMA-L11-453215800LMA90T_2P PL902 0.36UH_PCMB104T-R36MH1R105_30A_20% TPCA8065-H_PPAK56-8-5 D CPU_B+ B+ PC941 2200P_0402_25V7K [55] HG1 PC940 0.1U_0402_25V6 PQ901 PC939 10U_0805_25V6K PC938 10U_0805_25V6K CPU_B+ PC946 2200P_0402_25V7K 680P_0603_50V7K @ PC949 680P_0603_50V7K C C DC 35W CPU VID1=1.05V IccMax=53A Icc_Dyn=43A Icc_TDC=36A R_LL=1.9m ohm OCP~65A PQ907 PC960 2200P_0402_25V7K PC959 0.1U_0402_25V6 PC958 10U_0805_25V6K PC957 10U_0805_25V6K CPU_B+ B B [55] HG1A +VCC_GFXCORE_AXG 0.36UH_PCMB104T-R36MH1R105_30A_20% [55] SW1A @ PR967 4.7_1206_5% PQ909 TPCA8057-H_PPAK56-8-5 SNUB_GFX1 [55] LG1A V1N_GFX PL905 TPCA8065-H_PPAK56-8-5 PR971 CSREFA [55] 10_0402_1% @ PC968 SWN1A [55] 680P_0603_50V7K A A DC 35W GT2 VID1=1.23V IccMax=33A Icc_Dyn=20.2A Icc_TDC=21.5A R_LL=3.9m ohm OCP~40A Compal Secret Data Security Classification Issued Date 2009/12/01 Deciphered Date 2012/07/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR-CPU_CORE Size C Date: Compal Electronics, Inc Document Number C38-G series Chief River Schematic Wednesday, January 09, 2013 Sheet 56 of 62 Rev 0.1 +VCC_CORE +VCC_CORE PC1 10U_0805_6.3VAM PC2 10U_0805_6.3VAM PC3 10U_0805_6.3VAM Below is 458544_CRV_PDDG_0.5 Table 5-8 +VCC_GFXCORE_AXG Socket Bottom x 22 µF (0805) x (0805) no-stuff sites Socket Top x 22 µF (0805) x (0805) no-stuff sites PC4 10U_0805_6.3VAM PC5 10U_0805_6.3VAM +VCC_GFXCORE_AXG D @ 2 2 2 2 PC19 22U_0805_6.3V6M @ PC18 22U_0805_6.3V6M +VCC_CORE PC11 10U_0805_6.3V6M PC17 22U_0805_6.3V6M PC10 10U_0805_6.3VAM PC16 22U_0805_6.3V6M PC9 10U_0805_6.3VAM @ PC15 22U_0805_6.3V6M PC8 10U_0805_6.3VAM PC14 22U_0805_6.3V6M PC7 10U_0805_6.3VAM PC13 22U_0805_6.3V6M PC6 10U_0805_6.3VAM PC12 22U_0805_6.3V6M @ +V1.05S_VCCP @ PC68 22U_0805_6.3V6M @ PC69 22U_0805_6.3V6M PC65 330U_D2_2.5VY_R9M 20120514 Unpop PC58 + + 2 + PC66 330U_D2_2.5VY_R9M 2 PC67 330U_D2_2.5VY_R9M 20120514 Unpop PC66 PC70 22U_0805_6.3V6M @ 1 @ C @ @ PC64 22U_0805_6.3V6M @ PC56 22U_0805_6.3V6M 2 1 PC35 22U_0805_6.3V6M PC63 22U_0805_6.3V6M 2 @ PC55 22U_0805_6.3V6M PC62 22U_0805_6.3V6M @ PC34 22U_0805_6.3V6M PC61 22U_0805_6.3V6M PC59 330U_D2_2.5VY_R9M PC54 22U_0805_6.3V6M 2 2 PC33 22U_0805_6.3V6M PC60 22U_0805_6.3V6M + PC58 + PC57 330U_D2_2.5VY_R9M 330U_D2_2.5VY_R9M PC53 22U_0805_6.3V6M C 1 PC32 22U_0805_6.3V6M 1 PC52 22U_0805_6.3V6M PC48 22U_0805_6.3V6M PC31 22U_0805_6.3V6M @ 2 PC51 22U_0805_6.3V6M PC47 22U_0805_6.3V6M + 1 PC30 22U_0805_6.3V6M 2 PC50 22U_0805_6.3V6M PC46 22U_0805_6.3V6M 2 +V1.05S_VCCP 1 PC29 22U_0805_6.3V6M 2 1 PC49 22U_0805_6.3V6M PC45 22U_0805_6.3V6M 2 @ PC28 22U_0805_6.3V6M 2 1 PC27 22U_0805_6.3V6M PC44 22U_0805_6.3V6M 2 @ PC26 22U_0805_6.3V6M 2 PC43 22U_0805_6.3V6M PC42 22U_0805_6.3V6M PC41 22U_0805_6.3V6M @ PC40 22U_0805_6.3V6M PC24 22U_0805_6.3V6M PC39 22U_0805_6.3V6M PC23 22U_0805_6.3V6M PC38 22U_0805_6.3V6M PC22 22U_0805_6.3V6M PC37 22U_0805_6.3V6M PC21 22U_0805_6.3V6M PC36 22U_0805_6.3V6M PC20 22U_0805_6.3V6M PC25 22U_0805_6.3V6M 1 D PC71 22U_0805_6.3V6M +VCC_CORE B PC72 330U_D2_2.5VY_R9M + 2 + PC73 330U_D2_2.5VY_R9M PC76 330U_D2_2.5VY_R9M + + B + PC74 330U_D2_2.5VY_R9M PC75 330U_D2_2.5VY_R9M @ 20120514 Unpop PC75 Change PC72,PC73,PC74,PC76 to SGA00006100 from 330U_D2_2.5VY_R9M SGA00002680 20120318 Change PC72,PC73,PC74,PC75 to pin footprint A A Compal Secret Data Security Classification 2008/09/15 Issued Date Deciphered Date 2012/07/11 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Rev 0.1 LA-9601P Date: Compal Electronics, Inc PWR - PROCESSOR DECOUPLING W ednesday, January 09, 2013 Sheet 57 of 62 Version change list (P.I.R List) Item D Page of for PWR Reason for change PG# Modify List Date Phase For EC net name P48 PR206 change pull high voltage to +EC_VCCA from +3VLP 20120316 EVT 20120316 EVT Intersil advise P54 1.Change PR848 to 1.47K SD000009480 from 1.15K 2.Unmount PC864 VGA IMON setting P54 Change PR853 to 11K SD034110280 from 11.3K 20120316 EVT set OCP is 56A P54 Change PR869 to 1.58K (SD00000SJ80) from 1K 20120316 EVT For 1.5V current P51 Add PJ507 for 1.5V 20120321 EVT For B+ layout P55 P50 P51 P50 1.Change 2.Change 3.Change 4.Change 20120321 EVT P53 P54 1.Change +1.05S_VCCP netname to +V1.05S_VCCP 2.Change PQ802.5 netname to +V1.05S_VCCP from +1.05VS 20120330 EVT For HW net name C PC954 pull high to CPU_B+ from B+ 3/5VALWP B+ input netname to CPU_B+ 1.5VALWP B+ input netname to CPU_B+ PR411 netname to CPU_B+ from B+ D C For HW power sequence P54 1.Add control PU801 pin GPU_PWR_EN and reserve PR956 0_0402_5% 2.Change PR820 to SD034150380 150K_0402_1% from 100K 3.Change PC810 to SE071101J80 100P_0402_50V8J from 0.1u 20120330 EVT For Intersil advise P54 Change PR853 pull down netname to gnd 20120409 EVT 10 For IMON design P55 Change PU901 to NCP6132A from ISL95836 20120412 EVT 11 For layout design P54 1.Del PJ803 PJ804 2.Change net name to VGACORE from VGACOREP 20120511 DVT 12 For 1.05V, GFX_CORE,CPU_CORE design fine tune P57 Unpop PC58, PC66,PC75 330U_D2_2.5VY_R9M SGA00002680 20120514 DVT 13 For CPU_CORE design fine tune and ON advise P57 Change PC72,PC73,PC74,PC76 to S POLY C 330U 2V M D2 ESR9M SGA00006100 from 330U_D2_2.5VY_R9M SGA00002680 20120514 DVT 14 For CPU_CORE design fine tune and ON advise P55 1.Change PC928 to 560P_0402_50V7K SE074561K80 from 680P_0402_50V7K SE074681K80 2.Change PR949,PR951 to 140K from 130K 3.Change PR912 to 71.5K_0603_1% SD014715280 from 63.4K_0603_1% SD014634280 4.Change PH901,PH904 to SL200000L00 220K_0402_5%_TSM0B224J4702RE from SL200000500 220K_0402_5%_ERTJ0EV224J 20120514 DVT 15 For material EOL P55 Change PH901,PH904 to SL200000L00 220K_0402_5%_TSM0B224J4702RE from SL200000500 220K_0402_5%_ERTJ0EV224J 20120514 DVT 16 For HW VGA power sequence P54 Add PR972 SD028000080 0_0402_5% Unmount PD801 Change PR820 to 0_0402_5% SD028000080 from 150K_0402_1% SD034150380 Unmount PC810 20120516 DVT B A B 2009/01/06 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date A 2012/07/11 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR (PWR) Rev 0.1 Zx90 Date: W ednesday, January 09, 2013 Sheet 58 of 62 Version change list (P.I.R List) Page of for PWR Item Reason for change PG# Modify List Date Phase 17 For HW reset function P50 1.Add PR420 SD028000080 0_0402_5% for reserve reserve.PR419 and PR420 20120606 PVT 18 For ACDET function P49 1.Change PR313 to 60.4K_0603_1% SD014604280 from 64.9K_0603_1% SD014649280 20120615 PVT 19 For HW Grenn clock UMA sku trial tun P47 unmount PD103 Change PR108 to 150_0603_5% SD013150080 from 560_0603_5% SD013560080 Change PR109 to 1K_0603_5% SD013100180 from 560_0603_5% SD013560080 20120625 PVT 20 For ACDET function P49 1.Change PR313 to 59K_0603_1% SD014590280 from 60.4K_0603_1% SD014604280 20120705 PVT 21 For VR_HOT P55 1.unmount PR915 and PR946 20120705 PVT 22 For HW Grenn clock P47 mount PD103 Change PR108 to 150_0603_5% SD013150080 from 560_0603_5% SD013560080 Change PR109 to 1K_0603_5% SD013100180 from 560_0603_5% SD013560080 20120723 SVT 23 For material issue P51 1.Change PU502 to SA00004CY10 S IC RT8061AZQW WDFN 10P PWM from SA00003RU00 S IC SY8033BDBC DFN 10P SINGLE BUCK 20120723 SVT D C D C B B A A 2009/01/06 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2012/07/11 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR (PWR) Rev 0.1 Zx90 Date: W ednesday, January 09, 2013 Sheet 58 of 62 COMPAL CONFIDENTIAL 10 A1 3 10 V B4 EC PQ2 PCH_RSMRST#_R A4 PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# PM_SLP_SUS# B6 H_CPUPWRGD PLT_RST# SYSON 12 16 CPU SYSON# V +1.5V PU501 V V V PU702 +V1.05S PU602 +V1.05S_VCCP SA_PGOOD V C (DIS) U38 +5VS 8b 8a Q8 +1.5VS PU701 +0.75VS 8a B (DIS) U39 +3VS 13 VR_ON SVID DGPU_PWR_EN PU601 +VCC_SA B 13 DGPU_PWROK SUSP#,SUSP VGATE 11 V ON/OFF PBTN_OUT# 14 V B7 15 SYS_PWROK PM_DRAM_PWRGD PCH V A5 EC_ON V 51ON# V V B3 C PCH_PWROK V V V +5VALW V B2 B+ B7 V B1 A5 V V +3VALW V PU401 V B+ V V PU301 BATT +3V_PCH +5V_PCH B5 V A3 A2 VV VIN V V BATT MODE D PCH_PWROK AC MODE V D MODEL NAME: Power Sequence Block Diagram LA-7981P PCB NAME: REVISION: 2011/07/13 DATE: DGPU SVID PU901 +VCC_CORE A A 14 VGATE Compal Secret Data Security Classification Issued Date 2012/12/26 2012/07/11 Deciphered Date Title Compal Electronics, Inc Power sequence THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 LA-9603P Date: Wednesday, January 09, 2013 Sheet 60 of 62 Version change list (P.I.R List) Item Page of for HW PIR Reason for change PG# Modify List Date Phase Initial EVT D C B D For LVDS blacklight PWM P33 R431 change from 0ohm_short to 0ohm mount For Change Audio Woofer MOSFET from Dual to single channel P15 Changer Part from SB00000EO10 to SB00000EN00 For OVERT# Glitch issue at Power on status P23 5/7 EVT 5/7 EVT Add QV9 5/7 EVT to modify R897 value from ohm to 1K ohm add BT_DISABLE_F_R on JWLN1.51 add R5580 5/8 DVT For BT&WLAN Combo Card P36 For Factory request and cost down LVDS PIN Define P33 To Modify LVDS PIN Define 5/8 DVT P45 P42 To Add PWRSHARE_EN_R on U31.38 To Add EC_PWRSHARE_EN# on U31.74 add R5577 and R5578, delete CHG_ON# 5/8 DVT P42 to change R4959 value from 200K ohm to ohm add R5579 ohm 5/8 DVT P42 P43 add R5581,C1331,R5572,R5583,R5584 and Q156 add EC_TS_ON on U31.66 add +3VS_TS,+3VS_TS_R 5/8 DVT 5/8 DVT 5/8 DVT For USB Charger mode control request To change Reset IC G601 Reserved Touch Screen Power Control 10 To change Speaker PIN define for ME routing request 11 for Realtek Vendor recommand 12 for ME request P39 To Modify H21,H7,H18 PCB Footprint as below H21 from H_3P3 to H_4P6 H7 from H_2P8 to H_3P0 H18 from H_3P3 to H_3P9N 5/8 DVT 13 for LAN Clock be better P37 change C990 value from 5PF to ohm 5/9 DVT 14 for Audio Vendor recommand P43 change JUSB3.11 from GND to +3VS change JUSB3.12 from +3VS to AGND 5/10 DVT 15 for Crystal finetune Capacitor P43 C180,C181 from 18PF to 12PF 5/16 DVT 16 for DVT Board ID request P42 R695 from 33K to 18K 5/17 DVT 17 for PVT request P37 Change Reference from C990 to R5585 5/23 PVT 18 for Surge request P38 C1325,C1326,C1327 change package from 0402 to 0603 5/23 PVT 19 for Reset IC function 5/24 PVT P41 P41 SPK_L2+ R1556 net in JSPK1.1 SPK_L1- R1554 net in JSPK1.2 SPK_R1- R1555 net in JSPK1.3 SPK_R2+ R1553 net in JSPK1.4 R1123,C1134 close to U50.47 R5582,R1559 and C1135 Close to U73.1 EXT_MIC_R P42, add R612,PR420,R4960,R4961 P50,P43 Delete R4959 C B A A Compal Secret Data Security Classification Issued Date 2012/12/26 2012/07/11 Deciphered Date Title Compal Electronics, Inc HW-PIR1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev 1.0 LA-9603P Wednesday, January 09, 2013 Sheet 61 of 62 Version change list (P.I.R List) Item Page of for HW PIR Reason for change PG# Modify List Date P18 Remove R5575,connect DGPU_PWR_EN to U31.pin89 Add diode D60;D61 Phase D D 20 modify N14P_GV2 GPU power sequence 21 for GC6 function 22 for GC6 function 23 P46 P46 due to they are cap not resistor 11/13 PVT PVT add discharge(Q157) for DGPU_PWR_EN P23 Change RV54 from 10K to 100k 11/29 P46 Add a ohm R5597 between Q129 pin and Q130 pin 12/26 P46 R1108,R1112 location change to C1108,C1112 Pre-MP 12/26 Pre-MP C C B B A A Compal Secret Data Security Classification Issued Date 2012/12/26 Deciphered Date 2012/07/11 Title Compal Electronics, Inc HW-PIR1 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev 1.0 LA-9603P Wednesday, January 09, 2013 Sheet 62 of 62 www.s-manuals.com ... 10 6 10 8 11 0 11 2 11 4 11 6 11 8 12 0 12 2 12 4 12 6 12 8 13 0 13 2 13 4 13 6 13 8 14 0 14 2 14 4 14 6 14 8 15 0 15 2 15 4 15 6 15 8 16 0 16 2 16 4 16 6 16 8 17 0 17 2 17 4 17 6 17 8 18 0 18 2 18 4 18 6 18 8 19 0 19 2 19 4 19 6 19 8 200 ... 10 9 11 1 11 3 11 5 11 7 11 9 12 1 12 3 12 5 12 7 12 9 13 1 13 3 13 5 13 7 13 9 14 1 14 3 14 5 14 7 14 9 15 1 15 3 15 5 15 7 15 9 16 1 16 3 16 5 16 7 16 9 17 1 17 3 17 5 17 7 17 9 18 1 18 3 18 5 18 7 18 9 19 1 19 3 19 5 19 7 19 9 2 01 203 ... AH13 AH 10 AG 10 AC 10 Y 10 U 10 P 10 L 10 J14 J13 J12 J 11 H14 H12 H 11 G14 G13 G12 F14 F13 F12 F 11 E14 E12 D E 11 D14 D13 D12 D 11 C14 C13 C12 C 11 B14 B12 A14 A13 A12 A 11 C J23 +V1 .05 S_VCCP 1 C99 0. 1U _04 02 _16 V7K