A B C D E 1 KIWA7/A8 2 Schematics Document Mobile Penryn uFCPGA with Intel Cantiga_GM/PM+ICH9-M core logic 3 REV:0.4 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2008/03/25 Deciphered Date 2008/04/ Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Cover Sheet Size B Document Number Rev 0.4 KIWAX_LA-5082P Date: Wednesday, March 18, 2009 Sheet E of 53 A B C D E ZZZ Compal confidential File Name : CAP SENSE LEDs Board POWER Board USB board 15W_PCB_LA5082P VRAM 64*16 DDRIIpage21,22 Mobile Penryn uFCPGA-478 CPU PCI-E X16 NV10M-GS page16,17,18,19,20 40nm page23 H_A#(3 35) FSB page24 PCBGA 1329 DDR3-SO-DIMM X2 BANK 0, 1, 2, page 14,15 Dual Channel LVDS I/F page26 LVDS Connector DDR3 -800 DDR3-1066 Intel Cantiga GMCH CRT & TV OUT 667/800/1066MHz PCI-E Parade 8101T page24 Clock Gen SLG8SP556VTR ICS9LPRS387AKLFT page5,6,7 H_D#(0 63) HDMI CONN page 8,9,10,11,12,13 DMI page25 C-Line AMP&Audio Jack page36 AZALIA PCI Express Mini card Slot page31 6*PCI-E BUS New Card 3.3V / 33 MHz Audio Codec CX20561 mBGA-676 page35 USB 2.0 BUS page40 BCM5906 10/100/LAN 12*USB2.0 Intel ICH9-M page27,28,29,30 4*SATA serial Card Reader page32 RTS 5159 Northbridge Intel / Cantiga PM45 SA00002JJM0 S IC AC82PM45 QV11 A1 FCBGA 1329 PM C38 CMOS Camera LPC BUS page38 page41 BlueTooth Conn page41 RJ45 CONN page33 Card reader(XD/SD MMC/MS/MS-Pro HD SD) page38 EC ENE KB926 USB conn X2 page41 page37 Int.KBD Touch Pad BIOS SATA HDD Connector page39 Intel / Cantiga GM 45 SA00002JTD0 S IC AC82GM45 SLB94 B3 FCBGA1329 GM C38! SouthBridge Intel / ICH9M SA00002JH90 S IC AF82801IBM SLB8Q A3 676P ICH9M C38! (MP) VGA Chip Nvidia / N10M SA00002V810 S IC N10M-GE1-S-U2(H) BGA 533P C38 VRAM DDR2/512MB SA00002MF00 (14") S IC D2 64M16/500 HYB18T1G161C2F-20 page39 page40 Key component Manufacturer Compal P/N R1 Desc page34 SA00002UH00 (15.6") S IC D2 64M16/500 H5PS1G63EFR-20L FBGA84 SATA CDROM Connector page34 4 Compal Secret Data Security Classification 2007/10/15 Issued Date 2008/10/15 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc MB Block Diagram Size Document Number Custom Date: Rev 0.4 KIWAX_LA-5081P Wednesday, March 18, 2009 Sheet E of 53 A B C DDR3 Voltage Rails D E SMBUS, SPI and I2C Control Table SOURCE HDMI +5VS LVDS CRT HDCP SERIAL EEPROM +3VS +1.5VS power plane +0.75V +VCCP +5VALW +1.5V +B +CPU_CORE +VGA_CORE +3VALW +1.8VS State X LVDS_SCL LVDS_SDA Cantiga X V X X X X X X X X X X X GMCH_CRT_CLK GMCH_CRT_DAT Cantiga HDMICLK_NB HDMIDAT_NB Cantiga VGA X V X X X X X X X X X X X X X X X X X X O O O VGA_LVDS_SCL VGA_LVDS_DAT VGA X VGA_HDMI_SCL VGA_HDMI_DAT VGA X HDCP_SMB_CK1 HDCP_SMB_DA1 VGA X O X X X S5 S4/AC & Battery don't exist X X X X FSEL#SPICS#_SB FRD#SPI_SO_SB SPI_CLK_SB ICH9 FWR#SPI_SI_SB FSEL#SPICS# FRD#SPI_SO SPI_CLK FWR#SPI_SI KB926 X X X V V X V X X X X X X X X X X X X X X X X X X X X X X X X X THERMAL SENSOR (CPU) X V V X X O S5 S4/ Battery only THERMAL SENSOR (VGA) X V V ICH_SMBCLK ICH_SMBDAT S1 O BATT X X X X KB926 O O Mini ICH9 EC_SMB_CK2 EC_SMB_DA2 O S5 S4/AC Mini X V O O sensor CARD1 CARD2 X X X V X V X X X V O O CAP GEN X X X X X X KB926 VGA_DDCCLK VGA_DDCDATA O CLK CARD X X X X X X X X EC_SMB_CK1 EC_SMB_DA1 S0 S3 NEW V X X X X X X V X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X V X X X X X X X X 3 4 Compal Secret Data Security Classification 2007/10/15 Issued Date 2008/10/15 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc MB Notes List Size B Date: Document Number Rev 0.4 KIWAX_LA-5082P Wednesday, March 18, 2009 Sheet E of 53 A B VGA and DDR2 Voltage Rails C D (N10M) E EDP at Tj = 97C* Power Supply Rail NVVDD power plane 180mA 1.1 385mA 180mA +1.1VS (for 55nm) IFPE_IOVDD 1.1 385mA 180mA +1.05VS (for 40nm) IFPF_IOVDD 1.1 385mA 180mA PEX_IOVDD/Q 1.1 1550mA 1550mA PEX_PLLVDD 1.1 165mA 65mA PLLVDD 1.1 55mA 30mA SP_PLLVDD 1.1 25mA 10mA VID_PLLVDD 1.1 50mA 25mA TOTAL 1.1 3.425A 2.435A O O S5 S4/AC & Battery don't exist O X X X X X 25mA IFPD_IOVDD O X 25mA +VGA_CORE O S5 S4/ Battery only 1.1 10mA S1 O 13.47A FB_DLLAVDD 385mA O O 13.56A 10mA O S5 S4/AC 10.87A 1.1 O DDR2 11.22A 1.1 O O GDDR3 IFPC_IOVDD S0 O DDR2 FB_PLLAVDD State O Variable GDDR3 +3VS +1.8VS S3 N10M-GE1-S NB9M-GS (V) X X X X FBVDD/Q 1.8 IFPA_IOVDD 1.8 2.24A 50mA 1.65A 50mA IFPB_IOVDD 1.8 50mA 50mA IFPAB_PLLVDD 1.8 100mA 75mA IFPCD_PLLVDD 1.8 160mA 80mA IFPEF_PLLVDD 1.8 160mA TOTAL 1.8 2.76A 2.24A 1.75A 80mA 2.17A 2.575A DACA_VDD 3.3 110mA 110mA DACB_VDD 3.3 125mA 125mA DACC_VDD 3.3 110mA 110mA MIOA_VDDQ 3.3 10mA 10mA MIOB_VDDQ 3.3 10mA 10mA VDD33 3.3 80mA 80mA 3.3 0.445A 0.445A TOTAL 2.085A POWER SQUENCE The ramp time for any rail must be more than 40us 3 VDD33 (+3VS) PEX_VDD can ramp up any time (1.1VS or 1.05VS) PEX_VDD tNVVDD>=0 (+VGA_CORE) NVVDD tNV-FB tFBVDDQ>=0 (1.8VS) FBVDDQ Compal Secret Data Security Classification 2008/03/24 Issued Date 2008/04/ Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc VGA Notes List Size B Date: Document Number Rev 0.4 KIWA5/6 LA-5081P Wednesday, March 18, 2009 Sheet E of 53 XDP Reserve +3VS XDP_DBRESET# D H_ADSTB#1 (27) (27) (27) (27) H_STPCLK# H_INTR H_NMI H_SMI# A6 A5 C4 A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# A20M# FERR# IGNNE# H_STPCLK# D5 H_INTR C6 H_NMI B4 H_SMI# A3 STPCLK# LINT0 LINT1 SMI# M4 N5 T2 V3 B2 D2 D22 D3 F6 RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] B RSVD pins on the CPU should be left as NO CONNECT H_IERR# H_INIT# LOCK# H4 H_LOCK# RESET# RS[0]# RS[1]# RS[2]# TRDY# C1 F3 F4 G3 G2 H_RESET# H_RS#0 H_RS#1 H_RS#2 H_TRDY# HIT# HITM# G6 E4 H_HIT# H_HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 PROCHOT# THERMDA THERMDC THERMTRIP# H_THERMTRIP# A22 A21 CLK_CPU_BCLK CLK_CPU_BCLK# 54.9_0402_1% D XDP_TRST# R16 54.9_0402_1% XDP_TCK R15 54.9_0402_1% SA00001Z700 SA00001UN00 +3VS R95 10K_0402_5% C89 U5 C 2200p change to 1000p for ADT7421 XDP_DBRESET# (28) 68_0402_5% +3VS +VCCP SMCLK EC_SMB_CK2 DP SMDATA EC_SMB_DA2 DN ALERT# GND VDD H_THERMDA H_THERMDC 2200P_0402_50V7K THERM# THERM# C95 R84 H CLK BCLK[0] BCLK[1] XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET# EMC1402 ADT7421ARMZ +3VS H_HIT# (8) H_HITM# (8) C7 R12 (27) H_RESET# (8) H_RS#0 (8) H_RS#1 (8) H_RS#2 (8) H_TRDY# (8) H_THERMDA H_THERMDC 54.9_0402_1% XDP_TDO R83 56_0402_5% H_LOCK# (8) D21 A24 B25 54.9_0402_1% (8) H_INIT# H_PROCHOT# 2 D20 B3 THERMAL ICH H_A20M# H_FERR# H_IGNNE# (27) H_A20M# (27) H_FERR# (27) H_IGNNE# IERR# INIT# R14 @ (8) (8) (8) H_DEFER# (8) H_DRDY# (8) H_DBSY# (8) H_BR0# R11 XDP_TMS R94 10K_0402_5% EC_SMB_CK2 (16,36) EC_SMB_DA2 (16,36) EMC1402-1-ACZL-TR_MSOP8 Address:100_1100 H_PROCHOT# H_THERMTRIP# (8,27) G990 APL5605 RT9027 CLK_CPU_BCLK (22) CLK_CPU_BCLK# (22) SA00002GW00 SA00001Z900 SA000022J00 FAN1 Conn +5VS +5VS C594 H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil (36) EN_FAN1 +VCC_FAN1 EN_FAN1_R R667 1K_0402_5% Penryn VEN VIN VO VSET GND GND GND GND @ D16 BAS16_SOT23-3 G990P11U_SO8 C810 0.1U_0402_16V4Z C595 1U_0603_10V4Z +3VS C597 0.1U_0402_16V4Z 2 B D17 @ 1SS355TE-17_SOD323-2 U24 FAN solution RC (R=1Kohm,C=0.1uF) EN_FAN1 10U_0805_10V4Z (8) H_BR0# XDP_TDI C Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 H_DEFER# H_DRDY# H_DBSY# F1 BR0# ADDR GROUP_1 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1 H5 F21 E1 H_ADS# H_BNR# H_BPRI# +VCCP REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# H_ADS# H_BNR# H_BPRI# K3 H2 K2 J3 L1 DEFER# DRDY# DBSY# H1 E2 G5 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 ADS# BNR# BPRI# 0.1U_0402_16V4Z H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#[17 35] A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# CONTROL H_ADSTB#0 (8) (8) (8) (8) (8) (8) J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 ADDR GROUP_0 (8) H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0 XDP/ITP SIGNALS H_A#[3 16] RESERVED (8) +VCCP CONN@ JCPUA @ 1K_0402_5% R43 R469 10K_0402_5% 40mil JP13 +VCC_FAN1 (36) FAN_SPEED1 A C596 1000P_0402_50V7K 2 GND GND A E&T_3801-F03N-01R ME@ Compal Secret Data Security Classification 2007/10/15 Issued Date Deciphered Date 2008/10/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Penryn (1/3) Size B Date: Document Number Rev 0.4 KIWAX_LA-5082P W ednesday, March 18, 2009 Sheet of 53 +CPU_CORE +CPU_CORE CONN@ JCPUC R45 R46 H_DSTBN#1 H_DSTBP#1 H_DINV#1 @ 1K_0402_5% @ 1K_0402_5% T16 T15 T14 T17 T10 1 (22) CPU_BSEL0 (22) CPU_BSEL1 (22) CPU_BSEL2 Trace Close CPU < 0.5' D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# +CPU_GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2] Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2 D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3 COMP[0] COMP[1] COMP[2] COMP[3] R26 U26 AA1 Y1 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# E5 B5 D24 D6 D7 AE6 MISC COMP0 COMP1 COMP2 COMP3 A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 (8) H_DSTBN#2 (8) H_DSTBP#2 (8) H_DINV#2 (8) H_D#[48 63] (8) H_DSTBN#3 (8) H_DSTBP#3 (8) H_DINV#3 (8) R63 R64 R10 R9 2 2 27.4_0402_1% 54.9_0402_1% 27.4_0402_1% 54.9_0402_1% H_DPRSTP#_R H_DPSLP# H_DPW R# H_PW RGOOD H_CPUSLP# H_PSI# H_DPSLP# (27) H_DPW R# (8) H_PW RGOOD (27) H_CPUSLP# (8) H_PSI# (49) Penryn Width=4 mil , Spacing: 15mil (55Ohm) R1089 H_DPRSTP#_R (8) H_DPRSTP#_R @ CPU_BSEL1 C1165 C1164 @ 0.01U_0402_16V7K @ CPU_BSEL0 0.01U_0402_16V7K C1163 0.01U_0402_16V7K B CPU_BSEL2 0_0402_5% H_DPRSTP# H_DPRSTP# (27,49) TRACE CLOSELY CPU < 0.5' C1162 COMP0, 68P_0402_50V8K COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms) VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCA[01] VCCA[02] B26 C26 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] AD6 AF5 AE5 AF4 AE3 AF3 AE2 VCCSENSE AF7 VCCSENSE VSSSENSE AE7 VSSSENSE D For testing purpose only +VCCP R47 2 R8 C 0_0402_5% 1 0_0402_5% Near pin B26 20mils CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 (49) (49) (49) (49) (49) (49) (49) 2 0.01U_0402_16V7K (8) (8) (8) N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 DATA GRP C H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# C599 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_D#[16 31] D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# DATA GRP (8) (8) (8) (8) E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 DATA GRP D H_D#[32 47] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0 10U_0805_10V4Z C598 CONN@ JCPUB H_D#[0 15] DATA GRP (8) +1.5VS B VCCSENSE (49) VSSSENSE (49) Penryn layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs BCLK 533 133 0 BSEL2 BSEL1 BSEL0 667 166 1 800 200 1067 266 0 Length match within 25 mils The trace width/space/other is 16/7/25 FSB +VCCP R471 1K_0402_1% +CPU_GTLREF Layout note: Z0=55 ohm 0.5" max for GTLREF A Close to CPU pin AD26 within 500mils Compal Secret Data Security Classification 2007/10/15 Issued Date Deciphered Date 2008/10/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title R23 100_0402_1% VCCSENSE R24 100_0402_1% VSSSENSE Layout Note: Route VCCSENSE and VSSSENSE traces at 27.4 Ohms with 50 mil spacing Place PU and PD within inch of CPU Length matched to within 25 mils R470 2K_0402_1% +CPU_CORE Close to CPU pin within 500mils A Compal Electronics, Inc Penryn (2/3) Size B Date: Document Number Rev 0.4 KIWAX_LA-5082P W ednesday, March 18, 2009 Sheet of 53 CONN@ JCPUD +CPU_CORE Place these capacitors on L8 (North side,Secondary Layer) C13 10U_0805_6.3V6M C39 10U_0805_6.3V6M C36 10U_0805_6.3V6M C30 10U_0805_6.3V6M C27 10U_0805_6.3V6M 2 C19 10U_0805_6.3V6M C14 10U_0805_6.3V6M D C12 10U_0805_6.3V6M +CPU_CORE Place these capacitors on L8 (North side,Secondary Layer) @ C28 10U_0805_6.3V6M @ C24 10U_0805_6.3V6M C40 10U_0805_6.3V6M C37 10U_0805_6.3V6M C31 10U_0805_6.3V6M 2 C26 10U_0805_6.3V6M C20 10U_0805_6.3V6M C15 10U_0805_6.3V6M +CPU_CORE Place these capacitors on L8 (Sorth side,Secondary Layer) C583 10U_0805_6.3V6M C585 10U_0805_6.3V6M C586 10U_0805_6.3V6M C589 10U_0805_6.3V6M C591 10U_0805_6.3V6M 2 C593 10U_0805_6.3V6M C582 10U_0805_6.3V6M C584 10U_0805_6.3V6M C +CPU_CORE Place these capacitors on L8 (Sorth side,Secondary Layer) C588 10U_0805_6.3V6M C587 10U_0805_6.3V6M C590 10U_0805_6.3V6M C592 10U_0805_6.3V6M C35 10U_0805_6.3V6M 2 @ C29 10U_0805_6.3V6M C25 10U_0805_6.3V6M @ C33 10U_0805_6.3V6M Mid Frequence Decoupling South Side Secondary + + @ + C16 330U_D2_2.5VY_R9M C41 330U_D2_2.5VY_R9M +CPU_CORE C17 330U_D2_2.5VY_R9M B P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] 330U_D2_2.5VY_R9M C VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] C47 D A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 + North Side Secondary ESR 1980uF B +VCCP REMOVE? Penryn + C8 220U_D2_4VM 2 C11 0.1U_0402_16V4Z C10 0.1U_0402_16V4Z C51 0.1U_0402_16V4Z C50 0.1U_0402_16V4Z C48 0.1U_0402_16V4Z C9 0.1U_0402_16V4Z Place these inside socket cavity on L8 (North side Secondary) A A Compal Secret Data Security Classification 2007/10/15 Issued Date Deciphered Date 2008/10/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Penryn (3/3) Size B Date: Document Number Rev 0.4 KIWAX_LA-5082P W ednesday, March 18, 2009 Sheet of 53 U26B H_AVREF H_DVREF GM45@ H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 (6) (6) (6) (6) H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 (6) (6) (6) (6) H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 (5) (5) (5) (5) (5) H_RS#0 H_RS#1 H_RS#2 (5) (5) (5) (28,49) CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 CFG5 T48 T47 T45 T41 T50 T49 T39 T43 T38 T37 T46 T42 T55 T53 T54 +3VS R206 10K_0402_5% R217 10K_0402_5% PLT_RST# PM_BMBUSY# H_DPRSTP#_R PM_EXTTS#0 PM_EXTTS#1 PM_POK_R PLT_RST#_R H_THERMTRIP# DPRSLPVR (28) PM_BMBUSY# (6) H_DPRSTP#_R (14,15) PM_EXTTS#0 PM_EXTTS#1 PM_POK_R 0_0402_5% 0309 add @ 0_0402_5% PLT_RST#_R 100_0402_5% R177 R178 R103 +VCCP Near B3 pin SA_ODT_0 SA_ODT_1 SB_ODT_O SB_ODT_1 SM_RCOMP SM_RCOMP# SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF SM_PWROK SM_REXT SM_DRAMRST# DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# PEG_CLK PEG_CLK# DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 PM_SYNC# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 NC_17 NC_18 NC_19 NC_20 NC_21 NC_22 NC_23 NC_24 NC_25 NC_26 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 BC28 AY28 AY36 BB36 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB BA17 AY16 AV16 AR13 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# BD17 AY17 BF15 AY13 M_ODT0 M_ODT1 M_ODT2 M_ODT3 BG22 BH21 SMRCOMP SMRCOMP# BF28 BH28 SMRCOMP_VOH SMRCOMP_VOL AV42 AR36 BF17 BC36 +DDR_MCH_REF SM_PWROK SM_REXT TP_SM_DRAMRST# B38 A38 E41 F41 CLK_MCH_DREFCLK CLK_MCH_DREFCLK# MCH_SSCDREFCLK MCH_SSCDREFCLK# F43 E43 CLK_MCH_3GPLL CLK_MCH_3GPLL# AE41 AE37 AE47 AH39 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 AE40 AE38 AE48 AH40 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 AE35 AE43 AE46 AH42 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 AD35 AE44 AF46 AH43 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 B33 B32 G33 F33 E33 GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VID_4 C34 GFX_VR_EN T90 T89 T65 T64 T63 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 R497 (14) (14) (15) (15) DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CKE2_DIMMB DDR_CKE3_DIMMB (14) (14) (15) (15) DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS2_DIMMB# DDR_CS3_DIMMB# (14) (14) (15) (15) M_ODT0 M_ODT1 M_ODT2 M_ODT3 PAD PAD PAD PAD PAD (14) (14) (15) (15) (14) (14) (15) (15) +1.5V 20mil For Crestline: 20ohm For Calero: 80.6ohm For Cantiga: 80.6ohm 80.6_0402_1% D R125 80.6_0402_1% R483 R175 @ 0_0402_5% 12K_0402_5% R148 @ SM_DRAMRST# 1.5V_PGOOD (47) DDR3_SM_PWROK (36) 10K_0402_5% R111 499_0402_1% (14,15) DDR3 CLK_MCH_DREFCLK (22) CLK_MCH_DREFCLK# (22) MCH_SSCDREFCLK (22) MCH_SSCDREFCLK# (22) CLK_MCH_3GPLL (22) CLK_MCH_3GPLL# (22) DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 (28) (28) (28) (28) DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 (28) (28) (28) (28) DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 (28) (28) (28) (28) DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 (28) (28) (28) (28) C MCH_HDA_BCLK connect to power CPU_CORE C646 10P_0402_50V8J @ T91 +VCCP For AMT function AH37 AH36 AN36 AJ35 AH34 CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF CL_CLK0 CL_DATA0 R143 CL_CLK0 (28) CL_DATA0 (28) M_PWROK (28) CL_RST# (28) CL_RST# CL_VREF 1K_0402_1% 0.1U_0402_16V4Z N28 M28 G36 E36 K36 H36 DDPC_CTRLCLK DDPC_CTRLDATA SDVO_CTRLCLK SDVO_CTRLDATA CLKREQ# ICH_SYNC# HDMICLK_NB HDMIDAT_NB MCH_CLKREQ# MCH_ICH_SYNC# B12 TSATN# B28 B30 B29 C29 A28 HDA_BCLK HDA_RST# HDA_SDI HDA_SDO HDA_SYNC CANTIGA ES_FCBGA1329 T52 T51 56_0402_5% MCH_HDA_BCLK MCH_HDA_RST# MCH_HDA_SDIN MCH_HDA_SDOUT MCH_HDA_SYNC C238 HDMICLK_NB (23) HDMIDAT_NB (23) MCH_CLKREQ# (22) MCH_ICH_SYNC# (28) R105 GM45@ DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 AR24 AR21 AU24 AV20 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 COMPENSATION SA_CS#_0 SA_CS#_1 SB_CS#_0 SB_CS#_1 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 R80 R82 R79 R85 R81 B R147 499_0402_1% TSATN# (36) +VCCP 1GM_HDMI@2 1GM_HDMI@2 1GM_HDMI@2 1GM_HDMI@2 1GM_HDMI@2 0_0402_5% 0_0402_5% 33_0402_5% 0_0402_5% 0_0402_5% HDA_BITCLK_CODEC HDA_RST_CODEC# HDA_SDIN0 (27) HDA_SDOUT_CODEC HDA_SYNC_CODEC (16,27,34) (16,27,34) (16,27,34) (16,27,34) Notice: Please check HDA power rail to select HDA controller R162 10K_0402_5% 2 +DDR_MCH_REF +DDR_MCH_REF R185 10K_0402_5% C273 0.1U_0402_16V4Z 0.1U_0402_16V4Z C616 R482 221_0603_1% R484 within 100 mils from NB +1.5V H_SWNG 100_0402_1% C623 R89 24.9_0402_1% 1 R493 1K_0402_1% R488 2K_0402_1% Layout Note: V_DDR_MCH_REF trace width and spacing is 20/20 R29 B7 N33 P32 AT40 AT11 T20 R32 BG48 BF48 BD48 BC48 BH47 BG47 BE47 BH46 BF46 BG45 BH44 BH43 BH6 BH5 BG4 BH3 BF3 BH2 BG2 BE2 BG1 BF1 BD1 BC1 F1 A47 +VCCP CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 PM_EXTTS#0 PM_EXTTS#1 VGATE T25 R25 P25 P20 P24 C25 N24 M24 E21 C23 C24 N21 P21 T21 R20 M20 L21 H21 P29 R28 T28 NC (16,26,30,31) RSVD22 RSVD23 RSVD24 RSVD25 CLK MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 (22) MCH_CLKSEL0 (22) MCH_CLKSEL1 (22) MCH_CLKSEL2 (6) (6) (6) (6) (28,36) ICH_POK BG23 BF23 BH18 BF18 DMI H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 Route H_SCOMP and H_SCOMP# with trace width spacing and impedance (55 ohm) same as FSB data traces H_RCOMP T87 T88 T34 T35 RSVD20 SA_CKE_0 SA_CKE_1 SB_CKE_0 SB_CKE_1 AP24 AT21 AV24 AU20 1K_0402_1% SA_CK#_0 SA_CK#_1 SB_CK#_0 SB_CK#_1 DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 layout note: 0.1U_0402_16V4Z H_VREF AY21 R500 (5,27) H_THERMTRIP# (28,49) DPRSLPVR Layout Note: H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20 T40 RSVD15 RSVD16 RSVD17 H_ADS# (5) H_ADSTB#0 (5) H_ADSTB#1 (5) H_BNR# (5) H_BPRI# (5) H_BR0# (5) H_DEFER# (5) H_DBSY# (5) CLK_MCH_BCLK (22) CLK_MCH_BCLK# (22) H_DPWR# (6) H_DRDY# (5) H_HIT# (5) H_HITM# (5) H_LOCK# (5) H_TRDY# (5) CANTIGA ES_FCBGA1329 B B31 B2 M1 2 T56 T84 T83 DDR CLK/ CONTROL/ 1 C640 0.01U_0402_16V7K H_RS#0 H_RS#1 H_RS#2 C636 B6 F12 C8 0.01U_0402_16V7K H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 2.2U_0603_6.3V4Z C641 B15 K13 F13 B13 B14 2.2U_0603_6.3V4Z C635 L9 M8 AA6 AE5 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 SMRCOMP_VOL SA_CK_0 SA_CK_1 SB_CK_0 SB_CK_1 H_RS#_0 H_RS#_1 H_RS#_2 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 R501 3.01K_0402_1% NA lead free RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 H_CPURST# H_CPUSLP# L10 M7 AA5 AE6 SMRCOMP_VOH 1K_0402_1% M36 N36 R33 T33 AH9 AH10 AH12 AH13 K12 AL34 AK34 AN35 AM35 T24 GRAPHICS VID H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 R126 H_SWING H_RCOMP J8 L3 Y13 Y1 T69 T70 T58 T66 T23 T25 T27 T30 T26 T62 T61 T67 T68 T44 PM A11 B11 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# +1.5V ME H_VREF H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 H12 B16 G17 A9 F11 G12 E9 B10 AH7 AH6 J11 F9 H9 E12 H11 C9 (5) MISC H_RESET# H_CPUSLP# C12 E11 H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 HDA H_RESET# H_CPUSLP# H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# A14 C15 F16 H13 C18 M16 J13 P16 R16 N17 M13 E17 P17 F17 G20 B19 J16 E20 H16 J20 L17 A17 B17 L16 C21 J17 H20 B18 K17 B20 F21 K21 L20 C5 E3 H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 CFG H_SWNG H_RCOMP H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 RSVD C F2 G8 F8 E6 G2 H6 H2 F6 D4 H3 M9 M11 J1 J2 N12 J6 P2 L2 R2 N9 L6 M5 J3 N2 R1 N5 N6 P13 N8 L7 N10 M3 Y3 AD14 Y6 Y10 Y12 Y14 Y7 W2 AA8 Y9 AA13 AA9 AA11 AD11 AD10 AD13 AE12 AE9 AA2 AD8 AA3 AD3 AD7 AE14 AF3 AC1 AE3 AC3 AE11 AE8 AG2 AD6 D (5) (6) H_A#[3 35] U26A H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_D#[0 63] HOST (6) A A Compal Secret Data Security Classification Issued Date 2007/10/15 Deciphered Date 2008/10/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Cantiga GMCH(1/6)-GTL Size C Date: Compal Electronics, Inc Document Number Rev 0.4 KIWAX_LA-5082P Wednesday, March 18, 2009 Sheet of 53 D D (15) DDR_B_D[0 63] GM45@ BD21 BG18 AT25 DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2 SA_RAS# SA_CAS# SA_WE# BB20 BD20 AY20 DDR_A_RAS# DDR_A_CAS# DDR_A_W E# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 AM37 AT41 AY41 AU39 BB12 AY6 AT7 AJ5 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 AJ44 AT44 BA43 BC37 AW12 BC8 AU8 AM7 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 AJ43 AT43 BA44 BD37 AY12 BD8 AU9 AM8 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 SA_MA_14 BA21 BC24 BG24 BH24 BG25 BA24 BD24 BG27 BF25 AW24 BC21 BG26 BH26 BH17 AY25 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_BS#0 (14) DDR_A_BS#1 (14) DDR_A_BS#2 (14) DDR_A_RAS# (14) DDR_A_CAS# (14) DDR_A_W E# (14) SYSTEM MEMORY A DDR_A_DM[0 7] (14) DDR_A_DQS[0 7] DDR_A_DQS#[0 7] DDR_A_MA[0 14] (14) (14) (14) U26E DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 AK47 AH46 AP47 AP46 AJ46 AJ48 AM48 AP48 AU47 AU46 BA48 AY48 AT47 AR47 BA47 BC47 BC46 BC44 BG43 BF43 BE45 BC41 BF40 BF41 BG38 BF38 BH35 BG35 BH40 BG39 BG34 BH34 BH14 BG12 BH11 BG8 BH12 BF11 BF8 BG7 BC5 BC6 AY3 AY1 BF6 BF5 BA1 BD3 AV2 AU3 AR3 AN2 AY2 AV1 AP3 AR1 AL1 AL2 AJ1 AH1 AM2 AM3 AH3 AJ3 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 SB_BS_0 SB_BS_1 SB_BS_2 BC16 BB17 BB33 DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2 SB_RAS# SB_CAS# SB_WE# AU17 BG16 BF14 DDR_B_RAS# DDR_B_CAS# DDR_B_W E# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 AM47 AY47 BD40 BF35 BG11 BA3 AP1 AK2 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 AL47 AV48 BG41 BG37 BH9 BB2 AU1 AN6 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 AL46 AV47 BH41 BH37 BG9 BC2 AT2 AN5 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 SB_MA_14 AV17 BA25 BC25 AU25 AW25 BB28 AU28 AW28 AT33 BD33 BB16 AW33 AY33 BH15 AU33 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 B SA_BS_0 SA_BS_1 SA_BS_2 MEMORY B SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 DDR C AJ38 AJ41 AN38 AM38 AJ36 AJ40 AM44 AM42 AN43 AN44 AU40 AT38 AN41 AN39 AU44 AU42 AV39 AY44 BA40 BD43 AV41 AY43 BB41 BC40 AY37 BD38 AV37 AT36 AY38 BB38 AV36 AW36 BD13 AU11 BC11 BA12 AU13 AV13 BD12 BC12 BB9 BA9 AU10 AV9 BA11 BD9 AY8 BA6 AV5 AV7 AT9 AN8 AU5 AU6 AT5 AN10 AM11 AM5 AJ9 AJ8 AN12 AM13 AJ11 AJ12 SYSTEM U26D DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR (14) DDR_A_D[0 63] GM45@ CANTIGA ES_FCBGA1329 DDR_B_BS#0 (15) DDR_B_BS#1 (15) DDR_B_BS#2 (15) DDR_B_RAS# (15) DDR_B_CAS# (15) DDR_B_W E# (15) DDR_B_DM[0 7] (15) C DDR_B_DQS[0 7] (15) DDR_B_DQS#[0 7] DDR_B_MA[0 14] (15) (15) B CANTIGA ES_FCBGA1329 A A Compal Secret Data Security Classification 2007/10/15 Issued Date Deciphered Date 2008/10/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Cantiga GMCH (2/6)-DDRII Size B Date: Document Number Rev 0.4 KIWAX_LA-5082P W ednesday, March 18, 2009 Sheet of 53 Strap Pin Table 000 = FSB 1066MHz 010 = FSB 800MHz 011 = FSB 667MHz Others = Reserved CFG[2:0] FSB Freq select PCIE_MTX_C_GRX_N[0 15] PCIE_MTX_C_GRX_P[0 15] R90 R91 +3VS D GM@ GM@ 2.2K_0402_5% 2.2K_0402_5% PCIE_GTX_C_MRX_N[0 15] LVDS_SCL LVDS_SDA PCIE_MTX_C_GRX_N[0 15] (16) PCIE_MTX_C_GRX_P[0 15] (16) PCIE_GTX_C_MRX_N[0 15] PCIE_GTX_C_MRX_P[0 15] (16) CFG[4:3] Reserved CFG5 (DMI select) = DMI x = DMI x = The iTPM Host Interface is enable CFG6 Place the resistor within 500mils (1.27mm)of the (G)MCH PEGCOMP trace width and spacing is 20/25 mils U26C R167 (24) LVDS_ACLK# (24) LVDS_ACLK Note: All LVDS data signals/and it's compliments should be routed Differentially (24) LVDS_A0# (24) LVDS_A1# (24) LVDS_A2# R121 R122 PM@ PM@ 0_0402_5% 0_0402_5% 0_0402_5% 2 R122 GM@ GM@ R132 C41 C40 B37 A37 LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK LVDS_A0# LVDS_A1# LVDS_A2# T93 H47 E46 G40 A40 LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 LVDSA_DATA#_3 T94 H48 D45 F40 B40 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 LVDSA_DATA_3 T72 A41 H38 G37 J37 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 LVDSB_DATA#_3 T73 B42 G38 F37 K37 75_0402_5% TVA_DAC 75_0402_5% TVB_DAC 75_0402_5% TVC_DAC R124 TVA_DAC TVB_DAC TVC_DAC F25 H25 K25 TVA_DAC TVB_DAC TVC_DAC H24 TV_RTN C31 E32 TV_DCONSEL_0 TV_DCONSEL_1 GMCH_CRT_B E28 CRT_BLUE GMCH_CRT_G G28 CRT_GREEN J28 CRT_RED G29 CRT_IRTN R123 B PM@ 0_0402_5% PM@ PM@ 0_0402_5% 0_0402_5% GMCH_CRT_R (25) GMCH_CRT_B 150_0402_1% GMCH_CRT_G (25) GMCH_CRT_G 150_0402_1% GMCH_CRT_B (25) GMCH_CRT_R 150_0402_1% GMCH_CRT_CLK H32 GMCH_CRT_DATA J32 J29 E29 (25) GMCH_CRT_CLK (25) GMCH_CRT_DATA (25) GMCH_CRT_HSYNC R203 GMCH_CRT_R GM@ 33_0402_1% 20mil (25) GMCH_CRT_VSYNC L29 GM@ 33_0402_1% CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC T37 T36 PEGCOMP = The iTPM Host Interface is disable CFG7 (Intel Management Engine Crypto strap) +VCC_PEG 49.9_0402_1% R1631 PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 H44 J46 L44 L40 N41 P48 N44 T43 U43 Y43 Y48 Y36 AA43 AD37 AC47 AD39 PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_N15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 H43 J44 L43 L41 N40 P47 N43 T42 U42 Y42 W47 Y37 AA42 AD36 AC48 AD40 PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_P15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 J41 M46 M47 M40 M42 R48 N38 T40 U37 U40 Y40 AA46 AA37 AA40 AD43 AC46 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15 C277 C303 C317 C315 C325 C343 C358 C349 C368 C354 C371 C356 C372 C364 C375 C348 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_N15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 J42 L46 M48 M39 M43 R47 N37 T39 U36 U39 Y39 Y46 AA36 AA39 AD42 AD46 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15 C271 C296 C314 C311 C322 C336 C352 C344 C363 C346 C366 C351 C367 C359 C373 C347 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K 0.1U_0402_10V7K PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15 Please check Power source if want support IAMT * =(TLS)chiper suite with no confidentiality =(TLS)chiper suite with confidentiality CFG8 Reserved CFG9 = Reverse Lane,15->0, 14->1 (PCIE Graphics Lane Reversal) = Normal Operation,Lane Number in order CFG10 (PCIE Lookback enable) * = Enable = Disable CFG11 Reserved CFG[13:12] (XOR/ALLZ) 00 01 10 11 CFG[15:14] Reserved CFG16 (FSB Dynamic ODT) = Disabled * = Reserved = XOR Mode Enabled = All Z Mode Enabled = Normal Operation (Default) = Enabled * C * CFG[18:17] Reserved CFG19 (DMI Lane Reversal) = Normal Operation (Lane number in Order) * = Reverse Lane CFG20 (PCIE/SDVO concurrent) * = Only PCIE or SDVO is operational = PCIE/SDVO are operating simu B R204 VGA GM@ R132 GM@ R124 GM@ R123 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 LVDSB_DATA_3 TV R121 GM@ LVDS_ACLK# LVDS_ACLK R127 PM@ R127 LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDS_A0 LVDS_A1 LVDS_A2 (24) LVDS_A0 (24) LVDS_A1 (24) LVDS_A2 Layout Note: Place 150 Ohmtermination resistors close to GMCH C44 B43 E37 E38 2.37K_0402_1% PEG_COMPI PEG_COMPO LVDS C L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN T1 GMCH_ENBKL 10K_0402_5% 10K_0402_5% GRAPHICS (24) LVDS_SCL (24) LVDS_SDA (24) GM_ENVDD For Cantiga:2.37kohm For Crestline:2.4kohm For Calero: 1.5Kohm L32 G32 M32 M33 K33 J33 M29 R213 R159 LVDS_SCL LVDS_SDA GM_ENVDD PCI-EXPRESS (24) GMCH_ENBKL +3VS D * PCIE_GTX_C_MRX_P[0 15] (16) R140 0_0402_5% PM@ R138 R139 0_0402_5% PM@ CANTIGA ES_FCBGA1329 GM45@ 1.02K_0402_1% GM@ R138 A For Cantiga:1.02kohm For Crestline:1.3kohm For Calero: 255ohm PCIE_MTX_GRX_P3 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_N0 C670 C674 C669 C673 C662 C663 C658 C661 1 1 1 1 PM@ PCIE_GTX_C_MRX_P3 R640 2 2 2 2 GM_HDMI@0.1U_0402_10V7K GM_HDMI@0.1U_0402_10V7K GM_HDMI@0.1U_0402_10V7K GM_HDMI@0.1U_0402_10V7K GM_HDMI@0.1U_0402_10V7K GM_HDMI@0.1U_0402_10V7K GM_HDMI@0.1U_0402_10V7K GM_HDMI@0.1U_0402_10V7K 0_0402_5% GM_HDMI@ TMDS_B_CLK (23) TMDS_B_CLK# (23) TMDS_B_DATA0 (23) TMDS_B_DATA0# (23) TMDS_B_DATA1 (23) TMDS_B_DATA1# (23) TMDS_B_DATA2 (23) TMDS_B_DATA2# (23) A TMDS_B_HPD# (23) 0_0402_5% Compal Secret Data Security Classification 2007/10/15 Issued Date Deciphered Date 2008/10/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Cantiga GMCH (3/6)-VGA/LVDS/TV Size Document Number Custom Date: Rev 0.4 KIWAX_LA-5082P Sheet W ednesday, March 18, 2009 10 of 53 FOR EC 16M SPI ROM +3VALW 20mils C504 0.1U_0402_16V4Z R233 10K_0402_5% INT_SPI_CS# SPI_SO 15_0402_5% R234 1 U48 FRD#SPI_SO (36) FRD#SPI_SO CS# SO WP# GND VCC HOLD# SCLK SI SPI_CLK_R SPI_SI R235 R236 15_0402_5% 15_0402_5% SPI_CLK FWR#SPI_SI SPI_CLK (36) FWR#SPI_SI (36) SPI_CLK_R 2 MX25L1605AM2C-12G_SO8 R237 33_0402_5% +3VALW C505 22P_0402_50V8J U49 INT_SPI_CS# R239 15_0402_5% INB O @ R240 +3VALW JP29 FSEL#SPICS# SPI_SO (28) SB_INT_FLASH_SEL 22_0402_5% 8 INT_FLASH_EN# SPI_CLK_R SPI_SI FD1 FD2 FD3 FD4 ME@ E&T_2941-G08N-00E~D H1 HOLEA BT_LED# (40) WLAN_LED# (30) 0_0402_5% WLAN@ 0_0402_5% H11 HOLEA H23 HOLEA LED3 H12 HOLEA H20 HOLEA H14 HOLEA H15 HOLEA H21 HOLEA H16 HOLEA H10 HOLEA H9 HOLEA 1 H13 HOLEA H8 HOLEA H17 HOLEA R25 H7 HOLEA 1 BT@ R22 H6 HOLEA LED2 2 R241 300_0402_5% S LED 19-215SUBC/S280/TR8 0603 BLUE 470_0402_5% H4 HOLEA Green H5 HOLEA R242 H3 HOLEA H19 HOLEA DRIVE_LED# (27) S LED 19-215SUBC/S280/TR8 0603 BLUE LED +5VALW +5VS H2 HOLEA H H H H H L MC74VHC1G32DFT2G_SC70-5 FSEL#SPICS# (36) H FSEL#SPICS# L H INT_FLASH_EN# 100K_0402_5% G INA L L R238 L OR Gate OUTPUT Y B P INPUT A LED4 R243 470_0402_5% R244 300_0402_5% PWR_LED_SC# (36) S LED 19-215SUBC/S280/TR8 0603 BLUE LED5 Blue CHARGE_LED0# CHARGE_LED0# (36) S LED 19-215SUBC/S280/TR8 0603 BLUE 7.3mA +3VALW R245 499_0402_1% LED6 Amber CHARGE_LED1# CHARGE_LED1# (36) S LED 19-217/S2C-FM2P1VY/3T 0603 ORANGE 6mA Compal Secret Data Security Classification Issued Date 2007/10/15 Deciphered Date 2008/10/15 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc LED/EC SPI ROM Size B Date: Document Number Rev 0.4 KIWA5/6 LA-5081P Wednesday, March 18, 2009 Sheet 39 of 53 A B C D E +5VALW +USB_VCCA U50 C440 0.1U_0402_16V4Z (36) USB_ON USB_ON GND IN IN EN OUT OUT OUT OC# LIFT USB CONN USB_OC#0 (28) G545A1P1U_SO8 LIFT USB CONN USB_OC#1 (28) 1 +USB_VCCA C444 @ 1000P_0402_50V7K +USB_VCCA W=60mils +USB_VCCA W=60mils + 1 C443 150U_B2_6.3VM_R35M C441 470P_0402_50V7K 2 C442 470P_0402_50V7K JUSB1 D6 USB20_P0 USB20_N0 D7 USB20_P1 USB20_N1 USB20_N0 USB20_P0 (28) USB20_N0 (28) USB20_P0 VCC DD+ GND GND1 GND2 GND3 GND4 PJDLC05_SOT23-3 @ PJDLC05_SOT23-3 @ Source:DC233001X00 2nd source:DC233002C00 JUSB2 (39) USB20_N1 USB20_P1 (28) USB20_N1 (28) USB20_P1 Source:DC233001X00 2nd source:DC233002C00 SUYIN_020173MR004G579ZR ME@ BT_LED# S R247 0_0603_5% C445 0.1U_0402_16V4Z +5VS 2 Q19 SI2301BDS-T1-E3_SOT23-3 +3VS CMOS1 +3VS_BT 30mils 2 C446 0.1U_0402_16V4Z SI2301BDS-T1-E3_SOT23-3 change pin define for new symbol (JP22) on C test OUT C447 10U_0805_10V4Z ACES_88266-05001 (36) ME@ BT_OFF# IN Q22 DTC124EKAT146_SC59-3 3 GND OUT GND Q21 DTC124EKAT146_SC59-3 GND1 GND2 2 GND1 GND2 MOLEX_53780-0870 ME@ Q20 G USB20_N2 USB20_P2 USB20_N2 USB20_P2 R248 10K_0402_1% D JP31 (28) (28) 10 BTON_LED WLAN_ACTIVE BT_ACTIVE USB20_P6 USB20_N6 (30) WLAN_ACTIVE (30) BT_ACTIVE (28) USB20_P6 (28) USB20_N6 S GND1 GND2 GND3 GND4 SUYIN_020173MR004G579ZR ME@ IN JP30 IN G R246 10K_0402_5% GND 1 D VCC DD+ GND OUT +5VS (36) CMOS_OFF# BT MODULE CONN Q18 DTC124EKAT146_SC59-3 CMOS Camera Conn 2 LIFT USB CONN +5VALW +USB_VCCC U53 JP10 (28) USB20_P4 (28) USB20_N4 USB20_P4 USB20_N4 GND GND 1 C450 0.1U_0402_16V4Z (36) USB_ON GND IN IN EN OUT OUT OUT OC# + USB_OC#4 (28) G545A1P1U_SO8 C449 150U_B2_6.3VM_R35M C448 @ 470P_0402_50V7K D5 USB20_N4 USB20_P4 1 +USB_VCCC 1 R20 100K_0402_5% @ 2 ACES_85201-06051 ME@ PJDLC05_SOT23-3 @ C451 @ 1000P_0402_50V7K 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/08/18 Deciphered Date 2007/8/18 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Power OK, Reset and RTC Circuit, TP Size Document Number Custom Date: Rev 0.4 KIWA5/6 LA-5081P Wednesday, March 18, 2009 Sheet E 40 of 53 Switch Board Conn +5VS 2 +3VS +3VALW NOVO_BTN# 100K_0402_5% NUM_LED# =>ESB_DA 51_ON# (36) (36) (36) @ NOVO_BTN# R256 DAN202UT106_SC70-3 ON/OFF switchSW NOSB@ 51_ON# 51_ON# (43) W LAN@ 1 @ C457 1000P_0402_50V7K +3VALW (36) D43 @ RLZTE1120A LL34 KILL_SW # G R18 SW 100K_0402_5% 3 2 1 KILL_SW# @ @ @ D EC_ON NOVO_BTN# ON/OFF# (36) DAN202UT106_SC70-3 R261 4.7K_0402_5% ON/OFFBTN# I2C_INT_C ON/OFF# +3VALW EC_ON NOSB@ 0_0402_5% Kill Switch R260 100K_0402_5% D42 ON/OFFBTN# (36) ACES_87151-0807G ME@ done 0.1U_0402_25V6 @ JOPEN @ JOPEN Bottom Side @ C456ENE@ 18P_0402_50V8J +3VALW TOP Side 2 C455 18P_0402_50V8J ENE@ R256, R258 change SD028300080 to SM010027780 02/26 remove SMbus for CY SMT1-05_4P J6 ESB_CK_C ESB_DA_C I2C_INT_C J5 2 300_0402_5% 300_0402_5% 0_0402_5% R258 0_0402_5% Power Button R256 R258 ENE@ R259 ENE@ ENE@ ESB_CK ESB_DA I2C_INT GND GND 0.1U_0402_25V6 C454 51_ON# NOVO# ON/OFFBTN# NOVO_BTN# 0.1U_0402_16V4Z C453 (43) No switch board: CAPS_LED# =>ESB_CK JP33 10 C452 NOVO# PJSOT24C_SOT23-3 D41 (36) ENE@ 2 R250 ON/OFFBTN# R13 0_0603_5% R249 0_0603_5% D10 1BS003-1211L_3P W LAN@ Q23 S 2N7002_SOT23 R251 10K_0402_5% Lid Switch +VCC_LID 0_0402_5% R284 1 A3212ELHLT-T_SOT23W -3 OUTPUT LID_SW # (36) GND C475 0.1U_0402_16V4Z 100K_0402_5% VDD R283 +3VALW U58 C476 10P_0402_50V8J Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2008/03/25 Deciphered Date 2008/04/ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Audio Jack & SW connector Size Document Number Custom Rev 0.4 KIWA5/6 LA-5081P Date: W ednesday, March 18, 2009 Sheet 41 of 53 A B C +5VALW TO +5VS +3VALW R263 470_0603_5% B+ B+ D 1 3 C55 0.1U_0402_16V4Z C53 0.1U_0402_16V4Z C52 0.1U_0402_16V4Z C54 0.1U_0402_16V4Z SUSP G Q26 2N7002_SOT23 2 R267 47K_0402_5% C467 0.1U_0603_25V7K SUSP D Q29 2N7002_SOT23 G S @ S 1 R269 0_0402_5% Q28 2N7002_SOT23 S 5VS_GATE D G R264 470_0603_5% D SUSP G Q25 2N7002_SOT23 S R266 20K_0402_5% +5VS +3VS U55 D S D 1 S D S C461 C462 C463 G 10U_0805_10V4Z D 10U_0805_10V4Z 1U_0603_10V4Z 2 SI4800BDY-T1-E3_SO8 +5VS U54 D S D 1 S D S C458 C459 C460 G 10U_0805_10V4Z D 10U_0805_10V4Z 1U_0603_10V4Z 2 SI4800BDY-T1-E3_SO8 SUSP E +3VALW TO +3VS +5VALW D R270 0_0402_5% @ C468 0.1U_0603_25V7K +1.5V to +1.5VS +1.5V +0.75VS 1 R272 470_0603_5% +VCCP +1.5V 2 +1.5VS U57 D S 1 D S D S C470 C471 C472 D G 10U_0805_10V4Z 10U_0805_10V4Z 1U_0603_10V4Z 2 SI4800BDY-T1-E3_SO8 D D SYSON# G Q33 2N7002_SOT23 S D SUSP G Q34 2N7002_SOT23 S SUSP G Q35 2N7002_SOT23 1.5VS_GATE 1 @ C473 C474 0.1U_0603_25V7K 2 0.1U_0603_25V7K Q36 S R276 470_0603_5% 2 D R277 150K_0402_5% R275 470_0603_5% 3 S SUSP G Q31 2N7002_SOT23 R274 470_0603_5% D B+ R278 0_0402_5% SUSP G 2N7002_SOT23S @ 3 RTCVREF +5VALW 2 Q38 DTC124EKAT146_SC59-3 OUT @ SYSON# SYSON# (30,36,47) SYSON SYSON IN GND C1166 OUT IN GND C1167 @ 2 R281 100K_0402_5% (30,34,36,47,48) SUSP# 0.01U_0402_16V7K Q37 DTC124EKAT146_SC59-3 1 2 SUSP SUSP 0.01U_0402_16V7K @ R280 100K_0402_5% R279 10K_0402_5% (47,48) 1 +5VALW 2006/08/18 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title DC Interface Size Document Number Custom Date: Rev 0.4 KIWA5/6 LA-5081P Wednesday, March 18, 2009 Sheet E 42 of 53 A B C PJ101 1 @ JUMP_43X118 PF101 PC104 1000P_0402_50V7K VINDE-2 17.706 16.027 17.470 15.808 PR102 1M_0402_1% VIN VS PR104 10K_0805_5% PU102A LM393DG_SO8 PR109 10K_0402_1% RTCVREF (28,36,45) PACIN PR108 10K_0402_1% G PACIN O ACIN 2 - P PD102 RLZ4.3B_LL34 + PR105 10K_0402_1% 2 PC107 0.1U_0402_16V7K VINDE-3 PR107 22K_0402_1% PC106 1000P_0603_50V7K PR106 90.9K_0402_1% VINDE-1 2 PR103 84.5K_0402_1% PC105 0.01U_0402_25V7K VIN 2 JDCIN @ 4602-Q04C-09R 4P P2.5 PC103 100P_0402_50V8J 1 7A_24VDC_429007.W RML 1 High 17.944 Low 16.242 PL101 SMB3025500YA_2P 2 APDIN1 PC113 @ 0.018U_0603_50V7J PC101 1000P_0402_50V7K APDIN PC112 @ 0.018U_0603_50V7J Vin Detector VIN PC102 100P_0402_50V8J DC030006J00 D 3.3V VIN PD103 LL4148_LL34-2 1 PC109 0.1U_0603_25V7K RTC Battery RTCVREF +RTCBATT PR114 200_0603_5% +CHGRTC PR115 PR116 560_0603_5% 560_0603_5% 2RTCVREF-1 PD104 @ MAXEL_ML1220T10 3.3V OUT RB751V-40TE17_SOD323-2 PU101 G920AT24U_SOT89-3 IN 2CHGRTCIN GND PC110 10U_0805_6.3V6M 2 + VS 51ON-3 JRTC 1 PC111 1U_0805_25V4Z - PR113 22K_0402_1% 2 51ON-2 PR112 100K_0402_1% (41) 51_ON# PR111 68_1206_5% PR101 200_0603_5% PC108 0.22U_0603_25V7K CHGRTCP PR110 68_1206_5% PQ101 TP0610K-T1-E3_SOT23-3 51ON-1 1 PD101 LL4148_LL34-2 BATT+ 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/09/20 Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title DCIN & DETECTOR Size Document Number Custom Date: Rev 0.4 W ednesday, March 18, 2009 D Sheet 43 of 53 A B C D 1 PH1 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 56 degree C PJ201 @ JUMP_43X118 VMB PL201 SMB3025500YA_2P PF201 VL PR203 47K_0402_1% TM-2 EC_SMB_CK1 (36) O - 1 TM-3 D S PU102B LM393DG_SO8 PQ201 2N7002KW _SOT323-3 G VL PR208 100K_0402_1% PR210 100K_0402_1% 2 PC204 1000P_0402_50V7K A/D BATT_TEMPA (36) PR207 15.4K_0402_1% +3VALW P PC203 0.22U_0603_25V7K 1 PR211 10K_0402_1% + EC_SMB_DA1 (36) PR209 6.49K_0402_1% TM_REF1 PR205 13.7K_0402_1% TM-1 MAINPW ON (46) PH201 100K_0603_1%_TH11-4H104FT PR206 100_0402_5% P PC202 0.01U_0402_25V7K PC201 1000P_0402_50V7K PR202 47K_0402_1% G 2 1 2 PR204 100_0402_5% @ TYCO_1775789-1 VL BATT+ 12A_65V_451012MRL EC_SMCA EC_SMDA TS 1 2 GND GND 2 VMB2 JBATT BATT_SEL_HW (45) 3 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/6/22 Deciphered Date 2008/6/22 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title BATTERY CONN / OTP Size Date: Document Number Rev 0.4 W ednesday, March 18, 2009 D Sheet 44 of 53 A B C D 24751_PVCC PQ302 FDS6675BZ_SO8 B+ PR302 0.015_1206_1% 5B+_IN PJ301 CELLS PQ312 D 2N7002KW _SOT323-3 24751_SRN 17 TP 29 SRSET 16 IADAPT 15 1 3 2 (36) PC325 @0.01U_0402_25V7K ADP_I Current S 2.842V 3.3A Pre Cell 3.3V 4.35V 0V 4V 24751_VREF PC328 1000P_0402_50V7K CHGVADJ PR325 100K_0402_1% "CHGVADJ" connect to EC DA pin S PQ309 2N7002KW _SOT323-3 P + - G D G (36) FSTCHG LI-3S :13.5V BATT-OVP=1.5V BATT-OVP=0.1112*BATT+ PC330 0.01U_0402_25V7K CHGEN# PU302A LM358DR_SO8 (28,36,43) PQ311 @ 2N7002KW _SOT323-3 G OVP-2 PR331 105K_0402_1% PC314 10U_1206_25V6M ACIN D VADJ PR328 499K_0402_1% 2 IREF (36) @ 24751_ACGOOD# PC327 100P_0402_50V8J CHGVADJ PR335 100K_0402_1% PR322 180K_0402_1% PR321 10_0603_5% (36) IREF IADAPT 24751_VREF RTCVREF PR319 54.9K_0402_1% BATDRV PR324 @ 0_0402_5% (36) PC321 @0.1U_0603_25V7K 14 ICHG setting SRSET REGN PR326 210K_0402_1% PC313 10U_1206_25V6M 2 PC331 10U_1206_25V6M BATT_SEL_EC PR317 100K_0402_1% PR329 PR327 499K_0402_1% 340K_0402_1% PC329 0.01U_0402_25V7K G P - S PC320 0.1U_0603_25V7K (44) PC323 0.1U_0603_25V7K ACGOOD BQ24751ARHDR_QFN28_5X5 OVP-3 18 BAT 13 S OVP-1 + S BATT_SEL_HW S VS A/D PQ310 2N7002KW _SOT323-3 2BAT_SEL2 PR332 G @ 0_0402_5% PR333 @ 0_0402_5% D G SRN VADJ PQ307 2N7002KW _SOT323-3 PQ308 2N7002KW _SOT323-3 24751_SRP /BATDRV D G D G SRP 19 (36) PR334 @ 0_0402_5% VREF PC319 0.1U_0402_16V7K 20 CELLS ACOFF BATT+ 21 PC318 680P_0402_50V7K PR315 100K_0402_1% LEARN ACOFF AGND PR338 100K_0402_1% 1 24751_OCP-2 10 12 24751_ACGOOD# PC324 VMB2 1 24751_VREF OVPSET 0.1U_0603_25V7K 1 24751_OCP-1 24751_VREF 22 PGND 24751_LODRV 23 PR308 0.02_1206_1% 4 PL202 10U_LF919AS-100M-P3_4.5A_20% 224751_SW -1 PR312 4.7_1206_5% 1 24 LODRV /BATDRV PC312 LL4148_LL34-2 0.1U_0603_25V7K PC316 1U_0603_10V6K 2 124751_BTST PD301 2 PR318 200K_0402_1% PR320 100K_0402_1% PU302B LM358DR_SO8 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2008/05/21 Deciphered Date 2009/05/21 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC OVP-4 A 24751_PH PR303 100K_0402_1% PQ304 FDS6675BZ_SO8 24751_OCP-3 24751_VREF PR330 10K_0402_1% 25 224751_VDAC 11 VDAC PR336 0_0402_5% 1 PR337 @ 0_0402_5% +EC_AVCC VADJ ACSET 24751_VREF (36) BATT_OVP PH PC322 1U_0603_6.3V6M Fsw : 300KHz 24751_HIDRV 1 PR313 127K_0402_1% PQ306 SI2301BDS-T1-E3_SOT23-3 ACIN detect : 17.26V PC326 0.1U_0402_16V7K PR323 340K_0402_1% 26 24751_VREF PR316 100K_0402_1% HIDRV ACSET 224751_ACOP ACOP PC317 0.47U_0603_16V7K Input OVP : 22.3V ACOFF PR307 0_0402_5% 24751_BTST-1 24751_OVPSET 65W adapter Vacset=3.3*(115K/(165K+115K))=1.355V CP Point=(Vacset/Vvdac)*(0.1/PR302)=2.74A 27 REGN 2 CP Point Setting CP point=Iadapter*85% 90W adapter Vacset=3.3*(127K/(84.5K+127K))=1.885V CP Point=(Vacset/Vvdac)*(0.1/PR302)=4A BTST PQ303 SI7326DN-T1-E3_PAK1212-8 ACDRV ACDET 28 PQ305 SI7326DN-T1-E3_PAK1212-8 24751_ACDRV# ACDET 0.1U_0603_25V7K PVCC REGN 2 1 CHGEN ACN ACP ACSET CP setting PR314 54.9K_0402_1% PU301 PC302 0.01U_0402_25V7K 24751_SNB PC315 @ 0.01U_0402_25V7K PC310 24751_ACN 24751_ACP PR311 84.5K_0402_1% 24751_VREF PR310 54.9K_0402_1% PR309 340K_0402_1% CHG_B+ 1 2 PC308 0.1U_0603_25V7K PR306 340K_0402_1% PC309 @ 0.1U_0603_25V7K PR304 100K_0402_1% 2 PC307 0.1U_0402_16V7K 2 PC311 2.2U_0805_25V6K PC306 0.01U_0402_25V7K BK-2 1 BK-1 PR305 3.3_1210_5% PC301 0.01U_0402_25V7K @ JUMP_43X118 PC305 4.7U_1206_25V6K 2 CHGEN# PR301 3.3_1210_5% PC304 4.7U_1206_25V6K PC303 4.7U_1206_25V6K VIN PQ301 FDS6675BZ_SO8 B C Title CHARGER Size Date: Document Number Rev 0.4 W ednesday, March 18, 2009 D Sheet 45 of 53 ISL6237_B+ BST5A2 PR405 0_0603_5% SW 25 PHASE2 PHASE1 16 SW LG3 23 LGATE2 LGATE1 18 LG5 PGND 22 30 OUT2 OUT1 10 FB1 11 BYP SKIP 29 NC POK2 28 EN_LDO POK1 13 EN1 ILIM1 12 ILM1 ILIM2 31 ILIM2 FB3 32 VL REF LDOREFIN 14 3/5V_EN2 27 EN2 GND 3/5V_EN1 PC412 0.1U_0603_25V7K PC406 2200P_0402_50V7K PC404 4.7U_1206_25V6K PC405 4.7U_1206_25V6K 1 PC415 680P_0402_50V7K 21 + PC413 220U_6.3V_M 5V_SKIP PR410 @ 0_0402_5% PR411 0_0402_5% VL POK PU401 ISL6237IRZ-T_QFN32_5X5 C (28) PR414 301K_0402_1% PR415 301K_0402_1% B 13/5V_TON PR416 0_0402_5% FB5 PR420 0_0402_5% PJ402 +3VALWP PC418 1U_0603_6.3V6M 13/5V_NC 2 1 +3VALW @ JUMP_43X118 2VREF_ISL6237 2 PC420 @ 0.047U_0402_16V7K 1 0_0402_5% (44) 2VREF_ISL6237 PR419 @ 47K_0402_5% PC419 0.047U_0402_16V7K 806K_0603_1% MAINPW ON PR418 VL PR417 PD403 RB751V-40TE17_SOD323-2 TON PC417 0.22U_0603_25V7K EN_LDO NC 20 PR412 100K_0402_1% PR413 200K_0402_5% 1 EN_LDO-1 PR404 4.7_1206_5% REFIN2 PC416 0.22U_0603_25V7K PD401 RB751V-40TE17_SOD323-2 1BST5A-1 PC411 0.1U_0603_25V7K @ PD402 RLZ5.1B_LL34 HG5 17 2VREF_ISL6237 VS 4.7U_0603_6.3V6M PC409 15 BOOT1 PQ402 SI7326DN-T1-E3_PAK1212-8 1U_0603_10V6K UGATE1 +5VALWP PL402 4.7UH_PCMC063T-4R7MN_5.5A_20% PR407 @ 61.9K_0402_1% BOOT2 UGATE2 24 19 26 LDO PC408 3/5V_VCC VIN VCC 3/5V_VIN UG3 BST3A PC410 1U_0603_10V6K PVCC D PR409 0_0402_5% 2 PR408 10K_0402_1% C PR403 0_0603_5% TP PQ404 SI7716DN-T1-E3_PAK1212-8 15V_SNB PC414 680P_0402_50V7K 220U_6.3V_M BST3A-1 33 VL 1 + 13V_SNB PR402 4.7_1206_5% PR406 0_0402_5% +3VALWP PQ403 SI7716DN-T1-E3_PAK1212-8 PL401 4.7UH_PCMC063T-4R7MN_5.5A_20% PC407 0.1U_0603_25V7K PQ401 SI7326DN-T1-E3_PAK1212-8 5 PC403 2200P_0402_50V7K D PC402 4.7U_1206_25V6K PR401 0_0402_5% PC401 4.7U_1206_25V6K PJ401 @ JUMP_43X118 2 1 B ISL6237_B+ B+ PC421 PJ403 +5VALWP 2 1 +5VALW @ JUMP_43X118 A A 2007/06/22 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2008/06/22 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title 3VALW/5VALW Size Document Number Custom Date: Rev 0.4 Wednesday, March 18, 2009 Sheet 46 of 53 PJ501 1.5V_IN PGOOD 15 10 LG_1.5V DRVL +5VALW PGND GND PC509 @ 47P_0402_50V8J 2 PC508 1U_0603_10V6K V5DRV 1.5V_TRIP PR505 17.8K_0402_1% PU501 TPS51117RGYR_QFN14_3.5x3.5 PC511 4.7U_0805_10V6K + PJ504 +VCCPP 1 +VCCP @ PR507 21K_0402_1% 1 VFB SW _1.5V 11 +1.5VP 12 PL501 1.5UH_PCMC063T-1R5MN_9A_20% PC507 1000P_0402_50V7K 1.5V_FB LL TRIP D V5FILT UG_1.5V B+ VOUT 13 3 1.5V_V5FILT DRVH TON TP PR504 422_0603_1% 2 EN_PSV PC504 0.1U_0402_16V7K 14 0.1U_0603_25V7K +5VALW 1 PC506 10U_0805_6.3V6M PR503 PC503 0_0603_5% BST_1.5V 2BST_1.5V-1 1.5V_EN @ JUMP_43X79 PL503 @ HCB4532KF-800T90_1812 PC505 220U_D2_4VY_R15M PR502 0_0402_5% (30,36,42) SYSON VBST D PD501 @ 1SS355_SOD323-2 +5VALW PQ501 SI7326DN-T1-E3_PAK1212-8 PC532 @ 1000P_0402_50V7K PC531 11.5V_SNB @ 4.7U_1206_25V6K PC510 PR506 PC502 680P_0402_50V7K 4.7_1206_5% 4.7U_1206_25V6K PC501 4.7U_1206_25V6K 1.5V_TON PQ502 SI7716DN-T1-E3_PAK1212-8 PR501 240K_0402_5% JUMP_43X118 1.5V_PGOOD (8) LG_VCCP DRVL +5VS PU502 TPS51117RGYR_QFN14_3.5x3.5 PC521 4.7U_0805_10V6K 1 +0.75VS +VCCPP + B PR515 13.3K_0402_1% 2 @ JUMP_43X79 VCCP_TRIP PR514 12K_0402_1% C PJ506 +0.75VSP V5DRV 10 @ JUMP_43X79 PL504 @ HCB4532KF-800T90_1812 TRIP PGND PGOOD GND PC520 @ 47P_0402_50V8J SW _VCCP 11 PR512 4.7_1206_5% 12 1VCCP_SNB2 VFB PC519 1U_0603_10V6K B 14 15 V5FILT LL UG_VCCP PQ504 SI4634DY-T1-E3_SO8 VCCP_FB 13 +1.5V B+ PL502 1.5UH_PCMC063T-1R5MN_9A_20% VOUT DRVH VCCP_V5FILT VBST TON TP PR513 422_0603_1% 2 EN_PSV 0.1U_0603_25V7K PC515 0.1U_0402_16V7K +5VS PC522 680P_0402_50V7K PR511 PC514 0_0603_5% BST_VCCP1 2BST_VCCP-1 VCCP_EN PR510 0_0402_5% 2 1 JUMP_43X118 PC518 1000P_0402_50V7K PD502 @ 1SS355_SOD323-2 +5VS SUSP# PQ503 SI4686DY-T1-E3_SO8 PC534 @ 1000P_0402_50V7K PC533 @ 4.7U_1206_25V6K PC512 4.7U_1206_25V6K PC513 4.7U_1206_25V6K PR509 240K_0402_5% VCCP_TON 2 @ PJ502 VCCP_IN 42,48) +1.5VP PC517 10U_0805_6.3V6M PJ505 PC528 @0.1U_0402_16V7K 2 C PR521 100K_0402_1% PC516 220U_D2_4VY_R15M +1.5VP PR508 21K_0402_1% PR516 30.1K_0402_1% @ PJ503 JUMP_43X79 1 +1.5V 1 VCNTL GND NC VREF NC VOUT NC TP +3VALW PC524 1U_0603_6.3V6M A A VIN 2 PR517 1K_0402_1% PC523 4.7U_0603_6.3V6M 1 PU503 0.75V_IN 0.75V_REF APL5331KAC-TRL_SO8 PC525 0.1U_0402_16V7K S +0.75VSP PR520 1K_0402_1% 2 @ PC527 0.1U_0402_16V7K (42,48) SUSP D G PQ505 2N7002KW_SOT323-3 PR518 0_0402_5% PC526 10U_0805_6.3V6M 2007/11/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2008/11/12 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title 1.5V / 0.9V / VCCP Size Date: Document Number Rev 0.4 W ednesday, March 18, 2009 Sheet 47 of 53 PJ601 1.8V_IN PU601 TPS51117RGYR_QFN14_3.5x3.5 PC610 4.7U_0805_10V6K PJ602 +VGA_COREP PJ603 PC601 4.7U_1206_25V6K 2 1 1.0V 1.2V +1.8VS C PC633 10U_0805_6.3V6M 2 PC616 10U_0805_6.3V6M PC615 330U_D2_2.5VY_R15M PR615 10_0402_5% PC634 10U_0805_6.3V6M PC612 10U_1206_25V6M PR612 4.7_1206_5% + B PR617 0_0402_5% +VGASENSE (16,17) 1 TP 2007/11/12 S VREF NC VOUT NC TP +5VS PC624 @1U_0603_6.3V6M +1.8VSP A PC629 @10U_0805_6.3V6M Compal Electronics, Inc 2008/11/12 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC @ APL5331KAC-TRL_SO8 PC627 @ 0.1U_0402_16V7K Compal Secret Data Security Classification Issued Date PC631 @ 0.1U_0402_16V7K D G PC628 10U_0805_6.3V6M PR632 @ 31.6K_0402_1% SUSP PR628 @ 1.24K_0402_1% (42,47) 1 PR616=>9.09K PR622=>2.21K PR629,PR630,PC625,PQ606,PR620=>un-pop PR621,PR624,PC632,PQ607,PR618=>un-pop PR623 @ 1K_0402_1% LDO_1.8V_REF +1.1VSP PC626 0.1U_0402_16V7K For N10M-GS S PR627 3.16K_0402_1% NC PC622 1U_0603_6.3V6M VCNTL GND NC VIN NC VOUT VREF PC623 @ 4.7U_0603_6.3V6M NC 1 GND PU604 LDO_1.8V_IN +5VS VCNTL VIN D G @ @ APL5331KAC-TRL_SO8 PR625 30.1K_0402_1% 21.1V_EN PJ608 JUMP_43X79 PQ609 @ 2N7002KW_SOT323-3 0.95V 1 1 PR622 1.91K_0402_1% PQ608 2N7002KW_SOT323-3 VGA_CORE 1 +VGA_COREP 2 SUSP @ JUMP_43X79 @ JUMP_43X79 PU603 1.1V_IN S PQ607 2N7002KW _SOT323-3 PC630 0.1U_0402_16V7K GPU_VID0 +1.8VSP B+ PJ607 JUMP_43X79 D PC621 4.7U_0603_6.3V6M (42,47) +1.1VS 1 +3VS PC632 0.022U_0402_16V7K GPU_VID1 PC618 680P_0402_50V7K PC620 4.7U_0805_10V6K +1.8VSP PR618 113K_0402_1% G For N10M-GE1 GPIO15 GPIO20 PC611 10U_1206_25V6M PU602 TPS51117RGYR_QFN14_3.5x3.5 1VGA_SNB 1.1V_REF A LG_VGA DRVL PGND PGOOD PQ605 SI4634DY-T1-E3_SO8 10 +5VS V5DRV VGA_TRIP PR614 9.1K_0402_1% PL602 1UH_PCMB103E-1R0MS_20A_20% SW _VGA 11 PQ604 SI4634DY-T1-E3_SO8 12 2 LL PQ603 SI4686DY-T1-E3_SO8 15 14 UG_VGA VFB VBST 13 TRIP PC625 0.022U_0402_16V7K 1GVID0-1 PR624 10K_0402_1% V5FILT PR634 @ 0_0402_5% S PR621 10K_0402_1% 2 1GVID1-2 2 (16) GPU_VID0 1 1GVID1-1 PR630 G 10K_0402_1% PR629 10K_0402_1% VOUT PC619 @ 47P_0402_50V8J PR620 91K_0402_1% VGA_FB1 2 PR616 13.3K_0402_1% D PR619 39.2K_0402_1% 1GVID0-2 1 PQ606 2N7002KW_SOT323-3 PC529 @ 0.1U_0402_16V7K (16) GPU_VID1 DRVH VGA_PW ROK B TON PR522 100K_0402_1% PC617 1U_0603_10V6K VGA_FB 2 +3VS 1 VGA_V5FILT TP PQ610 2N7002KW _SOT323-3 S PR633 0_0402_5% +VGA_COREP 1VGA_VOUT PR613 422_0603_1% +5VS 0.1U_0603_25V7K G PC636 @ 0.1U_0402_16V7K 2 2 PR611 PC614 0_0603_5% BST_VGA 2BST_VGA-1 D EN_PSV SUSP 1 PJ604 +1.1VSP PJ605 VGA_EN GND PR626 0_0402_5% @ JUMP_43X118 VGA_IN PD601 1SS355_SOD323-2 +5VS 2,47) PR610 @ 0_0402_5% PC613 @ 0.1U_0402_16V7K SUSP# +VGA_CORE PJ606 PR609 205K_0402_1% VGA_TON 42,47) 1 @ JUMP_43X79 PR608 21K_0402_1% PC637 @ 0.1U_0402_16V7K C @ JUMP_43X118 PR607 30.1K_0402_1% + PC635 1000P_0402_50V7K LG_1.8V PC609 @ 47P_0402_50V8J DRVL 1 10 +5VS V5DRV 1.8V_TRIP PR606 16.5K_0402_1% PGND PGOOD GND PC607 1U_0603_10V6K 15 14 SW _1.8V 11 PC606 10U_0805_6.3V6M VFB 12 +1.8VSP PC605 220U_D2_4VY_R15M LL TRIP B+ D PR604 4.7_1206_5% 1.8V_FB UG_1.8V 1 PL601 2.2UH_PCMC063T-2R2MN_8A_20% V5FILT 13 VOUT DRVH 1.8V_V5FILT VBST TON TP EN_PSV PC604 0.1U_0402_16V7K 0.1U_0603_25V7K PR605 422_0603_1% +5VS @ JUMP_43X79 PC608 680P_0402_50V7K PR603 PC603 0_0603_5% BST_1.8V 2BST_1.8V-1 1.8V_EN PQ602 SI7716DN-T1-E3_PAK1212-8 1.8V_SNB PR631 40.2K_0402_1% SUSP# D 4,36,42,47) PQ601 SI7326DN-T1-E3_PAK1212-8 PD602 @ 1SS355_SOD323-2 +5VALW 1.8V_TON 2 PC602 4.7U_1206_25V6K PR601 240K_0402_5% 2 Title VGA_CORE/1.8V/1.1VS Size Date: Document Number Rev 0.4 W ednesday, March 18, 2009 Sheet 48 of 53 2 PR830 1.91K_0402_1% VGATE D PR801 17.8K_0402_1% 1 PR840 69.8K_0402_1% 2CPU_SN-1 PR842 28.7K_0402_1% PC829 0.033U_0402_16V7K PH801 100K_0603_1%_TH11-4H104FT CPU_CSN1 CPU_CSP1 PR848 17.8K_0402_1% 1CPU2_SNB PQ806 SI4634DY-T1-E3_SO8 +CPU_CORE CPU_CSP2 PC823 680P_0402_50V7K PR850 69.8K_0402_1% 2CPU_SN-2 PR851 28.7K_0402_1% PC835 0.033U_0402_16V7K B PH803 100K_0603_1%_TH11-4H104FT (6) (6) (6) CPU_VID0 (6) CPU_VID1 (6) CPU_VID2 (6) CPU_VID3 (6,27) CPU_VID4 CPU_VID5 C CPU_CSP2-1 PR829 4.7_1206_5% 3 + PL803 0.36UH_PCMC104T-R36MN1R17_30A_20% PQ805 SI4634DY-T1-E3_SO8 VID0 VID1 +5VS PD802 1SS355_SOD323-2 CPU_CSN2 21 PQ804 SI7686DP-T1-E3_SO8 PC839 1000P_0402_50V7K DRVH2 PC818 10U_1206_25V6M VBST2 BOOT_CPU2 PR846 2BOOT_CPU2-1 0_0603_5% PC834 UGATE_CPU2 0.22U_0603_10V7K PC817 10U_1206_25V6M PHASE_CPU2 22 B+ PC805 220U_25V_M PC838 1000P_0402_50V7K PC809 2200P_0402_50V7K PC804 10U_1206_25V6M 1 1CPU1_SNB PQ803 SI4634DY-T1-E3_SO8 1 LL2 LGATE_CPU2 23 20 19 VID2 18 VID4 VID3 17 16 VID5 15 PSI# DPRSTP# VID6 14 13 H_PSI# CPU_VID6 11 VR_TT# 0.033U_0402_16V7K 24 VSNS @ PC840 PGND GNDSNS H_DPRSTP# +5VS 10U_0805_6.3V6M DRVL2 (6) CSP2 PC815 680P_0402_50V7K +CPU_B+ 25 (6) CSN2 PC831 CPU_CSP1-1 PR819 4.7_1206_5% 26 PU801 TPS51620RHAR_QFN40_6X6 1 27 V5IN PQ802 SI4634DY-T1-E3_SO8 PGOOD DPRSLPVR CLK_EN# VR_ON PWRMON LGATE_CPU1 DRVL1 PC808 10U_1206_25V6M 2 0_0402_5% PR838 31 32 33 34 35 37 38 36 TRIPSEL TONSEL OSRSEL ISLEW GND V5FILT BOOT_CPU1 PR841 2BOOT_CPU1-1 PC827 0_0603_5% PHASE_CPU1 0.22U_0603_10V7K CSN1 PR849 20K_0402_5% (6) LL1 28 CSP1 VCCSENSE +CPU_CORE 29 PR847 100_0402_5% (6) VSSSENSE PR843 100_0402_5% VBST B UGATE_CPU1 GND CPU_THERM 10 THERM PR845 0_0402_5% 1 PR844 0_0402_5% CPU_VSNS 30 VREF 12 CPU_CSP1-2 33P_0402_50V8K CPU_CSN1-1 33P_0402_50V8K CPU_CSN2-1 33P_0402_50V8K CPU_CSP2-2 33P_0402_50V8K CPU_GNDSNS PD801 1SS355_SOD323-2 DRVH1 1CPU_DPRSTP# 0_0402_5% PSI# 0_0402_5% VID6 0_0402_5% VID5 0_0402_5% VID4 0_0402_5% VID3 0_0402_5% VID2 0_0402_5% VID1 0_0402_5% VID0 0_0402_5% CPU_CSP2 PR864 PC837 100P_0402_50V8J 470_0402_1% PC828 PC830 PC832 PC833 CPU_CSN1 PR862 CPU_CSN2 PR863 PC836 100P_0402_50V8J 470_0402_1% 470_0402_1% DROOP PL802 0.36UH_PCMC104T-R36MN1R17_30A_20% PR852 PR853 PR854 PR855 PR856 PR857 PR858 PR859 PR860 470_0402_1% CPU_CSP1 PR861 CPU_VREF PR839 5.76K_0402_1% CPU_DROOP PC825 68P_0402_50V8J 2CPU_VREF PC826 0.22U_0603_10V7K 39 41 C 40 +5VS PL801 HCB4532KF-800T90_1812 PQ801 SI7686DP-T1-E3_SO8 CPU_VR_ON CPU_DPRSLPVR PR837 1CPU_VREF 0_0402_5% 0_0402_5% 0_0402_5% +CPU_B+ CPU_TONSEL PR835 CPU_TRIPSEL PR836 124K_0402_1% PR833 CPU_OSRSEL CPU_V5FILT CPU_ISLEW PC824 1U_0603_10V6K (8,28) +5VS (36) +3VS DPRSLPVR PR834 @ 0_0402_5% PR865 0_0402_5% D VR_ON PR832 @ 0_0402_5% (28) CLK_ENABLE# CPU_CLK_EN# (8,28) PR831 @ 10K_0402_5% +3VS A A 2008/05/21 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2009/05/21 Deciphered Date +CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom Date: Rev 0.4 Wednesday, March 18, 2009 Sheet 49 of 53 Version change list (P.I.R List) Item D Fixed Issue Page of for PWR Reason for change Rev PG# Modify List Date Phase 2009.01.14 modify battery select circuit add PQ312 and PR338 change +1.1VS voltage to +1.05V change P622 to 2.21K only for N10M-GS(40nm) D C C 10 11 B 12 B 13 14 15 16 17 18 19 A A 20 21 2007/09/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2008/09/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PIR (PWR) Size Document Number Custom Rev 0.4 KIWAX_LA-5082P Date: W ednesday, March 18, 2009 Sheet 50 of 53 NO DATE PAGE MODIFICATION LIST PURPOSE 12/10 39 Remove D11, and add R22, R25 12/10 36 change PWR_LED_SC# from U46.38 to U46.34 D D C C B B A A Title Compal Electronics, Inc HW PIR Size B Date: Document Number Rev 0.4 KIWAX_LA-5082P Wednesday, March 18, 2009 Sheet 51 of 53 NO DATE PAGE MODIFICATION LIST PURPOSE 1/15 D 1/16 、H6 and H19 hold type 39 modify H19 hold size, and change the H5 42 add CAPs C52, C53, C54 and C55 for EMI 35 change C572 and C574 footprint from 0603 to 0402 34 add R44 for BEEP# test 30 Remove Remove Remove Remove Remove Remove 28 D one Mini-PCIE function! (Connector Side) component is JP18, R363, R364, R367, R369, R371, R373, R375, R377, R378, R379, R380 and R383 3G function! component is JP14, D12, R6, C6, C7, R7 and D13 one Mini-PCIE function!(SB side) component is C884 and C885 C C B B A A Title Compal Electronics, Inc HW PIR Size B Date: Document Number Rev 0.4 KIWAX_LA-5082P Wednesday, March 18, 2009 Sheet 52 of 53 NO DATE PAGE MODIFICATION LIST PURPOSE 3/16 06 add R1089, C1162 and H_DPRSTP#_R add C1163, C1164,and C1165 for EMC request D 08 change H_DPRSTP# to H_DPRSTP#_R 19 P19 add Bom structure 40nm@ GPU and 55nm@ GPU D R999 change to 24.9K 23 add R1095 pull high 35 swap HP_OUTL and HP_OUTR 36 add R1090, R1091, R1092, R1093 CAPS_LED#, NUJM_LED#, ESB_CK_R, and ESB_DA_R 41 add R256, R258 Bom configuration Remove CY SMBus C 3/16 42 add C1166, C1167 for EMC request 28 change PCIE Port1 to Port3 30 change PCIE Port1 to Port3 C B B A A Title Compal Electronics, Inc HW PIR Size B Date: Document Number Rev 0.4 KIWAX_LA-5082P Wednesday, March 18, 2009 Sheet 53 of 53 ... LPC_AD2 LPC_AD3 LAN_RSTSYNC D13 D12 E13 AF6 AH4 HDA_SYNC_R FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 K5 K4 L6 K2 GLAN_CLK LAN_RXD0 LAN_RXD1 LAN_RXD2 B28 B27 HDA_BITCLK_R INTVRMEN LAN100_SLP F14... 0.1U_0402_16V4Z C712 +LAN_BIASVDD C713 C706 0.1U_0402_16V4Z 2 LAN_TX0LAN_TX0+ LAN_RX1LAN_RX1+ LAN_TX0- (32) LAN_TX0+ (32) LAN_RX1- (32) LAN_RX1+ (32) T109 T110 T107 T108 +3V_LAN LOW PWR R405 1 R406... 58 WLAN_CLKREQ# 65 WLAN_CLKREQ1# 43 CLKREQ_LAN# CLK_PCIE_LAN (31) CLK_PCIE_LAN# CLK_PCIE_ICH SATA_CLKREQ#_R EXP_CLKREQ# WLAN_CLKREQ1# MCH_CLKREQ#_R CLKREQ_LAN# WLAN_CLKREQ# WLAN_CLKREQ2# (31) (28)