Acer 7750 7750g compal LA 6911p r0 3

A B C D E Compal Confidential m o c e u l b p o t p a l w W w Compal Confidential Model Name : P7YE0/P7YH0/P7YS0 File Name : LA-6911P BOM P/N:43 2 P7YE0/P7YH0/P7YS0 M/B Schematics Document Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH ATI Seymour/Whistler/Granville 2010-11-01 3 REV:0.3 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 2012/07/12 Deciphered Date Title SCHEMATIC,MB A6911 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev B 4019A9 Tuesday, November 09, 2010 Sheet E of 60 A B C m o c e u l b p o t p a l w W w D E Fan Control page 40 PEG(DIS) 100MHz PCI-E 2.0x16 5GT/s PER LANE ATI Seymour/ Whistler/ Granville 133MHz 204pin DDRIII-SO-DIMM X2 Channel A Intel Sandy Bridge BANK 0, 1, 2, Memory BUS(DDRIII) Two Dimm Per Channel 1.5V DDRIII 1066/1333/ Processor 204pin DDRIII-SO-DIMM X2 page22`29 HDMI(DIS) CRT(DIS) HDMI Conn LVDS(DIS) EDP(DIS) CRT Conn page 32 page 30 USB port page 12 page 4~10 DMI x4 100MHz 100MHz 2.7GT/s 1GB/s x4 LVDS(UMA) CRT(UMA) TMDS(UMA) HDMI(UMA) BANK 0, 1, 2, Channel B rPGA988B FDI x8 LVDS Conn USBx1(3D) page 31 page 11 Intel Cougar Point-M USB 2.0 conn x2 USB port 0,1 on USB/B Bluetooth Conn CMOS Camera Card Reader RTS5138 USB port 13 USB port 10 USB port 11 page 36 page 36 USBx14 3.3V 48MHz HD Audio 3.3V 24MHz page 36 page 30 PCH port port USB 2.0 conn x1 MINI Card x2 WLAN, WWAN USB port 8,9 page 35 page 42 port HDA Codec 100MHz PCI-Express x (ARD PCIE2.0 2.5GT/s) SATA x (GEN1 1.5GT/S ,GEN2 3GT/S) page 13~21 AR8151/8152 SPI ROM x1 page 34 RJ45 page 34 SATA HDD Conn x2 page 33 USB/B 2Port USB Port0,1 page 13 Int Speaker page 13 port SATA CDROM Conn page 33 Combo Jack x MIC Jack x1 page 39 page 39 LPC BUS 33MHz ENE KB930 Sub-board LS-6911P page 37 CPU XDP page 35 Int.KBD Touch Pad page 38 LS-6912P Power On/Off CKT page 39 SPI LAN(GbE) port 0,1 RTC CKT ALC271X/277X 989pin BGA 100MHz page page 38 LAN/B page 38 page 37 BIOS ROM DC/DC Interface CKT page 41 LS-6914P LS-6913P PWR/B page 38 LID/B page 34 Power Circuit DC/DC page 43~ Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 2012/07/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D SCHEMATIC,MB A6911 Rev B 4019A9 Tuesday, November 09, 2010 Sheet E of 60 A B C D Voltage Rails m o c e u l b p o t p a l w W w Power Plane Description S1 S3 S5 VIN Adapter power supply (19V) N/A N/A N/A BATT+ Battery power supply (12.6V) N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF +VGA_CORE Core voltage for GPU ON OFF OFF +VGFX_CORE Core voltage for UMA graphic ON OFF OFF +0.75VS +0.75VP to +0.75VS switched power rail for DDR terminator ON OFF OFF +1.0VSDGPU +1.0VSDGPU switched power rail for GPU ON OFF OFF Full ON ON ON ON LOW ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF +1.5V +1.5VP to +1.5V power rail for DDRIII ON ON OFF +1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF Vcc Ra/Rc/Re +1.5VSDGPU +1.5V to +1.5VSDGPU switched power rail for GPU ON OFF OFF Board ID +1.8VS (+5VALW or +3VALW) to 1.8V switched power rail to PCH & GPU ON OFF OFF ON* ON* ON OFF OFF +5VALW +5VALWP to +5VALW power rail ON ON ON* +5VALW_PCH +5VALW to +5VALW_PCH power rail for PCH (Short resister) ON ON ON* +5VS +5VALW to +5VS switched power rail ON OFF OFF +VSB +VSBP to +VSB always on power rail for sequence control ON ON ON* +RTCVCC RTC power ON ON ON ON HIGH OFF +3VALW to +3VS power rail Clock HIGH OFF +3VS ON HIGH OFF ON ON HIGH OFF ON ON LOW ON ON HIGH HIGH ON ON +VS HIGH LOW +1.05VS_VTTP to +1.05VS_VTT switched power rail for CPU +3VALW always on power rail +V HIGH LOW +1.05VS_VTT to +1.05VS_PCH power for PCH +3VALW to +3VALW_PCH power rail for PCH (Short Jumper) +VALW HIGH S1(Power On Suspend) +1.05VS_PCH +3VALW_PCH SLP_S1# SLP_S3# SLP_S4# SLP_S5# S3 (Suspend to RAM) +1.05VS_VTT +3VALW SIGNAL STATE E Board ID / SKU ID Table for AD channel 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V BOARD ID Table V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BTO Option Table BTO Item BOM Structure Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF Board ID PCB Revision UMA Only UMAO@ 0.1 Muxless/UMA UMA@ EC SM Bus1 address EC SM Bus2 address 0.2 P9,P19,P23,P30-32,P59 DIS Only DISO@ 0.3 P4,P14 Device Address Device Address Muxless/DIS DIS@ 1.0 P.22-28 Smart Battery 0001 011X b Muxless/DIS VGA@ BACO mode BACO@ P.26 ,P.29 PCH SM Bus address nonBACO mode NOBACO@ VRAM P/N P.27,28 Device Address VRAM X76@ SAM 64*16 900M SA00004GS10(S IC D3 64M16 K4W1G1646G-BC11 FBGA ABO!) P.27 ChannelA DIMM0 JDIMM1 1010 000X A0 SAM 64*16 800M SA000035720(S IC D3 64MX16 K4W1G1646E-HC12 FBGA ABO!) 128bit VRAM 128@ SAM 128*16 800M SA00003MQ60 (S IC D3 128M16 K4W2G1646C-HC12 FBGA ABO!) P.23,P.59 DIMM1 JDIMM3 1010 001X A2 HYN 64*16 900M SA000041S40(S IC D3 64MX16 H5TQ1G63DFR-11C FBGA ABO!) Granville GPU GRAN@ HYN 64*16 800M SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA ABO!) P.59 ChannelB JDIMM2 DIMM0 1010 010X A4 HYN 128*16 800M SA00003VS10 (S IC D3 128M16 H5TQ2G63BFR-12C FBGA ABO!) Whistler GPU WHIS@ SA0000324G0(S IC D3 64M16 H5TQ1G63DFR-12C FBGA ABO!) HYN 64*16 800M P.22-26 JDIMM4 DIMM1 1010 011X A6 Seymour GPU SEYM@ USB Port Table P.23,P.25 non Granville GPU NOGRAN@ BT Config GPU config BACO config External P.35 Blue Tooth BT@ USB 2.0 USB 1.1 Port USB Port BT@ WHIS@ BACO@ BACO: BT SKU: Whistler: Connector CONN@ SEYM@ NOBACO@ 4DIMM config Seymour: nonBACO: USB/B(Right side 2.0 option) UHCI0 Unpop @ 4DIMM@ Granville: GRAN@ DIMM: Muxless config USB/B(Right side 2.0 option) MUXL@ Muxless: Granville config LVDS/eDP config USB port(left side 2.0) P.30,59 UHCI1 DIS eDP DEDP@ GRAN@ (VDDCI) UMA LVDS: ULVDS@ Granville: nonMuxless: NOMUXL@ (DISO,UMAO) USB/B(Right side 3.0 option) P.30 EHCI1 UMA LVDS ULVDS@ DIS LVDS: DLVDS@ nonGranville: NOGRAN@ (VGA_CORE) UHCI2 VRAM BOM Config DIS LVDS DLVDS@ DEDP@ DIS eDP: GPU Frame config P.18,P.32 X76264BOL01: 64Mx16x4 Seymour 512M HYN NEW Muxless MUXL@ 128@ (WHIS,GRAN) 128bit: P.18 64Mx16x4 Seymour X76264BOL02: 512M HYN OLD UHCI3 non Muxless NOMUXL@ P.41 X76264BOL03: 64Mx16x8 Whistler/Granville 1G HYN NEW USB2.0 Conn USB2@ Mini Card(WLAN) P.41 X76264BOL04: 64Mx16x8 Whistler/Granville 1G HYN OLD UHCI4 USB3.0 Conn USB3@ Mini Card P.11-12 X76264BOL05: 128Mx16x8 Whistler/Granville 2G HYN Dimm 4DIMM@ 10 Camera X76264BOL06: 128Mx16x8 Whistler/Granville 2G SAM EHCI2 UHCI5 11 Card Reader X76264BOL07: 128Mx16x4 Seymour 1G SAM 12 X76264BOL08: 128Mx16x4 Seymour 1G HYN UHCI6 13 Blue Tooth BOM Config BT@/UMAO@/UMA@/ULVDS@/NOMUXL@ +DIMM,USB option * UMA Only LVDS Panel: BT@/DIS@/VGA@/DISO@/DLVDS@/NOMUXL@ +DIMM,USB option Security Classification +X76+GPU * DIS Only LVDS Panel: Compal Secret Data Compal Electronics, Inc Title 2010/07/12 2012/07/12 +DIMM,USB option BT@/DIS@/VGA@/DISO@/DEDP@/NOMUXL@ +X76+GPU Issued Date DIS Only EDP Panel: Deciphered Date SCHEMATIC,MB A6911 BT@/UMA@/DIS@/VGA@/ULVDS@/BACO@/MUXL@ +X76+GPU(S,W) +DIMM,USB option THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL * Muxless BACO LVDS Panel: Size Document Number Rev AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B +DIMM,USB option DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Muxless nonBACO LVDS Panel: BT@/UMA@/DIS@/VGA@/ULVDS@/NOBACO@/MUXL@ +X76+GPU(G) 4019A9 MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Tuesday, November 09, 2010 Sheet E of 60 A B C D PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms PEG_ICOMPO signals should be routed with max length = 500 mils - typical impedance = 14.5 mohms +1.05VS_VTT m o c e u l b p o t p a l w W w R532 24.9_0402_1% DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] 15 15 15 15 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 B28 B26 A24 B23 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] 15 15 15 15 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 G21 E22 F21 D21 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] 15 15 15 15 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 G22 D22 F20 C21 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] 15 15 15 15 15 15 15 15 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 A21 H19 E19 F18 B21 C20 D18 E17 FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] 15 15 15 15 15 15 15 15 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 A22 G19 E20 G18 B20 C19 D19 F17 FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] 15 FDI_FSYNC0 15 FDI_FSYNC1 J18 J17 FDI0_FSYNC FDI1_FSYNC 15 FDI_INT H20 FDI_INT 15 FDI_LSYNC0 15 FDI_LSYNC1 J19 H17 FDI0_LSYNC FDI1_LSYNC A18 A17 B16 eDP_COMPIO eDP_ICOMPO eDP_HPD C15 D15 eDP_AUX eDP_AUX# C17 F16 C16 G15 eDP_TX[0] eDP_TX[1] eDP_TX[2] eDP_TX[3] C18 E16 D16 F15 eDP_TX#[0] eDP_TX#[1] eDP_TX#[2] eDP_TX#[3] +1.05VS_VTT R118 24.9_0402_1% EDP_COMP eDP eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance CPU OK UNCOREPWRGOOD: CORE SM_DRAMPWROK:DRAM power ok RESET#: okCPU reset 1K_0402_5% C26 MISC 17 H_SNB_IVB# R116 Checklist1.0 P.58 Graphis Disable Guide DIS only SKU eDP disable DPLL_REF_SSCLK PD 1K_5% to GND DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT JCPU1B CLK_CPU_DPLL# Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 2012/07/12 Deciphered Date Title SCHEMATIC,MB A6911 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev B 4019A9 Tuesday, November 09, 2010 Sheet E of 60 A B C D JCPU1D m o c e u l b p o t p a l w W w DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 11 DDR_A_BS0 11 DDR_A_BS1 11 DDR_A_BS2 11 DDR_A_CAS# 11 DDR_A_RAS# 11 DDR_A_WE# C5 D5 D3 D2 D6 C6 C2 C3 F10 F8 G10 G9 F9 F7 G8 G7 K4 K5 K1 J1 J5 J4 J2 K2 M8 N10 N8 N7 M10 M9 N9 M7 AG6 AG5 AK6 AK5 AH5 AH6 AJ5 AJ6 AJ8 AK8 AJ9 AK9 AH8 AH9 AL9 AL8 AP11 AN11 AL12 AM12 AM11 AL11 AP12 AN12 AJ14 AH14 AL15 AK15 AL14 AK14 AJ15 AH15 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] AE10 AF10 V6 SA_BS[0] SA_BS[1] SA_BS[2] AE8 AD9 AF9 SA_CAS# SA_RAS# SA_WE# DDR SYSTEM MEMORY A 11 DDR_A_D[0 63] SA_CLK[0] SA_CLK#[0] SA_CKE[0] AB6 AA6 V9 SA_CLK_DDR0 11 12 DDR_B_D[0 63] SA_CLK_DDR#0 11 DDRA_CKE0_DIMMA 11 SA_CLK[1] SA_CLK#[1] SA_CKE[1] AA5 AB5 V10 SA_CLK_DDR1 11 SA_CLK_DDR#1 11 DDRA_CKE1_DIMMA 11 SA_CLK[2] SA_CLK#[2] SA_CKE[2] AB4 AA4 W9 SA_CLK_DDR2 11 SA_CLK_DDR#2 11 DDRA_CKE2_DIMMA 11 SA_CLK[3] SA_CLK#[3] SA_CKE[3] AB3 AA3 W10 SA_CLK_DDR3 11 SA_CLK_DDR#3 11 DDRA_CKE3_DIMMA 11 SA_CS#[0] SA_CS#[1] SA_CS#[2] SA_CS#[3] AK3 AL3 AG1 AH1 DDRA_CS0_DIMMA# DDRA_CS1_DIMMA# DDRA_CS2_DIMMA# DDRA_CS3_DIMMA# SA_ODT[0] SA_ODT[1] SA_ODT[2] SA_ODT[3] AH3 AG3 AG2 AH2 SA_ODT0 SA_ODT1 SA_ODT2 SA_ODT3 SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] C4 G6 J3 M6 AL6 AM8 AR12 AM15 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] D4 F6 K3 N6 AL5 AM9 AR11 AM14 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] AD10 W1 W2 W7 V3 V2 W3 W6 V1 W5 AD8 V4 W4 AF8 V5 V7 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 11 11 11 11 11 11 11 11 DDR_A_DQS#[0 7] DDR_A_DQS[0 7] DDR_A_MA[0 15] 11 11 11 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 12 DDR_B_BS0 12 DDR_B_BS1 12 DDR_B_BS2 12 DDR_B_CAS# 12 DDR_B_RAS# 12 DDR_B_WE# Sandy Bridge_rPGA_Rev0p61 CONN@ SM_DRAMRST# DIMM_DRAMRST#_R Q6 BSS138_NL_SOT23-3 G R79 4.99K_0402_1% 11,12,14 RST_GATE SB_BS[0] SB_BS[1] SB_BS[2] AA10 AB8 AB9 SB_CAS# SB_RAS# SB_WE# AE2 AD2 R9 SB_CLK_DDR0 12 SB_CLK_DDR#0 12 DDRB_CKE0_DIMMB 12 SB_CLK[1] SB_CLK#[1] SB_CKE[1] AE1 AD1 R10 SB_CLK_DDR1 12 SB_CLK_DDR#1 12 DDRB_CKE1_DIMMB 12 SB_CLK[2] SB_CLK#[2] SB_CKE[2] AB2 AA2 T9 SB_CLK_DDR2 12 SB_CLK_DDR#2 12 DDRB_CKE2_DIMMB 12 SB_CLK[3] SB_CLK#[3] SB_CKE[3] AA1 AB1 T10 SB_CLK_DDR3 12 SB_CLK_DDR#3 12 DDRB_CKE3_DIMMB 12 SB_CS#[0] SB_CS#[1] SB_CS#[2] SB_CS#[3] AD3 AE3 AD6 AE6 DDRB_CS0_DIMMB# DDRB_CS1_DIMMB# DDRB_CS2_DIMMB# DDRB_CS3_DIMMB# SB_ODT[0] SB_ODT[1] SB_ODT[2] SB_ODT[3] AE4 AD4 AD5 AE5 SB_ODT0 SB_ODT1 SB_ODT2 SB_ODT3 SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] D7 F3 K6 N3 AN5 AP9 AK12 AP15 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] C7 G3 J6 M3 AN6 AP8 AK11 AP14 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] AA8 T7 R7 T6 T2 T4 T3 R2 T5 R3 AB7 R1 T1 AB10 R5 R4 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 12 12 12 12 12 12 12 12 DDR_B_DQS#[0 7] DDR_B_DQS[0 7] DDR_B_MA[0 15] 12 12 12 Sandy Bridge_rPGA_Rev0p61 CONN@ C78 0.047U_0402_16V7K R63 1K_0402_5% DIMM_DRAMRST# 11,12 S0 DRAMRST_CNTRL_PCH hgih ,MOS ON SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH Dimm not reset S3 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# lo,DDR3 DRAMRST# HIGH Dimm not reset S4,5 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# lo,DDR3 DRAMRST# low Dimm reset Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 2012/07/12 Deciphered Date Title SCHEMATIC,MB A6911 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A R66 1K_0402_5% D S SM_DRAMRST# AA9 AA7 R6 SB_CLK[0] SB_CLK#[0] SB_CKE[0] @ R78 0_0402_5% reset DIMM SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] +1.5V Follow CRB1.0 CPU C9 A7 D10 C8 A9 A8 D9 D8 G4 F4 F1 G1 G5 F5 F2 G2 J7 J8 K10 K9 J9 J10 K8 K7 M5 N4 N2 N1 M4 N5 M2 M1 AM5 AM6 AR3 AP3 AN3 AN2 AN1 AP2 AP5 AN9 AT5 AT6 AP6 AN8 AR6 AR5 AR9 AJ11 AT8 AT9 AH11 AR8 AJ12 AH12 AT11 AN14 AR14 AT14 AT12 AN15 AR15 AT15 DDR SYSTEM MEMORY B JCPU1C E B C D Rev B 4019A9 Tuesday, November 09, 2010 Sheet E of 60 A B C D E CFG Straps for Processor 1 R234 1K_0402_1% m o c e u l b p o t p a l w W w CFG2 PEG Static Lane Reversal - CFG2 is for the 16x 1: Normal Operation; Lane # definition matches socket pin map definition CFG2 JCPU1E CFG2 CFG4 CFG5 CFG6 CFG7 AK28 AK29 AL26 AL27 AK26 AL29 AL30 AM31 AM32 AM30 AM28 AM26 AN28 AN31 AN26 AM27 AK31 AN29 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD28 RSVD29 RSVD30 RSVD31 RSVD32 L7 AG7 AE7 AK2 W8 RSVD33 RSVD34 RSVD35 AT26 AM33 AJ27 RSVD37 RSVD38 RSVD39 RSVD40 T8 J16 H16 G16 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 AR35 AT34 AT33 AP35 AR34 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 B34 A33 A34 B35 C35 RSVD51 RSVD52 AJ32 AK32 CFG4 UMA,Muxless eDP DISO eDP CFG0 CFG0 0:Lane Reversed * R204 1K_0402_1% @ eDP enable CFG4 1:Disable * 0:Enable CFG6 AJ26 RSVD5 B4 D1 RSVD6 RSVD7 F25 F24 F23 D24 G25 G24 E23 D23 C30 A31 B30 B29 D30 B31 A30 C29 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 J20 B18 A19 RSVD24 RSVD25 RSVD26 J15 RSVD27 CFG5 R230 1K_0402_1% @ RSVD1 RSVD2 RSVD3 RSVD4 @ R69 1K_0402_1% VCCIO_SEL VCCIO_SEL VCCIO_SEL For 2012 CPU support A19 * CFG[6:5] (Default) 1x16 PCI Express *11: 10: 2x8 PCI Express 01: Reserved RSVD53 AH27 RSVD54 RSVD55 AN35 AM35 RSVD56 RSVD57 RSVD58 AT2 AT1 AR1 PAD 00: 1x8,2x4 PCI Express T1 @ CFG7 R224 1K_0402_1% @ R520 10K_0402_5% @ PCIE Port Bifurcation Straps 1 R68 1K_0402_1% RESERVED SA_DIMM_VREFDQ SB_DIMM_VREFDQ 11 SA_DIMM_VREFDQ 12 SB_DIMM_VREFDQ SA_DIMM_VREFDQ SB_DIMM_VREFDQ For Future CPU M3 support, Sandey bridge not supportM3, Check list1.0&CRB say can NC R228 1K_0402_1% AJ31 AH31 AJ33 AH33 PAD @ PAD @ PAD @ PAD @ T4 T6 T5 T3 VCC_VAL_SENSE VSS_VAL_SENSE VAXG_VAL_SENSE VSSAXG_VALSENSE PEG DEFER TRAINING 1/NC : (Default) +1.05VS_VTT KEY B1 CFG7 0: +1.0VS_VTT CRB1.0 P.12 1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training Sandy Bridge_rPGA_Rev0p61 CONN@ 4 Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 Issued Date Deciphered Date 2012/07/12 Title SCHEMATIC,MB A6911 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev B 4019A9 Tuesday, November 09, 2010 Sheet E of 60 A B C E POWER JCPU1F SV type CPU D 5x TOP in,7x BOT in PEG AND DDR 1 + C594 + C601 330U_6.3V_R15M 330U_6.3V_R15M INTEL Recommend 2*330uF,12*22uF from PDDG 1.0 1 +1.05VS_VTT R580 75_0402_5% 2 SVID CORE SUPPLY R576 43_0402_1% R577 0_0402_5% R578 0_0402_5% H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT VR_SVID_ALRT# 52 VR_SVID_CLK 52 VR_SVID_DAT 52 Place the PU resistors close to VR Place the PU resistors close to CPU +CPU_CORE AJ35 VCCSENSE_R AJ34 VSSSENSE_R R579 R581 2 0_0402_5% 0_0402_5% VCCSENSE 52 VSSSENSE 52 VCC_SENSE VSS_SENSE R588 100_0402_1% B10 A10 R589 100_0402_1% VCCIO_SENSE 48 VSSIO_SENSE VCCIO_SENSE VSSIO_SENSE R105 10_0402_5% Place BOT Out Socket AJ29 AJ30 AJ28 change to SF000002080 OS-CON 330U 6.3V ESR 15mohm H6 R574 130_0402_5% VIDALERT# VIDSCLK VIDSOUT Place TOP IN Conn +1.05VS_VTT SENSE LINES Place BOT Out Socket 2 C165 22U_0805_6.3V6M SGA00001Q80 S POLY C 330U 2V M X LESR6M SX H1.9 change footprint to pin (C_X) C624 22U_0805_6.3V6M SGA00004V00 change footprint to pin (C_X) 2 C151 22U_0805_6.3V6M 2 @ C652 22U_0805_6.3V6M + C192 22U_0805_6.3V6M C678 J23 2 C180 22U_0805_6.3V6M + VCCIO40 @ C625 22U_0805_6.3V6M @ C354 E11 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 C109 22U_0805_6.3V6M + 330U_X_2VM_R6M C332 330U_X_2VM_R6M + 330U_X_2VM_R6M C653 470U 2V M D2 LESR4M + 470U 2V M D2 LESR4M C242 VCCIO25 VCCIO26 VCCIO27 VCCIO28 VCCIO29 VCCIO30 VCCIO31 VCCIO32 VCCIO33 VCCIO34 VCCIO35 VCCIO36 VCCIO37 VCCIO38 VCCIO39 +1.05VS_VTT 1 C632 22U_0805_6.3V6M AH13 AH10 AG10 AC10 Y10 U10 P10 L10 J14 J13 J12 J11 H14 H12 H11 G14 G13 G12 F14 F13 F12 F11 E14 E12 Place BOT IN Conn C248 22U_0805_6.3V6M C282 22U_0805_6.3V6M C247 22U_0805_6.3V6M C256 22U_0805_6.3V6M Place TOP Out Socket +CPU_CORE C333 22U_0805_6.3V6M C259 22U_0805_6.3V6M C335 22U_0805_6.3V6M 2 C312 22U_0805_6.3V6M 1 C342 22U_0805_6.3V6M 2 C305 22U_0805_6.3V6M 1 C346 22U_0805_6.3V6M 2 C283 22U_0805_6.3V6M 1 C272 22U_0805_6.3V6M INTEL Recommend 4*470uF,16*22uF and 10*10uF from PDDG 1.0 2 C232 22U_0805_6.3V6M C245 22U_0805_6.3V6M 2 C296 22U_0805_6.3V6M C325 22U_0805_6.3V6M VCCIO1 VCCIO2 VCCIO3 VCCIO4 VCCIO5 VCCIO6 VCCIO7 VCCIO8 VCCIO9 VCCIO10 VCCIO11 VCCIO12 VCCIO13 VCCIO14 VCCIO15 VCCIO16 VCCIO17 VCCIO18 VCCIO19 VCCIO20 VCCIO21 VCCIO22 VCCIO23 VCCIO24 C639 22U_0805_6.3V6M Place TOP IN Socket VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 +1.05VS_VTT Place TOP IN Conn C106 22U_0805_6.3V6M +CPU_CORE 8.5A C642 22U_0805_6.3V6M Place BOT IN Socket C649 10U_0805_6.3V6M C669 10U_0805_6.3V6M 2 C660 10U_0805_6.3V6M C666 10U_0805_6.3V6M C293 10U_0805_6.3V6M C634 10U_0805_6.3V6M C638 10U_0805_6.3V6M C656 10U_0805_6.3V6M 1 C627 10U_0805_6.3V6M C277 10U_0805_6.3V6M AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 C619 22U_0805_6.3V6M m o c e u l b p o t p a l w W w QC 94A DC 53A +CPU_CORE Should change to connect form power cirucit & layout differential with VCCIO_SENSE 4 CONN@ Sandy Bridge_rPGA_Rev0p61 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 2012/07/12 Deciphered Date Title SCHEMATIC,MB A6911 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev B 4019A9 Tuesday, November 09, 2010 Sheet E of 60 B m o c e u l b p o t p a l w W w UMA@ SGA00001Q80 S POLY C 330U 2V M X LESR6M SX H1.9 ‧ Can connect to GND if motherboard only supports external graphics and if GFX VR is not stuffed in a common motherboard design, ‧ VAXG can be left floating in a common motherboard design (Gfx VR keeps VAXG from floating) if the VR is stuffed SENSE LINES VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 AF7 AF4 AF1 AC7 AC4 AC1 Y7 Y4 Y1 U7 U4 U1 P7 P4 P1 10A VCCSA1 VCCSA2 VCCSA3 VCCSA4 VCCSA5 VCCSA6 VCCSA7 VCCSA8 VCCSA_SENSE H23 FC_C22 VCCSA_VID1 J6 @ 2 2 INTEL Recommend 1*330uF,3*10uF from PDDG 1.0 Place BOT IN Conn 6A M27 M26 L26 J26 J25 J24 H26 H25 +1.5V Place BOT OUT Conn Place BOT OUT Conn 2 JUMP_43X118 + C599 330U_D2_2V_Y +1.5VS J7 @ JUMP_43X118 Short for +1.5VS to +1.5V_CPU_VDDQ change to SF000002000 OS-CON 330U 6.3V ESR 15mohm H6 INTEL Recommend 1*330uF,6*10uF from PDDG 1.0 +VCCSA +VCCSA @ 2 2 R1281 0_0402_5% R1341 0_0402_5% VCCSA_SENSE VSSSA_SENSE 47 VCCSA_SENSE 47 CPU EDS1.3 P.93 VCCSA_VID0 Must PD C22 VCCSA_VID0 C24 VCCSA_VID1 VCCSA_VID1 47 MISC VCCPLL1 VCCPLL2 VCCPLL3 +1.5V_CPU_VDDQ 1.8V RAIL B6 A6 A2 SGA20331E10 S POLY C 330U 2V 9mohm H1.9 C222 10U_0603_6.3V6M C584 1U_0402_6.3V6K change to SF000002080 OS-CON 330U 6.3V ESR 15mohm H6 C583 1U_0402_6.3V6K C578 10U_0805_6.3V6M + R540 1K_0402_5% C643 10U_0805_6.3V6M +1.8VS_VCCPLL C582 330U_6.3V_R15M 1.2A Place BOT OUT Conn C131 10U_0805_6.3V6M R477 0_0805_5% C647 0.1U_0402_16V4Z C208 10U_0805_6.3V6M +V_SM_VREF AL1 +1.8VS SM_VREF R534 1K_0402_5% C107 10U_0805_6.3V6M Vaxg +V_SM_VREF should have 20 mil trace width C112 10U_0805_6.3V6M Place TOP OUT Conn +1.5V_CPU_VDDQ C149 10U_0805_6.3V6M C693 330U_X_2VM_R6M UMA@ VCC_AXG_SENSE 52 VSS_AXG_SENSE 52 C162 10U_0805_6.3V6M AK35 AK34 C172 10U_0805_6.3V6M + VAXG_SENSE VSSAXG_SENSE C116 10U_0805_6.3V6M VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 VAXG37 VAXG38 VAXG39 VAXG40 VAXG41 VAXG42 VAXG43 VAXG44 VAXG45 VAXG46 VAXG47 VAXG48 VAXG49 VAXG50 VAXG51 VAXG52 VAXG53 VAXG54 2 UMA@ C334 22U_0805_6.3V6M C694 22U_0805_6.3V6M C343 22U_0805_6.3V6M UMA@ C331 22U_0805_6.3V6M UMA@ UMA@ C338 22U_0805_6.3V6M UMA@ C665 22U_0805_6.3V6M Place TOP OUT Conn POWER VREF E JCPU1G AT24 AT23 AT21 AT20 AT18 AT17 AR24 AR23 AR21 AR20 AR18 AR17 AP24 AP23 AP21 AP20 AP18 AP17 AN24 AN23 AN21 AN20 AN18 AN17 AM24 AM23 AM21 AM20 AM18 AM17 AL24 AL23 AL21 AL20 AL18 AL17 AK24 AK23 AK21 AK20 AK18 AK17 AJ24 AJ23 AJ21 AJ20 AJ18 AJ17 AH24 AH23 AH21 AH20 AH18 AH17 UMA@ D SA RAIL 1 UMA@ C266 22U_0805_6.3V6M C280 22U_0805_6.3V6M UMA@ Place TOP IN Conn DISO@ C696 22U_0805_6.3V6M R184 0_0402_5% UMA@ UMA@ QC 33A DC 26A C672 22U_0805_6.3V6M UMA@ C699 22U_0805_6.3V6M Place BOT OUT Conn C708 22U_0805_6.3V6M INTEL Recommend 2*470uF,12*22uF from PDDG 1.0 Place BOT IN Conn GRAPHICS +VGFX_CORE C DDR3 -1.5V RAILS A R119 10K_0402_5% Sandy Bridge_rPGA_Rev0p61 CONN@ VCCSA INTEL Recommend 1*330uF,1*10uF and 2*1uF(0402) from PDDG 1.0 R129 0_0402_5% @ VID0 VID1 Vout 2011CPU 2012CPU 0 0.9V V V VCCSA_VID0 0.8V V V For 2012 future CPU VCCSA voltage select 0.725V X V 1 0.675V X V 4 Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 Issued Date Deciphered Date 2012/07/12 Title SCHEMATIC,MB A6911 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Tuesday, November 09, 2010 Rev B 4019A9 Sheet E of 60 A B C m o c e u l b p o t p a l w W w D JCPU1H AT35 AT32 AT29 AT27 AT25 AT22 AT19 AT16 AT13 AT10 AT7 AT4 AT3 AR25 AR22 AR19 AR16 AR13 AR10 AR7 AR4 AR2 AP34 AP31 AP28 AP25 AP22 AP19 AP16 AP13 AP10 AP7 AP4 AP1 AN30 AN27 AN25 AN22 AN19 AN16 AN13 AN10 AN7 AN4 AM29 AM25 AM22 AM19 AM16 AM13 AM10 AM7 AM4 AM3 AM2 AM1 AL34 AL31 AL28 AL25 AL22 AL19 AL16 AL13 AL10 AL7 AL4 AL2 AK33 AK30 AK27 AK25 AK22 AK19 AK16 AK13 AK10 AK7 AK4 AJ25 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 E JCPU1I AJ22 AJ19 AJ16 AJ13 AJ10 AJ7 AJ4 AJ3 AJ2 AJ1 AH35 AH34 AH32 AH30 AH29 AH28 AH26 AH25 AH22 AH19 AH16 AH7 AH4 AG9 AG8 AG4 AF6 AF5 AF3 AF2 AE35 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE9 AD7 AC9 AC8 AC6 AC5 AC3 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 Y9 Y8 Y6 Y5 Y3 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 U9 U8 U6 U5 U3 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 P9 P8 P6 P5 P3 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 M34 L33 L30 L27 L9 L8 L6 L5 L4 L3 L2 L1 K35 K32 K29 K26 J34 J31 H33 H30 H27 H24 H21 H18 H15 H13 H10 H9 H8 H7 H6 H5 H4 H3 H2 H1 G35 G32 G29 G26 G23 G20 G17 G11 F34 F31 F29 Sandy Bridge_rPGA_Rev0p61 CONN@ VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 VSS VSS234 VSS235 VSS236 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243 VSS244 VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 F22 F19 E30 E27 E24 E21 E18 E15 E13 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 D35 D32 D29 D26 D20 D17 C34 C31 C28 C27 C25 C23 C10 C1 B22 B19 B17 B15 B13 B11 B9 B8 B7 B5 B3 B2 A35 A32 A29 A26 A23 A20 A3 Sandy Bridge_rPGA_Rev0p61 CONN@ 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 2012/07/12 Deciphered Date Title SCHEMATIC,MB A6911 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev B 4019A9 Tuesday, November 09, 2010 Sheet E 10 of 60 C D E PL18 HCB4532KF-800T90_1812 PC76 4.7U_0805_25V6-K LGATE 10 PR100 4.7_1206_5% PQ39 AO4456_SO8 +5VALW DL_1.5V + PC71 330U_6.3V_R15M RT8209MGQW_WQFN14_3P5X3P5 PC69 4.7U_0805_10V6K PC74 680P_0402_50V7K 15 14 VDDP +1.5VP PR112 16.5K_0402_1% PC72 4.7U_0603_10V6K 11 PGOOD LX_1.5V CS PL9 1UH_FDUE1040D-1R0M-P3_21.3A_20% DH_1.5V 12 FB 13 PHASE PR99 PC83 2.2_0603_5% 0.1U_0603_25V7K 2BST_1.5V-1 BST_1.5V UGATE VFB=0.75V PQ33 AO4406AL_SO8 B+ PC73 680P_0402_50V7K VDD PGND VOUT BOOT NC EN/DEM TON PR97 100_0603_5% 2 GND PU6 PC84 @ 1U_0402_16V7K @ +5VALW PR109 2.2_0603_5% 35,36,40,41 SYSON PR98 47K_0402_5% m o c e u l b p o t p a l w W w PR110 267K_0402_1% PR108 0_0402_5% PC75 4.7U_0805_25V6-K 1.5_51117_B+ B A PR111 1 10K_0402_1% PR101 9.53K_0402_1% 2 +1.5VP Ipeak=21.56A;1.2Ipeak=25.87A ;Imax=15.09A Rton=267K, Fsw=298KHz ,Rdson=4.5~5.6mohm Rtrip=16.5K Iocp=25.97A~42.41A 3 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 2012/07/12 Deciphered Date Title SCHEMATIC,MB A6911 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev B 4019A9 Tuesday, November 09, 2010 Sheet E 46 of 60 B C PR106 9.76K_0402_1% B+ UG_VCCSAP PHASE 12 LX_VCCSAP CS 11 0_0402_5% PR117 SA_PGOOD 36 PC109 4.7U_0805_10V6K + 2 PC105 330U_6.3V_R15M 2 PR125 0_0402_5% @ PC113 470P_0603_50V8J PR147 0_0402_5% RT8209MGQW_WQFN14_3P5X3P5 LG_VCCSAP 10 VDDP LGATE PQ47 IRFH3707TRPBF_PQFN8-3 PR153 12.1K_0402_1% PC110 4.7U_0805_25V6-K @ PR151 4.7_1206_5% +5VALW PGOOD PGND FB PR137 10K_0402_5% PC106 4.7U_0603_6.3V6K Layout Note: Place near V5FILT Pin +3VS +VCCSAP 13 2 NC 15 14 UGATE VDD GND PR149 100_0603_1% +5VALW PL10 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20% VOUT BOOT VSSSA_SENSE 2 TON EN/DEM 1 PR156 PC111 2.2_0603_5% 0.1U_0603_25V7K BST_VCCSAP-1 2 PC112 @.1U_0402_16V7K JUMP_43X118 BST_VCCSAP PU12 @ PR135 47K_0402_5% EN_VCCSAP 48 VCCPPWRGOOD 51117_VCCSAP_B+ PC107 4.7U_0805_25V6-K PR159 267K_0402_1% PR164 0_0402_5% @PJ24 @ PJ24 PQ46 SIS412DN-T1-GE3_POWERPAK8-5 1.8VSP Ipeak=3.35A ; 1.2Ipeak=4.02 ;Imax=2.345A Vout=0.6*(1+(20K/10K))=1.8V -DVT- SY8033BDBC_DFN10_3X3 FB_1.8V NC FB=0.6Volt E +1.8VSP NC PR105 20K_0402_1% FB 2 PR107 4.7_1206_5% EN LX PC78 680P_0603_50V7K SVIN PC79 1U_0402_16V7K S PR103 1M_0402_5% @ 1 D PQ131 2N7002W-T/R7_SOT323-3 G 40,48 SUSP 2 PR104 510K_0402_5% 34,36,40,48 SUSP# PVIN 11 EN_1.8V TP PC82 22U_0805_6.3VAM JUMP_43X118 PC81 22U_0805_6.3VAM LX_1.8V LX m o c e u l b p o t p a l w W w @ PVIN 10 PC80 22U_0805_6.3VAM 1 PC77 68P_0402_50V8J 2 D PL11 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20% PU7 PJ20 +5VALW PG A PR160 2K_0402_1% PR162 VFB=0.75V VCCSA_SENSE 10_0402_5% +VCCSAP Ipeak=6A , Imax=4.2A, 1.2Ipeak=7.2A DCR= m(typ)~10 m(max) Rlimit=12.1K,Rdson=14.5~17.9mohm Iocp=7.24A~12.59A 1 +3VS PR283 15K_0402_1% PQ65 PMBT2222A_SOT23-3 0_0402_5% VCCSA_VID1 @ PR580 @PR580 10K_0402_5% PR585 @ PR280 @PR280 100K_0402_5% @ PC179 4700P_0402_25V7K 2 S D PR282 10K_0402_5% 1 PR150 30K_0402_1% 1 PR281 10K_0402_5% PQ64 2N7002W-T/R7_SOT323-3 G VID[0] 0 1 VID[1] 1 VCCSA Vout 0.9 V 0.8 V 0.75V 0.65V Require on 2011/ 2012 Required Yes/Yes Yes/Yes No/Yes No/Yes Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 Deciphered Date 2012/07/12 Title SCHEMATIC,MB A6911 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev B 4019A9 Tuesday, November 09, 2010 Sheet E 47 of 60 B C m o c e u l b p o t p a l w W w VIN VCNTL GND NC VREF NC NC TP VOUT PQ35 2N7002W-T/R7_SOT323-3 +0.75VSP PC94 10U_0603_6.3V6M S PR128 1K_0402_1% G2992F1U SO 8P PC92 1U_0402_16V7K D G PC91 1U_0603_10V6K 1 SUSP 1 PQ36 2N7002W-T/R7_SOT323-3 S G PC93 1U_0402_16V7K D PR127 267K_0402_1% 40,47 SUSP +3VALW PU8 PR126 1K_0402_1% PC90 4.7U_0805_6.3V6K E @ PJ18 JUMP_43X118 1 2 +1.5V D A For shortage changed PR130 680K_0402_5% @ PC97 @PC97 680P_0402_50V7K 1 LGATE DL_1.05VS_VCCP + PGOOD RT8209MGQW_WQFN14_3P5X3P5 PC101 680P_0402_50V7K PR136 10.7K_0402_1% PR133 0_0402_5% PC103 4.7U_0805_10V6K Change PR133 from 10 to 0ohm Change PR144 from to 10ohm 2 PC102 4.7U_0603_10V6K PC100 330U_6.3V_R15M +5VALW PR132 4.7_1206_5% PQ40 AO4456_SO8 FB +1.05VS_VTTP 1 VDDP 10 VFB=0.75V 5 LX_1.05VS_VCCP 11 NC 14 12 CS PR134 100_0603_5% PHASE PL19 1UH_FDUE1040D-1R0M-P3_21.3A_20% VDD 13 DH_1.05VS_VCCP VOUT BOOT PR131 PC98 2.2_0603_5% 0.1U_0603_25V7K BST_1.05VS_VCCP 2 UGATE PGND TON S +5VALW EN/DEM PU9 GND PC99 1U_0402_16V7K 15 1 @ PR702 47K_0402_5% D PQ37 AO4406AL_SO8 PQ130 2N7002W-T/R7_SOT323-3 SUSP G 34,36,40,47 SUSP# PR129 267K_0402_1% B+ PL16 HCB4532KF-800T90_1812 1.05VS_51117_B+ PC95 4.7U_0805_25V6-K PC96 4.7U_0805_25V6-K 2 PR141 4.02K_0402_1% PR144 10_0402_5% 1 VCCPPWRGOOD PR145 VCCIO_SENSE +3VALW 10K_0402_1% 2 47 PR142 10K_0402_1% PR146 @ 10K_0402_1% 4 +1.05VS_VTTP: Ipeak=14.05A;Imax=9.84A;1.2Ipeak=16.86A Rdson=4.5~5.6m ohm ; Freq=298KHz Rtrip=10.7Kohm,Vtrip450KHz 100K ==>390KHz 200K ==>350KHz (Currently setting) 470K ==>300KHz G VGA@ PQ125B S DMN66D0LDW-7_SOT363-6 VGA@ PR681 10K_0402_5% PR684 10K_0402_5% VGA@ PR687 10K_0402_5% D GPU_VID0 23 VGA@ PR683 10K_0402_5% @ PR680 10K_0402_5% 3 Ipeak Granville(35W) 47A Whistler(25W) 27A(VDDC+VDDCI) Seymour(15W) 14.2A(VDDC+VDDCI) VGA@ PR676 10K_0402_5% +3VSDGPU 82.5K_0402_1% 26.1K_0402_1% SEY@ PR672 SEY@ PR677 GRA@ PR672 82.5K_0402_1% +3VSDGPU WHI@ PR677 WHI@ PR672 Granville For Whistler 1/2Delta I=4.05A Vtrip=36.5K*10uA=0.365V Iocpmin=0.365V/(8*1.6m)+1/2Delta I=28.51A+4.05A =32.56A For Seymour 1/2Delta I=4.31A Vtrip=40.2K*10uA=0.402V Iocp=0.402V/(8*3.2m)+1/2Delta I =15.70A+4.31A=20.01A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 2012/07/12 Deciphered Date Title SCHEMATIC,MB A6911 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev B 4019A9 Tuesday, November 09, 2010 Sheet E 49 of 60 C 14 RT8209MGQW_WQFN14_3P5X3P5 2 1 GRA@ PQ118 IRFH3707TRPBF_PQFN8-3 GRA@ PR649 9.76K_0402_1% +VDDCIP GRA@ PC1074 330U_6.3V_R15M @ PC1075 470P_0603_50V8J VFB=0.75V Vo=VFB*(1+PR650/PR653)=1.01V Ton=19E-12*Ron*(((2/3)*Vo+150mV)/Vin)+50ns=2.4E-7 Freq=282KHz GRA@ PC1076 4.7U_0805_10V6K + @ PR647 4.7_1206_5% +5VALW LG_VDDCI VDDCI_SEN 25 10 LX_VDDCI VDDP LGATE B+ GRA@ PR643 10_0402_5% 11 NC BOOT 12 CS 1 PGOOD PHASE GRA@ PC1077 4.7U_0603_6.3V6K 15 FB Layout Note: Place near V5FILT Pin GRA@ PR648 100_0603_1% +5VALW GRA@ 1 GRA@ PL25 2.2UH_MSCDRI-74A-2R2M-E_6.5A_20% UG_VDDCI 13 VDD PGND VOUT GRA@ PR646 GRA@ PC1073 2.2_0603_5% 0.1U_0603_25V7K BST_VDDCI-11 UGATE TON EN/DEM GRA@ PC1072 1U_0402_16V7K @ PR645 47K_0402_5% 1 PU1001 BST_VDDCI GND GRA@ PR644 10K_0402_1% JUMP_43X118 VDDCI_SEN GRA@ PR642 267K_0402_1% 7,23,29,40,51 DGPU_PWR_EN GRA@ PC1071 4.7U_0805_25V6-K GRA@ PQ117 SIS412DN-T1-GE3_POWERPAK8-5 EN_VDDCI E @ PJ29 51117_VDDCI_B+ GRA@ PC1070 4.7U_0805_25V6-K m o c e u l b p o t p a l w W w D 1 B A Cesr=15m ohm Ipeak=4.60A Imax=2.70A 1.2Ipeak=5.52A Delta I=((19.5-1.0)*(1.0/19.5))/(L*Freq)=1.48A Rdson=14.5m~17.9m ohm Iocp=5.76A~10.19A GRA@ PR650 2.05K_0402_1% VFB=0.75V +3VALW GRA@ PR651 2.87K_0402_1% GPIO Broadway PRO VDDCI_VID VDDCI_VID VDDCI_VID 23 PQ119 2N7002W-T/R7_SOT323-3 GRA@ GRA@ PR655 10K_0402_5% 2 GRA@ PR654 10K_0402_5% VDDCI Voltage Level Comment 1 G GRA@ PR653 5.9K_0402_1% PR652 10K_0402_5% @ D S 1.00 V 0.90 V Default 3 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 2012/07/12 Deciphered Date Title SCHEMATIC,MB A6911 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev B 4019A9 Tuesday, November 09, 2010 Sheet E 50 of 60 A B C m o c e u l b p o t p a l w W w D E +3VALW VGA@ PC1079 1U_0402_6.3V6K VGA@ PU17 G971ADJF11U SO 8P EN POK FB +1.0VSDGPU VGA@ PR267 1.54K_0402_1% VGA@ PC180 0.022U_0402_25V7K VGA@ PC182 22U_0805_6.3V6M 1 GND FB=0.8V VGA@ PC181 4.7U_0603_6.3V6K VOUT VOUT 1 VCNTL VIN VIN @ PJ28 JUMP_43X79 1 +1.5V 2 VGA@ PR268 6.04K_0402_1% VGA@ PR269 15K_0402_1% PR270 22K_0402_5% @ 23,40 DGPU_PWR_EN# D 2 VGA@ PC183 1U_0402_6.3V6K 17,23,29,40,50 DGPU_PWR_EN S Ien=10uA, Vth=0.3V, notice the res and pull high voltage from HW VGA@ PQ120 2N7002W-T/R7_SOT323-3 G 3 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 2012/07/12 Deciphered Date Title SCHEMATIC,MB A6911 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev B 4019A9 Tuesday, November 09, 2010 Sheet E 51 of 60 PGND 26 UGATE1 25 BOOT1 GFX@ PC1003 10U_1206_25V6M GFX@ PC1002 10U_1206_25V6M PC1016 680P_0402_50V7K 2 GFX@ PQ104 TPCA8057-H 1N PPAK56-8 PR567 4.7_1206_5% PR568 GFX@ 10K_0402_1% 3 PC1028 2.2U_0603_10V6K PC1066 @ 0.01U_0402_16V7K +5VS +CPU_CORE QC@ PR155 10K_0402_1% 1ISEN1 QC@ PR158 10K_0402_1% 1ISEN2 QC@ PR161 1_0402_5% VSUM- PR699 10K_0402_1% PR607 10K_0402_1% PR612 1_0402_5% PR608 3.65K_0402_1% VSUM+ ISEN2 PR606 10K_0402_1% PR605 4.7_1206_5% 1 PC1045 680P_0402_50V7K 2.61K_0402_1% PQ113 TPCA8065-H 1N PPAK56-8 VSUM- PL24 36UH 20% PCMC104T-R36MN1R105 30A +CPU_CORE Ri is PR618 2010/07/12 Deciphered Date D Compal Electronics, Inc 2012/07/12 Title SCHEMATIC,MB A6911 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC C PR701 10K_0402_1% PR624 10K_0402_1% PR627 1_0402_5% PR625 3.65K_0402_1% VSUM+ ISEN1 PR623 10K_0402_1% PR622 4.7_1206_5% 1 PC1063 680P_0402_50V7K Issued Date Compal Secret Data Security Classification Rdroop is PR615 ISEN3 Ipeak=26A , Imax=18.2A , 1.2Ipeak=31.2A Rdson=3.6~4.5m ohm DCR=1.1m ohm HW output cap: (1)22U_0805_6.3V *12 (2)470U_D2_2V *2(ESR=4.5m ohm) @ PC1062 0.22U_0603_10V7K PQ116 TPCA8057-H 1N PPAK56-8 PR621 2.2_0603_5% 2 PHASE1 1U_0402_16V7K UGATE1 PC1053 10U_1206_25V6M PC1056 10U_1206_25V6M PR613 CPU_B+ PH6 10KB_0603_5%_ERTJ1VR103J PR616 11K_0402_1% QC@ PC1052 0.068U_0402_16V7K @ PR619 100_0402_1% @ 4 PQ112 TPCA8057-H 1N PPAK56-8 PC1040 0.22U_0603_10V7K PC1035 10U_1206_25V6M 1 LGATE2 LGATE1 B GFX@ PR581 590_0402_1% MUX@ PR639 0_0402_5% 1ISNG Date: A 100_0402_1% @ PR577 PL23 36UH 20% PCMC104T-R36MN1R105 30A +CPU_CORE PC1044 0.22U_0603_25V7K PR603 2.2_0603_5% 2 PQ111 TPCA8057-H 1N PPAK56-8 BOOT2 PC1034 10U_1206_25V6M +5VS +VGFX_COREP *OCP setting value=40A ISEN2 *Dual Core OCP setting value=70A *Qual Core OCP setting value=120A PC1017GFX@ 1U_0402_16V7K VSUM- Icc-max=53A Rdson=3.6~4.5m ohm DCR=1.1m ohm HW output cap: (1)10U_0805_4V *10 (2)22U_0805_6.3V *15 (3)470U_D2_2V *4(ESR=4.5m ohm) 1U_0402_16V7K GFX@ PC1013 2 QC@ PR157 3.65K_0402_1% VSUM+2 PHASE2 PQ115 TPCA8057-H 1N PPAK56-8 1 (Ipeak=56A) +CPU_CORE DC@ PR601 4.32K_0402_1% PC1061 1 CPU_B+ @ PC1060 330P_0402_50V7K PQ109 TPCA8065-H 1N PPAK56-8 VSUM+ DC@ PR618 1.47K_0402_1% 1 CPU_B+ QC@ PR601 590_0402_1% BOOT1 *Iccmax in Turbo Mode for SV (35W) is 53A LGATE1 PU1000 QC@ PR618 1.24K_0402_1% GFX@ 11K_0402_1% PR575 ISEN1 PC1059 1000P_0402_50V7K PH4 GFX@ 10K_0402_5%_TSM0A103J4302RE 7.5K_0402_1% PR571 GFX@ 21 QC@ PL17 36UH 20% PCMC104T-R36MN1R105 30A QC@ PR154 10K_0402_1% ISEN3 PC178 PR138 2 680P_0402_50V7K 4.7_1206_5% UG1 BOOT1 PR592 0_0402_5% QC@ PQ44 TPCA8057-H 1N PPAK56-8 PHASE1 1 PC1068 + PR569 GFX@ GFX@ 1_0402_5% 330U_X_2VM_R6M VSUM- QC@ PR615 3.83K_0402_1% PC1048 0.22U_0402_6.3V6K PC1049 0.22U_0402_6.3V6K PC1055 330P_0402_50V7K PR620 +5VS 27 0.33U_0603_10V7K VSUM- PC1054 PR617 10_0402_1% VSSSENSE DC@ PR638 0_0402_5% 2 PC1043 1U_0603_10V6K PC1047 470P_0402_50V7K DC@ PR615 3.32K_0402_1% QC@ PQ41 TPCA8065-H 1N PPAK56-8 @ PQ43 TPCA8057-H 1N PPAK56-8 28 PH1 2 QC@ PR152 0_0402_5% +VGFX_COREP LGATE ISPG GND PC1037 10U_1206_25V6M PL20 HCB4532KF-800T90_1812 CPU_B+ PC1036 10U_1206_25V6M @ PQ103 TPCA8057-H 1N PPAK56-8 PHASE UGATE PWM FCCM VSSP1 PROG1 QC@ PC122 0.22U_0603_10V7K B+ GFX@ PL21 36UH 20% PCMC104T-R36MN1R105 30A 23 QC@PR148 2.2_0603_5% QC@ PU10 ISL6208ACRZ-T_QFN8_3X3 VCC BOOT 1 37 LGG 39 UGG 38 29 24 VIN VDD QC@ PC117 1U_0603_10V6K LGATEG QC@ PR140 0_0402_5% LGATEG PHASEG UGATEG BOOTG 40 41 PROG2 BOOTG 42 43 ISNG NTCG 44 ISPG 46 45 RTNG 47 FBG PHG 30 LG1 PC1051 PR611 499_0402_1% VCCSENSE PWM3 PR604 1_0603_5% 2 10_0402_1% 0.22U_0603_10V7K UGATE2 330P_0402_50V7K PC1039 1 +CPU_CORE PC1096 470P_0402_50V8J 31 GFX@ PC1008 2.2_0603_5% LGATE2 PR600 0_0603_5% 2 150P_0402_50V8J PR700 2K_0402_1% VDDP DC@ PC1041 22P_0402_50V8J PR614 PC1050 412K_0402_1% 2 499K_0402_1% 32 ISEN3 PHASEG GFX@ PR565 BOOTG 2 QC@ 0.22U_0402_6.3V6K PC1046 33P_0402_50V8J PR610 ISUMP VW 22 NTC 12 21 11 @ 330P_0402_50V7K NTCG VR_HOT# ISUMN IMON 10 RTN 33 LG2 ISL95831CRZ-T_TQFN48_6X6 19 PGOOD VSSP2 PH5 470K_0402_5%_TSM0B474J4702RE PR5991 27.4K_0402_1% 1000P_0402_50V7K PR602 change from 43P to 47P for shortage problem 2010-03-15 8.06K_0402_1% PC1032 47P_0402_50V8J ISNG ISPG VR_ON VSEN 18 SCLK ISEN1 17 ALERT# ISEN1 3.83K_0402_1% VSENG GND SDA 13 470P_0402_50V7K PR598 COMPG @ PC1033 @PC1033 1 PR597 499_0402_1% +1.05VS_VTTP @ PHASE2 PC1058 VR_HOT# 34 ISEN2 For shortage changed PH2 ISEN3/ FB2 0_0402_5% UG2 PGOODG ISEN2 PR593 VR_ON PC1027 0.047U_0603_16V7K 36 36 PR596 19.1K_0402_1% VSSSENSE IMONG UGATE2 16 15,36 BOOT2 35 ISEN3 VGATE 36 15 1.91K_0402_1% IMVP_IMON 48 49 GFX_CORE_PWRGD +5VS PR579 @ 16.5K_0402_1% BOOT2 VWG FB 36 PR594 COMP VR_SVID_CLK 14 VR_SVID_ALRT# PR583 54.9_0402_1% VR_SVID_DAT UGATEG +VGFX_COREP +3VS PR584 GFX@ 1.91K_0402_1% For shortage changed Parallel and tune length GFX@ PQ102 TPCA8065-H 1N PPAK56-8 @ PQ101 TPCA8065-H 1N PPAK56-8 VCC_AXG_SENSE 330P_0402_50V7K PC1012 VSS_AXG_SENSE GFX@ 1000P_0402_50V7K GFX@ PR574 10_0402_1% 20 2 130_0402_1% PR582 GFX@ PC1018 0.047U_0603_16V7K GFX@ PR578 18.2K_0402_1% VSS_AXG_SENSE +1.05VS_VTTP PC1020@ 1U_0402_16V7K + GFX@ PR564 10_0402_1% PC1007GFX@ 2 GFX@ PR573 2.55K_0402_1% GFXVR_IMON DEL off page +3VS PC1011 GFX@ PC1010 GFX@ 680P_0402_50V7K 1 GFX@ PR563 27.4K_0402_1% GFX@ PR570 422_0402_1% PC1014 GFX@ 150P_0402_50V8J 2 PR572 GFX@ 475K_0402_1% 1 CPU_B+ NTCG GFX@ PR561 470P_0402_50V7K 3.83K_0402_1% 2 GFX@ PH3 470KB_0402_5%_ERTJ0EV474J PC1006 GFX@ 1000P_0402_50V7K PR562 GFX@ 8.06K_0402_1% 1 PC1009 GFX@ 39P_0402_50V7K PR566 @ 499K_0402_1% E CPU_B+ m o c e u l b p o t p a l w W w D @ PC1019 470P_0402_50V7K C PC999 @ 1 B PC1069 220U_25V_M A Alert# PU resister need close CPU, so the PU resister in HW schematic but DAT and CLK need close PWM-IC, so the PU resister in POWER schematic Rev B 4019A9 Tuesday, November 09, 2010 E Sheet 52 of 60 Version change list (P.I.R List) D C Fixed Issue Reason for change Rev PG# HW increase 1.8V voltage VGA Granville OVP issue Because VGA has happened OVP issue in Granville SKU, that is caused by outptut capacitor too small change PC1094 to SGA00004200 to solve it PC1088 must remove 1.8V Power sequence adjust HW adjust 1.8V power sequence 0.75V Power sequence adjust Modify List Date Phase 0.1 47 Change PR106 from SD034100280 to SD034976180 2010/09/23 DVT 0.1 49 Add PC1094 to SGA00004200 and delete PC1088 SF000002O00 2010/09/23 DVT 0.1 47 2010/09/23 DVT HW adjust 0.75V power sequence 0.1 48 Change PR127 from SD028150380 to SD034267380 2010/09/23 DVT adjust +1.05VS_VTT power sequence HW adjust +1.05VS_VTT power sequence 0.1 48 Change PC99 from SE107475K80 to SE076104K80 2010/09/23 DVT adjust +VDDCI power sequence HW adjust +VDDCI power sequence 0.1 50 Change PR644 from SD034301380 to SD034100280 2010/09/23 DVT HW request to delete PR103 HW request to delete PR103 0.2 47 Delete PR103 SD028100480 2010/09/28 DVT PR104 BOM error PR104 BOM error for power sequence 0.2 47 Change PR104 from SD034150380 to SD034510380 2010/09/28 DVT PR669 BOM error for Seymour only PR669 BOM error for Seymour only 0.2 49 Chnage PR669 from SD034681180 to SD034590180 2010/09/28 DVT 10 To same as P5WE0 VCCSAP choke To same as P5WE0 VCCSAP choke 0.2 47 Change PL10 from SH000009Q00 to SH00000M700 2010/09/28 DVT 0.3 47 48 Add PQ130 and PQ131 SB000006800 2010/10/05 DVT 0.3 42 Delete PR691 SD013000080 CHange PR6 from SD013560080 to SD013000080 2010/10/05 DVT 11 HW need to increase 1.8V voltage HW request to add PQ130 and PQ131 to speed HW request to add PQ130 and PQ131 to speed up to up to We reserve chargeable RTC battery to prevent over heat issue, Thermal team result is pass, so remove chargeable RTC battery change PR104 from SD028100380 to SD028150380 12 Remove chargable RTC battery 13 14 Chnage PL4 and PL5 to TOKO new part Chnage PL4 and PL5 to TOKO new part 0.3 44 Change PL4 and PL5 from SH000006J80 to SH00000MB00 2010/10/05 DVT for ISN issue for ISN issue 0.3 43 Add PL30 SH000009Q00 Delete PL28 SM010018210 2010/10/05 DVT 2010/10/05 DVT 15 B Page of for PWR m o c e u l b p o t p a l w W w Item to same as P5WE0 choke to same as P5WE0 choke 0.3 16 for QC+25WGPU and QC+35W GPU change CP point Becasue Acer deine QC with 25W/35W GPU to be 120W SKU, change CP point to meet Acer request 0.3 17 for QC+25WGPU and QC+35W GPU change CP point Becasue Acer deine QC with 25W/35W GPU to be 120W SKU, change CP point to meet Acer request 0.3 43 18 Modify adapter throttling at turbo mode setting point Modify adapter throttling at turbo mode setting point 0.3 45 CPU Transient responds issue Change CPU transient reponds RC time constant 0.4 52 Add PC1052 SE000003J80 Add PC1096 SE071471J80 Add PR700 SD034200180 for ISN issue 0.4 43 Make BOM same as P5WE0 0.4 19 20 21 for ISN issue Make BOM same as P5WE0 47 43 Change PL10 and PL11 from SH000009Q00 to SH00000F800 Delete PQ20 SB000006800 2010/10/05 Delete PR48 SD034255180 Change PR22 from SD000001F00 to SD021100D80 D C DVT B Change PR47 from SD034121280 to SD034100180 2010/10/05 DVT 2010/10/05 DVT 2010/10/07 DVT Change PL30 from SH000009Q00 to SH00000M700 2010/10/07 DVT 52 Change PL21,PL23,PL24 from SH000005680 to SH00000HK00 2010/10/07 DVT Change PR50 from SD034200280 to SD034511280 Add PR695 SD034154280 Add PR697 SD034174280 22 BOM loss Because BOM Config loss 65@ and 90W@, so miss PR695 and PR697 0.5 45 2010/10/26 PVT 23 Add PR695 SD034909180 9.09K_0402_1% ADD PR697 SD034162280 16.2K_0402_1% Modify CPU OCP Becuase original design is for phase DC, now change to phase DC, so modify OCP 0.5 52 Chnage PR618 from SD034698080 to SD000009480 2010/10/26 PVT 24 Modify DC LL Because DC OCP was modified, must also update LL of DC 0.5 52 Chnage PR615 from SD034215180 to SD034332180 2010/10/26 PVT A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/09/20 Deciphered Date 2008/09/20 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: SCHEMATIC,MB A6911 Rev B 4019BE Tuesday, November 09, 2010 Sheet 53 of 60 A B C D E Intel Sandy Bridge BATTERY 12.6V BATT+ PU1000 ISL95831CRZ-T +CPU_CORE +CPU_CORE 1.1V VCC CORE 94A +VGFX_CORE +VGFX_CORE 0.8~1.5V VAXG 33A +VCCSA 0.9V 1.5V VCCSA 6A +1.05VS_VTT 1.05V VCCIO 8.5A +1.8VS 1.8V VCCPLL 1.2A m o c e u l b p o t p a l w W w AC ADAPTOR 19V 90W PU2 CHARGER SL6251AHAZ-T B+ PU12 G5603RU1U VIN PU9 RT8209BGQW +1.5V +VCCSA VDDQ 10A +1.05VS_VTTP PU6 RT8209BGQW +1.5V PU998 APW7138NITRL +VGA_CORE PU7 SY8033BDBC RAM DDRIII SODIMMX4 1.5V VDD_MEM 14A 0.75V VTT_MEM 2A +0.75VS PU8 UP7711U8 Seymour / Whistler / Granville +VGA_CORE 0.85~1.1V 47A +VDDCI 4.6A (Granville only) 1V 2.775A 1.5V 34A 3.3V 0.19A +1.0VSDGPU PU17 G971-120ADJF11U VRAM 512M or 1GB 64Mx16 (K4B1G1646E) 1.5V 2.4 A +1.5VSDGPU U38 AO4430L +1.8VS 1V +3VSDGPU Q9 AO3413L +1.8VSDGPU U36 DMN3030LSS-13 1.8V U37 DMN3030LSS-13 2.174A Intel Cougar Point-M PCH V_PROC_IO 1mA VccCore 1.3A VccDMI 42mA +1.05VS_VCCP U35 +3VS DMN3030LSS-13 1.05V VccADPLLA 80mA VccADPLLB 80mA VccIO 2.925A VccASW 1.01A VccDIFFCLKN 55mA +3VALW +INVPWR_B+ PU3 RT8205EGQW +LCDVDD LCD panel 17.3" +1.5VS +5VALW U33 DMN3030LSS-13 Q19 AO3413L B+ 25mA +3VS 515mA 1.5V VccVRM 160mA +1.8VS 1.8V VccpNAND 190mA VccTX_LVDS 60mA +3VS 3.3V +5VS +5VALW_PCH RTC Bettary VccSPI 20mA VccDSW 3mA VccSus3_3 119mA VccSusHDA 10mA +3VALW_PCH FAN Control APL5607 Vcc3_3 266mA VccADAC 1mA VccALVDS 1mA 5V RTCVCC V5REF 1mA V5REF_Sus 1mA VCCRTC +5VS 250mA USB3.0X1 USB2.0 X2 +5VALW 3A +5VALW 2A +1.05V_USB3.0 500mA SATA Audio Codec ALC271X +5VS 3A +5VS 668mA +3VS +3VS 35mA Realtek RTS5138 LAN AR8151 +3VALW 217mA +3VS 217mA EC ENE KB930 Bluetooth +3.3VALW 30mA +3VS 3mA +3VS 61mA Mini Card Mini Card +1.5VS 500mA +3VS 1A +3VALW 330mA +1.5VS 500mA +3VS 1A +3VALW 330mA Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 Deciphered Date 2012/07/12 Title SCHEMATIC,MB A6911 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev B 4019A9 Tuesday, November 09, 2010 E Sheet 54 of 60 A B C D 1.5_VDDC_PWREN# m o c e u l b p o t p a l w W w VR_ON (PU1000) ISL95831CRZ-T (PU17) G971-120ADJF11U E +1.0VSDGPU Page 51 SYSON +CPU_CORE (U39) APL5930KAI +1.05V_USB3.0 Page 42 Page 55 1.5_VDDC_PWREN# (PU998) APW7138NITRL +VGA_CORE (U37) DMN3030LSS-13 SUSP +1.5VS Page 40 Page 49 ADAPTER SYSON (PU6) RT8209BGQW +0.75VS SUSP Page 48 Page 46 B+ BATTERY (PU8) UP7711U8 +1.5V VCCPPWRGOOD (PU12) G5603RU1U Page 47 VS_ON (U38) AO4430L +VCCSA (PU9) RT8209BGQW +1.5VSDGPU Page 40 DGPU_PWR_EN# +1.05VS_VTT +1.05VS_PCH (SUSP#) Page 48 CHARGER (PU3) RT8205EGQW Page 44 +5VALW SUSP SYSON# (U33) DMN3030LSS-13 Page 40 +3VALW SYSON# (U46) AP2301MPG-13 SUSP# (U42) AP2301MPG-13 Page 36 SUSP (PU7) SY8033BDBC Page 41 +3VALW_PCH JLAN1 (U35) DMN3030LSS-13 +3VALW_EC Page 47 SYSON (U40) RT9701-PB Page 40 Page 41 3 +5VS +USB_VCCB +USB_VCCA +1.8VS +3VS +3V_USB3.0 DGPU_PWR_EN# (U36) DMN3030LSS-13 +CRT_VCC Page 40 BT_ON# ENVDD (Q31) AO3413L +3VS_WWAN Page 35 +HDMI_5V_OUT DGPU_PWR_EN (Q19) AO3413L (Q9) AO3413L Page 30 +1.8VSDGPU +3VS_WLAN +BT_VCC +LCDVDD Page 23 +3VSDGPU +5VS_HDD1 +5VS_HDD2 4 +5VS_ODD +VDDA Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 2012/07/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D SCHEMATIC,MB A6911 Rev B 4019A9 Tuesday, November 09, 2010 Sheet E 55 of 60 A B C m o c e u l b p o t p a l w W w D E 2.2K H14 PCH_SMBCLK C9 PCH_SMBDATA 4.7K +3VALW_PCH 2.2K PCH 4.7K 2N7002 +3VS D_CK_SCLK 200 D_CK_SDATA 202 DIMM1, 2N7002 200 202 @ @ MINI_SMBCLK MINI_SMBDATA DIMM3, WLAN 4.7K +3VS 4.7K SMB_CLK_S3 53 SMB_DATA_S3 51 2N7002 CPU XDP 2N7002 53 2.2K 2.2K E14 PCH_SML1CLK M16 PCH_SML1DATA 51 4.7K PCH XDP +3VALW_PCH 4.7K EC_SMB_CK2 53 EC_SMB_DA2 51 2N7002 VGA Thermal Sensor 2N7002 2N7002 +3VSDGPU VGA_SMB_CK2 VGA_SMB_DA2 2N7002 2.2K 2.2K 79 EC_SMB_CK2 80 EC_SMB_DA2 +3VALW SCL2 SDA2 2.2K +3VALW KBC 2.2K 77 EC_SMB_CK1 78 EC_SMB_DA1 SCL1 SDA1 100 ohm 100 ohm BATTERY CONN KB930QF A0 PCH SM Bus address Device ChannelA ChannelB A0 1010 000X DIMM1 A2 1010 001X DIMM0 A4 1010 010X DIMM1 A6 1010 011X Compal Electronics, Inc Compal Secret Data Security Classification Issued Date Address DIMM0 2010/07/12 2012/07/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D SCHEMATIC,MB A6911 Rev B 4019A9 Tuesday, November 09, 2010 Sheet E 56 of 60 A C CLK_CPU_DMI CLK_CPU_DPLL CLK_CPU_DPLL 120MHZ (For eDP) DDR_A_CLK[1 2] CPU Sandy Bridge SOCKET BCLK E DIMMB*2 m o c e u l b p o t p a l w W w D DIMMA*2 B DDR_B_CLK[1 2] DPLL_REF_SCLK FDI 100MHZ DMI 100MHZ CLKOUT_PCIE1 CLK_OUT_DP CLK_PCIE_MINI1 Mini Card 100MHZ 2 CLK_CPU_DMI 100MHZ CLK_BUF_ICH_14M 14.318MHZ CLK_BUF_PCIE_SATA 100MHZ CLK_BUF_CPU_DMI 100MHZ CLK_BUF_DREF_96M 96MHZ CLKIN_GND1 100MHZ CLK_OUT_DMI CLKOUT_PCIE2 REFCLK14IN CLKOUT_PCIE3 24M Hz CLK_PCIE_USB30 USB3.0 100MHZ Y5 25M Hz CLK_PCIE_LAN# AR8151 100MHZ CLKIN_SATA CLKIN_DMI INTEL PCH Cougar Point CLKOUT_PCIE4 CLK_PCIE_MINI2 Mini Card 100MHZ CLKOUT_PCIE5 CLKIN_DOT_96 CLKOUT_PCIE6 CLKOUT_PCIE7 CLKIN_DMI2 CLKOUT_PEG_A 3 CLK_BCLK_ITP CPU XDP 100MHZ CLK_PCI_LPBACK CLKOUT_PEG_B CLKOUT_BCLK0 Seymour/ Whistler/ Granville CLK_PEG_VGA 100MHZ CLK_PCI_LPC CLKIN_PCILOOPBACK 27MHz Y3 EC KB930 A0 32.768K Hz X1 33MHZ CLK_SD_48M RTC SATA 32.768K Hz Y1 25M Hz RTS5138 48MHZ Y2 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 2012/07/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D SCHEMATIC,MB A6911 Rev B 4019A9 Tuesday, November 09, 2010 Sheet E 57 of 60 A C m o c e u l b p o t p a l w W w V V V B7 PLT_RST# V 14 15 CPU VGA_PWROK V +1.5VSDGPU U38 U35 +3VS V +1.0VSDGPU PU17 +VGA_CORE PU998 1.5_VDDC_PWREN# PU8 +0.75V VCCPPWRGOOD VGA 11 VGATE U37 +1.5VS V V PU9 +1.05VS_VTT V V V V U33 +5VS +1.8VSDGPU U36 V V DGPU_PWR_EN# V 8a (DIS) SUSP#,SUSP VR_ON +1.5V PU6 V DGPU_PWR_EN SYSON# V +3VSDGPU Q9 V V V SYSON V 8b (DIS) V V V ON/OFF H_CPUPWRGD V PM_SLP_S3# PM_SLP_S4# PM_SLP_S5# B6 PCH V PBTN_OUT# 13 PM_DRAM_PWRGD EC_ON A4 SYS_PWROK V V PCH_RSMRST# A5 12 EC 51ON# +5VALW +5VALW B4 PQ1 B3 +3VALW_PCH V B2 B+ 10 PCH_PWROK PU12 +VCCSA V B1 B7 V BATT A5 V +3VALW +5VALW V PU3 VV B+ +5VALW B5 V PU2 A3 V A2 E +3VALW_PCH J5 +3VALW VIN V V BATT MODE A1 V AC MODE D VV B PU1000 +CPU_CORE 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 2012/07/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D SCHEMATIC,MB A6911 Rev B 4019A9 Tuesday, November 09, 2010 Sheet E 58 of 60 A B C m o c e u l b p o t p a l w W w D E PCB ZZZ LA-6911P MB Rev0: DA80000LC00 LA-6911P MB Rev1: DA80000LC10 LA-6911P MB with Small Board Rev1: DAZ LA-69111P REV0 M/B VGA CRT Option Components Granville VGA_CORE CAP Option DIS EDP Option Components C622 C605 C591 GRAN@ C604 GRAN@ C598 DISO@ DISO@ DISO@ 2 15P_0402_50V8J 15P_0402_50V8J 15P_0402_50V8J 216-0769024 A12 R23 R17 R24 R22 DEDP@ DEDP@ 1U_0402_16V7K 1U_0402_16V7K SGA00003N00 S POLY C 470U 2V Y X LESR9M S H1.9 TXOUT_1P = DP1P TXOUT_1N = DP1N DEDP@ DEDP@ 1 2 R9 R7 1U_0402_16V7K 1U_0402_16V7K EC susclk/crystal Option Components I2CC_SCL = AUXP I2CC_SDA = AUXN X761@ Samsung : SA000035720 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA ABO!) X76264BOL01 L38 X76264BOL02 VRAM 512M HYN P7YE0 X762@ DISO@ 0_0805_5% DISO@ 0_0805_5% DISO@ 0_0805_5% L42 64Mx16x4 Seymour X76264BOL02 2 C504 100K_0402_5% X76264BOL01 X76264BOL01 VRAM 512M SAM P7YE0 470U_X_2VY_R9M 470U_X_2VY_R9M C600 15P_0402_50V8J: SE071150J80 12P_0402_50V8J: SE071120J80 X76 ZZZ C614 1U_0402_16V7K 1U_0402_16V7K TXOUT_2P = DP0P TXOUT_2N = DP0N DISO@ DISO@ DISO@ 2 12P_0402_50V8J 12P_0402_50V8J 12P_0402_50V8J 216-0810005 A11 ZZZ C623 1 WHISTLER PRO M2 A11: SA00004C720(S IC 216-0810005 A11 WHISTLER PRO FCBGA 962P ABO !) WHIS@ 2 U30 DEDP@ DEDP@ 1 2 1 Granville PRO M2 A12: SA00004C820(S IC 216-0769024 A12 GRANVILLE PRO ABO!) GRAN@ 2 U30 L35 Hynix : SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA ABO!) X76264BOL02 ZZZ 0_0805_5%: SD002000080 64Mx16x4 Seymour X76264BOL03 X76264BOL03 VRAM 1G SAM P7YE0 X763@ R307 Samsung : SA000035720 (S IC D3 64MX16 K4W1G1646E-HC12 FBGA ABO!) X76264BOL03 ZZZ 64Mx16x8 Whistler/Granville DISO@ 1K_0402_5% DIS only PCH DAC_IREF can use 1K_0402_5% PD to GND X76264BOL04 X76264BOL04 VRAM 1G HYN P7YE0 X764@ Hynix : SA000032420 (S IC D3 64MX16 H5TQ1G63BFR-12C FBGA ABO!) X76264BOL04 ZZZ 64Mx16x8 Whistler/Granville X76264BOL05 X76264BOL05 VRAM 2G HYN P7YE0 X765@ Hynix : SA00003VS10 (S IC D3 128M16 H5TQ2G63BFR-12C FBGA ABO!) X76264BOL05 ZZZ 128Mx16x8 Whistler/Granville X76264BOL06 X76264BOL06 VRAM 2G SAM P7YE0 X766@ Samsung : SA00003MQ60 (S IC D3 128M16 K4W2G1646C-HC12 FBGA ABO!) X76264BOL06 ZZZ 128Mx16x8 Whistler/Granville X76264BOL07 X76264BOL07 VRAM 1G SAM P7YE0 X767@ Samsung : SA00003MQ60 (S IC D3 128M16 K4W2G1646C-HC12 FBGA ABO!) X76264BOL07 ZZZ 128Mx16x4 Seymour X76264BOL08 X76264BOL08 VRAM 1G HYN P7YE0 X768@ Hynix : SA00003VS10 (S IC D3 128M16 H5TQ2G63BFR-12C FBGA ABO!) X76264BOL08 128Mx16x4 Seymour Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 2012/07/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D SCHEMATIC,MB A6911 Rev B 4019A9 Tuesday, November 09, 2010 Sheet E 60 of 60 A B 0923: rework ADD Q8 DMN66D0LDW-7(SB00000DH00) & change BOM structure to DIS@(DIS@ Granville can't power on issue) R72 100K_0402_5%(SD028100380)change BOM structure to DIS@(DIS@ Granville can't power on issue) R674 4.7K PH change BOM structure to @(+3VS GPIO19 leakage) D31 change BOM structure to @(EC debug CLK leakage) R531,R530 change BOM structure to DISO@(HSYN:VSYNC 11: Audio for both DisplayPort and HDMI) ADD C591 C604 BOM option (Seymour/Whistler option NOGRAN@ SGA20331E10 S POLY C 330U 2V 9mohm H1.9) (Granville option GRAN@ SGA00004200 S POLY C 470U 2V M D2 LESR4.5M SX H1.9) C746,C750 change from SF000001500 to SF000001580 E 0930: R534,R540 change from 100_0402_1% to 1K_0402_5%(SD028100180)(DG1.5 change save cost) C744,C745 change from 18P_0402_50V8J to 27P_0402_50V8J(SE071270J80)(25Mhz Crystal modify) R357,R358,R330,R331,R345,R346,R387,R393,R292 change BOM structure to @ (10K_0402_5%)PD to GND(DG1.5 unuse CLK NC) R666,R667 change BOM structure to @(XDP unuse) R573,R575,R571,R572,R562,R566,R567,R570 DEL option 499_0402_1% leave 680_0402_5% R318,R332 change from 0ohm to 22_0402_5%(SD028220A80) C448,C483 change to 4.7P_0402_50V8J(SE07147AC80) L47 change to 67ohm common mode choke CHENG HANN WCM2012F2SF-670T04(SM070000S80) -1 1025: R370,R413 change from SD028100380(100K_0402_5%) to SD028200380(200K_0402_5%) PCH_GPIO1 change net to WL_EN# LVDS Add +5VS (Pin34) & USB20_N4/P4 (Pin35, 36) change EDP_HPD to Pin18 PCH side add USB20_N4/P4 (Pin35, 36) For eDP interface AUX channel, please request Layout routing as differential signal to follow eDP Layout Guide (VGA_LCD_CLK & VGA_LCD_DATA / I2CC_SCL & I2CC_SDA) DEL DDR DM R50,R58,R59,R48,R56,R51,R60,R49 DIMMA R39,R52,R44,R43,R46,R38,R45,R40 DIMMA R77,R73,R109,R112,R180,R181,R192,R206 DIMMB R64,R83,R108,R115,R179,R183,R189,R208 DIMMB 1026: C604,C591 change from SGA00004200(470 4.5mohm)to SGA00003N00(470 9mohm) Pop R257(SD028100380 100K_0402_5%),R622(SD028820180 8.2K_0402_5%) Board ID R443 change from 100K_0402_5% to 10K_0402_5% (SD028100280) remove R471,R622(JMINI1,JMINI2 Pin42 0ohm series resister) J1,J2 change location to J6,J7 remove R222 0ohm_0402 (H_CPUPWRGD_R) remove R423,0ohm_0402 (MINI1_CLKREQ#_R) remove R392 0ohm_0402 (LAN_CLKREQ#_R) remove R685 0ohm_0402 (MINI2_CLKREQ#_R) remove R655 0ohm_0402 (WAKE#) remove R636 0ohm_0402 (PCH_RSMRST#) remove R377 0ohm_0402 (SUS_PWR_DN_ACK) remove R339 0ohm_0402 (PBTN_OUT#) remove R359 0ohm_0402 (DGPU_HOLD_RST#) remove R16 0ohm_0402 (BKOFF#) remove R448 0ohm_0402 (VGA_EDP_DET) remove R533 0ohm_0402 (VGA_HDMI_DET) remove R627 0ohm_0603 (+SPI_VCC) 0924: Q37,Q39,Q40,Q41, change from SB00000FG00 to SB00000FG10 U7 change from SB000007O00 to SB000007O10 USB3.0 schmetic change to unpop XDP change to unpop U19 A10,N10,P10,B12 connect to GND 0925: R249 change from U15.2 to U15.1(footprint issue) R105 change form 10K to 10_0402_5%(SD028100A80) R422 change BOM structure to @(crystal issue debug port1.2) R422 change +3VS to +3VALW_PCH (GPIO28) R674 change BOM structure to @(leakage issue debug port1.2) R674 change +3VALW_PCH to +3VS (GPIO19) ADD LED11 pop WLAN_LED#(SC500007700),LED12 @ MEDIA_LED#(SC591NB5A30) LED10 WLAN_LED#(SC500007700) change BOM structure to @ DEL D9,D10 USB3.0 old ESD diode ADD D32 new USB3.0 ESD diode (SC300001D00) DEL R238,R250,C401 USB3.0 conn PD resister & CAP EMI request: R595,R596 change to @ L47 change to POP(USB2.0 common mode choke) D m o c e u l b p o t p a l w W w Power sequence: BOT (adjust +5VS power sequence) R698 change from 200K to 100K_0402_5% (SD028100380) BOT (adjust +1.8VS power sequence) PR104 change from 100K to 510K_0402_5%(SD028510380) remove PR103 1M_0402_5% TOP (adjust +1.5VS power sequence) R67 change from 510K_0402_5% to 750K_0402_5%(SD028750380) TOP (adjust +0.75VS power sequence) PR127 change from 150K_0402_5% to 267K_0402_1%(SD034267380) TOP (adjust +1.05VS_VTT power sequence) PC99 change from 4.7U to 1U_0402_16V7K (SE076104K80) TOP (adjust +1.5VSDGPU power sequence) R113 510K change to 100K_0402_1% (SD034100380) BOT (adjust +VDDCI power sequence) PR644 301K change to 10K_0402_1% (SD034100280) Power: PR101 change from 10K to 9.53K (adjust +1.5V power) PR106 change from 10K to 9.76K (adjust +1.8VS power) Layout: D21 channge to SC600000B00 (for sourcer 2nd source) DEL C590,C603 (DEL colay Cap) L24,25,27,30,31 change from SM010004010 to SM010015410 BATT Blue light place at front side H1 change H3P0 to H4P6 DEL LED1,LED2,LED3,LED4 C 0929: DEL Rechargerable RTC schematic D21,R425,C551 ADD R39 0ohm_0402 LOCAL_DIM ADD R38 0ohm_0402 COLOR_ENG_EN C242,C653,C332,C354,C678 change footprint to C_X(2pin) 0927: Audio vender suggest: C913 change BOM structure to @ ADD C702 22K_0402_5%(SD028220280) change USB conn to USB2.0(SUYIN_020133GB004M25MZL_4P-T) modify Debug port note(GPIO19 PH +3VS GPIO28 PH +3VALW_PCH) R667,R666 change BOM structure to @(XDP CLK source) change SW4,SW5 BOM structure to @ (debug PWRBTN) change R432,R435,R437 from 1K_0402_5% to 300_0402_5%(orange LED resister) change USB3.0 schmetic BOM structure back to USB3@ C746,C750 change from SF000001500 to SF000001580 D4,D5 change from SCSH491D010(S SCH DIO CH491DPT SOT-23) to SCS00002000(S SCH DIO RB491D SOT-23 PANJIT) Q29,Q33,Q36 change from SB934130020(S TR AO3413L 1P SOT23-3) to SB000006R10(S TR AO3419L 1P SOT23-3) 0928: DEL R468 JMINI1.24 change power source from +3VS to +3VS_WLAN DEL R613 JMINI2.24change power source from +3VS to +3VS_WWAN DEL R352 change power source from +XDPWR_SDPWR_MSPWR to +CARDPWR Q21 change from SB324110080(2SC2411K) to SB039040020(MMBT3904) Change JUSB2 footprint to "SUYIN_020173GB004M25MZL_4P" ADD R613 1M PD to GND(HDA_SYNC_PCH_R) ADD SLP_A# at U37.G10 test point(for DFT request) ADD JTAG_TDI at U30.AN23 test point(for DFT request) ADD JTAG_TDO at U30.AM24 test point(for DFT request) JREAD1 change conn from TAITW_R013-P12-HM_44P_NR to TAITW_R013-P17-HM_40P_NR 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/07/12 2012/07/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D SCHEMATIC,MB A6911 Rev B 4019A9 Tuesday, November 09, 2010 Sheet E 59 of 60 ... N5 N6 P3 VDD 33 VDD 33 VDD 33 VDD 33 L 13 L14 VDD 33 VDD 33 L9 L10 VDD 33 VDD 33 F3 G3 G4 VDD 33 VDD 33 VDD 33 D10 F 13 F14 K 13 K14 J 13 C14 A6 N8 U2DP2 U3RXDP2 P8 B8 USB3@ R264 10K_0402_5% +3V_USB3.0 R291... VSS [31 5] VSS [31 6] VSS [31 7] VSS [31 8] VSS [31 9] VSS [32 0] VSS [32 1] VSS [32 2] VSS [32 3] VSS [32 4] VSS [32 5] VSS [32 8] VSS [32 9] VSS [33 0] VSS [33 1] VSS [33 3] VSS [33 4] VSS [33 5] VSS [33 7] VSS [33 8] VSS [34 0] VSS [34 2]... AD35 AD34 AD 33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC 33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA 33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y 33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35