COMPAL LA 3541p IFTXX REV 0 3

A B ZZZ1 PJP1 PJP1 PCB 14W_DCIN 15W_DCIN 14W_45@ 15W_45@ C D E 1 12/21 Add PJP1 for DCIN Cable on 45 Level One for 14W DCIN , PN: DC301001Y00 Another for 15W DCIN , PN: DC301001V00 Compal Confidential 2 IFTxx Schematics Document Intel Merom Processor with Crestline + DDRII + ICH8M (With nVIDIA MXM/B) 2006-1-31 3 REV: 0.3 4 2006/08/18 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/8/18 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Cover Page Size B Date: Document Number Rev 0.3 IFTXX M/B LA-3541P Schematic Sheet Friday, February 09, 2007 E of 53 A B C D E Compal Confidential Model Name : IFTXX File Name : LA-3541P Thermal Sensor Intel Merom Processor Fan Control Clock Generator ADM1032 page ICS9LPRS365 page uPGA-478 Package page 16 page 4,5,6 FSB 667/800MHz H_A#(3 35) CRT & TV-out H_D#(0 63) page 19 LCD Conn Video Processor page 18 page 18 LVDS SDVO LVDS Memory BUS(DDRII) Intel Crestline Dual Channel MXM II VGA/B page 7,8,9,10,11,12,13 DMI X4 mode page 17 USB conn x2 TO M/B page 33 3G/TV-Tuner Robson page LAN(GbE) BCM5787M/5906 ENE CB1410 32 page 30 RJ45 page 31 CardBus IDSEL:AD22 (PIRQG#,PIRQH#, GNT#0, REQ#0) CMOS Camera 33 Finger Print Conn page 42 page 42 USB 3.3V 48MHz 3.3V 24.576MHz/48Mhz 3.3V 33 MHz 3.3V ATA-100 BGA-676 S-ATA page 20,21,22,23 HD Audio IDE port CDROM Conn page 24 MDC 1.5 Conn page 42 HDA Codec ALC268 page 38 R5C833 page 28 1394 Conn page 28 S-ATA HDD Conn page 24 in socket Audio AMP page 39 LPC BUS page 29 RTC CKT SUPER I/O ENE KB925 page 21 TPMpage 29 LPC47N217 page 34 Power On/Off CKT page 37 Card Reader page 26 PCMCIA Socket page 26 Bluetooth Conn page Intel ICH8-M PCI BUS New Card MINI Card x3 WLAN, Socket USB conn x2 TO I/O/B page 33 PCI-Express IDSEL:AD20 (PIRQC#,PIRQD#, GNT#2, REQ#2) page 14,15 BANK 0, 1, 2, 1.8V DDRII 533/667 uFCBGA-1299 PCI-Express 200pin DDRII-SO-DIMM X2 page 41 Switch/B Conn page 37 Int.KBD Touch Pad page 35 page 36 page 35 DC/DC Interface CKT page 43 Power Circuit DC/DC page 44,45,47,48 49,50,51 CHARGER G-Sensor I/O Conn FRONT LCD /B LID SW BIOS page 25 SCREW page 40 page 36 page 37 2006/08/18 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification page 46 2007/8/18 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Block Diagrams Size B Date: Document Number IFTXX M/B LA-3541P Schematic Sheet Thursday, February 08, 2007 E of 53 Rev 0.2 A B C D E Voltage Rails Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF Power Plane Description S1 S3 S5 VIN Adapter power supply (19V) N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF +0.9VS ( Actual +0.9V ) 0.9V switched power rail for DDR terminator ON ON OFF +1.05VS 1.05V switched power rail ON OFF OFF +1.25VS 1.25V switched power rail ON OFF OFF +1.5VS 1.5V switched power rail ON OFF OFF +1.8V 1.8V power rail for DDR ON ON OFF +1.8VS 1.8V switched power rail ON OFF OFF +2.5VS 2.5V switched power rail ON OFF OFF Device Address Device Address +3VALW 3.3V always on power rail ON ON ON* Smart Battery 0001 011X b ADI ADM1032 1001 100X b +3VS 3.3V switched power rail ON OFF OFF EEPROM(24C16/02) 1010 000X b NVIDIA NB8X +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON External PCI Devices DEVICE SIGNAL SLP_S1# SLP_S3# SLP_S4# SLP_S5# PIRQ C,D 1394+Cardreader AD22 G,H +VALW +V +VS Clock ON ON HIGH HIGH HIGH ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Vcc Rb ID1 ID0 IFT00 ( 00@ ) R284 R283 IFT01 ( 01@ ) R284 R281 IFL90 ( 10@ ) R694 R283 IFT91 ( 11@ ) R694 R281 Board ID 10 11 12 Structure 15W@ 14W@ MIC ID Table R R785 Single MIC R786 Array MIC Structure INT@ DUAL@ 1101 001Xb DDR DIMM0 1010 000Xb DDR DIMM1 1010 010Xb 3.3V +/- 5% 47K +/- 5% Rb NA 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) 47K(RB@) R743 R743 R743 R743 R743 4.7K_0402_5% H_14_C@ 10K_0402_5% H_14_MP 18K_0402_5% H_15_B@ 27K_0402_5% H_15_C@ 39K_0402_5% H_15_MP@ R743 R743 R743 R743 R743 56K_0402_5% L_14_B@ 82K_0402_5% L_14_C@ 120K_0402_5% L_14_MP@ 220K_0402_5% L_15_B@ 470K_0402_5% L_15_C@ Ra 4.7K +/- 5% 4.7K +/- 5% 10K +/- 5% 18K +/- 5% 27K +/- 5% 39K +/- 5% 56K +/- 5% 82K +/- 5% 120K +/- 5% 220K +/- 5% 470K +/- 5% NA V AD_BID V 0.274 V 0.553V 0.849V 1.129 V 1.415 V 1.712 V 2.020V 2.303 V 2.670 V 2.972 V 3.135 V V AD_BID typ V 0.300 V 0.578 V 0.913V 1.204 V 1.496 V 1.794 V 2.097 V 2.371 V 2.719 V 3.000 V 3.300 V 2006/08/18 2007/8/18 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Ra BOM Structure H_14_B@ H_14_C@ H_14_MP@ H_15_B@ H_15_C@ H_15_MP@ L_14_B@ L_14_C@ L_14_MP@ L_15_B@ L_15_C@ NA for L_15_MP V AD_BID max V 0.328 V 0.628 V 0.981 V 1.282 V 1.579 V 1.876 V 2.173 V 2.437 V 2.765 V 3.026 V 3.465 V Compal Electronics, Inc Compal Secret Data Security Classification Issued Date Address Clock Generator (ICS9LPRS325AKLFT_MLF72) Rb~ R740 Ra~ R743 BOARD ID Table R Ra (R743) Rb (R740) EC SM Bus2 address Device SKU ID Table PROJECT ID Table ICH8M SM Bus address HIGH Full ON REQ/GNT # AD20 EC SM Bus1 address STATE IDSEL # CARD BUS CB1410 D Title Notes List Size B Date: Document Number Rev 0.2 IFTXX M/B LA-3541P Schematic Sheet Thursday, February 15, 2007 E of 53 H_A#[3 35] H_A#[3 35] Place close to CPU within 500mil H_REQ#[0 4] H_REQ#[0 4] JP36A H_ADSTB#0 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 K3 H2 K2 J3 L1 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# A6 A5 C4 A20M# FERR# IGNNE# H_STPCLK# H_INTR H_NMI H_SMI# D5 C6 B4 A3 STPCLK# LINT0 LINT1 SMI# M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10] A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# H1 E2 G5 H_ADS# H_BNR# H_BPRI# H5 F21 E1 H_DEFER# H_DRDY# H_DBSY# F1 IERR# INIT# D20 B3 LOCK# H4 RESET# RS[0]# RS[1]# RS[2]# TRDY# C1 F3 F4 G3 G2 HIT# HITM# G6 E4 BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 PROCHOT# THERMDA THERMDC THERMTRIP# D21 A24 B25 H_BR0# H_INIT# H_LOCK# H_RESET# H_RS#0 H_RS#1 H_RS#2 CRB pull 75 Ohm H_RESET# +1.05VS 12/13 NA for Intel recommend Checklist recommend 39 Ohm H_PREQ# R559 @ 56_0402_5% H_IERR# R560 56_0402_5% ITP_TMS R562 56_0402_5% ITP_TDI R563 150_0402_1% H_PROCHOT# R565 56_0402_5% ITP_TCK R568 27.4_0402_1% ITP_TRST# R569 680_0402_5% H_IERR# D H_TRDY# H_HIT# H_HITM# ADM1032 +3VS C687 0.1U_0402_16V4Z H_PREQ# ITP_TCK ITP_TDI U38 C688 ITP_TMS ITP_TRST# ITP_DBRESET# 2200P_0402_50V7K ITP_DBRESET# H_PROCHOT# THERMAL ICH H_PROCHOT# VDD SCLK EC_SMB_CK2 THERMDA D+ SDATA EC_SMB_DA2 THERMDC D- ALERT# THERM# GND Connect SB SYS_RESET# or just left NC THERMDA THERMDC C ADM1032ARMZ_MSOP8 C7 H_THERMTRIP# A22 A21 CLK_CPU_BCLK CLK_CPU_BCLK# F75383M_MSOP8 H CLK BCLK[0] BCLK[1] 12/21 Change D4,D5 from @ to mount FAN1 Conn D5 change from 1N4148 to SC100000Y10 12/27 change C28,C29 to 10U_0805 H_THERMDA, H_THERMDC routing together, Trace width / Spacing = 10 / 10 mil 0208 Change D5 from SC100000Y10 to SC1BAS16000 12/29 change D4 to SC1SS355010 (IEL10) +5VS C28 +5VS 10U_0805_10V4Z 1 BR0# ADDR GROUP DEFER# DRDY# DBSY# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 C ADS# BNR# BPRI# CONTROL J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 ADDR GROUP D H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 XDP/ITP SIGNALS H_RS#[0 2] H_RS#[0 2] RESERVED B U5 EN_FAN1 +VCC_FAN1 EN_FAN1 B D4 VEN VIN VO VSET GND GND GND GND 1SS355_SOD323 Merom Ball-out Rev 1a conn@ G993P1UF_SOP8 D5 BAS16_SOT23-3 C29 10U_0805_10V4Z +3VS C30 1000P_0402_50V7K R44 10K_0402_5% 40mil JP6 +VCC_FAN1 FAN_SPEED1 C31 1000P_0402_50V7K 3 GND GND A A ACES_85205-03001 Compal Electronics, Inc Compal Secret Data Security Classification 2006/08/18 Issued Date Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Merom (1/3) Size B Date: Document Number IFTXX M/B LA-3541P Schematic Thursday, February 15, 2007 Sheet of 53 Rev H_D#[0 63] H_D#[0 63] H_DSTBN#0 H_DSTBP#0 H_DINV#0 C +1.05VS R549 1K_0402_1% Width=20 mil R551 R553 GTL_REF TEST1 @ 1K_0402_5% TEST2 @ 1K_0402_5% TEST3 T19 PAD @ 0.1U_0402_16V4Z TEST4 TEST5 T20 PAD TEST6 T21 PAD 2 C684 AD26 C23 D25 C24 AF26 AF1 A26 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 B22 B23 C21 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 DATA GRP D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# COMP[0] COMP[1] COMP[2] COMP[3] R26 U26 AA1 Y1 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# E5 B5 D24 D6 D7 AE6 MISC R556 2K_0402_1% H_DSTBN#1 H_DSTBP#1 H_DINV#1 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 DATA GRP H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 Close to CPU pin AD26 within 500mils D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# DATA GRP D E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 DATA GRP H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 JP36C +CPU_CORE JP36B BSEL[0] BSEL[1] BSEL[2] H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_DSTBN#3 H_DSTBP#3 H_DINV#3 COMP0 COMP1 COMP2 COMP3 R550 R552 R554 R555 1 1 H_PWRGOOD H_CPUSLP# 2 2 27.4_0402_1% 54.9_0402_1% 27.4_0402_1% 54.9_0402_1% H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# H_PSI# Merom Ball-out Rev 1a conn@ B layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 166 1 200 1 Resistor placed within 0.5" of CPU pin.Trace should be at least 25 mils away from any other toggling signal COMP[0,2] trace width is 18 mils COMP[1,3] trace width is mils A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCA[01] VCCA[02] B26 C26 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] AD6 AF5 AE5 AF4 AE3 AF3 AE2 VCCSENSE AF7 VCCSENSE VSSSENSE AE7 VSSSENSE Merom Ball-out Rev 1a conn@ +CPU_CORE D Place this cap more close to B26/C26 rather than 10UF C +1.05VS + C677 330U_D2E_2.5VM_R9 20mils +1.5VS CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 R557 C686 0.01U_0402_16V7K 100_0402_1% C685 10U_0805_10V4Z B +CPU_CORE VCCSENSE VSSSENSE R558 100_0402_1% Length match within 25 mils The trace width/space/other is 20/7/25 Close to CPU pin within 500mils A Compal Electronics, Inc Compal Secret Data Security Classification 2006/08/18 Issued Date Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Title Merom (2/3) Size B Date: Document Number Rev IFTXX M/B LA-3541P Schematic Friday, February 09, 2007 Sheet of 53 +CPU_CORE +CPU_CORE x 330uF(9mOhm/3) JP36D A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 D C B VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] Merom Ball-out Rev 1a conn@ + x 330uF(9mOhm/3) 1 C645 + @ 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 2 330U_D2E_2.5VM_R9 C643 C644 + + C648 + @ 330U_D2E_2.5VM_R9 330U_D2E_2.5VM_R9 2 330U_D2E_2.5VM_R9 C646 C647 + D South Side Secondary North Side Secondary +CPU_CORE CRB no stuff Reserved! 1 C649 C650 C651 C652 C653 C654 C655 C656 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 2 2 2 2 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M (Place these capacitors on South side,Secondary Layer) +CPU_CORE 1 C657 C658 C659 C660 C661 C662 C663 C664 9/25 10U checked OK for use! 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 2 2 2 2 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M C (Place these capacitors on North side,Secondary Layer) +CPU_CORE 1 C665 C666 C667 C668 C669 C670 C700 C701 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 2 2 2 2 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M (Place these capacitors on South side,Primary Layer) +CPU_CORE 1 C671 C672 C673 C674 C675 C676 C702 C703 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 2 2 2 2 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M (Place these capacitors on North side,Primary Layer) +CPU-CORE Decoupling SPCAP,Polymer MLCC 0805 X5R B C,uF ESR, mohm ESL,nH 6X330uF 9m ohm/6 1.8nH/6 32X22uF 3m ohm/32 0.6nH/32 32X10uF 3m ohm/32 0.6nH/32 +1.05VS C678 C679 C680 C681 C682 C683 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z A A Compal Electronics, Inc Compal Secret Data Security Classification 2006/08/18 Issued Date Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Merom (3/3) Size B Date: Document Number Rev IFTXX M/B LA-3541P Schematic Thursday, February 08, 2007 Sheet of 53 1/2 change U37 PM part number to SA00001DJ90 D +1.05VS R539 221_0402_1% H_SWNG R540 100_0402_1% 0.1U_0402_16V4Z C C641 Near B3 pin H_RCOMP R541 24.9_0402_1% +1.05VS Route H_SCOMP and H_SCOMP# with trace width, spacing and impedance (55 ohm) same as FSB data traces layout note: R542 R543 54.9_0402_1% H_A#[3 35] U37A H_D#[0 63] H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 54.9_0402_1% E2 G2 G7 M6 H7 H3 G4 F3 N8 H2 M10 N12 N9 H5 P13 K9 M2 W10 Y8 V4 M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4 W3 N1 AD12 AE3 AD9 AC9 AC7 AC14 AD11 AC11 AB2 AD7 AB1 Y3 AC6 AE2 AC5 AG3 AJ9 AH8 AJ14 AE9 AE11 AH12 AJ5 AH5 AJ6 AE7 AJ7 AJ2 AE5 AJ3 AH2 AH13 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 HOST 1 B +1.05VS H_RESET# H_CPUSLP# R544 H_SWNG H_RCOMP B3 C2 H_SWING H_RCOMP H_SCOMP H_SCOMP# W1 W2 H_SCOMP H_SCOMP# H_RESET# H_CPUSLP# B6 E5 H_CPURST# H_CPUSLP# 1K_0402_1% H_VREF R546 C642 B9 A9 J13 B11 C11 M11 C15 F16 L13 G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17 B15 E17 C18 A19 B19 N19 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_BNR# H_BPRI# H_BREQ# H_DEFER# H_DBSY# HPLL_CLK HPLL_CLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# G12 H17 G20 C8 E8 F12 D6 C10 AM5 AM7 H8 K7 E4 C6 G10 B7 H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 K5 L2 AD13 AE13 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 M7 K3 AD2 AH11 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 L7 K2 AC2 AJ10 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 M14 E13 A11 H13 B12 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#_0 H_RS#_1 H_RS#_2 E12 D7 D8 H_RS#0 H_RS#1 H_RS#2 U37 965GM GM@ D 1/2 change U37 GM part number to SA00000ZW80 H_ADS# H_ADSTB#0 H_ADSTB#1 H_BNR# H_BPRI# H_BR0# H_DEFER# H_DBSY# CLK_MCH_BCLK CLK_MCH_BCLK# H_DPWR# H_DRDY# H_HIT# H_HITM# H_LOCK# H_TRDY# H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 C H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_REQ#[0 4] H_RS#[0 2] B H_AVREF H_DVREF CRESTLINE_1p0 PM@ 0.1U_0402_16V4Z 2K_0402_1% H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 within 100mil to Ball A9,B9 A A Compal Electronics, Inc Compal Secret Data Security Classification Layout Note: H_RCOMP / H_VREF / H_SWNG trace width and spacing is 10/20 2006/08/18 Issued Date Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Crestline (1/7)-GTL Size B Date: Document Number IFTXX M/B LA-3541P Schematic Friday, February 09, 2007 Sheet of 53 Rev U37B MCH_CFG_16 MCH_CFG_19 MCH_CFG_20 B PLT_RST_BUF# H_THERMTRIP# PM_DPRSLPVR PM_EXTTS#0 PM_EXTTS#1 R525 R527 100_0402_5% 0_0402_5% GMCH_PWROK MCH_RSTIN# G41 L39 L36 J36 AW49 AV20 N20 G36 PM_BM_BUSY# PM_DPRSTP# PM_EXT_TS#_0 PM_EXT_TS#_1 PWROK RSTIN# THERMTRIP# DPRSLPVR If THERMTRIP no used, left NC Use VGATE for GMCH_PWROK ICH_POK ICH_POK A R533 R535 GMCH_PWROK @ 0_0402_5% 0_0402_5% NC_1 NC_2 NC_3 NC_4 NC_5 NC_6 NC_7 NC_8 NC_9 NC_10 NC_11 NC_12 NC_13 NC_14 NC_15 NC_16 BE29 AY32 BD39 BG37 DDRA_CKE0 DDRA_CKE1 DDRB_CKE0 DDRB_CKE1 SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 BG20 BK16 BG16 BE13 DDRA_SCS0# DDRA_SCS1# DDRB_SCS0# DDRB_SCS1# SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 BH18 BJ15 BJ14 BE16 DDRA_ODT0 DDRA_ODT1 DDRB_ODT0 DDRB_ODT1 SM_RCOMP SM_RCOMP# BL15 BK14 SMRCOMP SMRCOMP# SM_RCOMP_VOH SM_RCOMP_VOL BK31 BL31 SM_RCOMP_VOH SM_RCOMP_VOL SM_VREF_0 SM_VREF_1 AR49 AW4 R514 3.01K_0402_1% Layout Note: SM_VREF trace width and spacing is 20/20 C636 2.2U_0603_6.3V6K 0.01U_0402_16V7K C637 +1.8V +1.25VS CLK_DREF_96M# R518 CLK_DREF_SSC# 20mil CLK_DREF_96M CLK_DREF_96M# CLK_DREF_SSC CLK_DREF_SSC# PEG_CLK PEG_CLK# K44 K45 CLK_MCH_3GPLL CLK_MCH_3GPLL# DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 AN47 AJ38 AN42 AN46 DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 AM47 AJ39 AN41 AN45 DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 AJ46 AJ41 AM40 AM44 DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 AJ47 AJ42 AM39 AM43 DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3 CLK_DREF_96M CLK_DREF_96M# CLK_DREF_SSC CLK_DREF_SSC# CLK_DREF_96M CLK_DREF_SSC 1K_0402_1% DMI_MTX_IRX_N0 DMI_MTX_IRX_N1 DMI_MTX_IRX_N2 DMI_MTX_IRX_N3 DMI_MTX_IRX_P0 DMI_MTX_IRX_P1 DMI_MTX_IRX_P2 DMI_MTX_IRX_P3 0_0402_5% 0_0402_5% 0_0402_5% 011 = 667MT/s FSB 010 = 800MT/s FSB = DMI x = DMI x * (Default) = Lane Reversal Enable = Normal Operation * (Default) 00 = Reserved 01 = XOR Mode Enabled 10 = All Z Mode Enabled 11 = Normal Operation * (Default) = Dynamic ODT Disabled = Dynamic ODT Enabled * (Default) = Normal Operation *(Default) = DMI Lane Reversal Enable = Only PCIE or SDVO is operational * (Default) = PCIE/SDVO are operating simu CFG[2:0] CFG5 0_0402_5% Strap Pin Table CFG[19:18] have internal pull down DMI_ITX_MRX_P0 DMI_ITX_MRX_P1 DMI_ITX_MRX_P2 DMI_ITX_MRX_P3 PM@ PM@ PM@ PM@ CFG[17:3] have internal pull up CLK_MCH_3GPLL CLK_MCH_3GPLL# DMI_ITX_MRX_N0 DMI_ITX_MRX_N1 DMI_ITX_MRX_N2 DMI_ITX_MRX_N3 R574 R575 R576 R577 R520 0.1U_0402_16V4Z B42 C42 H48 H47 1K_0402_1% DPLL_REF_CLK DPLL_REF_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# 12/13 Modified from +1.05VS to +1.25VS by Intel recommend C638 2.2U_0603_6.3V6K 0.01U_0402_16V7K +1.8V 20_0402_1% 20_0402_1% SM_VREF D SM_RCOMP_VOL R515 1K_0402_1% R516 R517 SM_RCOMP_VOH C635 MUXING DDR SM_CKE_0 SM_CKE_1 SM_CKE_3 SM_CKE_4 CFG9 CFG[13:12] CFG16 CFG19 CFG20 (PCIE/SDVO select) = No SDVO Device Present C * (Default) = SDVO Device Present B MCH_CFG_5 GFX_VID_0 GFX_VID_1 GFX_VID_2 GFX_VID_3 GFX_VR_EN R521 @ 4.02K_0402_1% R522 @ 4.02K_0402_1% R523 @ 4.02K_0402_1% R524 @ 4.02K_0402_1% R526 @ 4.02K_0402_1% R529 @ 4.02K_0402_1% R530 @ 4.02K_0402_1% R532 10K_0402_5% R534 10K_0402_5% MCH_CFG_9 E35 A39 C38 B39 E36 MCH_CFG_12 MCH_CFG_13 +1.25VS CL_CLK CL_DATA CL_PWROK CL_RST# CL_VREF AM49 AK50 AT43 AN49 AM50 MCH_CFG_16 R528 1K_0402_1% CL_CLK0 CL_DATA0 CL_PWROK CL_RST# CL_VREF MCH_CFG_19 +3VS MCH_CFG_20 C640 NC VGATE VGATE BJ51 BK51 BK50 BL50 BL49 BL3 BL2 BK1 BJ1 E1 A5 C51 B50 A50 A49 BK2 DDRA_CLK0# DDRA_CLK1# DDRB_CLK0# DDRB_CLK1# 12/22 Change from 0805 to 0603 SDVO_CTRLDATA PM PM_BMBUSY# H_DPRSTP# PM_EXTTS#0 PM_EXTTS#1 AW30 BA23 AW25 AW23 R513 1K_0402_1% MCH_CFG_12 MCH_CFG_13 CFG MCH_CFG_9 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 SM_CK#_0 SM_CK#_1 SM_CK#_3 SM_CK#_4 MCH_CFG_5 P27 N27 N24 C21 C23 F23 N23 G23 J20 C20 R24 L23 J23 E23 E20 K23 M20 M24 L32 N33 L35 DDRA_CLK0 DDRA_CLK1 DDRB_CLK0 DDRB_CLK1 MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 AV29 BB23 BA25 AV23 R531 392_0402_1% PM_EXTTS#0 +3VS PM_EXTTS#1 SDVO_CTRL_CLK SDVO_CTRL_DATA CLK_REQ# ICH_SYNC# H35 K36 G39 G40 TEST_1 TEST_2 A37 R32 SDVO_CTRL_CLK SDVO_CTRL_DATA MCH_CLKREQ# 0.1U_0402_16V4Z MCH_CLKSEL0 MCH_CLKSEL1 MCH_CLKSEL2 CLK C SM_CK_0 SM_CK_1 SM_CK_3 SM_CK_4 C639 DMI 9/20 Modify NB symbol for Pin BJ29/BE24/C48/D47 GRAPHICS VID DDRA_SMA14 DDRB_SMA14 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 RSVD29 RSVD30 RSVD31 SA_MA_14 SB_MA_14 RSVD34 RSVD35 RSVD36 LVDSA_DATA#_3 LVDSA_DATA_3 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 ME DDRA_SMA14 DDRB_SMA14 H10 B51 BJ20 BK22 BF19 BH20 BK18 BJ18 BF23 BG23 BC23 BD24 BJ29 BE24 BH39 AW20 BK20 C48 D47 B44 C44 A35 B37 B36 B34 C34 +1.8V MISC D RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD P36 P37 R35 N35 AR12 AR13 AM12 AN13 J12 AR37 AM36 AL36 AM37 D20 MCH_CLKREQ# R536 MCH_CLKREQ# MCH_ICH_SYNC# SDVO_CTRL_CLK R578 MCH_TEST_1 MCH_TEST_2 R537 R538 SDVO_CTRL_DATA 0_0402_5% 20K_0402_5% R579 10K_0402_5% 1 @ @ 2 0_0402_5% A 0_0402_5% CRESTLINE_1p0 PM@ Compal Electronics, Inc Compal Secret Data Security Classification 2006/08/18 Issued Date Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Crestline (2/7)-DMI/DDR Size Document Number Custom Rev IFTXX M/B LA-3541P Schematic0 Date: Friday, February 09, 2007 Sheet of 53 DDRA_SDQ[0 63] DDRA_SMA[0 13] DDRB_SMA[0 13] DDRB_SMA[0 13] D B MEMORY SA_BS_0 SA_BS_1 SA_BS_2 BB19 BK19 BF29 DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7 DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15 DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31 DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39 DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55 DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63 DDRA_SBS0 DDRA_SBS1 DDRA_SBS2 SA_CAS# BL17 SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6 DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 AT46 BE48 BB43 BC37 BB16 BH6 BB2 AP3 AT47 BD47 BC41 BA37 BA16 BH7 BC1 AP2 DDRA_SDQS0 DDRA_SDQS1 DDRA_SDQS2 DDRA_SDQS3 DDRA_SDQS4 DDRA_SDQS5 DDRA_SDQS6 DDRA_SDQS7 DDRA_SDQS0# DDRA_SDQS1# DDRA_SDQS2# DDRA_SDQS3# DDRA_SDQS4# DDRA_SDQS5# DDRA_SDQS6# DDRA_SDQS7# SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 BJ19 BD20 BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28 BC19 BE28 BG30 BJ16 DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13 SA_RAS# SA_RCVEN# BE18 AY20 SA_WE# BA19 DDRA_SCAS# SA_RCVEN# DDRA_SDQS0 DDRA_SDQS1 DDRA_SDQS2 DDRA_SDQS3 DDRA_SDQS4 DDRA_SDQS5 DDRA_SDQS6 DDRA_SDQS7 DDRA_SDQS0# DDRA_SDQS1# DDRA_SDQS2# DDRA_SDQS3# DDRA_SDQS4# DDRA_SDQS5# DDRA_SDQS6# DDRA_SDQS7# DDRA_SRAS# PAD T18 DDRA_SWE# CRESTLINE_1p0 PM@ AP49 AR51 AW50 AW51 AN51 AN50 AV50 AV49 BA50 BB50 BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43 BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40 BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12 BJ10 BL9 BK5 BL5 BK9 BK10 BJ8 BJ6 BF4 BH5 BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3 AY2 AY3 AU2 AT2 SB_DQ_0 SB_DQ_1 SB_DQ_2 SB_DQ_3 SB_DQ_4 SB_DQ_5 SB_DQ_6 SB_DQ_7 SB_DQ_8 SB_DQ_9 SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19 SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29 SB_DQ_30 SB_DQ_31 SB_DQ_32 SB_DQ_33 SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39 SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49 SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59 SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63 B U37E SYSTEM SA_DQ_0 SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5 SA_DQ_6 SA_DQ_7 SA_DQ_8 SA_DQ_9 SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15 SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25 SA_DQ_26 SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31 SA_DQ_32 SA_DQ_33 SA_DQ_34 SA_DQ_35 SA_DQ_36 SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46 SA_DQ_47 SA_DQ_48 SA_DQ_49 SA_DQ_50 SA_DQ_51 SA_DQ_52 SA_DQ_53 SA_DQ_54 SA_DQ_55 SA_DQ_56 SA_DQ_57 SA_DQ_58 SA_DQ_59 SA_DQ_60 SA_DQ_61 SA_DQ_62 SA_DQ_63 DDR C AR43 AW44 BA45 AY46 AR41 AR45 AT42 AW47 BB45 BF48 BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40 BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41 AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11 BE10 BD10 BD8 AY9 BG10 AW9 BD7 BB9 BB5 AY7 AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8 AN10 AT9 AN9 AM9 AN11 A U37D DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7 DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63 MEMORY DDRA_SMA[0 13] DDRB_SDM[0 7] DDRB_SDM[0 7] SB_BS_0 SB_BS_1 SB_BS_2 AY17 BG18 BG36 DDRB_SBS0 DDRB_SBS1 DDRB_SBS2 SB_CAS# BE17 SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2 DDRB_SDM0 DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 AT50 BD50 BK46 BK39 BJ12 BL7 BE2 AV2 AU50 BC50 BL45 BK38 BK12 BK7 BF2 AV3 DDRB_SDQS0 DDRB_SDQS1 DDRB_SDQS2 DDRB_SDQS3 DDRB_SDQS4 DDRB_SDQS5 DDRB_SDQS6 DDRB_SDQS7 DDRB_SDQS0# DDRB_SDQS1# DDRB_SDQS2# DDRB_SDQS3# DDRB_SDQS4# DDRB_SDQS5# DDRB_SDQS6# DDRB_SDQS7# SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 BC18 BG28 BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37 BG17 BE37 BA39 BG13 DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13 SB_RAS# SB_RCVEN# AV16 AY18 SB_WE# BC17 SYSTEM D DDRB_SDQ[0 63] DDRB_SDQ[0 63] DDRA_SDM[0 7] DDRA_SDM[0 7] DDR DDRA_SDQ[0 63] DDRB_SCAS# SB_RCVEN# DDRB_SDQS0 DDRB_SDQS1 DDRB_SDQS2 DDRB_SDQS3 DDRB_SDQS4 DDRB_SDQS5 DDRB_SDQS6 DDRB_SDQS7 DDRB_SDQS0# DDRB_SDQS1# DDRB_SDQS2# DDRB_SDQS3# DDRB_SDQS4# DDRB_SDQS5# DDRB_SDQS6# DDRB_SDQS7# C DDRB_SRAS# PAD T17 B DDRB_SWE# CRESTLINE_1p0 PM@ A A Compal Electronics, Inc Compal Secret Data Security Classification 2006/08/18 Issued Date Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Crestline (3/7)-DDRII Size B Date: Document Number Rev IFTXX M/B LA-3541P Schematic Thursday, February 08, 2007 Sheet of 53 U37C C792 D 100P_0402_50V8J GMCH_LCD_CLK GMCH_LCD_DATA GMCH_ENVDD R493 CRB 2.37K_1% to GND C GM@ GMCH_TZCLKGMCH_TZCLK+ GMCH_TXCLKGMCH_TXCLK+ LVDS_IBG 2.4K_0402_1% R588 GM@ 0_0402_5% GMCH_TZCLKGMCH_TZCLK+ GMCH_TXCLKGMCH_TXCLK+ LVDS_IBG LVDS_VBG LVDS_VREFH LVDS_VREFL LVDSA_CLK# LVDSA_CLK LVDSB_CLK# LVDSB_CLK GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2- G51 E51 F49 LVDSA_DATA#_0 LVDSA_DATA#_1 LVDSA_DATA#_2 GMCH_TZOUT0+ GMCH_TZOUT1+ GMCH_TZOUT2+ GMCH_TZOUT0+ GMCH_TZOUT1+ GMCH_TZOUT2+ G50 E50 F48 LVDSA_DATA_0 LVDSA_DATA_1 LVDSA_DATA_2 GMCH_TXOUT0 GMCH_TXOUT1 GMCH_TXOUT2- GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2- G44 B47 B45 LVDSB_DATA#_0 LVDSB_DATA#_1 LVDSB_DATA#_2 GMCH_TXOUT0+ GMCH_TXOUT1+ GMCH_TXOUT2+ GMCH_TXOUT0+ GMCH_TXOUT1+ GMCH_TXOUT2+ E44 A47 A45 LVDSB_DATA_0 LVDSB_DATA_1 LVDSB_DATA_2 GMCH_TV_COMPS GMCH_TV_LUMA GMCH_TV_CRMA E27 G27 K27 TVA_DAC TVB_DAC TVC_DAC F27 J27 L27 TVA_RTN TVB_RTN TVC_RTN M35 P33 TV_DCONSEL_0 TV_DCONSEL_1 2 R495 R496 TV_DCONSEL_0 TV_DCONSEL_1 1 GM@ GM@ 150_0402_1% 150_0402_1% GM@ 150_0402_1% TV GMCH_TZOUT0 GMCH_TZOUT1 GMCH_TZOUT2- GMCH_TV_COMPS GMCH_TV_LUMA GMCH_TV_CRMA R494 L41 L43 N41 N40 D46 C45 D44 E42 LVDS L_BKLT_CTRL L_BKLT_EN L_CTRL_CLK L_CTRL_DATA L_DDC_CLK L_DDC_DATA L_VDD_EN GRAPHICS GMCH_ENBKL J40 H39 E39 E40 C37 D35 K40 PCI-EXPRESS LBKLT_EN LCTLA_CLK LCTLB_DATA GMCH_LCD_CLK GMCH_LCD_DATA GMCH_ENVDD Change to 0Ohm when use PM chip GMCH_CRT_B GMCH_CRT_R H32 G32 K29 J29 F29 E29 GM@ 150_0402_1% GM@ 150_0402_1% GM@ 150_0402_1% CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# B GM@39_0402_1% GM@39_0402_1% R500 R501 0_0402_5% 0_0402_5% PM@ PM@ C793 R502 1.3K_0402_1% PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_N15 PEG_RX_0 PEG_RX_1 PEG_RX_2 PEG_RX_3 PEG_RX_4 PEG_RX_5 PEG_RX_6 PEG_RX_7 PEG_RX_8 PEG_RX_9 PEG_RX_10 PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15 J50 L50 M47 U44 T49 T41 W45 W41 AB50 Y48 AC45 AC41 AH47 AG49 AH45 AG42 PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_P15 PEG_TX#_0 PEG_TX#_1 PEG_TX#_2 PEG_TX#_3 PEG_TX#_4 PEG_TX#_5 PEG_TX#_6 PEG_TX#_7 PEG_TX#_8 PEG_TX#_9 PEG_TX#_10 PEG_TX#_11 PEG_TX#_12 PEG_TX#_13 PEG_TX#_14 PEG_TX#_15 N45 U39 U47 N51 R50 T42 Y43 W46 W38 AD39 AC46 AC49 AC42 AH39 AE49 AH44 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_N15 PEG_TX_0 PEG_TX_1 PEG_TX_2 PEG_TX_3 PEG_TX_4 PEG_TX_5 PEG_TX_6 PEG_TX_7 PEG_TX_8 PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12 PEG_TX_13 PEG_TX_14 PEG_TX_15 M45 T38 T46 N50 R51 U43 W42 Y47 Y39 AC38 AD47 AC50 AD43 AG39 AE50 AH43 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_P15 C604 C606 C608 C610 C612 C614 C616 C618 C620 C622 C624 C626 C628 C630 C632 C634 24.9_0402_1% C603 PM@ 0.1U_0402_10V7K C605 PM@ 0.1U_0402_10V7K C607 PM@ 0.1U_0402_10V7K C609 PM@ 0.1U_0402_10V7K C611 PM@ 0.1U_0402_10V7K C613 PM@ 0.1U_0402_10V7K C615 PM@ 0.1U_0402_10V7K C617 PM@ 0.1U_0402_10V7K C619 PM@ 0.1U_0402_10V7K C621 PM@ 0.1U_0402_10V7K C623 PM@ 0.1U_0402_10V7K C625 PM@ 0.1U_0402_10V7K C627 PM@ 0.1U_0402_10V7K C629 PM@ 0.1U_0402_10V7K C631 PM@ 0.1U_0402_10V7K C633 PM@ 0.1U_0402_10V7K PM@ 0_0402_5% GMCH_LCD_CLK R589 PM@ 0_0402_5% GMCH_CRT_B PM@ 0_0402_5% GMCH_LCD_DATA R590 PM@ 0_0402_5% GMCH_CRT_G R582 PM@ 0_0402_5% LCTLB_DATA R591 PM@ 0_0402_5% GMCH_CRT_R R583 PM@ 0_0402_5% LCTLA_CLK R592 PM@ 0_0402_5% GMCH_TV_COMPS GMCH_CRT_CLK R593 PM@ 0_0402_5% GMCH_TV_LUMA R504 GM@ 2.2K_0402_5% GMCH_LCD_DATA R585 PM@ 0_0402_5% GMCH_CRT_DATA R594 PM@ 0_0402_5% GMCH_TV_CRMA R505 GM@ 10K_0402_5% LCTLB_DATA R586 PM@ 0_0402_5% TV_DCONSEL_0 R506 GM@ 10K_0402_5% LCTLA_CLK R587 PM@ 0_0402_5% TV_DCONSEL_1 TV_DCONSEL_0 2.2K_0402_5% TV_DCONSEL_1 1 1 1 1 1 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_P1 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_P3 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_P5 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_P7 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_P9 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_P11 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15 B Compal Electronics, Inc Compal Secret Data Security Classification 2006/08/18 Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A Issued Date PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_N1 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_N5 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_N7 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_N9 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_N11 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_N13 PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_N15 PM@ PM@ 0_0402_5% 2.2K_0402_5% CRESTLINE_1p0 R584 GM@ PCIE_GTX_C_MRX_P[0 15] C GMCH_LCD_CLK GM@ PCIE_GTX_C_MRX_N[0 15] PCIE_GTX_C_MRX_P[0 15] 2.2K_0402_5% R510 PCIE_MTX_C_GRX_P[0 15] PCIE_GTX_C_MRX_N[0 15] R503 GM@ R509 D PCIE_MTX_C_GRX_N[0 15] PCIE_MTX_C_GRX_P[0 15] R581 +3VS +1.05VS PCIE_MTX_C_GRX_N[0 15] C794 R580 CRB 2.2K , Follow! A CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_TVO_IREF CRT_VSYNC J51 L51 N47 T45 T50 U40 Y44 Y40 AB51 W49 AD44 AD40 AG46 AH49 AG45 AG41 CRT_IREF K33 G35 F33 C32 E33 PEG_RX#_0 PEG_RX#_1 PEG_RX#_2 PEG_RX#_3 PEG_RX#_4 PEG_RX#_5 PEG_RX#_6 PEG_RX#_7 PEG_RX#_8 PEG_RX#_9 PEG_RX#_10 PEG_RX#_11 PEG_RX#_12 PEG_RX#_13 PEG_RX#_14 PEG_RX#_15 20/25mils 1 R718 R719 100P_0402_50V8J GMCH_CRT_VSYNC GMCH_CRT_CLK GMCH_CRT_DATA 100P_0402_50V8J GMCH_CRT_CLK GMCH_CRT_DATA GMCH_CRT_HSYNC R492 N43 M43 VGA R497 R498 R499 GMCH_CRT_G PEG_COMP PEG_COMPI PEG_COMPO Title Crestline (4/7)-VGA/LVDS/TV Size B Date: Document Number Rev IFTXX M/B LA-3541P Schematic0 Friday, February 09, 2007 Sheet 10 of 53 A B C D E APA2056 SPK/HP Amplifier +5VALW AMPL +5VS R56 R57 AMP_RHPIN 4.7U_0805_10V4Z AMP_LHPIN C44 4.7U_0805_10V4Z AMP_SD# R768 0_0402_5% C45 AMP_RIGHT_HP C43 @ R58 AMP_LEFT_HP R59 ROUT+ ROUT- 22 21 SPKR+ SPKR- LOUT+ LOUT- SPKL+ SPKL- HP_R HP_L 17 18 HP_R HP_L CVSS 15 VSS 16 AMP_EN#27 /AMP EN 100K_0402_5% AMP_SD#24 HP EN 39K_0402_5% 39K_0402_5% INR_H INL_H 26 AMP_BEEP 28 0_0402_5% AMP_CP+ 12 AMP_CP14 1U_0805_10V7K AMP_BIAS 25 2.2U_0603_6.3V6K 0.1U_0402_16V4Z 2 0.47U_0603_16V4Z R60 C46 C47 C49 1 MIC1_R MIC1_L MIC1_R MIC1_L JP55 INR_H INL_H C37 220P_0402_50V7K 2 VDD 19 11 20 10 PVDD PVDD HVDD INR_A INL_A 100K_0402_5% 2.2K_0402_5% MIC_SENSE MIC_SENSE U6 AMPR 1U_0603_10V4Z 1U_0603_10V4Z 10mil R51 2.2K_0402_5% HP_SENSE C38 220P_0402_50V7K 2 HP_SENSE HP_R HP_L /SD BEEP CP+ CP- R61 23 13 GND PGND PGND CGND BIAS CVSS R62 0_0402_5% @ C48 C50 0_0402_5% @ 10P_0402_50V8J 2 C51 ACES_87212-1200 ME@ 10P_0402_50V8J 12/13 Modified this symbol for pin 13 and 14 Do not re-copy this symbol for other use IN_A Gain = 10dB (Internal Speaker) IN_H Gain = 0dB (Headphone) 9/5 If implement AMP BEEP, Swap C155 and R79 R79 change from Ohm to 47K 1 10 11 12 G1 G2 1U_0805_10V7K APA2056_TSSOP28 2 10 11 12 13 14 1 C41 +MIC1_VREFO_R R50 1U_0402_6.3V4Z AMP_LEFT C36 C39 10mil +3VALW AMP_RIGHT @ 1.5K_0402_1% @ 1.5K_0402_1% 2 C35 CVDD R52 R53 1 10U_0805_10V4Z C34 0.1U_0402_16V4Z 680P_0402_50V7K C33 1/31 Modified fo=1/(2*3.14*R*C)=106Hz R=1.5K / C= 1uF +MIC1_VREFO_L W=40mil 12/15 Modified 12/1 Modified to X7R 12/27 C48 change PN to SE092105K80 12/1 Modified to X7R 12/27 C46 change PN to SE092105K80 EC_MUTE# EC_MUTE# R64 @ 0_0402_5% EAPD R65 0_0402_5% 12/7 Added for 15w" use AMP_SD# JP58 EAPD 10 11 12 13 14 MIC_SENSE MIC1_R MIC1_L HP_SENSE 3 HP_R HP_L SINGLE INT MIC/DUAL INT MIC R790 @ 0_0402_5% GND GND 1 R70 RB751V_SOD323 DUAL@ MIC2_R_L 2 C52 ACES_88231-02001 DUAL@ 2.2K_0402_5% L58 MBK1608121YZF_0603 R781 @ 220P_0402_50V7K DUAL@ MIC_GND D52 R71 R791 2 @ 0_0402_5% MIC_L_3 0_0402_5% +MIC2_VREFO R804 0_0402_5% MIC2_L_1 0_0402_5% R802 @ 0_0402_5% 1 MIC2_L 1/31 change JP9 following JP50 C769 JP9 SPKL+ SPKLSPKR+ SPKR- 0206 => Change R803,R804,R807,R808 from @ to mount Change R801,R802,R805,R806 from mount to @ For EMI Request PSOT05C-LF-T7 SOT-23-3 R700 R701 R702 R703 20mil 1 1 2 2 0_0603_5% 0_0603_5% 0_0603_5% 0_0603_5% SPK_L1+ SPK_L1SPK_R1+ SPK_R1- Speaker Conn D11 MIC2_L_2 0_0402_5% R801 @ 15P_0402_50V8J @ @ 0_0402_5% INT@ R803 1 R72 2.2K_0402_5% L59 MBK1608121YZF_0603 RB751V_SOD323 R807 MIC2_R_2 0_0402_5% R808 0_0402_5% R805 @ MIC2_R_1 0_0402_5% R806 @ 0_0402_5% MIC2_R GND1 GND2 ACES_88231-0400 ME@ 3 MIC_L1 E&T_3703-E12N-03R ME@ @ D54 PSOT05C-LF-T7 SOT-23-3 +MIC2_VREFO @ D53 PSOT05C-LF-T7 SOT-23-3 DUAL@ D10 2/01 Add D52 for INT MIC use( PN:SCD0T05CA20 ) For EMI Request D52 is a modified symbol 0208 => Change L57 , L58 from @ to mount Change R781 , R782 from mount to @ 10 11 12 G1 G2 D46 GND GND MIC2_R_R C54 ACES_88231-02001 R782 @ 220P_0402_50V7K PSOT24C_SOT23 @ C770 D47 PSOT24C_SOT23 @ 15P_0402_50V8J @ MIC_GND MIC_R_3 0_0402_5% 1 MIC_R1 0208 => Remove R797 , Add L63 For EMI Request 12/21 Place these parts close to CODEC (U7) L63 MBK1608121YZF_0603 0_0603_5% @ GNDA A 2006/08/05 Issued Date MIC_GND Compal Electronics, Inc Compal Secret Data Security Classification R798 2007/08/05 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B C D Title AMP/VR/Audio Jack/MIC Size Document Number Custom LA-3541P Date: Rev 0.1 Sheet Thursday, February 15, 2007 E 39 of 53 H2 HOLEA H14 HOLEA H13 HOLEA H12 HOLEA H11 HOLEA H9 HOLEA H8 HOLEA H7 HOLEA 1 H6 HOLEA H16 HOLEA H15 HOLEA H5 HOLEA H4 HOLEA H3 HOLEA 12/18 Del H10 for layout request 1 H1 HOLEA H_C125BC220D122 H31 HOLEA H26 HOLEA H25 HOLEA H24 HOLEA H23 HOLEA H22 HOLEA H21 HOLEA H20 HOLEA 1 H19 HOLEA H18 HOLEA H17 HOLEA 95.10.5 add H34 HOLEA H_O122X220D122X220N M7 HOLEA @ @ CF9 @ CF10 @ CF8 @ CF7 @ CF6 @ CF5 @ 1 FD6 @ CF4 @ 1 CF3 @ FD5 @ @ CF23 @ M6 HOLEA 1 M5 HOLEA FD4 @ CF2 @ CF11 M4 HOLEA FD3 @ 1 CF1 FD2 @ 1 FD1 H33 HOLEA H32 HOLEA H30 HOLEA 1 H29 HOLEA H28 HOLEA H27 HOLEA H_O220X368D220X368N H_O122X220D122X220N H_O236X295D236X295N 95.12.18 add for layout request Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/08/18 Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title FAN & Screw Hole Size B Date: Document Number Rev IFTXX M/B LA-3541P Schematic0 Thursday, February 08, 2007 Sheet 40 of 53 A B C D E SUPER I/O SMsC LPC47N217 +3VS R38 LPC_AD[0 3] LPC_AD[0 3] 10/19 : Change P/N from SA472170000 to SA472170010 SIO_GPIO11 SIO_SMI# SIO_IRQ +3VS R32 217@ R33 @ R607 217@ 10K_0402_5% SUS_STAT# 10K_0402_5% SIO_SMI# 10K_0402_5% SIO_PME# CLK14 IRRX INIT# SLCTIN# PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 SLCT PE BUSY ACK# ERROR# ALF# STROBE# 41 42 44 46 47 48 49 50 51 53 55 56 57 58 59 60 61 CLOCK 23 24 25 27 28 29 30 31 32 33 34 35 36 40 GPIO40 GPIO41 GPIO42 GPIO43 GPIO44 GPIO45 GPIO46 GPIO47 GPIO10 GPIO11/SYSOPT GPIO12/IO_SMI# GPIO13/IRQIN1 GPIO14/IRQIN2 GPIO23 22 43 52 VSS VSS VSS VSS 217@ @ 10K_0402_5% 10K_0402_5% VTR VCC VCC VCC VCC POWER Agilent IRRX unpop 10K Vishay IRRX pop 10K 11 26 45 54 C25 217@ +3VS R775 1 FORCEON 10K_0402_5% @ FORCEOFF# 1 15P_0402_50V8J @ C27 15P_0402_50V8J @ 2 10_0402_5% @ R772 R774 10K_0402_5% @ 10K_0402_5% @ 1 R43 C26 C695 R773 10K_0402_5% @ 2 CLK_PCI_SIO R42 C24 217@ C763 217@ C764 217@ R776 SUSP# R777 0.1U_0402_16V4Z 217@ 2 10K_0402_5% @ +3VS +3VS CLK_14M_SIO 10K_0402_5% U41 28 C1+ 24 C1C2+ 14 13 12 19 18 17 16 15 20 C2TIN1 TIN2 TIN3 ROUT1 ROUT2 ROUT3 ROUT4 ROUT5 ROUTB2 FORCEON 23 FORCEON FORCEOFF# 22 C696 0.1U_0402_16V4Z 217@ C697 0.1U_0402_16V4Z 217@ DTR#1 RTS#1 TXD1 CTS#1 RI#1 RXD1 DCD#1 DSR#1 FORCEON 0_0402_5% 26 R40 +3VS +3VS VCC R39 IRRX RP56 10K_1206_8P4R_5% 217@ 2 R756 217@ LPC47N217_STQFP64 217@ SIO_IRQ 37 38 39 IRRX2 IRTX2 IRMODE/IRRX3 FIR 1K_0402_5% 217@ 0.1U_0402_16V4Z CLKRUN# PCI_CLK SER_IRQ IO_PME# 0.1U_0402_16V4Z PCI_RESET# LPCPD# 19 20 21 R41 0.1U_0402_16V4Z 17 18 PM_CLKRUN# CLK_PCI_SIO SERIRQ SIO_PME# CLK_14M_SIO CLK_14M_SIO SIO_RST# SUS_STAT# RXD1 TXD1 DSR#1 RTS#1 CTS#1 DTR#1 RI#1 DCD#1 0.1U_0402_16V4Z PM_CLKRUN# CLK_PCI_SIO SERIRQ LFRAME# LDRQ# 62 63 64 SERIAL I/F 217@ 0_0402_5% @ 0_0402_5% SUS_STAT# 15 16 LPC I/F R36 R37 LPC_FRAME# LPC_DRQ0# RXD1 TXD1 DSR1# RTS1# CTS1# DTR1# RI1# DCD1# PARALLEL I/F PLT_RST_BUF# PCI_RST# LAD0 LAD1 LAD2 LAD3 GPIO LPC_FRAME# LPC_DRQ0# 10 12 13 14 Base I/O Address * = 02Eh = 04Eh SIO_GPIO11 U4 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 10K_0402_5% @ V+ 27 V- TOUT1 TOUT2 TOUT3 RIN1 RIN2 RIN3 RIN4 RIN5 10 11 INVLD# 21 GND 25 C698 C699 217@ 0.1U_0402_16V4Z 217@ 0.1U_0402_16V4Z DTR# RTS# TXD CTS# RI# RXD DCD# DSR# DTR# RTS# TXD CTS# RI# RXD DCD# DSR# FORCEOFF# MAX3243CAI_SSOP28 217@ FORCEOFF# 0_0402_5% AutoShutdown Mode : FORCEOFF# = VCC, FORCEON = GND 4 12/15 Modified Compal Secret Data Security Classification 2005/05/26 Issued Date 9/18 modify this page following IGT1x A 2006/07/26 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B C D Title Compal Electronics, Inc SUPER I/O LPC47N217 Size Document Number Rev 0.2 LA-3541P UMA Date: Sheet Friday, February 09, 2007 E 41 of 53 MDC Conn Camera Conn +5VS C753 R25 33_0402_5% 20mil 1U_0603_10V4Z Q52 SI2301BDS_SOT23 W=40mils +5VS_CMOS +5VS_CMOS +MDC_VCC GND GND GND GND GND GND HDA_SYNC_MDC HDA_SDIN1 HDA_RST_MDC# 10 12 HDA_SDOUT_MDC GND1 RES0 IAC_SDATA_OUT RES1 GND2 3.3V IAC_SYNC GND3 IAC_SDATA_IN GND4 IAC_RESET# IAC_BITCLK 100K_0402_5% D JP2 11 R736 C754 G CAMERA_ON# S 0.1U_0402_16V4Z C693 HDA_BITCLK_MDC C16 @ 22P_0402_50V8J 4.7U_0805_10V4Z C755 1 4.7U_0805_10V4Z @ 2 C17 0.1U_0402_16V4Z C18 0.1U_0402_16V4Z 13 14 15 16 17 18 JP3 Connector for MDC Rev1.5 USB20_N7 USB20_P7 USB20_N7 USB20_P7 R783 R784 1 USB20_R_N7 USB20_R_P7 0_0603_5% 0_0603_5% ACES_88018-124G ME@ D1 @ PSOT24C_SOT23 GND1 GND2 ACES_88266-05001 ME@ 12/13 Reserved for EMI request 12/18 modified +3VALW C748 C749 1U_0603_10V4Z G 1/05 Modified D3 to SCA00000A00 Finger Print board Q51 SI2301BDS_SOT23 100K_0402_5% D R735 MDC_ON# S 0.1U_0402_16V4Z For EMI 0208 Remove D3 , Add D55 (SC300000G00) W=40mils +MDC_VCC C750 4.7U_0805_10V4Z D55 C751 I/O VCC I/O GND 0.1U_0402_16V4Z 9/29 follow HEL80's PRTR5V0U2X_SOT143 USB20_P9 USB20_N9 JP4 USB20_P9 USB20_N9 +3VS +5VS 1 4.7U_0805_10V4Z @ 2 C19 LED +5VALW R28 14W@ 820_0402_5% LED1 2 GND GND ACES_85201-06051 ME@ C20 0.1U_0402_16V4Z 2/1 change JP4 pin to +5VS for LTT FP use PWR_LED# HT-191NB_BLUE_0603 14W@ +5VS R27 14W@ 820_0402_5% LED2 3G_LED# HT-191NB_BLUE_0603 HS@ R31 14W@ 430_0402_5% LED3 A +5VALW R30 14W@ 680_0402_5% B +5VALW Amber CHARGE_LED0# Blue CHARGE_LED1# HT-297UD/CB _BLUE/AMB_0603 14W@ Blue&Amber R709 14W@ 430_0402_5% LED4 A +5VS R708 14W@ 680_0402_5% B +5VS Amber BT_LED# Blue WLAN_LED# 12/7 Modified LED footprint to LED_HT-297UD-CB_4P 12/15 Modified to correct LED symbol! Issued Date Compal Electronics, Inc Compal Secret Data Security Classification HT-297UD/CB _BLUE/AMB_0603 14W@ 2006/08/18 Deciphered Date 2007/8/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title MDC/CIR & LED Size B Date: Document Number Rev IFTXX M/B LA-3541P Schematic Thursday, February 15, 2007 Sheet 42 of 53 A B C D E 1/18 Change U3 PN from SB000009580 to SB000005D80 +5VALW TO +5VS +5VALW +3VALW TO +3VS +3VALW +1.8V to +1.8VS +5VS +1.8V +3VS +1.8VS U1 D S 2 SUSP G Q2 2N7002_SOT23 @ C7 R17 C12 10U_0805_10V4Z 2 1U_0603_10V4Z +VSB C5 R738 47K_0402_5% C13 SUSP G Q5 2N7002_SOT23 @ +VSB Q53 G 2N7002_SOT23 S S S S G C756 C10 C11 R18 10U_0805_10V4Z PM@ 1U_0603_10V4Z PM@ SUSP 0.1U_0603_25V7K 470_0603_5% @ D 1.8VS_GATE R19 33K_0402_5% PM@ S SUSP 0.1U_0603_25V7K D D D D AO4468_SO8 PM@ 10U_0805_10V4Z PM@ 10U_0805_10V4Z PM@ 470_0603_5% @ D D D SUSP G Q6 2N7002_SOT23 @ C14 0.1U_0603_25V7K PM@ G Q7 S 2N7002_SOT23 PM@ 3 S SUSP Q3 G 2N7002_SOT23 C6 3 R14 33K_0402_5% S S S S G AO4468_SO8 D 5VS_GATE C9 D D D D 10U_0805_10V4Z 2 10U_0805_10V4Z 10U_0805_10V4Z 2 10U_0805_10V4Z C8 470_0603_5% @ 1 10U_0805_10V4Z 2 1U_0603_10V4Z 1 R12 1 C2 U3 1 AO4468_SO8 +VSB C1 1 C4 U2 S S S G D D D D C3 2 +5VALW R11 100K_0402_5% D S Q1 2N7002_SOT23 G SYSON SYSON# SYSON 1 D D D D S S 2 SYSON# G Q12 2N7002_SOT23 @ SUSP G Q54 2N7002_SOT23 @ R15 100K_0402_5% SYSON# G Q11 2N7002_SOT23 @ 12/7 Modified D S SUSP Q4 2N7002_SOT23 G SUSP# SUSP S SUSP G Q10 2N7002_SOT23 @ S SUSP G Q9 2N7002_SOT23 @ S SUSP G Q8 2N7002_SOT23 @ 3 S +5VALW 1 D D R739 470_0603_5% @ R24 470_0603_5% @ R23 470_0603_5% @ R22 470_0603_5% @ +1.25VS 2 +1.8V R21 470_0603_5% @ +0.9VS R20 470_0603_5% @ +1.05VS +2.5VS +1.5VS R13 100K_0402_5% R16 100K_0402_5% C778 100P_0402_50V8J 2 4 2006/08/18 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2007/8/18 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title DC Interface Size B Date: Document Number Rev IFTXX M/B LA-3541P Schematic0 Sheet Thursday, February 08, 2007 E 43 of 53 A B C D ACIN Precharge detector Min typ Max H >L 14.589V 14.84V 15.243V L >H 15.562V 15.97V 16.388V DC301001Y00 PR1 10_1206_5% PR2 1K_1206_5% PR3 1K_1206_5% RLS4148_LL34-2 PR5 PC5 @10K_0402_1% @ 0.01U_0402_25V7K 2 PR10 10K_0402_1% PR12 10K_0402_1% ACIN PACIN PACIN Vin Detector ACOFF PQ3 DTC115EUA_SC70-3 High 18.764 17.901 17.063 Low 17.745 16.9 16.03 3.3V B+ RTCVREF PQ2 DTC115EUA_SC70-3 PR17 10K_0402_1% 1 PR16 10K_0402_1% O PU1A LM393DG_SO8 P - + G PC7 0.1U_0402_16V7K PR8 1K_1206_5% PD3 RLZ4.3B_LL34 PR11 84.5K_0402_1% PR15 20K_0402_1% PC6 1000P_0402_50V7K 2 VS PR14 22K_0402_1% PR4 1K_1206_5% VS PR9 1M_0402_1% VIN PQ1 TP0610K-T1-E3_SOT23-3 1 PR13 100K_0402_5% 2 PD2 VIN PR7 100K_0402_5% @ PR6 100K_0402_5% @ PD1 RLZ24B_LL34 PC4 1000P_0402_50V7K PC3 100P_0402_50V8J PC2 100P_0402_50V8J 2 PJP1 PC1 1000P_0402_50V7K ADPIN @ SINGA_2DW-0268-B16 1 2 3 4 VIN PL1 HCB4532KF-800T90_1812 BATT ONLY Precharge detector Min typ Max H >L 6.138V 6.214V 6.359V L >H 7.196V 7.349V 7.505V VIN PR18 2.2M_0402_5% VL PD4 (7A,280mils ,Via NO.=14) +5VALW PJ5 PAD-OPEN 3x3m PC12 0.01U_0402_25V7K 2 PR28 499K_0402_1% PR27 191K_0402_1% D PQ5 PR31 RHU002N06_SOT323-3 47K_0402_1% 2 G PACIN S (8A,320mils ,Via NO.= 16) +0.9VSP PR30 34K_0402_1% 1 RTCVREF PU1B LM393DG_SO8 +1.05VSP PJ3 PAD-OPEN 3x3m +1.05VS PQ6 DTC115EUA_SC70-3 +5VALWP @ (16A,800mils ,Via NO.= 24) +0.9VS +5VALWP PJ4 PAD-OPEN 3x3m +1.8VP +1.5VS - PR32 66.5K_0402_1% +1.5VSP PJ2 PAD-OPEN 3x3m +1.8V + O 1 RB715F_SOT323-3 PQ4 TP0610K-T1-E3_SOT23-3 PJ1 PAD-OPEN 3x3m PRG++ 1 ACON PC14 1000P_0402_50V7K P MAINPWON 2 PD6 PC11 0.1U_0603_25V7K 51_ON# PR29 22K_0402_1% PC10 0.22U_1206_25V7K CHGRTCP GND 2 PC9 4.7U_0805_6.3V6K +CHGRTC PR25 200_0805_5% 2 IN PR26 100K_0402_5% OUT PC8 1U_0805_25V4Z PU2 G G920AT24U_SOT89-3 PR24 PR23 560_0603_5% 560_0603_5% 2 VS VS RLS4148_LL34-2 PR22 100K_0402_1% PR20 68_1206_5% PR21 68_1206_5% BATT+ RTCVREF PC13 0.1U_0603_25V7K PD5 3.3V PR19 499K_0402_1% RLS4148_LL34-2 (6A,240mils ,Via NO.= 12) +3VALWP PJ6 PAD-OPEN 3x3m (2A,80mils ,Via NO.= 4) PJ7 +3VALW +2.5VSP 1 2 +2.5VS JUMP_43X79 (6A,240mils ,Via NO.=12) +1.25VSP PJ8 PAD-OPEN 3x3m +1.25VS (6A,240mils ,Via NO.=12) A (1A,40mils ,Via NO.= 2) +VSBP PJ9 PAD-OPEN 3x3m Issued Date Compal Electronics, Inc Compal Secret Data Security Classification +VSB 2005/10/17 Deciphered Date 2006/10/17 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC (0.3A,40mils ,Via NO.= 2) B C Title DCIN/DECTOR Size B Date: Document Number Rev 0.2 Sheet Friday, February 16, 2007 D 44 of 52 B C 2/16 Change to 89 degree C for thermal request BATT+ PH1 under CPU botten side : CPU thermal protection at 85 degree C Recovery at 70 degree C PJP2 PR42 78.7K_0603_1% PU3A + - 1 PR37 150K_0402_1% MAINPWON 1SS355TE-17_SOD323-2 PR43 150K_0402_1% VL PR45 150K_0402_1% 2 2 PR46 1K_0402_1% PD8 LM358ADR_SO8 PC20 1U_0603_6.3V6M +3VALWP 2 PR44 6.49K_0402_1% PH1 100K_0603_1%_TH11-4H104FT 1 PC19 1000P_0402_50V7K EC_SMB_DA1 PR41 100_0402_1% 2 PR40 100_0402_1% PR39 442K_0603_1% TM_REF1 EC_SMB_CK1 VL P VL PR38 10K_0402_1% VS PC17 0.01U_0603_50V7K PR36 1K_0402_1% SUYIN_200275MR009G180ZR @ 100K_0402_5% @ PR33 100K_0402_5% +3VALWP 2 PC16 1000P_0603_50V7K PR34 +3VALWP CNT1 CNT2 EC_SMCA EC_SMDA TS_A GND PC15 1000P_0603_50V7K PR35 0_0402_5% BATT++ 10 11 2 G1 G2 G PL2 HCB4532KF-800T90_1812 DC040003600 D BATT++ PC18 0.1U_0603_25V7K A BATT_TEMP PQ7 TP0610K-T1-E3_SOT23-3 PR50 0_0402_5% 1 D SPOK S 2 PC21 0.22U_1206_25V7K PQ8 RHU002N06_SOT323-3 G PC23 0.1U_0402_16V7K PR49 100K_0402_5% PR47 100K_0402_5% PR48 22K_0402_1% VL +VSBP PC22 0.1U_0603_25V7K B+ 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2005/10/17 Deciphered Date 2006/10/17 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title BATTERY CONN / OTP Size B Date: Document Number Rev 0.1 Sheet Friday, February 16, 2007 D 45 of 52 B C D ADP_I = 19.9*Iadapter*Rsense 65W, Iadapter=0~3.42A, Current sense=0.02ohm, PR69=39.2K, CP=3.079A 90W, Iadapter=0~4.74A, Current Sense=0.015ohm, PR69=28.7K, CP=4.263A B+ CELLS CSOP 21 ICOMP CSIN 20 VCOMP CSIP 19 ICM PHASE 18 LX_CHG PC27 2200P_0402_50V7K D D D D G S S S PQ17 SI4800BDY-T1-E3_SO8 PR72 10K_0402_1% 12 16 ACLIM VDDP 15 VADJ LGATE 14 GND PGND 13 PR67 PC41 BST_CHG BST_CHGA 2.2_0603_5% PD10 0.1U_0603_25V7K 1SS355TE-17_SOD323-2 26251VDD 4.7_0603_5% PR71 BATT+ PR65 0.02_2512_1% PC45 4.7U_0805_6.3V6K PR73 @ 274K_0402_1% 2 6251VREF PQ21 @SI2301BDS-T1-E3_SOT23-3 PR212 100K_0402_1% VS BATT+ 6251_EN CHGSEL 13050mV LOW 12.90V 12600mV HIGH 12.60V - LM358ADR_SO8 P PU3B + G PR76 499K_0402_1% PR78 105K_0402_1% PC48 0.01U_0402_25V7K OVP voltage : LI-3S :13.50V BATT-OVP=1.5V @ BATT-OVP=0.111*BATT+ 2 CV mode PR77 10K_0402_1% PC47 0.01U_0402_25V7K BATT_OVP 12/21 PR211 20K_0402_1% PR75 340K_0402_1% 1 E PC118 0.01U_0402_25V7K CSON PQ44 @ 2SC2411K_SC59 B PC46 0.01U_0402_25V7K C CC=0.6~3.4A VCHLM=0.24V~1.36V IREF=0.972*Icharge IREF=0.5832V~3.3V 2800mAH 3S pack PQ19 SI4800BDY-T1-E3_SO8 6251VDDP DL_CHG CHG BOOT DH_CHG 10UH_SIL1045RA-100PF_4.5A_30% 0_0402_5% CHLIM D D D D 10 11 17 PL3 G S S S UGATE If charge current is small, you can change to 16uH choke VREF 1 39.2K_0402_1% If this area float, Charge voltage is 4.2V/cell Charging Voltage CHGSEL (0x15) CSOP S PC43 10U_1206_25V6M CSON PC34 1U_0805_16V7K PR61 2.2_0603_5% PR62 18_0603_5% PC37 0.1U_0603_25V7K 22 PQ15 RHU002N06_SOT323-3 PACIN G CSON D PC42 10U_1206_25V6M EN 3 23 1 PR74 @ 100K_0402_1% CP mode Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) where Vaclm=0.5535V, Iinput=3.079A where Vaclm=0.6667V, Iinput=4.263A BATT Type VIN ISL6251AHAZ-T_QSOP24 6251VREF PD9 1SS355TE-17_SOD323-2 0.1U_0603_25V7K ACSET ACPRN DTC115EUA_SC70-3 PQ20 PR69 6251VREF 1 ACOFF PQ13 DTC115EUA_SC70-3 BATT+ IREF 0.1U_0402_16V7K Be careful the PR70 IREF voltage!!100K_0402_1% 1 6251DC_IN 24 PR68 143K_0402_1% ACOFF 200K_0402_1% PR141 PR64 100_0402_1% PC40 S PC44 ACON ACON 1SS355TE-17_SOD323-2 DCIN 6251VREF ADP_I 0.01U_0402_25V7K PQ18 RHU002N06_SOT323-3 G D 1 PC31 6251_EN PR63 10K_0402_1% PC39 100P_0402_50V8J PR55 10K_0402_1% EC_ON PC32 VDD PACIN PR66 22K_0402_1% PACIN VIN PD7 FSTCHG EC_ON PU4 1 PC36 6800P_0402_25V7K PC38 PR52 47K_0402_1% PR56 0.01U_0402_25V7K PC26 0.1U_0603_25V7K 1 2 PR59 100K_0402_1% CSON RB715F_SOT323-3 PC35 @ 680P_0402_50V7K 2 PR60 150K_0402_1% 1 0.1U_0402_16V7K PQ14 DTC115EUA_SC70-3 D D D D PQ9 PD17 S S S G 12/21 PC97 0.1U_0603_25V7K 6251VDD PR57 10K_0402_1% PC56 PR58 0_0402_5% PQ43 DTC115EUA_SC70-3 PR210 FSTCHG CSIN 6251DC_IN 1SS355TE-17_SOD323-2 PD16 JUMP_43X118 CSIP PR209 100K_0402_1% PQ12 DTA144EUA_SC70-3 PJ14 VIN PQ16 D RHU002N06_SOT323-3 G S PQ42 TP0610K-T1-E3_SOT23-3 PC29 5600P_0402_25V7K 2 PC28 0.1U_0603_25V7K PR54 200K_0402_1% 2 CHG_B+ PC25 10U_1206_25V6M PQ11 PR53 47K_0402_1% PR51 0.02_2512_1% FDS4435BZ_SO8 PC24 10U_1206_25V6M D D D D S S S G 1 1 S S S G D D D D 2.2U_0603_6.3V6K VIN FDS4435BZ_SO8 P3 FDS4435BZ_SO8 100K_0402_1% P2 PQ10 PC33 0.1U_0603_25V7K A 4 Normal 3S LI-ON Cells Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2006/05/18 Deciphered Date 2007/05/18 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title CHARGER Size Document Number Rev 1.0 CHARGER Date: Friday, February 16, 2007 Sheet D 46 of 52 A B C D PJ15 JUMP_43X118 BST5B PC49 0.1U_0402_16V7K 2 B+ PC50 0.1U_0402_16V7K BST3B B+++ B+++ CHP202UPT_SOT323-3 PD11 PQ23 SI4800BDY-T1-E3_SO8 D D D D G S S S 1 PL6 28 26 24 27 22 DH3 PR95 6.49K_0402_1% 2 4.7UH_PCMC063T-4R7MN_5.5A_20% D D D D PQ25 SI4810BDY-T1-E3_SO8 DL3 @ PC30 100P_0402_50V8J G S S S PR87 0_0603_5% BST3A PR89 499K_0402_1% 11 10U_1206_25V6M 2 PR84 0_0603_5% PR86 200K_0402_1% PR85 200K_0402_1% PR88 499K_0402_1% 1 PC54 0.1U_0402_16V7K 2 17 VCC PRO# TON LDO3 LD05 3HG LX3 +3VALWP + SPOK PC63 220U_6.3V_M 2 PR98 10K_0402_1% REF ILIM3 4.7U_0805_6.3V6K 10 PR97 0_0402_5% 2 PR99 47K_0402_1% PC65 0.22U_0603_16V7K PR203 0_0402_5% 25 12 GND PC67 0.047U_0603_16V7K PC64 0.047U_0603_16V7K @PR94 @PR94 10_0402_5%2 13 LX5 DL5 ILIM5 OUT5 PU6 FB5 BST3 N.C.MAX8734AEEI+_QSOP28 DH3 DL3 SHDN# LX3 ON5 OUT3 ON3 FB3 SKIP# PGOOD 8734_VREF PZD1 PR93 RLZ5.1B_LL34 47K_0402_1% 2 15 19 21 23 PR91 0_0402_5% 20 DH5 V+ BST5 16 VS 18 14 PC66 BST5A 8734_VREF PC59 1U_0805_16V7K PC60 4.7U_0805_6.3V6K DL5 PC61 0.1U_0603_25V7K PC58 1U_0805_25V4Z @ VL PR96 100K_0402_5% +5V Ipeak = 6.66A ~ 10A PQ24 SI4810BDY-T1-E3_SO8 D D D D S S S G 2 PR90 10.5K_0402_1% + PR92 6.81K_0402_1% PC62 150U_V_6.3VM_R18 +5VALWP PL5 4.7UH_PCMC063T-4R7MN_5.5A_20% 2 PR82 4.7_1206_5% PR80 47_0402_5% DH5 LX5 PC55 2200P_0402_50V7K PC57 2 PR79 0_0603_5% PR83 0_0603_5% PR81 4.7_1206_5% B+++ 5HG VL PQ22 SI4800BDY-T1-E3_SO8 D D D D S S S G PC53 10U_1206_25V6M VFB=2V +3.3V Ipeak = 6.66A ~ 10A PC68 1U_0603_6.3V6M MAINPWON 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2005/10/17 Deciphered Date 2006/10/17 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title +5VALWP/+3VALWP Size Document Number Custom Date: Rev 0.1 Sheet Friday, February 16, 2007 D 47 of 52 D D OZ813A_B+ PJ16 +3VALW 4.7U_1206_25V6K + PC88 330U_D2_2.5VY_R15M 2 PC78 4700P_0402_25V7K 1 PC72 330U_D2_2.5VY_R15M PR104 51_0402_1% + OCP==>8A~~9.7A @ Vripple==>40mV C PR202 2.8K_0402_1% @ PC85 2.2U_0603_6.3V6K PR117 51_0402_1% + PC87 220U_6.3V_M OCP==>8A~~9.7A PC92 1.8VS1P B Vripple==>40mV 3300P_0402_25V7K PC95 4700P_0402_25V7K 2 PR124 @2.8K_0402_1% G S S S PQ29 SI4810BDY-T1-E3_SO8 1.8VS1N PC93 @ 0.1U_0402_16V7K D D D D +1.8VP PR120 PR121 100K_0402_1% 280K_0402_1% 2 PQ28 SI4800BDY-T1-E3_SO8 PL9 1.8UH_SIL104R-1R8PF_9.5A_30% PC94 22P_0402_50V8J 4.7U_1206_25V6K PC90 PC89 4.7U_1206_25V6K D D D D G S S S @ 1K_0402_1% DL_1.8V DH_1.8V-2 PR119 0_0603_5% 2 PR118 0_0402_5% +3VALW OZ813A_B+ PC91 PR116 680P_0603_50V7K 4.7_1206_5% 2 2 1SS355TE-17_SOD323-2 PC84 0.1U_0402_16V7K PR122 PC77 22P_0402_50V8J G S S S +5VALW LX1.8V 1.8VS1P PC76 PR105 680P_0603_50V7K 4.7_1206_5% 2 +1.05VSP PD13 BST_1.8V 10 11 12 1.8VS1N 2 PC72=>220UF/15m, Del PC88 1.05VS2N VSET1 CS1N CS1P PGD1 LX1 HDR1 PC79 1U_0805_16V7K PR123 0_0402_5% B+ For discrete PR106 PR107 100K_0402_1% 280K_0402_1% 2 PC75 3300P_0402_25V7K 1.05VS2P 2 1SS355TE-17_SOD323-2 +5VALW DH_1.8V-1 PC86 1000P_0402_50V7K B 1 PD12 OZ813LN_QFN24 1 PR115 150K_0402_1% DL_1.05V BST_1.05V 18 17 16 15 14 13 BST2 LDR2 VDDP GDNP LDR1 BST1 @ SYSON PC74 0.1U_0402_16V7K 24 23 22 21 20 19 25 GNDA VSET2 CS2N CS2P PGD2 LX2 HDR2 ON/SKIP2 VIN VREF TSET VDDA ON/SKIP1 1.8SET PR114 61.9K_0402_1% PL8 1.8UH_SIL104R-1R8PF_9.5A_30% D D D D PC83 0.01U_0402_25V7K 2 1.05VSET VFB=2.75V OZ813A_DREF PR112 100K_0402_1% PR113 75K_0402_1% PC81 0.1U_0402_16V7K @ PC80 0.022U_0402_16V7K PR111 24K_0402_1% PR110 0_0402_5% PR109 1K_0402_1% @ PU7 PC82 1U_0603_6.3V6M C DH_1.05V-2 PQ27 SI4810BDY-T1-E3_SO8 PC71 1000P_0402_50V7K +5VALW PR108 22_0402_1% 2 SUSP# PQ26 SI4800BDY-T1-E3_SO8 LX_1.05V 1.05VSET PC73 0.01U_0402_25V7K PR103 0_0402_5% PC69 G S S S 2 PR101 @ 0_0402_5% @ PR102 DH_1.05V-1 0_0603_5% 4.7U_1206_25V6K PC70 D D D D PR100 1K_0402_1% 1.05VS2N 1.05VS2P JUMP_43X118 A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2005/10/17 2006/10/17 Deciphered Date 1.05VSP/1.8VP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom Date: Rev 0.1 Friday, February 16, 2007 Sheet 48 of 52 PJ17 B+ D @ 1 D JUMP_43X118 PHASE_1.5V 0_0603_5% PR127 PC99 0_0603_5% +5VALW BOOT_1.5V 0.1U_0402_16V7K PR128 0_0603_5% 13 14 15 VCC FCCM PVCC 12 LG 11 PGND 10 ISEN PR129 6269_1.5V 4.7_0603_5% 2 BOOT UG PHASE VIN PGOOD GND PC104 2.2U_0603_6.3V6K LG_1.5V PL4 1.8UH_SIL104R-1R8PF_9.5A_30% PR130 + PR137 4.7_1206_5% D D D D PQ31 SI4810BDY-T1-E3_SO8 OCP==>7A~~8.5A +1.5VSP Vripple==>40mV PC112 220U_6.3V_M C 2 1 ISEN_1.5V PR134 4.42K_0402_1% ISL6269ACRZ-T_QFN16_4X4 PR136 2.26K_0402_1% PC105 680P_0603_50V7K PC103 0.01U_0402_25V7K PR133 57.6K_0402_1% PR135 1.5K_0402_1% 2 +1.5VSP 1 PR132 49.9K_0402_1% PC101 22P_0402_50V8J 1 2 +1.5VSP G S S S COMP EN PC100 0.1U_0402_16V7K @ 0_0402_5% VO 0_0402_5% SUSP# FSET PR131 C FB PC106 2.2U_0603_6.3V6K 1 6269_1.5V PQ30 SI4800BDY-T1-E3_SO8 G S S S PU8 16 17 D D D D 10K_0402_5% PR125 2 PC96 4.7U_1206_25V6K 1 PR126 6269_1.5V PC98 4.7U_1206_25V6K PC102 6800P_0402_25V7K 2 PJ18 JUMP_43X79 @ +5VALW B PC108 1U_0603_6.3V6M 2 PC107 10U_0805_6.3V6M 1 B PU12 +1.25VSP OCP==>3A 1 APL5913-KAC-TRL_SO8 PR140 1.15K_0402_1% PC111 22U_1206_6.3V6M PC109 0.01U_0402_25V7K PC110 0.1U_0402_16V7K @ FB EN POK GND VOUT VOUT 2 0_0402_5% VCNTL VIN VIN SUSP# PR138 PR139 2K_0402_1% A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2005/10/17 2006/10/17 Deciphered Date 1.5VSP/1.25VP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom Date: Rev 0.1 Friday, February 16, 2007 Sheet 49 of 52 +3VS D PJ11 JUMP_43X79 Un-pop 2.5VSP for UMA and DIS sku +5VS PC123 @ 10U_0805_6.3V6M 1 2 1 D PC122 @ 1U_0603_6.3V6M PU9 VCNTL VIN VIN EN POK VOUT VOUT FB +2.5VSP PC126 2.15K_0402_1% APL5913-KAC-TRL_SO8 @ @ PC124 2 PC127 @0.1U_0402_16V7K @ PR150 2 GND 1 SUSP# 0.01U_0402_25V7K 22U_1206_6.3V6M PR149 0_0402_5% @ @ @ PR151 1K_0402_1% C C PJ12 JUMP_43X118 2 1 +1.8V PU10 VCNTL GND NC VREF NC VOUT NC TP PR152 1K_0402_1% 2 1 S PR154 1K_0402_1% G PC131 22U_1206_6.3V6M @ PC132 0.1U_0402_16V7K PC129 1U_0603_6.3V6M +0.9VSP D 1 0_0402_5% SUSP B APL5331KAC-TRL_SO8 PR153 +3VALW VIN 2 PC128 10U_0805_6.3V6M 1 B PQ34 RHU002N06_SOT323-3 PC130 0.1U_0402_16V7K A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2005/10/17 2006/10/17 Deciphered Date +2.5VSP/0.9VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom Date: Rev 0.1 Friday, February 16, 2007 Sheet 50 of 52 +5VS CPU_B+ B+ PR155 33 D2 LX1 28 LX1 CPU CPU_VID3 34 D3 DL1 26 DL1 CPU CPU_VID4 35 D4 PGND1 27 CPU_VID5 36 D5 GND 18 CPU_VID6 37 D6 CSP1 17 TIME CSN1 16 CSN1_CPU CCV FB 12 FB_CPU 11 REF CCI 10 DPRSLPVR DH2 21 DH2_CPU-1 BST2 20 BST2_CPU LX2 22 LX2_CPU DL2 24 DL2 CPU PGND2 23 2 40 PSI PWRGD CLKEN DPRSTP D D D D G S S S PR183 0_0402_5% VSSSENSE VSSSENSE @ 1 PR187 3K_0603_1% PC138 2200P_0402_50V7K PC139 100U_25V_M PC137 0.1U_0603_25V7K 100_0402_1% PC148 4700P_0402_25V7K @ PC149 470P_0603_50V8J CPU_B+ PQ38 SI7686DP-T1-E3_SO8 2.2_0603_5% PR195 DH2_CPU-2 PR197 @ 10_0402_5% C PR184 B PC157 0.1U_0402_16V7K PR196 10K_0402_1% 2 PC158 680P_0603_50V7K DL2 CPU G S S S 1 PL15 0.36H_ETQP4LR36WFC_24A_20% G S S S PQ40 SI4856DY-T1-E3_SO8 D D D D D D D D 8 PR198 4.7_1206_5% POUT PC136 10U_1206_25V6M 1 PR192 100_0402_1% PR189 20K_0402_1% H_PROCHOT# 1 PR194 B 4700P_0402_25V7K @PR193 @ PR193 56_0402_5% NTC PR186 @ 3K_0603_1% PC151 +3VS PR191 @ 10K_0402_5% PR190 0_0402_5% PC150 2 @ MAX8770GTL+_TQFN40 41 TP POUT VCCSENSE PC147 @ 0.022U_0402_16V7K CPU_VCC_SENSE 3.65K_0402_1% 2 GNDS PR180 CSN2 CPU 13 15 0.22U_0603_16V7K PR176 0_0402_5% PR179 @ 3K_0603_1% BSTM2_CPU 0_0402_5% @ PR188 @PR188 14 CSN2 @ PR178 0_0402_5% VR_ON CSP2 VRHOT SHDN CLK_ENABLE# 1 VGATE 38 PR182 @ 2K_0402_1% 2 PR181 10K_0402_1% PR185 0_0402_5% CSP2_CPU PC145 PQ37 SI4856DY-T1-E3_SO8 0_0402_5% H_PSI# +3VS 0.22U_0603_16V7K 39 CCI_CPU PH2 NTC 10KB_0603_5%_ERTJ1VR103J H_DPRSTP# 0_0402_5% PC146 3.48K_0402_1% PR172 1 PR199 2.1K_0402_1% PM_DPRSLPVR 499_0402_1% PC144 CSP1 CPU +CPU_CORE CPU_VID2 +CPU_CORE PL14 0.36H_ETQP4LR36WFC_24A_20% 1 PQ36 SI4856DY-T1-E3_SO8 10_0402_5% DH1 CPU-1 29 PR171 DH1 PC156 2200P_0402_50V7K D1 D PC155 0.1U_0603_25V7K 32 PC154 10U_1206_25V6M 1 PC153 10U_1206_25V6M 2 PC152 10U_1206_25V6M CPU_VID1 0.22U_0603_16V7K PC142 BSTM1_CPU 0_0603_5% PR162 PC143 680P_0603_50V7K 2.1K_0402_1% PR168 BST1_CPU PR166 4.7_1206_5% 30 BST1 D0 31 71.5K_0402_1% PC135 10U_1206_25V6M 1 C PR177 47P_0402_50V8J PR175 CPU_VID0 PR173 PR174 DL1 CPU PR170 0_0402_5% TON D D D D PR169 0_0402_5% VDD THRM G S S S PR167 0_0402_5% 25 Vcc PR165 0_0402_5% + 2.2_0603_5% PR159 2DH1_CPU-24 0_0603_5% PR164 0_0402_5% 19 0.22U_0603_16V7K PR163 0_0402_5% VCC PQ35 SI7686DP-T1-E3_SO8 PU11 NTC 100K_0402_5% PR160 PR161 0_0402_5% PC141 1U_0603_6.3V6M 200K_0402_1% PR157 2 PR158 13K_0402_5% 2 PC140 2.2U_0603_6.3V6K PC134 10U_1206_25V6M 0_1206_5% PR156 10_0402_5% D PL13 HCB4532KF-800T90_1812 PC133 0.01U_0402_25V7K 5VS12 PR200 3.48K_0402_1% NTC PH3 10KB_0603_5%_ERTJ1VR103J PQ39 SI4856DY-T1-E3_SO8 PR201 0_0402_5% A 2005/10/17 Deciphered Date 2006/10/17 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 0.22U_0603_16V7K A Compal Electronics, Inc Compal Secret Data Security Classification Issued Date PC159 Title +CPU_CORE Size Document Number Custom Date: Rev 0.1 Friday, February 16, 2007 Sheet 51 of 52 Pre EVT page Reason for change Modify list P50 For H/W 0.9V sequence deamd Delete PQ34 Modify Bead to Jump for costdown PL1,PL2,PL4,PL7,PL10 Modify 10UH/X6S to 10UH/X5R for common source PC53,PC57,PC96,PC116,PC134,PC135,PC136,PC152,PC153,PC154 Modify CH751H to RB751V for common source PD10 Keep Batt_OVP to 1.5V Change PR78 form 150K to 105K Take out PC148 & PC150 form VTT tool test Delete PC148 &PC150 Adjust PR183 to 39.2K for loadline PR183 Modify CPU_High side form SI7840 to SI7686 for vender shortage PQ35,PQ38 Modify PosCAP to Alu CAP for cost PC63,PC87,PC99 DFX footprint issue, Modify RLS4148_LLDS2 to LL34 PD2,PD4 Add skip mode function form skip pin of 3/5V IC PR203 ADD Battery in function in page 45 PR204,PR205,PR206,PR207,PR208,PC51,PC52,PQ41 Defence charger IC leakage current in page 46 PR57,PR209,PR210,PR211,PR212,PC118,PC97,PC56,PD16,PD17,PQ42,PQ43,PQ44 ADD Battery in and DC-IN Bead PL1,PL2 D D DVT 95/12/28 C C PC30 ADD 100PF in SPOK PIN for noise but unpop B B ADD CPU high side gate resister 2.2 OHM for EMI demand PR159,PR195 96/01/03 Change PR137 to L/F PR137 Change PR95 form 6.81K to 6.49K for power loss PR95 Disable battery in function, EC control PR204,PR205,PR206,PR207,PR208,PC51,PC52,PQ41 Modify 0.01U_0402 to 1000P_0402 PC1,PC4 Remove PR1 & PD1 for cost PR1,PD1 Modify AO4407 to FDS4435 for UMA cost PQ10,PQ11,PQ9 Modify RB751V to 1SS355 for cost PD12,PD13,PD14,PD15,PD10 Remove 2.5VSP function for UMA PR149,PR150,PR151,PC122,PC123,PC124,PC126,PC127,PU9 Change 1.05VSP High/Low side MOS for cost PQ26,PQ27 Change 0.9UH to 1.8uH for 1.05vsp cost PL8 Change PC72 330U/R9 to 330U/R15 and del PC88 PC72,PC88 A A Add PR207 280K_0402 and delete PR202 PR207,PR202 Modify PC139 for 100uH at 3000hurs PC139 Modify charge Low side gate to SI4800BDY PQ19 2005/10/17 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2006/10/17 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Power PIR Size Document Number Custom Date: Rev 0.1 Friday, February 16, 2007 Sheet 52 of 52 page Reason for change 96/01/03 DVT D 96/01/19 DVT-2 96/01/19 PVT Modify list Disable battery in function, EC control PR204,PR205,PR206,PR207,PR208,PC51,PC52,PQ41 Modify 0.01U_0402 to 1000P_0402 for common design PC1,PC4 Remove PR1 & PD1 for common design PR1,PD1 Modify AO4407 to FDS4435 for UMA PQ10,PQ11,PQ9 Modify RB751V to 1SS355 for common design PD12,PD13,PD14,PD15,PD10 D Remove 2.5VSP function for UMA sku PR149,PR150,PR151,PC122,PC123,PC124,PC126,PU9 Change 1.05VSP High/Low side MOS for rating PQ26(SI4800),PQ27(Si4810) Change 0.9UH to 1.8uH for 1.05vsp rating PL8 Change PC72 C form 330U/R9 to 330U/R15 and del PC88 for rating PC72,PC88 Add PR107 280K_0402 and delete PR202 for 1.05VSP OCP PR107,PR202 Modify PC75 form 4700P to 3300P for 1.05VSP OCP PC75 Modify PC139 for 100uH at 3000hurs PC139 Modify charge Low MOS gate to SI4800BDY PQ19 Disable CC-CV overshoot function , need verify it PQ44 0.9V sequence for H/W deamd Change CPU low side mos to SI4856 Add PQ34 PQ36,PQ37,PQ39,PQ40 Chage 1.5V/1.25V dual to single and LDO portion DEL PR141,PR143,PR144,PR145,PR146,PR148,PC110,PC113,PC114,PC115,PC116,PC117,PC120,PC121,PL11,PL12, PQ32,PQ33,PD14,PD15 ADD PR125,PR126,PR136,PU12,PL4 C Modify PR128,PR129,PR130,PR131,PR132,PR133,PR134,PR135,PR136,PR137,PR138,PR139,PR140 PC96,PC98,PC99,PC101,PC102,PC103,PC104,PC105,PC106,PC107,PC108,PC109,PC111,PC112 PU8 Combine PU5 LM358 and PU3 LM393 Del PU5,ADD PD8 Change PD5 form RB751 to RLS4148 for cost PD5 Change 0.1U_0603 to 0.1U_0402 for cost PC49,PC50,PC74,PC84,PC81 Remove PC147 for cost PC147 Change PC128 form 10U_1206 to 10U_0805 for cost PC128 B B 96/02/16 PVT Modify CPU OTP 85 degree C to 89 degree C for thermal request PR42_78.7K, PR38_10K A A 2005/10/17 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2006/10/17 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Power PIR Size Document Number Custom Date: Rev 0.1 Friday, February 16, 2007 Sheet 52 of 52 ... 0_ 0 402 _5% 0_ 0 402 _5% 0_ 0 402 _5% 0_ 0 402 _5% 833 @ C2 80 0 .33 U _06 03_ 16V4Z C279 0. 01U _04 02_16V7K 1 833 @ R 234 56.2 _06 03_ 1% 833 @ R 233 56.2 _06 03_ 1% L21 1U _06 03_ 10V4Z 833 @ 12/22 Change from 10u_1 206 to 10u _08 05 IEEE 139 4TPA+/-... VCC_SM _33 VCC_SM _34 VCC_SM _35 VCC_SM _36 VCC GFX NCTF AU32 AU 33 AU35 AV 33 AW 33 AW35 AY35 BA32 BA 33 BA35 BB 33 BC32 BC 33 BC35 BD32 BD35 BE32 BE 33 BE35 BF 33 BF34 BG32 BG 33 BG35 BH32 BH34 BH35 BJ32 BJ 33. .. AK35 AK36 AK37 AD 33 AJ36 AM35 AL 33 AL35 AA 33 AA35 AA36 AP35 AP36 AR35 AR36 Y32 Y 33 Y35 Y36 Y37 T 30 T34 T35 U29 U31 U32 U 33 U35 U36 V32 V 33 V36 V37 VSS NCTF AW45 BC39 BE39 BD17 BD4 AW8 AT6 +1 .05 VS