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A B C D E ZZZ 1 PCB Compal Confidential 2 NDWG0 Schematics Document AMD S1g3/ RS880M/ SB710 2009 / 09 / 22 LA-5991P 3 Rev:0.1 4 Compal Electronics, Inc Compal Secret Data Security Classification 2009/09/11 Issued Date Deciphered Date 2010/03/12 Title SCHEMATIC,MB A5991 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom 401830 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Tuesday, October 13, 2009 Rev A Sheet E of 47 Compal confidential Project Code: NDWG0/H0 File Name : LA-5991P Clock Generator SLG8SP626 ICS9LPRS488BKLFT Thermal Sensor ADM1032ARM page D AMD S1g3 CPU 638P PGA DDRII 533/667/800 DDRII-SO-DIMM X2 page 10,11 page 6,7,8,9 Dual Channel page 17 D H_A#(3 31) H_D#(0 63) HT 16x16 1000MHZ CRT ATI-RS880M page 24 465 BGA LCD CONN page 12,13,14,15,16 page 25 A-Link Express x PCIE PCIE X1 USB 2.0 C C Mini card WLAN ATI-SB710 10/100 LAN AR8114 / AR8132 page 31 Camera USB conn X2 549 BGA page 26 HD Audio HDA Codec ALC272 page 18,19,20,21,22 page 39 CardReader RTS5159 AMP & Audio Jack TPA6017 page 40 MDC Conn page 41 RJ45 CONN HeadPhone Out page 27 SATA0 HDD Conn page 23 LPC BUS MIC In B B SATA2 ODD Conn page 23 ENE KB926 Ver:D3 Power On/Off CKT / LID switch / Power OK CKT page 28 page 37 Second HDD/ODD DC/DC Interface CKT CIR/LED RTC CKT page 41 page 38 page 18 Int KBD page 29 Touch Pad CONN page Power Circuit DC/DC 29 SPI BIOS SATA1 HDD Conn SATA3 ODD Conn page 30 page 42~48 A A 2009/09/11 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/03/12 Deciphered Date Title SCHEMATIC,MB A5991 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom 401830 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev A Tuesday, October 13, 2009 Sheet of 47 SIGNAL STATE Voltage Rails D SLP_S1# SLP_S3# SLP_S4# SLP_S5# Full ON VIN Adapter power supply (19V) B+ AC or battery power rail for power circuit +VALW +V +VS Clock HIGH HIGH HIGH HIGH ON ON ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF D +CPU_CORE Core voltage for CPU +0.9V 0.9V switched power rail for DDR terminator +1.2V_HT 1.2V switched power rail ON OFF OFF +1.5VS 1.5V switched power rail ON +1.8V 1.8V power rail for DDR ON +1.8VS 1.8V switched power rail +2.5VS 2.5V switched power rail ON OFF OFF +3VALW 3.3V always on power rail ON ON ON* +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON OFF Board ID / SKU ID Table for AD channel ON* Vcc Ra/Rc/Re OFF Board ID C 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V C BOARD ID Table Board ID External PCI Devices Device IDSEL# REQ#/GNT# Interrupts PCB Revision No Support VaryBright Support VaryBright BTO Option Table BTO Item 10/100 Lan GIGA Lan 17" ID 15" ID Support VaryBright BOM Structure 8114@ 8132@ 17@ 15@ VARY@ B B EC SM Bus1 address Device Address Smart Battery 0001 011X b Device ADM1032 SB600 SM Bus address A EC SM Bus2 address Device Address Clock Generator 1101 001Xb DDR DIMM0 1001 000Xb DDR DIMM2 1001 010Xb PROJECT ID Table Address SKU ID 1001 100X b SB600 SM Bus address Device SKU NCWG0 NAL00 NCWH0 Address New Card A Wireless Lan 2009/09/11 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/03/12 Deciphered Date Title SCHEMATIC,MB A5991 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom 401830 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev A Tuesday, October 13, 2009 Sheet of 47 DIMMA DDR_A_CLK[1 2] D D CPU S1G1 SOCKET 200MHZ H_CLKI[1:0] DIMMB CPU CLK DDR_B_CLK[1 2] Host Bus H_CLKO[1:0] C C SBLINK_CLK 100MHZ NBSRC_CLK 14.31818MHz ATI NB RS780MN 100MHZ EXTERNAL CLK GEN SLG8SP626 / ICS9LPRS488 HTREFCLK 66MHZ NB_OSC 14.318MHZ CLK_14M_SB B B 14.318MHZ SB_OSCIN CLK_PCIE_LAN 100MHZ 100MHZ CLK_PCIE_MINI 14.318MHZ ATI SB SB700 SBSRC_CLKP 100MHZ CLK_PCI_LPC CLK_48M_USB EC ENE KB926D3 33MHZ 48MHZ RTC Mini PCI Socket Mini card A SATA 32.768K Hz LAN Atheros AR8114/AR8132 32.768K Hz 25M Hz A 2009/09/11 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/03/12 Deciphered Date Title SCHEMATIC,MB A5991 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom 401830 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev A Wednesday, October 14, 2009 Sheet of 47 AMD CPU S1G1 socket +2.5VS PU21 APL5915KAI AC ADAPTOR 19V 65W D BATTERY 11.1V 2.2Ah/6-cell PU12 ISL6264CRZ-T VIN +CPU_CORE BATT+ +1.2VALW U46 AO4430 +1.2V_HT VDDA 2.5V 250 mA VDD 0.9V 0.95V 24.5 A VDDIO 1.8V 3.6 A VTT 0.9V 1.75 A VLDT 1.2V 500 mA D +NB_CORE PU17 BATTERY CHARGER BQ24751ARHDR PU18 ISL6228HRTZ-T B+ DDRII SODIMMX2 +1.2VALW +1.8V +0.9V PU22 APL5331KAC VDD_MEM 1.8V 6.08 A VTT_MEM 0.9V 500 mA NB RS780MN VDDC +1.2VALW +1.8V PU19 TPS51117RGYR +3VS 1.0-1.1V 680 mA PLLVDD 1.1V VDDPCIE C 2.5 A +3VALW PU16 ISL6237IRZ-T VDDA18PCIE +3.3 350mA +5VS SB +1.2V_HT 15 mA 3.3V 110 mA 60 mA SB700 VDD 510mA S5_1.2V 113 mA USB_PHY_1.2V 197 mA AVDDCK_1.2V FAN Control APL5607 Realtek RTS5159 EC ENE KB926 +3.3VS 300mA +5VS 500mA +3.3VALW 30mA +3.3VS 3mA LAN Atheros AR8114 +3.3VALW 201mA Mini Card ICS9LPRS488B +1.5VS 500mA +3.3VS 1A +3.3VALW 330mA Audio Codec ALC272 +5V 25mA +5V 45mA +5V 3A +3.3VS 25mA +3.3V PCIE_PVDD 43 mA PCIE_VDDR 600 mA AVDD_SATA 567 mA PLLVDD_SATA_1 93 mA S5_3.3V 32 mA AVDDC 17 mA 658 mA 3.3V VDDQ +1.2V 131 mA VDD33_18 71 mA AVDDCK_3.3V 47 mA XTLVDD_SATA RTC Bettary Audio AMP TPA6017A2 62 mA AVDD TX/RX +3.3V 400mA mA VBAT 3V SATA Compal Electronics, Inc Compal Secret Data 2009/09/11 Issued Date 2010/03/12 Deciphered Date Title SCHEMATIC,MB A5991 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom 401830 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev A Wednesday, October 14, 2009 Sheet B 1.2V CKVDD_1.2 Date: 300 mA AVDD VDD33 Security Classification B+ 300mA 10 mA VDDLTP18 A LCD panel 15.6" 120 mA VDDLT18 +3VS +5V Dual 1.5A 700 mA VDD18 +USB_VCCA USB X2 20 mA 1.8V VDDA18PCIEPLL +3VS U7 AO4468 20 mA VDDA18HTPLL +1.5VS +5VS 20 mA PLLVDD18 +5VALW U4 TPS2061DRG4 mA AVDDDI U41 AO4468 C 400 mA AVDDQ +1.8VS PU23 APL5915KAI B 680 mA 1.2V VDDHTTX U37 AO4430 65 mA VDDHTRX +1.2VALW +1.8V 10 A VDD_HT PU20 +1.1VS APL5912 KAC-TRL of 47 A D D H_CADIP[0 15] H_CADIN[0 15] H_CADIP[0 15] H_CADOP[0 15] H_CADIN[0 15] H_CADON[0 15] +1.2V_HT H_CADOP[0 15] H_CADON[0 15] Change as 10U for Tigris +1.2V_HT JCPU1A L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1 H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15 FAN1 Conn +5VS C92 U1 +VCC_FAN1 EN_DFAN1 R733 D13 1SS355_SOD323-2 @ R247 0_0603_5% @ 0_0402_5% C760 EN VIN VOUT VSET GND GND GND GND +3VS 0.01U_0402_25V4Z @D4 @ D4 BAS16_SOT23-3 C97 10U_0805_10V4Z APL5607KI-TRG_SO8 @ Reserve when PVT for cos down +5VS 10U_0805_10V4Z H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1 N1 P1 P3 P4 AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3 L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1 L0_CADOUT_H0 L0_CADOUT_L0 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15 R37 10K_0402_5% 40mil JP12 +VCC_FAN1 FAN_SPEED1 C91 1000P_0402_50V7K CONN@ ACES_85205-03001 LDO FAN +3VS L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CLKOUT_H1 L0_CLKOUT_L1 Y1 W1 Y4 Y3 H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1 L0_CTLOUT_H0 L0_CTLOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1 R2 R3 T5 R5 H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1 R40 10K_0402_5% @ FANPWM JP38 +VCC_FAN1 FANPWN PWM FAN Athlon 64 S1 Processor Socket +1.2V_HT CONN@ ACES_85205-0400 6090022100G_B B C C96 1000P_0402_50V7K J3 J2 J5 K5 10U_0805_10V4Z H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1 C C84 L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15 AE2 AE3 AE4 AE5 E3 E2 E1 F1 G3 G2 G1 H1 J1 K1 L3 L2 L1 M1 N3 N2 E5 F5 F3 F4 G5 H5 H3 H4 K3 K4 L5 M5 M3 M4 N5 P5 VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3 VLDT_A0 VLDT_A1 VLDT_A2 VLDT_A3 H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15 HT LINK D1 D2 D3 D4 VLDT=1500mA for HT3 B VLDT CAP 250 mil C86 10U_0805_10V4Z C82 10U_0805_10V4Z Change as 10U for Tigris C90 0.22U_0603_16V4Z C89 0.22U_0603_16V4Z C83 180P_0402_50V8J C85 180P_0402_50V8J Near CPU Socket A A 2009/09/11 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/03/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC SCHEMATIC,MB A5991 Rev A 401830 Date: Sheet Tuesday, October 13, 2009 of 47 A B C D E PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH Processor DDR2 Memory Interface DDRA_CLK0 DDRA_CLK0# C104 1.5P_0402_50V8C DDRA_CLK1 +1.8V R4 1K_0402_1% 2 C102 1.5P_0402_50V8C DDRB_CLK0 C100 1000P_0402_25V8J R5 1K_0402_1% C16 0.1U_0402_16V4Z +MCH_REF DDRA_CLK1# DDRB_CLK0# C105 1.5P_0402_50V8C DDRB_CLK1 DDRB_CLK1# C17 1.5P_0402_50V8C +0.9V +0.9V JCPU1B Place them close to CPU within 1" R6 1 R7 +1.8V DDRA_ODT0 DDRA_ODT1 DDRA_SCS0# DDRA_SCS1# DDRA_CKE0 DDRA_CKE1 DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1# DDRA_SMA[15 0] DDRA_SBS0# DDRA_SBS1# DDRA_SBS2# DDRA_SRAS# DDRA_SCAS# DDRA_SWE# 39.2_0402_1% 2 39.2_0402_1% DDRA_ODT0 DDRA_ODT1 DDRA_SCS0# DDRA_SCS1# DDRA_CKE0 DDRA_CKE1 D10 C10 B10 AD10 VTT1 VTT2 VTT3 VTT4 AF10 AE10 MEMZP MEMZN MEM:CMD/CTRL/CLK VTT5 VTT6 VTT7 VTT8 VTT9 H16 RSVD_M1 T19 V22 U21 V19 MA0_ODT0 MA0_ODT1 MA1_ODT0 MA1_ODT1 T20 U19 U20 V20 MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1 J22 J20 MA_CKE0 MA_CKE1 W10 AC10 AB10 AA10 A10 VTT_SENSE Y10 MEMVREF W17 @ PAD T2 +MCH_REF @ RSVD_M2 B18 MB0_ODT0 MB0_ODT1 MB1_ODT0 W26 W23 Y26 DDRB_ODT0 DDRB_ODT1 MB0_CS_L0 MB0_CS_L1 MB1_CS_L0 V26 W25 U22 DDRB_SCS0# DDRB_SCS1# MB_CKE0 MB_CKE1 J25 H26 DDRB_CKE0 DDRB_CKE1 DDRB_CLK0 DDRB_CLK0# DDRB_CLK1 DDRB_CLK1# PAD N19 N20 E16 F16 Y16 AA16 P19 P20 MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1 MA_CLK_H2 MA_CLK_L2 MA_CLK_H3 MA_CLK_L3 MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1 MB_CLK_H2 MB_CLK_L2 MB_CLK_H3 MB_CLK_L3 P22 R22 A17 A18 AF18 AF17 R26 R25 DDRA_SMA0 DDRA_SMA1 DDRA_SMA2 DDRA_SMA3 DDRA_SMA4 DDRA_SMA5 DDRA_SMA6 DDRA_SMA7 DDRA_SMA8 DDRA_SMA9 DDRA_SMA10 DDRA_SMA11 DDRA_SMA12 DDRA_SMA13 DDRA_SMA14 DDRA_SMA15 N21 M20 N22 M19 M22 L20 M24 L21 L19 K22 R21 L22 K20 V24 K24 K19 MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15 MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15 P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24 DDRB_SMA0 DDRB_SMA1 DDRB_SMA2 DDRB_SMA3 DDRB_SMA4 DDRB_SMA5 DDRB_SMA6 DDRB_SMA7 DDRB_SMA8 DDRB_SMA9 DDRB_SMA10 DDRB_SMA11 DDRB_SMA12 DDRB_SMA13 DDRB_SMA14 DDRB_SMA15 DDRA_SBS0# DDRA_SBS1# DDRA_SBS2# R20 R23 J21 MA_BANK0 MA_BANK1 MA_BANK2 MB_BANK0 MB_BANK1 MB_BANK2 R24 U26 J26 DDRB_SBS0# DDRB_SBS1# DDRB_SBS2# DDRA_SRAS# DDRA_SCAS# DDRA_SWE# R19 T22 T24 MA_RAS_L MA_CAS_L MA_WE_L MB_RAS_L MB_CAS_L MB_WE_L U25 U24 U23 DDRB_SRAS# DDRB_SCAS# DDRB_SWE# DDRA_CLK0 DDRA_CLK0# DDRA_CLK1 DDRA_CLK1# JCPU1C DDRB_SDQ[63 0] T17 DDRB_ODT0 DDRB_ODT1 DDRB_SCS0# DDRB_SCS1# DDRB_CKE0 DDRB_CKE1 DDRB_CLK0 DDRB_CLK0# DDRB_CLK1 DDRB_CLK1# DDRB_SMA[15 0] DDRB_SBS0# DDRB_SBS1# DDRB_SBS2# DDRB_SRAS# DDRB_SCAS# DDRB_SWE# DDRB_SDM[7 0] DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS2 DDRB_SDQS2# DDRB_SDQS3 DDRB_SDQS3# DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS5 DDRB_SDQS5# DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS7 DDRB_SDQS7# MEM:DATA DDRB_SDQ0 DDRB_SDQ1 DDRB_SDQ2 DDRB_SDQ3 DDRB_SDQ4 DDRB_SDQ5 DDRB_SDQ6 DDRB_SDQ7 DDRB_SDQ8 DDRB_SDQ9 DDRB_SDQ10 DDRB_SDQ11 DDRB_SDQ12 DDRB_SDQ13 DDRB_SDQ14 DDRB_SDQ15 DDRB_SDQ16 DDRB_SDQ17 DDRB_SDQ18 DDRB_SDQ19 DDRB_SDQ20 DDRB_SDQ21 DDRB_SDQ22 DDRB_SDQ23 DDRB_SDQ24 DDRB_SDQ25 DDRB_SDQ26 DDRB_SDQ27 DDRB_SDQ28 DDRB_SDQ29 DDRB_SDQ30 DDRB_SDQ31 DDRB_SDQ32 DDRB_SDQ33 DDRB_SDQ34 DDRB_SDQ35 DDRB_SDQ36 DDRB_SDQ37 DDRB_SDQ38 DDRB_SDQ39 DDRB_SDQ40 DDRB_SDQ41 DDRB_SDQ42 DDRB_SDQ43 DDRB_SDQ44 DDRB_SDQ45 DDRB_SDQ46 DDRB_SDQ47 DDRB_SDQ48 DDRB_SDQ49 DDRB_SDQ50 DDRB_SDQ51 DDRB_SDQ52 DDRB_SDQ53 DDRB_SDQ54 DDRB_SDQ55 DDRB_SDQ56 DDRB_SDQ57 DDRB_SDQ58 DDRB_SDQ59 DDRB_SDQ60 DDRB_SDQ61 DDRB_SDQ62 DDRB_SDQ63 C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11 Y11 AE14 AF14 AF11 AD11 MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63 DDRB_SDM0 DDRB_SDM1 DDRB_SDM2 DDRB_SDM3 DDRB_SDM4 DDRB_SDM5 DDRB_SDM6 DDRB_SDM7 A12 B16 A22 E25 AB26 AE22 AC16 AD12 MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7 DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQS1 DDRB_SDQS1# DDRB_SDQS2 DDRB_SDQS2# DDRB_SDQS3 DDRB_SDQS3# DDRB_SDQS4 DDRB_SDQS4# DDRB_SDQS5 DDRB_SDQS5# DDRB_SDQS6 DDRB_SDQS6# DDRB_SDQS7 DDRB_SDQS7# C12 B12 D16 C16 A24 A23 F26 E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12 MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7 Athlon 64 S1 Processor Socket MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63 G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12 DDRA_SDQ0 DDRA_SDQ1 DDRA_SDQ2 DDRA_SDQ3 DDRA_SDQ4 DDRA_SDQ5 DDRA_SDQ6 DDRA_SDQ7 DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ12 DDRA_SDQ13 DDRA_SDQ14 DDRA_SDQ15 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ20 DDRA_SDQ21 DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDQ26 DDRA_SDQ27 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQ30 DDRA_SDQ31 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ36 DDRA_SDQ37 DDRA_SDQ38 DDRA_SDQ39 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQ46 DDRA_SDQ47 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ52 DDRA_SDQ53 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDQ58 DDRA_SDQ59 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQ62 DDRA_SDQ63 MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7 E12 C15 E19 F24 AC24 Y19 AB16 Y13 DDRA_SDM0 DDRA_SDM1 DDRA_SDM2 DDRA_SDM3 DDRA_SDM4 DDRA_SDM5 DDRA_SDM6 DDRA_SDM7 MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7 G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13 DDRA_SDQS0 DDRA_SDQS0# DDRA_SDQS1 DDRA_SDQS1# DDRA_SDQS2 DDRA_SDQS2# DDRA_SDQS3 DDRA_SDQS3# DDRA_SDQS4 DDRA_SDQS4# DDRA_SDQS5 DDRA_SDQS5# DDRA_SDQS6 DDRA_SDQS6# DDRA_SDQS7 DDRA_SDQS7# DDRA_SDQ[63 0] DDRA_SDM[7 0] DDRA_SDQS0 DDRA_SDQS0# DDRA_SDQS1 DDRA_SDQS1# DDRA_SDQS2 DDRA_SDQS2# DDRA_SDQS3 DDRA_SDQS3# DDRA_SDQS4 DDRA_SDQS4# DDRA_SDQS5 DDRA_SDQS5# DDRA_SDQS6 DDRA_SDQS6# DDRA_SDQS7 DDRA_SDQS7# Athlon 64 S1 Processor Socket 6090022100G_B 1 Compal Secret Data Security Classification 2009/09/11 Issued Date 2010/03/12 Deciphered Date Title Compal Electronics, Inc SCHEMATIC,MB A5991 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D 401830 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Rev A Sheet Tuesday, October 13, 2009 E of 47 +2.5VDDA L4 FCM2012CF-800T06_2P +2.5VS 3300P_0402_50V7K C113 + 2 +1.8V R18 C22 0.22U_0603_16V4Z R8 1 10K_0402_5% 300_0402_5% 150U_D2_6.3VM C118 B change to polymer C116 4.7U_0805_10V4Z CPU_THERMTRIP#_R CPU_CLKIN_SC_P CPU_CLKIN_SC_N 3900P_0402_50V7K 1 C109 R22 169_0402_1% CPU_LDT_REQ# CLK_CPU_BCLK# C23 3900P_0402_50V7K +1.8VS +1.2V_HT LDT_RST# C721 0.01U_0402_25V4Z @ +CPU_CORE_1 C +1.8VS R346 300_0402_5% +1.8V C720 0.01U_0402_25V4Z @ SIC SID ALERT_L R6 P6 HT_REF0 HT_REF1 LDT_STOP# W7 W8 THERMDC_CPU THERMDA_CPU PAD PAD CPU_VDD1_FB_H CPU_VDD1_FB_L CPU_VDD1_FB_H Y6 CPU_VDD1_FB_L AB6 VDD1_FB_H VDD1_FB_L VDDNB_FB_H VDDNB_FB_L H6 G6 CPU_VDDNB_FB_H CPU_VDDNB_FB_L DBREQ_L E10 CPU_DBREQ# TDO AE9 CPU_TDO PAD CPU_TEST23 AD7 TEST23 T8 PAD T12 PAD CPU_TEST18 CPU_TEST19 H10 G9 TEST18 TEST19 PAD PAD PAD PAD PAD PAD T22 PAD TEST25_L CPU_TEST21 CPU_TEST20 CPU_TEST24 CPU_TEST22 CPU_TEST12 CPU_TEST27 0_0402_5% CPU_TEST6 E9 E8 AB8 AF7 AE7 AE8 AC8 AF8 TEST25_H TEST25_L TEST21 TEST20 TEST24 TEST22 TEST12 TEST27 C2 AA6 TEST9 TEST6 A3 A5 B3 B5 C1 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 R20 H_PROCHOT# +1.8V B CPU_VDDNB_FB_H CPU_VDDNB_FB_L H_PROCHOT_R# TEST28_H TEST28_L J7 H8 CPU_TEST28_H_PLLCHRZ_P CPU_TEST28_L_PLLCHRZ_N TEST17 TEST16 TEST15 TEST14 D7 E7 F7 C7 CPU_TEST17 CPU_TEST16 CPU_TEST15 CPU_TEST14 TEST7 TEST10 C3 K8 CPU_TEST7 CPU_TEST10 TEST8 C4 CPU_TEST8 TEST29_H TEST29_L C9 C8 PAD PAD PAD PAD PAD PAD T20 T19 T11 T21 PAD PAD T13 T14 PAD T28 R201 10_0402_5% 2 R202 10_0402_5% CPU_VDDNB_FB_H CPU_VDDNB_FB_L +1.2V_HT T9 T10 C CPU_TEST10 @ 0_0402_5% +1.8V CPU_SVC R152 RSVD10 RSVD9 RSVD8 RSVD7 RSVD6 CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N PAD PAD R151 CPU_SVD T18 T16 R153 H18 H19 AA7 D5 C5 CPU_TEST21 6090022100G_B CPU_TEST23 1K_0402_5% 1K_0402_5% R154 R155 300_0402_5% 300_0402_5% R160 R162 300_0402_5% 300_0402_5% B R216 2.2K_0402_5% CPU_SID CPU_TEST18 CPU_TEST19 CPU_TEST22 R220 R221 R222 R217 CPU_SIC FDV301N, the Vgs is: = 0.65V Typ = 0.85V Max = 1.5V C119 CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST# CPU_TDO U3 THERMDA_CPU C120 THERMDC_CPU 3300P_0402_50V7K C449 3300p for tigris 2200p change to 1000p for ADT7421 SCLK EC_SMB_CK2 D+ SDATA EC_SMB_DA2 D- ALERT# GND VDD THERM# @ @ @ JP3 11 13 15 17 19 21 23 @ EC_SMB_CK2 EC_SMB_DA2 NOTE: HDT TERMINATION IS REQUIRED FOR REV Ax SILICON ONLY 10 12 14 16 18 20 22 24 26 R25 @ 0_0402_5% +3VS 0.1U_0402_16V4Z +3VS @ 300_0402_5% @ 300_0402_5% @ 300_0402_5% +1.8V U51 HDT_RST# B A Y 2.2K_0402_5% 220_0402_5% R33 220_0402_5% R38 220_0402_5% R34 220_0402_5% R35 300_0402_5% R36 +1.8V @ SAMTEC_ASP-68200-07 LDT_RST# SB_PWRGD @ NC7SZ08P5X_NL_SC70-5 A ADM1032ARMZ_MSOP8 Address:100_1101 2009/09/11 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/03/12 Deciphered Date Title SCHEMATIC,MB A5991 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev A 401830 Date: D +CPU_CORE_NB T5 T6 C719 0.01U_0402_25V4Z @ +1.8V A R52 CPU_TEST20 H_THERMTRIP# 300_0402_5% CPU_TEST24 R213 @ 510_0402_5% MAINPWON R211 510_0402_5% R342 300_0402_5% THERMDC THERMDA W9 Y9 DBRDY TMS TCK TRST_L TDI @ 0_0402_5% 0_0402_5% 0_0402_5% VDDIO_FB_H VDDIO_FB_L G10 AA9 AC9 AD9 AF9 +1.8V TEST25_H CPU_THERMTRIP#_R H_PROCHOT# R218 300_0402_5% AF6 AC7 AA8 VDD0_FB_H VDD0_FB_L R214 R212 510_0402_5% THERMTRIP_L PROCHOT_L MEMHOT_L CPU_SVC CPU_SVD F6 E6 TEST25_H TEST25_L +1.8V +1.8VS AF4 AF5 AE6 CPU_SVC CPU_SVD CPU_VDD0_FB_H CPU_VDD0_FB_L T4 T24 T26 T25 T7 T27 R212, R211 pop for Tigris R210 @ 510_0402_5% LDT_STOP# CPU_SIC CPU_SID 10K_0402_5% R209 1 RESET_L PWROK LDTSTOP_L LDTREQ_L A6 A4 R17 MMBT3904_NL_SOT23-3 M11 W18 CPU_VDD0_FB_H CPU_VDD0_FB_L T3 H_PWRGD H_PWRGD B7 A7 F10 C6 CPU_DBRDY CPU_TMS CPU_TCK CPU_TRST# CPU_TDI R206 10K_0402_5% 2CPU_VDD1_FB_H 2CPU_VDD1_FB_L SVC SVD LDT_RST# H_PWRGD LDT_STOP# CPU_LDT_REQ# 44.2_0402_1% CPU_HTREF0 44.2_0402_1% CPU_HTREF1 1 CLKIN_H CLKIN_L R2 P LDT_RST# +CPU_CORE_0 R204 10_0402_5% 2CPU_VDD0_FB_H 2CPU_VDD0_FB_L R205 10_0402_5% R16 R61 A9 A8 KEY1 KEY2 G R334 300_0402_5% VDDA1 VDDA2 C CLK_CPU_BCLK F8 F9 Q3 E JCPU1D D Sheet Tuesday, October 13, 2009 of 47 VDD0 = 18A VDD(+CPU_CORE) decoupling +CPU_CORE_0 + + C26 330U_X_2VM_R6M + C32 330U_X_2VM_R6M + C45 @ 330U_X_2VM_R6M C27 330U_X_2VM_R6M + C28 330U_X_2VM_R6M Near CPU Socket +CPU_CORE_0 VDDNB=4A (For Tigris) VDDNB=3A +CPU_CORE_1 +CPU_CORE_NB C33 22U_0805_6.3V6M C36 22U_0805_6.3V6M C34 22U_0805_6.3V6M C35 22U_0805_6.3V6M C178 22U_0805_6.3V6M C41 22U_0805_6.3V6M +CPU_CORE_0 1 C190 22U_0805_6.3V6M C39 22U_0805_6.3V6M VDDIO=3A +1.8V +CPU_CORE_1 C128 0.22U_0603_16V4Z C129 0.01U_0402_25V4Z VDD1 =18A JCPU1E +CPU_CORE_0 +CPU_CORE_1 D 1 C151 180P_0402_50V8J C122 0.22U_0603_16V4Z C47 0.01U_0402_25V4Z C5 180P_0402_50V8J Under CPU Socket C G4 H2 J9 J11 J13 J15 K6 K10 K12 K14 L4 L7 L9 L11 L13 L15 M2 M6 M8 M10 N7 N9 N11 VDD0_1 VDD0_2 VDD0_3 VDD0_4 VDD0_5 VDD0_6 VDD0_7 VDD0_8 VDD0_9 VDD0_10 VDD0_11 VDD0_12 VDD0_13 VDD0_14 VDD0_15 VDD0_16 VDD0_17 VDD0_18 VDD0_19 VDD0_20 VDD0_21 VDD0_22 VDD0_23 K16 M16 P16 T16 V16 VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5 H25 J17 K18 K21 K23 K25 L17 M18 M21 M23 M25 N17 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 +CPU_CORE_1 VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8 VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26 P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2 VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13 Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18 +1.8V 6090022100G_B Athlon 64 S1 Processor Socket VDDIO decoupling +CPU_CORE_NB +1.8V C170 22U_0805_6.3V6M C181 22U_0805_6.3V6M 1 C124 0.22U_0603_16V4Z 2 C147 0.22U_0603_16V4Z C6 decoupling +CPU_CORE_NB C7 180P_0402_50V8J 180P_0402_50V8J 2 C8 22U_0805_6.3V6M C9 22U_0805_6.3V6M C11 22U_0805_6.3V6M JCPU1F AA4 AA11 AA13 AA15 AA17 AA19 AB2 AB7 AB9 AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21 AD6 AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23 B4 B6 B8 B9 B11 B13 B15 B17 B19 B21 B23 B25 D6 D8 D9 D11 D13 D15 D17 D19 D21 D23 D25 E4 F2 F11 F13 F15 F17 F19 F21 F23 F25 H7 H9 H21 H23 J4 J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6 D C Athlon 64 S1 Processor Socket Between CPU Socket and DIMM +0.9V +1.8V Near Power Supply B C157 0.22U_0603_16V4Z C182 0.22U_0603_16V4Z C68 0.22U_0603_16V4Z +1.8V VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 6090022100G_B Under CPU Socket VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 C175 0.01U_0402_25V4Z C159 0.01U_0402_25V4Z C188 0.22U_0603_16V4Z change to polymer 180PF Qt'y follow the distance between CPU socket and DIMM0 C189 180P_0402_50V8J C66 + +1.8V 1 VTT decoupling C136 180P_0402_50V8J 2 220U_D2_4VM_R15 B C14 22U_0805_6.3V6M +0.9V C156 180P_0402_50V8J C158 180P_0402_50V8J C155 4.7U_0805_10V4Z C146 4.7U_0805_10V4Z +1.8V C184 0.22U_0603_16V4Z C173 0.22U_0603_16V4Z C72 1000P_0402_25V8J C145 1000P_0402_25V8J C180 180P_0402_50V8J C121 180P_0402_50V8J Near CPU Socket Right side +0.9V 1 C76 4.7U_0805_10V4Z C167 4.7U_0805_10V4Z C187 4.7U_0805_10V4Z C132 4.7U_0805_10V4Z + C162 220U_Y_4VM NBO CAP + C12 220U_Y_4VM @ C73 4.7U_0805_10V4Z 2 C70 4.7U_0805_10V4Z C127 0.22U_0603_16V4Z C185 0.22U_0603_16V4Z C164 1000P_0402_25V8J 2 C163 1000P_0402_25V8J C152 180P_0402_50V8J C179 180P_0402_50V8J A A Near CPU Socket Left side 2009/09/11 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/03/12 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC SCHEMATIC,MB A5991 Rev A 401830 Date: Sheet Tuesday, October 13, 2009 of 47 A B +1.8V C D E +1.8V RESERVE +V_DDR_MCH_REF BUFFER CIRCUIT JDIMM1 DDRA_SDQS1# DDRA_SDQS1 DDRA_SDQS1# DDRA_SDQS1 DDRA_SDQ10 DDRA_SDQ11 DDRA_SDQ16 DDRA_SDQ17 DDRA_SDQS2# DDRA_SDQS2 DDRA_SDQS2# DDRA_SDQS2 DDRA_SDQ18 DDRA_SDQ19 DDRA_SDQ24 DDRA_SDQ25 DDRA_SDM3 DDRA_SDQ26 DDRA_SDQ27 DDRA_CKE0 DDRA_CKE0 DDRA_SBS2# DDRA_SBS2# DDRA_SMA12 DDRA_SMA9 DDRA_SMA8 DDRA_SMA5 DDRA_SMA3 DDRA_SMA1 DDRA_SMA10 DDRA_SBS0# DDRA_SWE# DDRA_SBS0# DDRA_SWE# DDRA_SCAS# DDRA_SCS1# DDRA_SCAS# DDRA_SCS1# DDRA_ODT1 DDRA_ODT1 DDRA_SDQ32 DDRA_SDQ33 DDRA_SDQS4# DDRA_SDQS4 DDRA_SDQS4# DDRA_SDQS4 DDRA_SDQ34 DDRA_SDQ35 DDRA_SDQ40 DDRA_SDQ41 DDRA_SDM5 DDRA_SDQ42 DDRA_SDQ43 DDRA_SDQ48 DDRA_SDQ49 DDRA_SDQS6# DDRA_SDQS6 DDRA_SDQS6# DDRA_SDQS6 DDRA_SDQ50 DDRA_SDQ51 DDRA_SDQ56 DDRA_SDQ57 DDRA_SDM7 DDRA_SDQ58 DDRA_SDQ59 SB_CK_SDAT SB_CK_SCLK SB_CK_SDAT SB_CK_SCLK +3VS C448 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD GND VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 GND 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 204 DDRA_SDQ[0 63] DDRA_SDM[0 7] DDRA_SDQ6 DDRA_SDQ7 DDRA_SMA[0 15] DDRA_SDQ12 DDRA_SDQ13 DDRA_SDM[0 7] DDRA_SMA[0 15] DDRA_SDM1 +1.8V +0.9V RP1 DDRA_CLK0 DDRA_CLK0# DDRA_SMA6 DDRA_SMA7 DDRA_SMA11 DDRA_SMA15 DDRA_SDQ14 DDRA_SDQ15 +1.8V DDRA_SDQ20 DDRA_SDQ21 DDRA_SDM2 +V_DDR_MCH_REF DDRA_SDQ22 DDRA_SDQ23 DDRA_SDQ28 DDRA_SDQ29 DDRA_SDQS3# DDRA_SDQS3 DDRA_SDQS3# DDRA_SDQS3 DDRA_SDQ30 DDRA_SDQ31 DDRA_CKE1 DDRA_CKE0 DDRA_SBS2# DDRA_CKE1 DDRA_SMA14 R398 1K_0402_1% +V_DDR_MCH_REF DDRA_SRAS# DDRA_SMA0 DDRA_SMA2 DDRA_SMA4 R397 1K_0402_1% DDRA_SMA12 DDRA_SMA9 DDRA_SMA8 DDRA_SMA5 DDRA_SMA11 DDRA_SMA7 DDRA_SMA6 +1.8V DDRA_SMA4 DDRA_SMA2 DDRA_SMA0 DDRA_SBS1# DDRA_SRAS# DDRA_SCS0# DDRA_ODT0 DDRA_SMA13 DDRA_SBS1# DDRA_SRAS# DDRA_SCS0# 0.1U_0402_16V4Z C60 DDRA_ODT0 C63 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z C64 C139 0.1U_0402_16V4Z 0.1U_0402_16V4Z C192 C88 0.1U_0402_16V4Z 0.1U_0402_16V4Z C117 C144 0.1U_0402_16V4Z 0.1U_0402_16V4Z C114 C95 0.1U_0402_16V4Z 0.1U_0402_16V4Z C81 47_0804_8P4R_5% RP2 47_0804_8P4R_5% RP3 47_0804_8P4R_5% RP4 C193 C125 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDRA_SCS1# DDRA_ODT1 DDRA_SWE# DDRA_SCAS# 47_0804_8P4R_5% RP6 C103 C99 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDRA_SMA13 DDRA_SCS0# DDRA_ODT0 DDRA_SBS1# 47_0804_8P4R_5% RP7 C107 C98 0.1U_0402_16V4Z 0.1U_0402_16V4Z 47_0804_8P4R_5% DDRA_SDQ36 DDRA_SDQ37 DDRA_SDM4 +0.9V DDRA_SDQ38 DDRA_SDQ39 @ 0.1U_0402_16V4Z DDRA_SDQ44 DDRA_SDQ45 DDRA_SDQS5# DDRA_SDQS5 1 C67 DDRA_SDQS5# DDRA_SDQS5 2 @ 0.1U_0402_16V4Z DDRA_SDQ46 DDRA_SDQ47 C69 @ 0.1U_0402_16V4Z C71 C75 2 @ 0.1U_0402_16V4Z DDRA_SDQ52 DDRA_SDQ53 DDRA_CLK1 DDRA_CLK1# DDRA_SDM6 DDRA_SDQ54 DDRA_SDQ55 DDRA_SDQ60 DDRA_SDQ61 DDRA_SDQS7# DDRA_SDQS7 DDRA_SDQS7# DDRA_SDQS7 DDRA_SDQ62 DDRA_SDQ63 R12 R10 1 10K_0402_5% 10K_0402_5% C310 0.1U_0402_16V4Z DIMM1 REV H:5.2mm (BOT) Compal Secret Data Security Classification 2009/09/11 Issued Date 2010/03/12 Deciphered Date Title Compal Electronics, Inc SCHEMATIC,MB A5991 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A 47_0804_8P4R_5% RP5 C65 2 0.1U_0402_16V4Z DDRA_SBS0# DDRA_SMA10 DDRA_SMA1 DDRA_SMA3 DDRA_CKE1 DDRA_SMA15 DDRA_SMA14 FOX_AS0A426-M2RN-7F CONN@ +3VS 4.7U_0805_10V4Z 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 203 DDRA_SDQ[0 63] DDRA_SDM0 DDRA_SDQ8 DDRA_SDQ9 DDRA_SDQ4 DDRA_SDQ5 1 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 DDRA_SDQ2 DDRA_SDQ3 VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS DDRA_SDQS0# DDRA_SDQS0 DDRA_SDQS0# DDRA_SDQS0 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS C503 0.1U_0402_16V4Z DDRA_SDQ0 DDRA_SDQ1 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 C507 1000P_0402_25V8J +V_DDR_MCH_REF B C D Rev A 401830 Sheet Tuesday, October 13, 2009 E 10 of 47 ... 10 2 10 4 10 6 10 8 1 10 11 2 11 4 11 6 11 8 1 20 12 2 12 4 12 6 12 8 1 30 13 2 13 4 13 6 13 8 1 40 14 2 14 4 14 6 14 8 1 50 15 2 15 4 15 6 15 8 1 60 16 2 16 4 16 6 16 8 1 70 17 2 17 4 17 6 17 8 1 80 18 2 18 4 18 6 18 8 1 90 19 2 19 4 19 6 19 8... 10 6 10 8 1 10 11 2 11 4 11 6 11 8 1 20 12 2 12 4 12 6 12 8 1 30 13 2 13 4 13 6 13 8 1 40 14 2 14 4 14 6 14 8 1 50 15 2 15 4 15 6 15 8 1 60 16 2 16 4 16 6 16 8 1 70 17 2 17 4 17 6 17 8 1 80 18 2 18 4 18 6 18 8 1 90 19 2 19 4 19 6 19 8 200 204 ... 11 3 11 5 11 7 11 9 12 1 12 3 12 5 12 7 12 9 13 1 13 3 13 5 13 7 13 9 14 1 14 3 14 5 14 7 14 9 15 1 15 3 15 5 15 7 15 9 16 1 16 3 16 5 16 7 16 9 17 1 17 3 17 5 17 7 17 9 18 1 18 3 18 5 18 7 18 9 19 1 19 3 19 5 19 7 19 9 2 01 VSS DQ16 DQ17
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