Compal EH78F LA g161p rev 1c (0 1) схема

A B C D E Compal Confidential EH78F MB Schematic Document 2 LA-G161P 3 Rev:1C 2019.01.16 4 Compal Secret Data Security Classification 2017/11/23 Issued Date Deciphered Date 2018/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Cover Sheet Size Document Number Custom EH78F M/B Date: A B C D Compal Electronics, Inc Rev 0.1 LA-G161PR01 W ednesday, January 16, 2019 Sheet E of 102 A eDP Panel Conn page B eDP lane 38 C RTC circuit eDP redriver TUSB546 HDMI 2.0 Conn page Display Port Conn x1 page 39 USB3.1 gen2 DP lane DP lane Memory BUS Dual Channel Processor 1.2V DDR4 2400 260pin DDR4-SO-DIMM page 24 page 06~13 X4 DMI Offline USB Charger DPRedriver TUSB546 page 47 page 23 CoffeeLake H PROCESSOR BGA1440 (42X28) (CFL-H_6+2) Active MUX ANX7440 USB3.1 Retimer ANX7490page 46 page 54 260pin DDR4-SO-DIMM PEG X16 (0~15) 8GT/s page 25~37 DP lane page 55 page 31 40 Hall sensor Thermal sensor page 54 VBIOS ROM 1.8V 8Mbit eDPx4 HDMI lane E Fan Control page 21 page 41 D USB3.0 Conn.(M/B) page 42 ON XBOX/B ON USB3.0_Audio/B page 71 USB3.0 2 USB3.1 Passive MUX ANX7428 USB2.0 Cannonlake PCH - H FCBGA(23X23) page 48 NV TYPE-C Conn DP/USB3.1 Silego USB charger SLGC55544 DP lane USB3.0 Conn.(USB/B) page 71 USB2.0 Conn.(XBOX/B) page 73 page 73 USB3.0 USB2.0 USB Bus page 49 PD CCG4 M.2 page 49 837pin FCBGA TBT TYPE-C Conn TBT/DP/USB2.0/USB3.1 page 45 Thunderbolt AR4C FHD CAM Conn Key Board Conn page 38 PCIe x4 USB2.0 page 43, 44 Blue Tooth page 63 page 52 USB2.0 USB2.0 PD TPS65982 HD Audio page 45 3.3V 24MHz HDA Codec Ext Amp ALC289 ALC1006 page 56 Speaker Conn page 57 page 56 Flexible I/O PCIe x2 PCIe x1 M.2 WLAN Dual Band page 52 LAN(GbE) Killer Ethernet E3000 page 51 802.11 ac/agn 6.0 Gb/s PCIe x4 SATA3.0 PCIe x4 SATA3.0 M.2 SSD M.2 SSD Conn Conn page 68 Head Phone Jack Conn page 14~21 SPI page 68 SPI ROM 16M MIC Jack Conn page 16 RJ45 ON USB3.0_Audio/B page 73 Conn page 51 LED driver TLC59116 SUB/B page 62 SMBUS ENE KB9022 page 58 4 G+Gyro-sensor/B Hall/B USB 3.0_Audio/B Macro Key page 38 page 66 Touch Pad page 73 Issued Date I2C/PS2 page 77 Compal Electronics, Inc Compal Secret Data Security Classification page 63 2017/11/23 Deciphered Date 2018/09/01 Title Block Diagrams THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 0.1 EH78F M/B LA-G161PR01 Date: A B C D Wednesday, January 16, 2019 E Sheet of 102 A B C D Board ID Table for AD channel Vcc Ra Board ID 1 10 11 12 13 14 15 16 17 18 19 Power State BOM Structure Table 3.3V +/- 5% 100K +/- 5% Rb 12K +/- 1% 15K +/- 1% 20K +/- 1% 27K +/- 1% 33K +/- 1% 43K +/- 1% 56K +/- 1% 75K +/- 1% 100K +/- 1% 130K +/- 1% 160K +/- 1% 200K +/- 1% 240K +/- 1% 270K +/- 1% 330K +/- 1% 430K +/- 1% 560K +/- 1% 750K +/- 1% NC V BID 0.347 0.423 0.541 0.691 0.807 0.978 1.169 1.398 1.634 1.849 2.015 2.185 2.316 2.395 2.521 2.667 2.791 2.905 3.000 V V V V V V V V V V V V V V V V V V V V BID typ 0.000 V 0.345 V 0.430 V 0.550 V 0.702 V 0.819 V 0.992 V 1.185 V 1.414 V 1.650 V 1.865 V 2.031 V 2.200 V 2.329 V 2.408 V 2.533 V 2.677 V 2.800 V 2.912 V 3.000 V V BID max 0.300 V 0.360 V 0.438 V 0.559 V 0.713 V 0.831 V 1.006 V 1.200 V 1.430 V 1.667 V 1.881 V 2.046 V 2.215 V 2.343 V 2.421 V 2.544 V 2.687 V 2.808 V 2.919 V EC 0x00 0x14 0x1F 0x26 0x31 0x3B 0x46 0x55 0x65 0x77 0x88 0x97 0xA5 0xB0 0xB8 0xC0 0xCA 0xD5 0xDE 0xF1 AD - 0x13 - 0x1E - 0x25 - 0x30 - 0x3A - 0x45 - 0x54 - 0x64 - 0x76 - 0x87 - 0x96 - 0xA4 - 0xAF - 0xB7 - 0xBF - 0xC9 - 0xD4 - 0xDD - 0xF0 - 0xFF I2C Address Table BUS Device I2C_0 (+3VS) I2C_1 (+3VS) Address(7 bit) Address(8bit) Write LIS2DH12TR (G-sensor) TM-03461-001 (Touch Pad) Read BOM Option Table Item BOM Structure Unpop @ Connector CONN@ HDMI royalty 45@ i5 CPU I5@ i7 CPU I7@ PCH PCH@ CMC CMC@ dGPU circuit VGA@ OVRM-Onsemi onsemi@ OVRM-Onsemi upi@ FGC6 FGC6@ NON FGC6 NFGC6@ Intel CNVi (reserve) CNVI@ USB charger CHG@ GSYNC GSYNC@ NON GSYNC NGSYNC@ Thunderbolt TBT@ Thermal sensor TMS@ for SW debug board UART@ EMI/ESD requirement EMC@ EMI/ESD require reserve XEMC@ DIS sequency control NGPK@ M/B GSENSOR MBGSEN@ GSENSOR ISH path ISHGSEN@ GSENSOR EC path ECGSEN@ EC_SMB_CK1 (+3VLP) N18E-G3 (VGA) TMS(NCT7718W )hot TMS(W83L771AWG-2 )cool LIS2DH12TR(M/B) LIS2DH12TR(SUB/B) ISL88739 (Charger IC) BATTERY PACK 0x11 0x16 EC_SMB_CK3 (+3VALW) PD(TPS65982) LED driver 0x70 0xC0 PCH_SML1CLK EC_SMB_CK2 (+3VALW) SIGNAL +VALW +V +VS Clock S0 (Full ON) HIGH HIGH HIGH ON ON ON ON S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF STATE SLP_S3# SLP_S4# SLP_S5# Voltage Rails Power Plane DIMM1 DIMM2 PCH_SMBCLK (+3VALW) E 0x9E 0x98 0x9A Description +RTCVCC RTC Battery Power S0 ON ON S4 ON +19V_VIN Adapter power supply N/A N/A N/A N/A +12.6V_BATT Battery power supply N/A N/A N/A N/A +19VB AC or battery power rail for power circuit N/A N/A N/A N/A +3VLP +19VB to +3VLP power rail for suspend power ON ON ON ON +5VALW +5V Always power rail ON ON ON +3VALW System +3VALW always on power rail ON ON ON ON ON* +3VALW_DSW +3VALW power for PCH DSW rails ON ON ON ON +3VALW_PCH_PRIM +3VALW power for PCH power rails ON ON ON ON* +3VALW_SPI +3VALW_PRIM supply for the SPI IO ON ON ON ON +1.05VALW +1.05V Always power rail ON ON ON ON +1.2V_VDDQ DDR4 +1.2V power rail ON ON OFF OFF +1.05V_VCCST Sustain voltage for processor in Standby modes ON OFF OFF +5VS System +5V power rail ON ON OFF OFF OFF +3VS System +3V power rail ON OFF OFF OFF +1.05VS_VCCSTG +1.05VALW_PRIM Gated version of VCCST ON OFF OFF OFF +0.6VS_VTT DDR +0.6VS power rail for DDR terminator ON OFF OFF OFF +VCC_CORE Core voltage for CPU ON OFF OFF OFF +VCC_GT Sliced graphics power rail ON OFF OFF OFF +VCCIO CPU IO +0.95VS power rail ON OFF OFF OFF +VCC_SA System Agent power rail ON OFF OFF OFF +1.8VSDGPU_AON +1.8VS power rail for GPU(AON rails) ON OFF OFF OFF +1.8VSDGPU_MAIN +1.8VS power rail for GPU GC6 ON OFF OFF OFF +VGA_CORE Core voltage for VGA (merge core & core_s) ON OFF OFF OFF +1.35VSDGPU +1.35VS power rail for GPU ON OFF OFF OFF OFF ON* S3 +1.0VSDGPU +1.0VS power rail for GPU ON OFF OFF +1.8VALW System +1.8VALW always on power rail ON ON ON S5 ON 3 Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF EC_SMB_CK4 (+3VALW) BOARD ID Table Board ID 43 level BOM table 43 Level 43 Description EH78F 1180 BOM Structure I7@/QNDQ@/CMC@/VGA@/NGPK@/CNVI@/CHG@/XBOX@/TBT@/EMC@ Compal Secret Data Security Classification Issued Date PCB Revision 0.1 1.0 1A 1B 1C 2017/11/23 Deciphered Date 2018/09/01 Title Board ID 10 11 12 13 14 15 16 17 18 19 PCB Revision 1.0 w/ EC gensor Compal Electronics, Inc Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 0.1 EH78F M/B LA-G161PR01 Date: A B C D Wednesday, January 16, 2019 E Sheet of 102 EN:DGPU_PWR_EN +1.8VSDGPU_AON DC_IN GPU +1.8VSDGPU_MAIN PL101 UG27 PJP101 +19V_VIN AC CONN +12.6V_BATT+ +12.6V_BATT UQ2 BATTERY PL201,PL202 +1.8VS +1.8VDDA RA3 CODEC PJP201 +1.8VALWP IMVP8 D +19VB PU301 +VCC_CORE PL8101,PL8104,PL8105,PL8106 CPU +19VB +1.8VALW +VCC_GT DIMM1 DDR4 +1.0VSDGPU GPU PJ1401 CPU +3VS JPQ1 UQ1 EN:DRON U5 +3VS_WLAN UM1 PU8301 +VCC_SA PL8301 +19VB JNGFF1 TPM WLAN CARD (IOAC) G-SENSOR RZ1 +3VS_SSD_NGFF RM1 +3V_LAN CPU SATA Re-driver UO1 +3VALW_TPM R19 D PCH DIMM2 +1.0VSDGPUP PL8107 +1.8VALW _PRIM +2.5V PJ7103 PU1401 PU8106 RH100 +2.5VP PU7102 EN:VR_ON CHARGER PJ7107 PU7105 PU1802 PU8103 PU8104 PU8105 UL2 UL2 +3VS_TPM R20 EN:DRON +3V_PTP UK1 JTP1 TP +LCDVDD UX1 +3VALWP EN:3V_EN +19VB +3VALW_PCH_PRIM RH97 +3VALW PJ401 EC,LID C PJ501 +1.2V_VDDQ UH2 SPI +3VS_DVDDIO +1.2V_VCCPLL_OC RC24 +3VALW_HDA CPU PCH +3VALW_DSW CODEC +3VS_DVDD CODEC C PCH RH99 CPU +FP_VCC FP UK2 +19VB PANEL +3VS_DVDDIO +3VS_DVDD RA4 JPC1,C2 TPM +3.3V_CC RS1 RH101 +1.2VP +3VALW_SPI +3VLP +1.2V_VDDQ_CPU SSD U5 JEDP1 RA2 PU401 EN:SYSON RH98 JSSD1 LAN PU501 EN:SM_PG_CTRL +0.6VSP PJ502 +0.6VS_VTT +1.05VALWP PU601 PJ601 +19VB RH92 +1.05VALW_PRIM PCH RH94 +1.05VALW_PCH PCH +1.05VALW RH102 RH103 EN:+3VALW PCH RH105 +19VB PU7201 PJ7201 +1.05VALW _VCCMPHY RH93 +0.95VS_VCCIOP +VCCIO CPU PCH +1.05V_VCCST UQ2 CPU EN:SUSP# RQ61 UC4 +1.05VS_VCCSTG B B US2 +5V_CC USB2.0 Conn/ IOB JIO3 PU402 +5VALWP +19VB +19VB_NVVDD PL1502 PL1503 PU1501 PU1502 EN:1.35VS_DGPU_PG +1.35VSDGPUP +19VB A +5VALW PJ402 +19VB PL1301 PJ1302 PJ1303 PL1501 PL1502 US11 +USB3_VCCC US1 +USB_VCCA JPQ2 +5VS US2 JTYPEC1 UQ1 GPU RF4 +VCC_FAN1 FAN1 RF7 +VCC_FAN2 FAN2 +VGA_CORE +VDDA UA1 CODEC U4 +5VS_BL JBL1 KB BackLight RO4 +5VS_HDD JHDD1 HDD JHDMI1 HDMI JPA1 GPU UY2 +1.35VSDGPU LX1 +HDMI_5V_OUT A +TS_PWR RX7 +19VB →+19V_CPU Type C Conn USB3.0 Conn +INVPWR_B+ JEDP1 TS PANEL Compal Secret Data Security Classification Issued Date 2017/11/23 Deciphered Date 2018/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Power Map Rev 0.1 EH78F M/B LA-G161PR01 Date: Compal Electronics, Inc Size Document Number Custom Wednesday, January 16, 2019 Sheet of 102 A B EH78F_EVT Power Sequence BIOS : 0.05 EC : 0.05 C Power On D S3 E Power Off S3 Resume AC mode Plug in +3VLP +3VLP EC_ON EC_ON → 353.6ms +5VALW → 356.4ms +5VALW ON/OFFBTN# ON/OFFBTN# +3VALW → 94.89ms → 8.880s +3VALW +1.8VALW → 96.19ms → 8.879s +1.8VALW +1.05ALW → 97.17ms → 8.879S +1.05ALW → 8.834 EC_RSMRST# → 8.834 PBTN_OUT# EC_RSMRST# 42.10ms → 24ms PBTN_OUT# → ←← → 164.6ms 2 PM_SLP_S4# PM_SLP_S3# SYSON → 19.08ms → 19.11ms +1.05V_VCCST +1.2V_VDDQ +2.5V SUSP# +1.05VS_VCCSTG +VCCIO +5VS +3VS +1.8VS EC_VCCST_PG SM_PG_CTRL +VCC_SA PCH_PWROK SYS_PWROK 10.27ms → PM_SLP_S3# 10.42ms → SYSON 299.4us → 97.92us +1.05V_VCCST → 717.2us → 376.7us +1.2V_VDDQ → 1.006ms → 12.67ms → 13.89us → 48.05ms → → 8.417us → → 255.0us → → 955us → → 651.9us → → 460.4us → → 25.6ms → 8.782us → → 25.38ms → 9.195us → 55.56us 747.1us 401.1us 2.349ms 1.169ms +2.5V 10.28ms → → 8.7us → → 239.4us → → 939.9us → → 704.1us → → 434.1us → 32.16ms 1.244ms SUSP 73.86us +1.05VS_VCCSTG 790.4us +VCCIO 598.9us +5VS 2.47ms +3VS 1.132ms +1.8VS → 8.739us EC_VCCST_PG → 9.244us SM_PG_CTRL → 2.060us → → → 12.36ms 172.7ms → → 60.60us → → 74.83us → → 89.21us → 2.163ms 176.2ms 812.8us +VCC_SA → 74.11us PCH_PWROK → 88.46us SYS_PWROK 1.207ms PLT_RST# 179.9ms → VR_ON 87.5us → 12.8ms +0.6VS_VTT 10.29ms → → → 596.1us → 30.02ms → 1.098ms 176.5ms → → 2.78us 19.21us → 2.158ms 30.02ms 2.048ms → 25.38ms → PLT_RST# +VCC_CORE PM_SLP_S4# → +0.6VS_VTT VR_ON 10.27ms → 4.8ms → 10.41ms → → 2.174ms +VCC_CORE → 4 Compal Secret Data Security Classification Issued Date 2017/11/23 Deciphered Date 2018/09/01 Title Compal Electronics, Inc Power Sequence THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 0.1 EH78F M/B LA-G161PR01 Date: A B C D Wednesday, January 16, 2019 E Sheet of 102 A B C D E 1 CFL-H UC1D K36 K37 J35 J34 H37 H36 J37 J38 PCB DAZ D27 E27 ZZZ PCB@ H34 H33 F37 G38 F34 F35 E37 E36 DAZ2HB00100 PCB EH78F LA-G161P LS-G161P/G162P/G163P/G164P/G165P/G168P F26 E26 Coffee Lake-H CPU SKU C34 D34 B36 B34 F33 E33 C33 B33 UC1 CFL-H_BGA1440 S IC CL8068403359524 SR3YY U0 2.2G ABO! SA0000BPZ40 i7@ A27 B27 DDI1_TXP_0 DDI1_TXN_0 DDI1_TXP_1 DDI1_TXN_1 DDI1_TXP_2 DDI1_TXN_2 DDI1_TXP_3 DDI1_TXN_3 EDP_TXP_0 EDP_TXN_0 EDP_TXP_1 EDP_TXN_1 EDP_TXP_2 EDP_TXN_2 EDP_TXP_3 EDP_TXN_3 DDI1_AUXP DDI1_AUXN EDP_AUXP EDP_AUXN DDI2_TXP_0 DDI2_TXN_0 DDI2_TXP_1 DDI2_TXN_1 DDI2_TXP_2 DDI2_TXN_2 DDI2_TXP_3 DDI2_TXN_3 EDP_DISP_UTIL DISP_RCOMP D29 E29 F28 E28 A29 B29 C28 B28 C26 B26 +VCCIO A33 DP_RCOMP D37 RC1 24.9_0402_1% Trace Width/Space: 15 mil/ 20 mil Max Trace Length: 600 mil DDI2_AUXP DDI2_AUXN DDI3_TXP_0 DDI3_TXN_0 DDI3_TXP_1 DDI3_TXN_1 DDI3_TXP_2 DDI3_TXN_2 DDI3_TXP_3 DDI3_TXN_3 DDI3_AUXP DDI3_AUXN PROC_AUDIO_CLK PROC_AUDIO_SDI ofPROC_AUDIO_SDO 13 G27 G25 G29 CPU_DISPA_SDI RC2 20_0402_5% CPU_DISPA_BCLK_R CPU_DISPA_SDO_R CPU_DISPA_SDI_R CPU_DISPA_BCLK_R CPU_DISPA_SDO_R CPU_DISPA_SDI_R follow CRB CFL-H_BGA1440 @ Cannon Lake PCH SKU UH1 CFL-H_BGA1440 S IC FH82HM370 SR40B B0 BGA 874P PCH-H ABO! SA0000BVP10 PCH@ NV N18E-G3 Need check USE QS PN UG9 VGA@ S IC TU104-750-A1 FCBGA 2228 GPU ABO ! Compal Secret Data Security Classification SA0000CD510 2017/11/23 Issued Date Deciphered Date 2018/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom B C D Rev 0.1 EH78F M/B LA-G161PR01 Date: A Compal Electronics, Inc CFL-H(1/8)DDI/eDP W ednesday, January 16, 2019 Sheet E of 102 A B C D E CHANNEL-A Interleaved Memory CFL-H UC1A DDR CHANNEL A DDR_A_D[0 63] DDR4(IL)/LP3-DDR4(NIL) DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 BR6 BT6 BP3 BR3 BN5 BP6 BP2 BN3 BL4 BL5 BL2 BM1 BK4 BK5 BK1 BK2 BG4 BG5 BF4 BF5 BG2 BG1 BF1 BF2 BD2 BD1 BC4 BC5 BD5 BD4 BC1 BC2 AB1 AB2 AA4 AA5 AB5 AB4 AA2 AA1 V5 V2 U1 U2 V1 V4 U5 U4 R2 P5 R4 P4 R5 P2 R1 P1 M4 M1 L4 L2 M5 M2 L5 L1 BA2 BA1 AY4 AY5 BA5 BA4 AY1 AY2 For ECC DIMM LP3/DDR4 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3 DDR0_DQ_8/DDR0_DQ_8 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3 DDR0_DQ_13/DDR0_DQ_13 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3 DDR0_DQ_18/DDR0_DQ_34 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3 DDR0_DQ_23/DDR0_DQ_39 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR0_DQ_27/DDR0_DQ_43 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR0_DQ_31/DDR0_DQ_47 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 DDR0_DQ_34/DDR1_DQ_2 DDR0_CAB_5/DDR0_MA_2 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_3/DDR0_MA_8 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 DDR0_DQ_42/DDR1_DQ_10 DDR0_CAB_7/DDR0_MA_10 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 DDR0_DQ_44/DDR1_DQ_12 DDR0_CAA_6/DDR0_MA_12 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT# DDR0_DQ_48/DDR1_DQ_32 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT# DDR0_DQ_51/DDR1_DQ_35 DDR4(IL)/LP3-DDR4(NIL) DDR0_DQ_52/DDR1_DQ_36 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 DDR0_DQ_57/DDR1_DQ_41DDR0_DQSN_4/DDR1_DQSN_0 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 DDR0_DQ_59/DDR1_DQ_43DDR0_DQSN_6/DDR1_DQSN_4 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5 DDR0_DQ_61/DDR1_DQ_45 DDR0_DQ_62/DDR1_DQ_46DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQ_63/DDR1_DQ_47DDR0_DQSP_1/DDR0_DQSP_1 DDR0_DQSP_2/DDR0_DQSP_4 LP3/DDR4 DDR0_DQSP_3/DDR0_DQSP_5 NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 NC/DDR0_ECC_1 DDR0_DQSP_5/DDR1_DQSP_1 NC/DDR0_ECC_2 DDR0_DQSP_6/DDR1_DQSP_4 NC/DDR0_ECC_3 DDR0_DQSP_7/DDR1_DQSP_5 NC/DDR0_ECC_4 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 NC/DDR0_ECC_6 DDR0_DQSN_8/DDR0_DQSN_8 OF 13 NC/DDR0_ECC_7 AG1 AG2 AK2 AK1 AL3 AK3 AL2 AL1 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 AT1 AT2 AT3 AT5 DDR_A_CKE0 DDR_A_CKE1 AD5 AE2 AD2 AE5 DDR_A_CS#0 DDR_A_CS#1 AD3 AE4 AE1 AD4 DDR_A_ODT0 DDR_A_ODT1 AH5 AH1 AU1 DDR_A_BA0 DDR_A_BA1 DDR_A_BG0 AH4 AG4 AD1 DDR_A_MA16_RAS# DDR_A_MA14_W E# DDR_A_MA15_CAS# AH3 AP4 AN4 AP5 AP2 AP1 AP3 AN1 AN3 AT4 AH2 AN2 AU4 AE3 AU2 AU3 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_BG1 DDR_A_ACT# AG3 AU5 DDR_A_PAR DDR_A_ALERT# BR5 BL3 BG3 BD3 AA3 U3 P3 L3 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 BP5 BK3 BF3 BC3 AB3 V3 R3 M3 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 AY3 BA3 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_A_CKE0 DDR_A_CKE1 DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0 DDR_A_ODT1 DDR_A_BA0 DDR_A_BA1 DDR_A_BG0 DDR_A_MA16_RAS# DDR_A_MA14_W E# DDR_A_MA15_CAS# DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_BG1 DDR_A_ACT# DDR_A_PAR DDR_A_ALERT# DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 For ECC DIMM CFL-H_BGA1440 @ 4 Compal Secret Data Security Classification 2017/11/23 Issued Date Deciphered Date 2018/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title CFL-H(2/8)DIMMA Size Document Number Custom B C D Rev 0.1 EH78F M/B LA-G161PR01 Date: A Compal Electronics, Inc W ednesday, January 16, 2019 Sheet E of 102 A B C D E CHANNEL-B Interleaved Memory CFL-H UC1B DDR_B_D[0 63] DDR CHANNEL B DDR4(IL)/LP3-DDR4(NIL) DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 BT11 BR11 BT9 BR8 BP11 BN11 BP8 BN8 BL12 BL11 BL8 BJ8 BJ11 BJ10 BL7 BJ7 BG11 BG10 BG8 BF8 BF11 BF10 BG7 BF7 BB11 BC11 BB8 BC8 BC10 BB10 BC7 BB7 AA11 AA10 AC11 AC10 AA7 AA8 AC8 AC7 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 W8 W7 V10 V11 W11 W10 V7 V8 R11 P11 P7 R8 R10 P10 R7 P8 L11 M11 L7 M8 L10 M10 M7 L8 AW11 AY11 AY8 AW8 AY10 AW10 AY7 AW7 For ECC DIMM RC3 RC4 RC5 121_0402_1% SM_RCOMP0 75_0402_1% SM_RCOMP1 100_0402_1% SM_RCOMP2 1 Trace Width/Space: 15 mil/ 25 mil Max Trace Length: 500 mil G1 H1 J2 LP3/DDR4 DDR1_DQ_0/DDR0_DQ_16 DDR1_DQ_1/DDR0_DQ_17 DDR1_DQ_2/DDR0_DQ_18 DDR1_DQ_3/DDR0_DQ_19 DDR1_DQ_4/DDR0_DQ_20 DDR1_DQ_5/DDR0_DQ_21 DDR1_DQ_6/DDR0_DQ_22 DDR1_DQ_7/DDR0_DQ_23 DDR1_DQ_8/DDR0_DQ_24 DDR1_DQ_9/DDR0_DQ_25 DDR1_DQ_10/DDR0_DQ_26 DDR1_DQ_11/DDR0_DQ_27 DDR1_DQ_12/DDR0_DQ_28 DDR1_DQ_13/DDR0_DQ_29 DDR1_DQ_14/DDR0_DQ_30 DDR1_DQ_15/DDR0_DQ_31 DDR1_DQ_16/DDR0_DQ_48 DDR1_DQ_17/DDR0_DQ_49 DDR1_DQ_18/DDR0_DQ_50 DDR1_DQ_19/DDR0_DQ_51 DDR1_DQ_20/DDR0_DQ_52 DDR1_DQ_21/DDR0_DQ_53 DDR1_DQ_22/DDR0_DQ_54 DDR1_DQ_23/DDR0_DQ_55 DDR1_DQ_24/DDR0_DQ_56 DDR1_DQ_25/DDR0_DQ_57 DDR1_DQ_26/DDR0_DQ_58 DDR1_DQ_27/DDR0_DQ_59 DDR1_DQ_28/DDR0_DQ_60 DDR1_DQ_29/DDR0_DQ_61 DDR1_DQ_30/DDR0_DQ_62 DDR1_DQ_31/DDR0_DQ_63 DDR1_DQ_32/DDR1_DQ_16 DDR1_DQ_33/DDR1_DQ_17 DDR1_DQ_34/DDR1_DQ_18 DDR1_DQ_35/DDR1_DQ_19 DDR1_DQ_36/DDR1_DQ_20 DDR1_DQ_37/DDR1_DQ_21 DDR1_DQ_38/DDR1_DQ_22 DDR1_DQ_39/DDR1_DQ_23 DDR1_CKP_0/DDR1_CKP_0 DDR1_CKN_0/DDR1_CKN_0 DDR1_CKP_1/DDR1_CKP_1 DDR1_CKN_1/DDR1_CKN_1 NC/DDR1_CKP_2 NC/DDR1_CKN_2 NC/DDR1_CKP_3 NC/DDR1_CKN_3 DDR1_CKE_0/DDR1_CKE_0 DDR1_CKE_1/DDR1_CKE_1 DDR1_CKE_2/DDR1_CKE_2 DDR1_CKE_3/DDR1_CKE_3 DDR1_CS#_0/DDR1_CS#_0 DDR1_CS#_1/DDR1_CS#_1 NC/DDR1_CS#_2 NC/DDR1_CS#_3 DDR1_ODT_0/DDR1_ODT_0 NC/DDR1_ODT_1 NC/DDR1_ODT_2 NC/DDR1_ODT_3 DDR1_CAB_3/DDR1_MA_16 DDR1_CAB_2/DDR1_MA_14 DDR1_CAB_1/DDR1_MA_15 DDR1_CAB_4/DDR1_BA_0 DDR1_CAB_6/DDR1_BA_1 DDR1_CAA_5/DDR1_BG_0 DDR1_CAB_9/DDR1_MA_0 DDR1_CAB_8/DDR1_MA_1 DDR1_CAB_5/DDR1_MA_2 NC/DDR1_MA_3 NC/DDR1_MA_4 DDR1_CAA_0/DDR1_MA_5 DDR1_CAA_2/DDR1_MA_6 DDR1_CAA_4/DDR1_MA_7 DDR4(IL)/LP3-DDR4(NIL) DDR1_DQ_40/DDR1_DQ_24 DDR1_CAA_3/DDR1_MA_8 DDR1_DQ_41/DDR1_DQ_25 DDR1_CAA_1/DDR1_MA_9 DDR1_DQ_42/DDR1_DQ_26 DDR1_CAB_7/DDR1_MA_10 DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 DDR1_DQ_44/DDR1_DQ_28 DDR1_CAA_6/DDR1_MA_12 DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13 DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT# DDR1_DQ_48/DDR1_DQ_48 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT# DDR1_DQ_51/DDR1_DQ_51 DDR4(IL)/LP3-DDR4(NIL) DDR1_DQ_52/DDR1_DQ_52 DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 DDR1_DQ_55/DDR1_DQ_55DDR1_DQSN_2/DDR0_DQSN_6 DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 DDR1_DQ_57/DDR1_DQ_57DDR1_DQSN_4/DDR1_DQSN_2 DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 DDR1_DQ_59/DDR1_DQ_59DDR1_DQSN_6/DDR1_DQSN_6 DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7 DDR1_DQ_61/DDR1_DQ_61 DDR1_DQ_62/DDR1_DQ_62DDR1_DQSP_0/DDR0_DQSP_2 DDR1_DQ_63/DDR1_DQ_63DDR1_DQSP_1/DDR0_DQSP_3 DDR1_DQSP_2/DDR0_DQSP_6 LP3/DDR4 NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7 NC/DDR1_ECC_5 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8 DDR_RCOMP_0 DDR_RCOMP_1 DDR_RCOMP_2 DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ OF 13 AM9 AN9 AM7 AM8 AM11 AM10 AJ10 AJ11 DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1 AT8 AT10 AT7 AT11 DDR_B_CKE0 DDR_B_CKE1 AF11 AE7 AF10 AE10 DDR_B_CS#0 DDR_B_CS#1 AF7 AE8 AE9 AE11 DDR_B_ODT0 DDR_B_ODT1 AH10 AH11 AF8 DDR_B_MA16_RAS# DDR_B_MA14_W E# DDR_B_MA15_CAS# AH8 AH9 AR9 DDR_B_BA0 DDR_B_BA1 DDR_B_BG0 AJ9 AK6 AK5 AL5 AL6 AM6 AN7 AN10 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 AN8 AR11 AH7 AN11 AR10 AF9 AR7 AT9 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_BG1 DDR_B_ACT# AJ7 AR8 DDR_B_PAR DDR_B_ALERT# BN9 BL9 BG9 BC9 AC9 W9 R9 M9 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 BP9 BJ9 BF9 BB9 AA9 V9 P9 L9 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 AW9 AY9 BN13 BP13 BR13 DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1 DDR_B_CKE0 DDR_B_CKE1 DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1 DDR_B_MA16_RAS# DDR_B_MA14_W E# DDR_B_MA15_CAS# DDR_B_BA0 DDR_B_BA1 DDR_B_BG0 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_BG1 DDR_B_ACT# DDR_B_PAR DDR_B_ALERT# DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 For ECC DIMM +0.6V_VREFCA +0.6V_B_VREFDQ +0.6V_VREFCA +0.6V_B_VREFDQ CFL-H_BGA1440 @ Compal Secret Data Security Classification 2017/11/23 Issued Date Deciphered Date 2018/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D CFL-H(3/8)DIMMB Size Document Number Custom Rev 0.1 EH78F M/B LA-G161PR01 Date: A Compal Electronics, Inc W ednesday, January 16, 2019 Sheet E of 102 A B C D E PEG&DMI 0806, chagne PEG AC cap to 0402 X7R To DGPU PEG Lane Reversed To DGPU PEG Lane Reversed 0806, chagne PEG AC cap to 0402 X7R CFL-H UC1C PEG_CRX_C_GTX_P15 PEG_CRX_C_GTX_N15 CC1 CC3 VGA@ VGA@ 0.22U_0402_16V7K 0.22U_0402_16V7K PEG_CRX_GTX_P15 PEG_CRX_GTX_N15 E25 D25 PEG_CRX_C_GTX_P14 PEG_CRX_C_GTX_N14 CC5 CC6 VGA@ VGA@ 0.22U_0402_16V7K 0.22U_0402_16V7K PEG_CRX_GTX_P14 PEG_CRX_GTX_N14 E24 F24 PEG_CRX_C_GTX_P13 PEG_CRX_C_GTX_N13 CC7 VGA@ CC14 VGA@ 0.22U_0402_16V7K 0.22U_0402_16V7K PEG_CRX_GTX_P13 PEG_CRX_GTX_N13 E23 D23 PEG_CRX_C_GTX_P12 PEG_CRX_C_GTX_N12 CC16 VGA@ CC17 VGA@ 0.22U_0402_16V7K 0.22U_0402_16V7K PEG_CRX_GTX_P12 PEG_CRX_GTX_N12 E22 F22 E21 D21 PEG_CRX_C_GTX_P11 PEG_CRX_C_GTX_N11 CC19 VGA@ CC20 VGA@ 0.22U_0402_16V7K 0.22U_0402_16V7K PEG_CRX_GTX_P11 PEG_CRX_GTX_N11 PEG_CRX_C_GTX_P10 PEG_CRX_C_GTX_N10 CC10 VGA@ CC23 VGA@ 0.22U_0402_16V7K 0.22U_0402_16V7K PEG_CRX_GTX_P10 PEG_CRX_GTX_N10 E20 F20 PEG_CRX_C_GTX_P9 PEG_CRX_C_GTX_N9 CC25 VGA@ CC27 VGA@ 0.22U_0402_16V7K 0.22U_0402_16V7K PEG_CRX_GTX_P9 PEG_CRX_GTX_N9 E19 D19 PEG_CRX_C_GTX_P8 PEG_CRX_C_GTX_N8 CC29 VGA@ CC31 VGA@ 0.22U_0402_16V7K 0.22U_0402_16V7K PEG_CRX_GTX_P8 PEG_CRX_GTX_N8 E18 F18 PEG_CRX_C_GTX_P7 PEG_CRX_C_GTX_N7 CC33 VGA@ CC35 VGA@ 0.22U_0402_16V7K 0.22U_0402_16V7K PEG_CRX_GTX_P7 PEG_CRX_GTX_N7 D17 E17 PEG_CRX_C_GTX_P6 PEG_CRX_C_GTX_N6 CC37 VGA@ CC39 VGA@ 0.22U_0402_16V7K 0.22U_0402_16V7K PEG_CRX_GTX_P6 PEG_CRX_GTX_N6 F16 E16 PEG_CRX_C_GTX_P5 PEG_CRX_C_GTX_N5 CC41 VGA@ CC43 VGA@ 0.22U_0402_16V7K 0.22U_0402_16V7K PEG_CRX_GTX_P5 PEG_CRX_GTX_N5 D15 E15 PEG_CRX_C_GTX_P4 PEG_CRX_C_GTX_N4 CC45 VGA@ CC47 VGA@ 0.22U_0402_16V7K 0.22U_0402_16V7K PEG_CRX_GTX_P4 PEG_CRX_GTX_N4 F14 E14 PEG_CRX_C_GTX_P3 PEG_CRX_C_GTX_N3 CC49 VGA@ CC51 VGA@ 0.22U_0402_16V7K 0.22U_0402_16V7K PEG_CRX_GTX_P3 PEG_CRX_GTX_N3 D13 E13 F12 E12 PEG_CRX_C_GTX_P2 PEG_CRX_C_GTX_N2 CC53 VGA@ CC55 VGA@ 0.22U_0402_16V7K 0.22U_0402_16V7K PEG_CRX_GTX_P2 PEG_CRX_GTX_N2 PEG_CRX_C_GTX_P1 PEG_CRX_C_GTX_N1 CC57 VGA@ CC59 VGA@ 0.22U_0402_16V7K 0.22U_0402_16V7K PEG_CRX_GTX_P1 PEG_CRX_GTX_N1 D11 E11 PEG_CRX_C_GTX_P0 PEG_CRX_C_GTX_N0 CC61 VGA@ CC63 VGA@ 0.22U_0402_16V7K 0.22U_0402_16V7K PEG_CRX_GTX_P0 PEG_CRX_GTX_N0 F10 E10 PEG_RXP_0 PEG_RXN_0 PEG_TXP_0 PEG_TXN_0 PEG_RXP_1 PEG_RXN_1 PEG_TXP_1 PEG_TXN_1 PEG_RXP_2 PEG_RXN_2 PEG_TXP_2 PEG_TXN_2 PEG_RXP_3 PEG_RXN_3 PEG_TXP_3 PEG_TXN_3 PEG_RXP_4 PEG_RXN_4 PEG_TXP_4 PEG_TXN_4 PEG_RXP_5 PEG_RXN_5 PEG_TXP_5 PEG_TXN_5 PEG_RXP_6 PEG_RXN_6 PEG_TXP_6 PEG_TXN_6 PEG_RXP_7 PEG_RXN_7 PEG_TXP_7 PEG_TXN_7 PEG_RXP_8 PEG_RXN_8 PEG_TXP_8 PEG_TXN_8 PEG_RXP_9 PEG_RXN_9 PEG_TXP_9 PEG_TXN_9 PEG_RXP_10 PEG_RXN_10 PEG_TXP_10 PEG_TXN_10 PEG_RXP_11 PEG_RXN_11 PEG_RXP_12 PEG_RXN_12 PEG_RXP_13 PEG_RXN_13 PEG_RXP_14 PEG_RXN_14 PEG_RXP_15 PEG_RXN_15 PEG_TXP_11 PEG_TXN_11 PEG_TXP_12 PEG_TXN_12 PEG_TXP_13 PEG_TXN_13 PEG_TXP_14 PEG_TXN_14 PEG_TXP_15 PEG_TXN_15 B25 A25 PEG_CTX_GRX_P15 0.22U_0402_16V7K PEG_CTX_GRX_N15 0.22U_0402_16V7K 2 1VGA@ CC2 1VGA@ CC4 B24 C24 PEG_CTX_GRX_P14 0.22U_0402_16V7K PEG_CTX_GRX_N14 0.22U_0402_16V7K 2 1VGA@ CC11 1VGA@ CC12 B23 A23 PEG_CTX_GRX_P13 0.22U_0402_16V7K PEG_CTX_GRX_N13 0.22U_0402_16V7K 2 1VGA@ CC13 1VGA@ CC15 B22 C22 PEG_CTX_GRX_P12 0.22U_0402_16V7K PEG_CTX_GRX_N12 0.22U_0402_16V7K 2 1VGA@ CC8 1VGA@ CC18 B21 A21 PEG_CTX_GRX_P11 0.22U_0402_16V7K PEG_CTX_GRX_N11 0.22U_0402_16V7K 2 1VGA@ CC9 1VGA@ CC21 B20 C20 PEG_CTX_GRX_P10 0.22U_0402_16V7K PEG_CTX_GRX_N10 0.22U_0402_16V7K 2 1VGA@ CC22 1VGA@ CC24 B19 A19 PEG_CTX_GRX_P9 PEG_CTX_GRX_N9 0.22U_0402_16V7K 0.22U_0402_16V7K 2 1VGA@ CC26 1VGA@ CC28 B18 C18 PEG_CTX_GRX_P8 PEG_CTX_GRX_N8 0.22U_0402_16V7K 0.22U_0402_16V7K 2 1VGA@ CC30 1VGA@ CC32 A17 B17 PEG_CTX_GRX_P7 PEG_CTX_GRX_N7 0.22U_0402_16V7K 0.22U_0402_16V7K 2 1VGA@ CC34 1VGA@ CC36 C16 B16 PEG_CTX_GRX_P6 PEG_CTX_GRX_N6 0.22U_0402_16V7K 0.22U_0402_16V7K 2 1VGA@ CC38 1VGA@ CC40 A15 B15 PEG_CTX_GRX_P5 PEG_CTX_GRX_N5 0.22U_0402_16V7K 0.22U_0402_16V7K 2 1VGA@ CC42 1VGA@ CC44 C14 B14 PEG_CTX_GRX_P4 PEG_CTX_GRX_N4 0.22U_0402_16V7K 0.22U_0402_16V7K 2 1VGA@ CC46 1VGA@ CC48 A13 B13 PEG_CTX_GRX_P3 PEG_CTX_GRX_N3 0.22U_0402_16V7K 0.22U_0402_16V7K 2 1VGA@ CC50 1VGA@ CC52 C12 B12 PEG_CTX_GRX_P2 PEG_CTX_GRX_N2 0.22U_0402_16V7K 0.22U_0402_16V7K 2 1VGA@ CC54 1VGA@ CC56 A11 B11 PEG_CTX_GRX_P1 PEG_CTX_GRX_N1 0.22U_0402_16V7K 0.22U_0402_16V7K 2 1VGA@ CC58 1VGA@ CC60 C10 B10 PEG_CTX_GRX_P0 PEG_CTX_GRX_N0 0.22U_0402_16V7K 0.22U_0402_16V7K 2 1VGA@ CC62 1VGA@ CC64 B8 A8 DMI_CTX_PRX_P0 DMI_CTX_PRX_N0 C6 B6 DMI_CTX_PRX_P1 DMI_CTX_PRX_N1 B5 A5 DMI_CTX_PRX_P2 DMI_CTX_PRX_N2 D4 B4 DMI_CTX_PRX_P3 DMI_CTX_PRX_N3 PEG_CTX_C_GRX_P15 PEG_CTX_C_GRX_N15 PEG_CTX_C_GRX_P14 PEG_CTX_C_GRX_N14 PEG_CTX_C_GRX_P13 PEG_CTX_C_GRX_N13 PEG_CTX_C_GRX_P12 PEG_CTX_C_GRX_N12 PEG_CTX_C_GRX_P11 PEG_CTX_C_GRX_N11 PEG_CTX_C_GRX_P10 PEG_CTX_C_GRX_N10 PEG_CTX_C_GRX_P9 PEG_CTX_C_GRX_N9 PEG_CTX_C_GRX_P8 PEG_CTX_C_GRX_N8 PEG_CTX_C_GRX_P7 PEG_CTX_C_GRX_N7 PEG_CTX_C_GRX_P6 PEG_CTX_C_GRX_N6 PEG_CTX_C_GRX_P5 PEG_CTX_C_GRX_N5 PEG_CTX_C_GRX_P4 PEG_CTX_C_GRX_N4 PEG_CTX_C_GRX_P3 PEG_CTX_C_GRX_N3 PEG_CTX_C_GRX_P2 PEG_CTX_C_GRX_N2 PEG_CTX_C_GRX_P1 PEG_CTX_C_GRX_N1 PEG_CTX_C_GRX_P0 PEG_CTX_C_GRX_N0 +VCCIO RC6 24.9_0402_1% PEG_RCOMP G2 PEG_RCOMP Trace Width/Space: 15 mil/ 15 mil Max Trace Length: 600 mil DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 To PCH DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 D8 E8 DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 E6 F6 DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 D5 E5 DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 J8 J9 DMI_RXP_0 DMI_RXN_0 DMI_TXP_0 DMI_TXN_0 DMI_RXP_1 DMI_RXN_1 DMI_TXP_1 DMI_TXN_1 DMI_RXP_2 DMI_RXN_2 DMI_TXP_2 DMI_TXN_2 DMI_RXP_3 DMI_RXN_3 OF 13 DMI_TXP_3 DMI_TXN_3 DMI_CTX_PRX_P0 DMI_CTX_PRX_N0 DMI_CTX_PRX_P1 DMI_CTX_PRX_N1 To PCH DMI_CTX_PRX_P2 DMI_CTX_PRX_N2 DMI_CTX_PRX_P3 DMI_CTX_PRX_N3 CFL-H_BGA1440 @ 4 Compal Secret Data Security Classification 2017/11/23 Issued Date Deciphered Date 2018/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D CFL-H(4/8)PEG/DMI Size Document Number Custom Rev 0.1 EH78F M/B LA-G161PR01 Date: A Compal Electronics, Inc W ednesday, January 16, 2019 Sheet E of 102 A B C D E CFL-H UC1E PCH_CPU_BCLK_P PCH_CPU_BCLK_N PCH_CPU_BCLK_P PCH_CPU_BCLK_N PCH_CPU_PCIBCLK_P PCH_CPU_PCIBCLK_N PCH_CPU_24M_CLK_P 571391_CFL_H_PDG_Rev0p5 PCH_CPU_24M_CLK_N The total Length of Data and Clock (from CPU to each VR) must be equal (±0.1 inch) Route the Alert signal between the Clock and the Data signals Place those resistors close CPU side B31 A32 PCH_CPU_PCIBCLK_P PCH_CPU_PCIBCLK_N D35 C36 PCH_CPU_24M_CLK_P PCH_CPU_24M_CLK_N E31 D31 BCLKP BCLKN CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 PCI_BCLKP PCI_BCLKN CLK24P CLK24N Sensitive CPU_SVID_CLK CPU_SVID_ALERT# CPU_SVID_CLK CPU_SVID_DAT H_PROCHOT#_R BH31 BH32 BH29 BR30 DDR_PG_CTRL BT13 VIDALERT# VIDSCK VIDSOUT PROCHOT# DDR_VTT_CNTL CFG_17 CFG_16 CFG_19 CFG_18 VCCST_PWRGD BPM#_0 BPM#_1 BPM#_2 BPM#_3 Sensitive EC_VCCST_PG 0_0402_5% H_CPUPW RGD H_PLTRST_CPU# H_PM_SYNC_R H_PM_DOW N H_PECI H_THERMTRIP# BT31 BP35 BM34 BP31 BT34 J31 TP@ TC5 SKTOCC# BR33 BN1 TP@ TC6 CATERR# BM30 H_CPUPW RGD H_PLTRST_CPU# H_PM_SYNC_R H_PECI PCH_THERMTRIP#_R RC17 @ PROC_SELECT# should be unconnected on CFL processor EDS1.2 8/21 H13 PROCPWRGD RESET# PM_SYNC PM_DOWN PECI THERMTRIP# CATERR# CFG_RCOMP CFG0 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 AU13 AY13 CFG0 CFG2 CFG4 CFG5 CFG6 CFG7 TC22 TP@ disable eDP XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 BR27 BT27 BM31 BT30 BT28 BL32 BP28 BR28 CPU_XDP_TDO CPU_XDP_TDI CPU_XDP_TMS CPU_XDP_TCK0 BP30 BL30 BP27 CPU_XDP_TRST# XDP_PREQ# XDP_PRDY# CFG_RCOMP RC18 BT25 TC1 TC2 TC3 TC4 RC7 RC8 RC9 RC10 RC11 RC12 1 1 1 @ @ @ @ @ 2 2 2 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% 1K_0402_5% The CFG signals have a default value of '1' if not terminated on the board CFG[0]: Stall reset sequence after PCU PLL lock until de-asserted * = (Default) Normal Operation; = Stall CFG[2]: PCI Express* Static x16 Lane Numbering Reversal = Normal operation * = Lane numbers reversed CFG[4]: eDP enable: * = Disabled = Enabled CFG[6:5]: PCI Express* Bifurcation: 00 = x8, x4 PCI Express* 01 = reserved 10 = x8 PCI Express* * 11 = x16 PCI Express* BN23 BP23 BP22 BN22 ZVM# MSM# H_CPUPW RGD EMC@ CC66 1000P_0402_50V7K PROC_TRST# PROC_PREQ# PROC_PRDY# SKTOCC# PROC_SELECT# AT13 AW13 XEMC@ CC65 1U_0402_16V7K PROC_TDO PROC_TDI PROC_TMS PROC_TCK BN25 BN27 BN26 BN28 BR20 BM20 BT20 BP20 BR23 BR22 BT23 BT22 BM19 BR19 BP19 BT19 TP@ TP@ TP@ TP@ CFG[7]: PEG Training: * = (default) PEG Train immediately following RESET# de assertion = PEG Wait for BIOS for training *CFG Pin Use CMC debug on DDX03 R02 Schematic CPU_XDP_TDO CPU_XDP_TDI CPU_XDP_TMS CPU_XDP_TCK0 To be confirm CPU_XDP_TRST# TC19 TP@ TC20 TP@ XDP_PREQ# XDP_PRDY# 49.9_0402_1% XDP_PREQ# XDP_PRDY# Trace Width/Space: mil/ 12 mil Max Trace Length: 600 mil RSVD1 RSVD2 H_PROCHOT#_R OF 13 +1.05VS_VCCSTG XEMC@ CC67 1U_0402_16V7K H_THERMTRIP# EMC@ CC68 1000P_0402_50V7K EC_VCCST_PG Near CPU Place to CPU side side Request +1.05V_VCCST 1K_0402_5% H_THERMTRIP# DDR_PG_CTRL 3 +1.05VS_VCCSTG NC VCC A Y RC23 330K_0402_5% CC69 UC3 1U_0402_16V7K SM_PG_CTRL CMC@ 51_0402_5% RC77 CMC@ 51_0402_5% CPU_XDP_TDI RC78 CMC@ 51_0402_5% CPU_XDP_TDO RC79 CMC@ 51_0402_5% CPU_XDP_TCK0 RC81 @ 51_0402_5% CPU_XDP_TRST# RC80 @ 51_0402_5% PCH_JTAG_TCK1 Place to CPU side RH1 GND PCH_JTAG_TCK1 SM_PG_CTRL PU 330K follow CRB 8/21 Place to PCH side 74AUP1G07GW _TSSOP5 CPU_XDP_TMS RC76 +3VS +1.2V_VDDQ follow 1050 8/21 CFL-H_BGA1440 @ RC21 1K_0402_5% SVID RC14 H_PROCHOT# 499_0402_1% H_PROCHOT#_R +1.05V_VCCST RC22 1K_0402_5% EC_VCCST_PG_R RC16 H_PM_DOW N_R 20_0402_5% H_PM_DOW N EC_VCCST_PG CPU_SVID_ALERT#_R RC20 100_0402_1% RC13 1 60.4_0402_1% RC19 56_0402_1% RC15 1 1 +1.05V_VCCST @ CPU_SVID_ALERT# CPU_SVID_DAT CPU_SVID_DAT RH2 13_0402_5% 220_0402_5% Compal Secret Data Security Classification 2017/11/23 Issued Date Deciphered Date 2018/09/01 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D CFL-H(5/8)CFG,SVID Size Document Number Custom Rev 0.1 EH78F M/B LA-G161PR01 Date: A Compal Electronics, Inc W ednesday, January 16, 2019 Sheet E 10 of 102 D D @EMI@ PC7204 680P_0402_50V7K @EMI@ PR7202 4.7_1206_5% SNB_+VCCIOP 11 +VCCIOP_ILMT 13 15 EN NC ILMT NC BYP NC PAD 10 12 FB = 0.6V 21 +3VALW and PC15 @ PR7210 0_0402_5% SUSP# PR7214 1K_0402_5% PC7212 22U_0603_6.3V6M VCCIO_SENSE @ PR7218 0_0402_5% VSSIO_SENSE VCCIO_SENSE VSSIO_SENSE +VCCIOP_EN 2 check delay time with HW PC7218 0.1U_0402_25V6 SUSP# PR7215 1M_0402_5% VR_ON @ PR7208 0_0402_5% C VR_ON +VCCIOP_ILMT B Vout=0.6V* (1+Rup/Rdown) =0.6*(1+(12k/20.5k)) OVP=0.95V*115%=1.0925V Vout=0.951 V 2% VCCIO_SENSE_R +VCCIOP_LDO_3V @ PR7213 0_0402_5% Rup PR7205 12K_0402_1% SY8286RAC_QFN20_3X3 @ 16 Pin BYP is for CS Common NB can delete @ PR7211 0_0402_5% PC7211 22U_0603_6.3V6M +VCCIOP_LDO_3V PC7216 2.2U_0402_6.3V6M PC7210 22U_0603_6.3V6M 17 1 +VCCIOP_FB 14 PC7209 22U_0603_6.3V6M VCC PC7208 22U_0603_6.3V6M GND +VCCIOP FB 20 PC7207 22U_0603_6.3V6M LX GND 19 GND PC7217 1U_0201_6.3V6M +3VALW LX Ipeak=6.42A, Iocp:7.7A PL7201 0.68UH_7.9A_20%_5X5X3_M Rdown C +VCCIOP_EN IN +VCCIOP_LX PR7203 10_0402_1% 18 LX IN Imax=4.5A, 5X5X3 Isat:14A DCR: 12mΩ(Max) (Common Part) SH00000Z300 BS @ PR7201 PC7205 0_0603_5% 0.1U_0402_25V7K +VCCIOP_BST +VCCIOP_BST_R IN PR7204 1K_0402_1% PG PR7206 20.5K_0402_1% IN PC7215 10U_0603_25V6M JUMP_43X79 PC7206 330P_0402_50V7K PU7201 +19VB_VCCIO PC7203 10U_0603_25V6M 2 @EMI@ PC7202 0.1U_0402_25V6 1 @EMI@ PC7201 2200P_0402_50V7K 1 @ PJ7201 +19VB B The current limit is set to 6.5A, 9.5A or 12.5A when this pin is pull low, floating or pull high @ PJ7202 +VCCIOP 1 2 +VCCIO JUMP_43X118 A A Compal Secret Data Security Classification Issued Date 2016/02/01 2017/12/31 Deciphered Date Title 0.95VS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev 0.1 Wednesday, January 16, 2019 Sheet 88 of 102 Place close to Choke in VCCSA first phase circuit PC808 1000P_0402_50V7K PR873 +VCC_CORE PR817 12.4K_0402_1% 100_0402_1% 2 VSSSENSE PR874 PC812 1000P_0402_50V7K PR824 1K_0402_1% PR823 0_0402_5% 100_0402_1% 2 PR820 34.8K_0402_1% @ PR822 0_0402_5% 2 PR808 45.3_0402_1% PR807 45.3_0402_1% PR806 100_0402_1% PR805 499_0402_1% VCCCORE_VR_PWRGD CPU_EN 81215_SCLK 81215_ALERT 81215_SDIO VSP_4PH PWM1_1PH/ICCMAX1 PR815 10K_0402_1% PR819 PC810 1.5K_0402_1% 0.01U_0402_25V7K 2 @ PR821 0_0402_5% VCCSENSE PR812 @ 100_0402_1% LA-F611PR01_0531C.DSN 81215_VR_HOT PCH_PWROK change to IMVP_VR_PG(P.72 PUZ01.45) +3VS PC809 1000P_0402_50V7K PC806 2200P_0402_50V7K CSN_1PH_R PC805 3300P_0402_50V7-K PR813 29.4K_0402_1% 100_0402_1% CSP_1PH PR811 1.65K_0402_1% VSP_1PH 2 IMON_1PH PR876 +VCC_SA +1.05V_VCCST @ PC807 470P_0402_50V8J VCCSA_SENSE PR1199 NA, need confirm SW_1PH PC803 0.1U_0402_25V6 A LA-F611PR01_0531D.DSN PROCHOT# change to H_PROCHOT#(P.72 PUZ01.39) VR_HOT# 81215_SCLK PR814 49.9_0402_1% CPU_SVID_CLK 81215_ALERT PR816 0_0402_5% CPU_SVID_ALERT#_R 81215_SDIO PR818 10_0402_1% CPU_SVID_DAT VR_ON LA-F611PR01_0531C.DSN IMVP_VR_ON change to VR_ON(P.72 PUZ01.43) PC811 15P_0402_50V8J VSN_4PH VSN_1PH VSP_1PH PC813 2200P_0402_50V7K COMP_1PH ILIM_1PH PC804 1000P_0402_50V7K @ PR810 0_0402_5% VSN_1PH PR803 7.5K_0603_1% PC802 0.01UF_0402_25V7K PR804 10_0402_1% PR809 1K_0402_5% VSSSA_SENSE @ PR801 0_0402_5% A PH801 PR802 100K_0402_1%_TSM0B104F4251RZ 12K_0402_1% 2 100_0402_1% CSN_1PH PR875 PC801 2200P_0402_50V7K H82@ PR829 24.9K_0402_1% VSP_4PH VSN_4PH PC821 470P_0402_50V8J 1 10 11 12 13 SW3_4PH PR859 97.6K_0402_1% TSENSE_4PH CSP4_4PH @ PR868 100K_0402_1% PC838 0.1U_0402_25V6 CSREF_4PH 2 PR865 1.62K_0402_1% 2 SW4_4PH PWM4_4PH/ROSCM @ PR864 100K_0402_1% CSREF_4PH C PWM2_4PH/ADDR CSP3_4PH PC837 0.1U_0402_25V6 PWM2_2PH/ROSC1 PWM3_4PH/VBOOT CSREF_4PH PR863 1.62K_0402_1% 2 DRVON @ PR862 100K_0402_1% PC836 0.1U_0402_25V6 CSP2_4PH SW2_4PH PWM1_4PH/ICCMAX4 @ PR854 100K_0402_1% CSP1_4PH CSREF_4PH PR861 1.62K_0402_1% +5VALW PC834 0.1U_0402_25V6 C PR850 2.2_0603_5% PR851 24.9K_0402_1% H82@ PR855 110K_0402_1% +5VALW CSP4_4PH H62@ PR855 100K_0402_1% +5VALW PR853 1.62K_0402_1% Place close to H-side,L-side MOS in VCORE first phase SW1_4PH @ PR847 1K_0402_1% 14 15 16 17 18 19 20 21 22 23 24 25 26 PC831 0.01U_0402_50V7K PC830 0.1U_0402_25V6 TSENSE_4PH PC833 1U_0402_6.3V6K CSREF_4PH CSREF_4PH PR840 1K_0402_1% PR858 97.6K_0402_1% 2 1 2 CPU_B+ PR848 1K_0402_1% 81215_VR_HOT 39 38 37 36 35 34 33 32 31 30 29 28 27 SW4_4PH 0.1U_0402_25V7K SW3_4PH PC824 VRHOT# VSP_2PH VSN_2PH IMON_2PH DIFFOUT_2PH FB_2PH COMP_2PH ILIM_2PH CSCOMP_2PH CSSUM_2PH CSREF_2PH CSP1_2PH CSP2_2PH PR866 0_0402_5% SW2_4PH CSP1_4PH CSP2_4PH CSP3_4PH B PR841 130K_0603_1% PR845 130K_0603_1% PR846 130K_0603_1% PR849 130K_0603_1% PC826 680P_0402_50V7K SW1_4PH ILIM_4PH 30.1K_0402_1% VSP_4PH VSN_4PH IMON_4PH DIFFOUT_4PH FB_4PH COMP_4PH ILIM_4PH CSCOMP_4PH CSSUM_4PH CSREF_4PH CSP1_4PH CSP2_4PH CSP3_4PH PR842 165K_0402_1% 220K_0402_5%_ERTJ0EV224J PR836 CSCOMP_4PH CSSUM_4PH PC825 470P_0402_50V8J 1 PH802 PR838 75K_0402_1% DIFFOUT_4PH FB_4PH COMP_4PH PR857 24.9K_0402_1% PC818 2200P_0402_50V7K Place close to Choke in VCORE first phase circuit 52 51 50 49 48 47 46 45 44 43 42 41 40 53 PR830 1K_0402_1% PU801 NCP81215MNTXG_QFN52_6X6 VSP_1PH VSN_1PH COMP_1PH ILIM_1PH CSN_1PH CSP_1PH IMON_1PH VR_RDY PWM_1PH/ICCMAX_1PH EN SCLK ALERT# SDIO PR856 4.32K_0402_1% 1 H62@ PR829 26.7K_0402_1% TAB PR831 3.65K_0402_1% PR828 PC817 49.9_0402_1% 470P_0402_50V8J 2 TSENSE_4PH VRMP VCC DRON PWM1_4PH/ICCMAX_4PH PWM2_4PH/ADDR PWM3_4PH/VBOOT PWM4_4PH/ROSC_MPH PWM2_2PH/ROSC_1PH PWM1_2PH/ICCMAX_2PH TTSENSE_1PH/PSYS TTSENSE_2PH CSP4_4PH PC816 15P_0402_50V8J B PH804 PR869 61.9K_0402_1% 2 220K_0402_5%_ERTJ0EV224J D D Compal Secret Data Security Classification Issued Date 2016/02/01 Deciphered Date 2017/12/31 Title Compal Electronics, Inc THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Document Number Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 0.1 CPU IC SKL_H 42 Date: Wednesday, January 16, 2019 Sheet 89 of 102 Main Func = CORE @ +VCC_CORE TDC 86A Peak Current 140A OCP Current 168A DCR 1mohm +/-5% PC909 10U_0603_25V6M PC908 10U_0603_25V6M @ PC907 10U_0603_25V6M 1 PC906 10U_0603_25V6M 2@ + @EMI@ PC905 0.1U_0402_25V6 1 + 2 @EMI@ PC904 2200P_0402_50V7K + PC903 100U_D3L_25VM_R60M PC902 33U_D2_25VM_R40M EMI@ PL902 5A_Z80_0805_2P PC901 33U_D2_25VM_R40M CPU_B+ EMI@ PL901 5A_Z80_0805_2P +19VB +5VALW D PR902 PC911 4.7_0603_1% 0.22U_0603_25V7K 2CORE_BST1_R CORE_PHASE1 +VCC_CORE PR905 10_0402_1% 0.22UH_SRPG1003-R22M-AD-1D0E_30A_20% CSREF_4PH PC917 10U_0603_25V6M PC916 10U_0603_25V6M CORE_PHASE2 PL904 NC AGND 18 EMI@ PR907 4.7_1206_5% CORE_SW2 11 12 +VCC_CORE PR908 10_0402_1% 0.22UH_SRPG1003-R22M-AD-1D0E_30A_20% CSREF_4PH NCP302045MNTXG_PQFN33_5X5 rating: TDC:45A TDP:75A EMI@ PC923 680P_0402_50V7K PC929 10U_0603_25V6M PC928 10U_0603_25V6M PC927 10U_0603_25V6M PC926 10U_0603_25V6M @EMI@ PC925 0.1U_0402_25V6 CGND PGND PGND GL GL SW SW CORE_BST2 CORE_PHASE3 SW2_4PH CORE_SW3 10x10x3 Isat:50A DCR:1mΩ+/-5% PL905 +VCC_CORE PR913 4.7_0603_1% 2 DRVON PC942 2.2U_0402_6.3V6M PWM4_4PH/ROSCM +5VALW VCC VCCD THWN DISB# PWM SMOD# 10 14 13 19 CGND PGND PGND GL GL VIN VIN BOOT PHASE SW SW NC AGND CORE_BST4 CORE_PHASE4 SH000013N00 10x10x3 Isat:50A DCR:1mΩ+/-5% PL906 CORE_SW4 11 12 PC937 10U_0603_25V6M PC936 10U_0603_25V6M @ PC940 0.22U_0603_25V7K CORE_BST4_R +VCC_CORE 1 PU904 PVCC_CORE4 15 @ PR930 0_0402_5% 17 16 @ PR931 0_0402_5% 2 @ 18 EMI@ PR916 4.7_1206_5% 2 PR911 2_0603_5% PC939 1U_0402_6.3V6K +5VALW PC935 10U_0603_25V6M CPU_B+ PR915 0.22UH_SRPG1003-R22M-AD-1D0E_30A_20% 10_0402_1% CSREF_4PH 2 EMI@ PC941 680P_0402_50V7K SW3_4PH NCP302045MNTXG_PQFN33_5X5 rating: TDC:45A TDP:75A B CSREF_4PH 18 PR912 0.22UH_SRPG1003-R22M-AD-1D0E_30A_20% 10_0402_1% PC934 10U_0603_25V6M NC AGND BOOT PHASE SH000013N00 10x10x3 Isat:50A DCR:1mΩ+/-5% PC931 0.22U_0603_25V7K CORE_BST3_R SH000013N00 CORE_BST3 11 12 THWN DISB# PWM SMOD# VIN VIN SW SW @ 10 14 13 19 VCC VCCD 1 CGND PGND PGND GL GL BOOT PHASE THWN DISB# PWM SMOD# VIN VIN B 10 14 13 19 VCC VCCD @ EMI@ PR914 4.7_1206_5% +5VALW PR910 4.7_0603_1% PU903 PVCC_CORE3 15 @ PR928 0_0402_5% 17 16 @ PR929 0_0402_5% 2 2 2 DRVON PC938 2.2U_0402_6.3V6M PWM3_4PH/VBOOT PC930 1U_0402_6.3V6K PR909 2_0603_5% @EMI@ PC924 2200P_0402_50V7K +5VALW +5VALW @ PR906 PC920 4.7_0603_1% 0.22U_0603_25V7K 2CORE_BST2_R PU902 PVCC_CORE2 15 @ PR926 0_0402_5% 17 @ PR927 0_0402_5% 16 DRVON 1 PC922 2.2U_0402_6.3V6M PWM2_4PH/ADDR CPU_B+ @ C PC919 1U_0402_6.3V6K C 2 PR903 2_0603_5% EMI@ PC921 680P_0402_50V7K +5VALW PC915 10U_0603_25V6M CPU_B+ SW1_4PH rating: TDC:45A TDP:75A PC914 10U_0603_25V6M 18 NCP302045MNTXG_PQFN33_5X5 NC AGND PL903 CORE_SW1 CGND PGND PGND GL GL CORE_BST1 11 12 @EMI@ PC913 0.1U_0402_25V6 SW SW @EMI@ PC933 0.1U_0402_25V6 10 14 13 19 BOOT PHASE @EMI@ PC932 2200P_0402_50V7K THWN DISB# PWM SMOD# SH000013N00 10x10x3 Isat:50A DCR:1mΩ+/-5% EMI@ PR904 4.7_1206_5% VIN VIN +5VALW VCC VCCD @EMI@ PC912 2200P_0402_50V7K PU901 PVCC_CORE1 15 @ PR924 0_0402_5% 17 16 @ PR925 0_0402_5% DRVON PC918 2.2U_0402_6.3V6M PWM1_4PH/ICCMAX4 2 PR901 2_0603_5% PC910 1U_0402_6.3V6K D NCP302045MNTXG_PQFN33_5X5 SW4_4PH rating: TDC:45A TDP:75A Compal Secret Data Security Classification Issued Date A EMI@ PC943 680P_0402_50V7K A 2016/02/01 Deciphered Date 2017/12/31 Title CPU_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev 0.1 Wednesday, January 16, 2019 Sheet 90 of 102 Main Func = VCCGT/+VCCSA CPU_B+ PR922 4.7_0603_1% PU906 PC961 2.2U_0402_6.3V6M DRVON PWM1_1PH/ICCMAX1 15 17 16 10 14 13 19 VCC VCCD THWN DISB# PWM SMOD# CGND PGND PGND GL GL VIN VIN BOOT PHASE SW SW NC AGND PC960 BST_SA_R 0.22U_0603_25V7K BST_SA +VCCSA TDC PL2 :10A Peak Current 11A OCP Current 13A DCR 6.2mohm +/-5% Load Line 10.3mV/A SH000015M00 5X5X3 Isat:16A DCR:6.2mΩ+/-5% C PL908 0.47UH_MMD05CZR47M_12A_20% PHASE_SA SW_SA 11 12 PC958 10U_0603_25V6M PC957 10U_0603_25V6M 1 @ PVCC_SA C @ 18 +VCC_SA CSN_1PH B SW_1PH EMI@ PC962 680P_0402_50V7K 2 NCP302035MNTXG_PQFN33_5X5 EMI@ PR923 4.7_1206_5% 2_0603_5% PC959 1U_0402_6.3V6K PC956 10U_0603_25V6M PR921 2 +5VALW PC955 10U_0603_25V6M D @EMI@ PC954 0.1U_0402_25V6 D B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 Deciphered Date 2017/01/06 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: +VCC_GT/+VCC_SA Document Number Rev 0.1 C1PRG LA-E051P Wednesday, January 16, 2019 Sheet 91 of 102 2 2 2 2 Issued Date PC9064 1U_0201_6.3V6M PC9063 1U_0201_6.3V6M @ PC9065 1U_0201_6.3V6M 1 X 220uF X 330uF 18 X22uF_0603 12+8@ X1uF_0201 C Security Classification 2016/02/01 @ @ PC9067 1U_0201_6.3V6M PC9066 1U_0201_6.3V6M @ @ @ PC9068 1U_0201_6.3V6M 1 @ @ PC9069 1U_0201_6.3V6M 1 @ PC9070 1U_0201_6.3V6M PC9004 22U_0603_6.3V6M PC9005 22U_0603_6.3V6M PC9006 22U_0603_6.3V6M PC9007 22U_0603_6.3V6M PC9008 22U_0603_6.3V6M PC9009 22U_0603_6.3V6M PC9010 22U_0603_6.3V6M PC9011 22U_0603_6.3V6M PC9014 1U_0201_6.3V6M PC9015 1U_0201_6.3V6M PC9016 1U_0201_6.3V6M PC9017 1U_0201_6.3V6M PC9018 1U_0201_6.3V6M PC9019 1U_0201_6.3V6M PC9020 1U_0201_6.3V6M PC9021 1U_0201_6.3V6M PC9022 1U_0201_6.3V6M PC9041 1U_0201_6.3V6M PC9042 1U_0201_6.3V6M PC9043 1U_0201_6.3V6M PC9044 1U_0201_6.3V6M PC9045 1U_0201_6.3V6M PC9046 1U_0201_6.3V6M PC9047 1U_0201_6.3V6M PC9048 1U_0201_6.3V6M PC9040 1U_0201_6.3V6M 2 PC9012 22U_0603_6.3V6M PC9013 1U_0201_6.3V6M 1 PC9003 22U_0603_6.3V6M PC9039 1U_0201_6.3V6M 2 PC9038 22U_0603_6.3V6M @ PC9062 1U_0201_6.3V6M PC9037 22U_0603_6.3V6M 2 PC9036 22U_0603_6.3V6M @ PC9061 1U_0201_6.3V6M PC9035 22U_0603_6.3V6M PC9140 22U_0603_6.3V6M PC9034 22U_0603_6.3V6M @ PC9139 22U_0603_6.3V6M PC9033 22U_0603_6.3V6M Deciphered Date + 2 @ @ PC9023 220U_D7_2VM_R4.5M 1 @ PC9082 22U_0603_6.3V6M PC9138 22U_0603_6.3V6M PC9032 22U_0603_6.3V6M @ PC9081 22U_0603_6.3V6M PC9080 22U_0603_6.3V6M PC9137 22U_0603_6.3V6M PC9031 22U_0603_6.3V6M PC9002 22U_0603_6.3V6M + THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 2017/12/31 + @ PC9025 220U_D7_2VM_R4.5M Date: + @ PC9026 220U_D7_2VM_R4.5M + @ PC9050 220U_D7_2VM_R4.5M + PC9051 220U_D7_2VM_R4.5M +VCC_CORE PC9024 220U_D7_2VM_R4.5M PC9079 22U_0603_6.3V6M 1 PC9078 22U_0603_6.3V6M PC9077 22U_0603_6.3V6M @ PC9100 1U_0201_6.3V6M PC9136 22U_0603_6.3V6M PC9030 22U_0603_6.3V6M PC9076 22U_0603_6.3V6M PC9099 1U_0201_6.3V6M 1 PC9135 22U_0603_6.3V6M PC9029 22U_0603_6.3V6M PC9075 22U_0603_6.3V6M PC9134 22U_0603_6.3V6M 1 PC9098 1U_0201_6.3V6M 2 2 PC9074 22U_0603_6.3V6M 1 PC9096 1U_0201_6.3V6M 2 2 PC9073 22U_0603_6.3V6M 1 PC9145 22U_0603_6.3V6M 2 PC9144 22U_0603_6.3V6M 1 PC9133 22U_0603_6.3V6M PC9028 22U_0603_6.3V6M PC9095 1U_0201_6.3V6M B 2 PC9143 22U_0603_6.3V6M @ 1 PC9142 22U_0603_6.3V6M 2 PC9141 22U_0603_6.3V6M 1 PC9132 22U_0603_6.3V6M 2 PC9131 22U_0603_6.3V6M 1 PC9130 22U_0603_6.3V6M PC9001 22U_0603_6.3V6M A PC9027 22U_0603_6.3V6M PC9049 22U_0603_6.3V6M +VCC_CORE A 2+1 @ X 220uF 36+5 @ X22uF_0603 24+6 @ X1uF_0201 B +VCC_SA SE00000M000 Total VCCSA Output Capacitor: X 1uF_0201 7+3@ X22uF_0603 SE00000UC00 C D D Compal Secret Data Size Document Number Custom Title Processor decoupling Wednesday, January 16, 2019 Sheet 92 of 102 Rev 0.1 SKL_H 42 @ PCV1 0.1U_0402_25V6 @ PRV1 0_0402_5% PRV3 2 12.4K_0402_1% B O A @ PRV155 0_0402_5% GPU_DRVON @ PRV54 @ PRV56 @ PRV58 @ PRV60 @ PRV62 @ PRV65 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% GPU_PWM1 GPU_PWM2 GPU_PWM3 GPU_PWM4 GPU_PWM5 GPU_PWM6 2016/01/06 Issued Date Deciphered Date @ PCV8 0.1U_0402_25V6 2 @ PCV17 0.1U_0402_25V6 FDMF3170_REFIN