Alienware 17 r4 compal LA d751p rev 1 0 схема

A ZZZ B C D E MODEL NAME : BAP10(15")/BAP20(17") PROJECT CODE : ANRBAP1000/ANRBAP2000 PCB NO : DAC00004000 LA-D751P M/B(NV) DAC00005000 LA-D751P M/B(NV_G3) DA4002AV000 LS-D751P LOGO_15/B DA80017I000 LS-D752P LOGO_17/B DA4002B000S LS-D753P PWR_15/B DA4002AW000 LS-D754P PWR_17/B DA80017J000 LS-D755P IO_12L/B DA4002AY000 LS-D757P TRON_LCD_15/B DA4002AZ000 LS-D758P TRON_REAR_15/B DA80017K000 LS-D759P IO_14L/B DA4002D4000 LS-D75AP TRON_LCD_17/B DA4002D5000 LS-D75BP TRON_REAR_17/B DA4002D7000 LS-D75CP TRON_FRONT_15/B DA4002D8000 LS-D75DP TRON_FRONT_17/B DA30000W300 LF-D751P Head_15/B DA30000W400 LF-D752P Head_17/B DA30000W401 LF-D752P Head_17/B(For LOGO_15/B) DA30000SY00 LF-D753P TRON_15/B DA30000WX00 LF-D754P TRON_17/B BAP10/BAP20 Skylake/Kabylake-H 45W PCB@ PCB 1JM LA-D751P REV0 M/B NV 16 Skylake/Kabylake PCH with nVidia N17P/N17E REV : 1.0 (A00) 2016.08.15 @ : Nopop Component EMI@,ESD@,RF@ : EMI/ESD/RF part CONN@ : Connector Component @EMI@,@ESD@,@RF@ : Total debug Component DAC00004000 ZZZ PCBR1@ PCB 1JM LA-D751P REV1 M/B NV 16 DAC00004010 ZZZ PCBR3@ PCB 1JM LA-D751P REV1 MB NV TRIP 16 A31! DAC00004011 ZZZ DAZR1@ PCB BAP10 LA-D751P LS-D751P-2P/D754P/D757P-DP 02 DAZ1JM00100 3 ZZZ DAZR3@ PCB BAP10 LA-D751P LS-D751P-2P/D754P/D757P-DP 02 TRI A31 ! DAZ1JM00101 HDMI@ ROYALTY HDMI W/LOGO Part Number RO0000003HM Description HDMI W/Logo:RO0000003HM Layout Dell logo COPYRIGHT 2015 ALL RIGHT RESERVED REV: X00 PWB: XXXXX DATE: 1450-06 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Cover Page Size A B C D Document Number Rev 1.0 LA-D751P Date: Friday, August 19, 2016 Sheet E of 82 A B C D E Block Diagram ~ P P P 5 ~ P P eDP 1.3 Mini DP connector DP1.3 P HDMI2.0 HDMI connector nVidia N17P/N17E GPU N17PG1: 50W N17EG1: 78W N17EG2: 115W 6/8pcs GDDR5 256X32 4pcs GDDR5 128X32 ~ P P CIO/USB3.1 Thunderbolt Alpine Ridge-DP P USB3.1 TypeC connector USB PD TPS65982 I2C/USB2 PEG(Gen3)x8 port8~port15 Fan control P.42 NCT7718W W83L771AWG-2 Intel Skylake/Kabylake-H BGA CPU 45W 1440 Pins DP 1.2 (DDI 1) DP 1.2 (DDI 2) PEG(Gen3)x4 port0~port3 PEG(Gen3)x4 port4~port7 Memory Bus Dual Channel 1.2V DDR4 (X.M.P) 1866/2133/2400/2666 MHz P.14 15 DDR4-SODIMM x2 P P DMI x PCIe Re-driver DS80PCI402 2 ~ P Caldera connector P.33 FFS KXCNL-1010 eDP 1.3 MUX PS8331B eDP panel Support G-SYNC USB3.0 port3 P.37 USB2.0 port4 AlienFX / ELC , C8051F383 USB2.0 port3 P.25 USB2.0 port6 Touch screen P P RJ45 connector LAN(Gigabit) Killer E2400/E2500 P.2 NGFF (M.2) WLAN+BT PCI-E port5 USB2.0 port7 PCI-E port6 USB3.0 port1 USB2.0 port1 USB2.0 port5 USB3.0 port4 USB2.0 port2 Intel Skylake/Kabylake BGA PCH CM236 837 Pins P.2 NGFF (M.2) SSD1 (2 lanes) PCI-E port 13~14 SATA3.0 port P.2 NGFF (M.2) SSD2 (4 lanes) PCI-E port 17~20 SATA3.0 port USB3.0 port2 USB3.0 port5 USB2.0 port8 P.33 30 pin connector with cable 2.5” HDD x1 USB connector , lef t si de USB power share P.35 USB connector , right side USB3.0 on D/B P.35 IO/B P.36 USB connector , right side USB3.0 TypeC connector P.2 NGFF (M.2) SSD3 (4 lanes) Digital camera(with digital MIC) P.34 USB2.0 port9 PCI-E port 9~12 SATA3.0 port Tobii (17" only) P.31 SATA3.0 port ; option:HDD digital MIC Audio codec Realtek ALC3266 HD Audio P.31 Headphone/MIC Global headset combo JACK P.31 Headphone/MIC Retaskable combo JACK P.17 DC in Bat t er y 1.00V dGPU Core 3V/5V 2.5V Charger SPI ROM 128Mbit SPI P.32 PS2/SMBus P.3 Touch pad System 1.2V CPU Vcore dGPU 1.35V LPC Bus P.43 AMP ALC1309 P.43 P.4 KC3810 P.43 Int KBD + Marco Key ENE KB9022 AMP ALC1309 KC3810 2016/01/06 Deciphered Date Compal Electronics, Inc 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Block Diagram Size B C D Document Number Rev 1.0 LA-D751P Date: A IO/B Subwoofer (17" Only) on D/B Compal Secret Data Security Classification Issued Date P.32 Speaker Tuesday, August 16, 2016 E Sheet of 82 A B C D E PCB LS-D75CP TRON_FRONT_15/B LS-D75DP TRON_FRONT_17/B Led x Wire 12 Pin Wire 12 Pin LS-D75CP TRON_FRONT_15/B LS-D75DP TRON_FRONT_17/B FPC Led x Module LS-D758P TRON_REAR_15/B LS-D75BP TRON_REAR_17/B Led x LS-D759P IO_14L/B LS-D755P IO_12L/B USB3.0 x Coaxial/Wire 30 Pin Led x FFC 16 Pin 30 Pin TP module Lid Switch Led x Subwoofer (17"Only) Coaxial/Wire 30 Pin JHDD 2.5" HDD Wire Pin M/B LS-D753P PWR_15/B LS-D754P PWR_17/B LS-D758P TRON_REAR_15/B LS-D75BP TRON_REAR_17/B Touch sensor pin FFC Pin 40 Pin Coaxial/Wire 40 pin Coaxial 23 Pin eDP Panel 30 pin on / off SW Led x Wire 13 Pin KSI/KSO 30 Pin Backlight 20 Pin Wire 16 Pin KSI/KSO 10 Pin Backlight Pin IR Camera 14 pin 3 Marco Key LS-D751P LOGO_15/B LS-D752P LOGO_17/B Keyboard Led x LS-D757P TRON_LCD_15/B LS-D75AP TRON_LCD_17/B Led x LF-D753P TRON_15/B LF-D754P TRON_17/B Led x Wire 12 Pin Wire 12 Pin FFC Pin LS-D757P TRON_LCD_15/B LS-D75AP TRON_LCD_17/B Led x LF-D753P TRON_15/B LF-D754P TRON_17/B FPC Led x LF-D751P Head_15/B LF-D752P Head_17/B Led x 4 FPC Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 2017/01/06 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Cable Routing Diagram Size B C D R ev 1.0 LA-D751P Date: A Document Number Tuesday, August 16, 2016 Sheet E of 82 A Board ID Table for AD channel Vcc Ra Board ID 10 11 12 13 14 15 16 17 18 19 3.3V +/- 1% 100K +/- 1% Rb 12K +/- 1% 15K +/- 1% 20K +/- 1% 27K +/- 1% 33K +/- 1% 43K +/- 1% 56K +/- 1% 75K +/- 1% 100K +/- 1% 130K +/- 1% 160K +/- 1% 200K +/- 1% 240K +/- 1% 270K +/- 1% 330K +/- 1% 430K +/- 1% 560K +/- 1% 750K +/- 1% NC V AD_BID 0.000V 0.347V 0.423V 0.541V 0.691V 0.807V 0.978V 1.169V 1.398V 1.634V 1.849V 2.015V 2.185V 2.316V 2.395V 2.521V 2.667V 2.791V 2.905V 3.000V PCH-H CM236 V AD_BID typ 0.000V 0.354V 0.430V 0.550V 0.702V 0.819V 0.992V 1.185V 1.414V 1.650V 1.865V 2.031V 2.200V 2.329V 2.408V 2.533V 2.677V 2.800V 2.912V 3.300V V AD_BID max 0.300V 0.360V 0.438V 0.559V 0.713V 0.831V 1.006V 1.200V 1.430V 1.667V 1.881V 2.046V 2.215V 2.343V 2.421V 2.544V 2.687V 2.808V 2.919V 3.300V Voltage Rails Power Plane Descript i on S3 S0 S4 / S5 VIN Adapter power supply N/A N/A N/A Bat t er y po wer s uppl y N/A N/A N/A BATT+ AC or bat t er y po wer r ail f or po wer ci rc ui t N/A N/A N/A +19VB OFF OFF +VCC_CORE Core voltage for CPU ON OFF OFF +VCC_GT Sliced graphics power rail ON DDR +0.6VS power rail for DDR terminator OFF OFF +0.6VS_VTT ON +1VALW System +1VALW power rail ON ON ON* +1V_PRIM System +1VALW power rail ON ON ON* OFF OFF +VCCIO +1.0VS IO power rail ON +1.0VS power rail for GPU OFF OFF +VGA_PCIE ON +MEM_GFX +1.5VS power rail for GPU OFF OFF ON OFF +1.2V_VDDQ DDR-IV +1.2V power rail ON ON OFF +1VS_VCCST +1.0V power rail for CPU ON ON +1.0VS power rail for CPU OFF OFF +1VS_VCCSTG ON +3VALW System +3VALW always on power rail ON ON ON* +19VB to +3VLP power rail for suspend power +3VLP ON ON ON +3VALW_DSW +3VALW power for PCH DSW rails ON ON ON* +3V_LAN +3VALW power for LAN power rails ON ON ON* +3VS OFF OFF System +3VS power rail ON +1.8VS +1.8VS power rail for GPU OFF OFF ON +3VGS +3VS power rail for GPU OFF OFF ON +5VALW System +5VALW power rail ON ON ON* +5VS OFF OFF System +5VS power rail ON +3VL_RTC RTC power ON ON ON OFF OFF +VCC_SA System Agent power rail ON Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF EC 0x00 0x14 0x1F 0x26 0x31 0x3B 0x46 0x55 0x65 0x77 0x88 0x97 0xA5 0xB0 0xB8 0xC0 0xCA 0xD5 0xDE 0xF1 AD3 - 0x13 - 0x1E - 0x25 - 0x30 - 0x3A - 0x45 - 0x54 - 0x64 - 0x76 - 0x87 - 0x96 - 0xA4 - 0xAF - 0xB7 - 0xBF - 0xC9 - 0xD4 - 0xDD - 0xF0 - 0xFF NVIDIA Graphic AMD Graphic Board ID TABLE SKL ID NV KBL ID NV PCB Revision EVT DVT-1 DVT-1.1 DVT-2 / DVT-2.1 GC6 Pilot build PCB Revision EVT DVT-1 / DVT-1.1 GC6 DVT-2 Pilot build * USB2 JUSB1,type A 2 JUSBC2,type C JIO(IO/B) 3 Caldera Caldera 4 JIO,IO/B 5 JUSBC2,type C ELC Bluetooth 6 Touch screen 7 Camera 8 JUSBC2 9 Tobii 10 10 JUSB1(Powershare) 10 11 LAN 11 12 WLAN 12 13 13 14 14 15 16 10 17 11 18 12 22 16 21 15 20 14 19 13 23 17 24 18 25 19 26 20 JSSD3 M.2 2280 SATA PCIe x4 Symbol Note : JSSD5/HDD SATA Digital Ground JSSD1 SATA/PCIe x2 Analog Ground JSSD2 M.2 2280 SATA PCIe x4 CPU,C DDR,D GPU,DP,HDMI,EDP,V LAN,L AUDIO,A NGFF,N USB,U CALDERA,M HDD,S ELC,E FAN,F TP,T KBC,K DC,O * PCIe 13~16 in "Lane Reversal Mode" (HSIO Port 19~22) Compal Electronics, Inc Compal Secret Data 2016/01/06 Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Notes List Size Document Number R ev 1.0 LA-D751P Date: A Function USB3 Security Classification Issued Date PCIe SATA3 Function HSIO Monday, August 22, 2016 Sheet of 82 1K SMBUS Address [0x9A] +3VS 1K AW44 BB43 PCH_SMBCLK PCH_SMBDATA 253 254 DIMMA SMBUS Address [0xA0] 253 254 DIMMB SMBUS Address [0xA4] 499 D D +3V_PCH 499 Kaby Lake PCH-H AY44 BB39 51 52 SML0CLK SML0DATA PS8331B 15 16 SMBUS Address [0x66/67] JTP SMBUS Address [0x2C] 1K +3V_PCH 1K AW42 AW45 N-MOS N-MOS SML1CLK SML1DATA EC_SMB_CK2 EC_SMB_DA2 Free Fall Sensor SMBUS Address [0X1D] 10 U2407 Thermal sensor SMBUS Address [0x9A] B5 A5 UT4 TPS65982 SMBUS Address [0x70] 50 49 UM8 PCIE redriver SMBUS Address [0xB2] 10K +3VS 10K C 2.2K 10K +3VS 2.2K 79 80 +3VS 10K EC_SMB_CK2 EC_SMB_DA2 1.8K +1V8_AON 1.8K N-MOS N-MOS 2.2K 2.2K B 77 78 KBC KB9022QD ohm ohm EC_SMB_CK1 EC_SMB_DA1 SCL SDA 100 ohm 100 ohm 17 18 12 11 EC_ESB_CLK EC_ESB_DAT BJ8 BH8 VGA_SMB_CK2 VGA_SMB_DA2 +3VALW C PU700 POWER Charger SMBUS Address [0x12] PBATT1 SMBUS Address [0x16] UG9 GPU SMBUS Address [0x9E] B UE6 KB3810 SMBUS Address [0x00] UE10 KB3810 SMBUS Address [0x08] 1K 1K 83 84 I2C0_SCL_EC I2C0_SDA_EC ohm ohm I2C0_SCL_AMP_R I2C0_SDA_AMP_R ohm ohm A +3.3V_1.8V_DVDD UA4 ALC1309 SMBUS Address [0x20] Subwoofer ALC1309 SMBUS Address [0x22] A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 2017/01/06 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title SMBus Block Diagram Size R ev 1.0 LA-D751P Date: Document Number Tuesday, August 16, 2016 Sheet of 82 D D CMC_DEBUG_36P JPCMC +1VALW OBS DATA +3V_PCH C RC9 CMC@ 1K_0402_5% XDP_SPI_SI +1VALW RC353 CMC@ 1K_0402_5% CFG0 CFG1 CFG2 CFG4 CFG5 CFG6 CFG7 CFG17 CFG16 CFG3 XDP_ITP_PMODE RC35 RC348 CMC@ 51_0402_1% @ 51_0402_1% RH497 CMC@ 51_0402_5% CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG19 CFG18 11 13 15 JTAG/RC/HOOKS DATA_0 DATA_1 DATA_2 DATA_3 DATA_4 DATA_5 DATA_6 DATA_7 17 21 VCCOBS_AB XDP_TRST* XDP_TDI XDP_TMS XDP_TCK0 XDP_TCK1 XDP_TDO DATA_CLK_1P DATA_CLK_1N 10 12 14 16 XDP_PREQ* XDP_PRDY* DATA_8 DATA_9 DATA_10 DATA_11 DATA_12 DATA_13 DATA_14 DATA_15 18 20 HOOK_0 HOOK_3 HOOK_6 XDP_PRSNT_PCH* XDP_PRSNT_CPU* DATA_CLK_2P DATA_CLK_2N GND GND 22 28 29 30 32 31 35 33 34 XDP_PREQ# XDP_PRDY# 27 25 26 XDP_HOOK0 RC355 XDP_SPI_SI XDP_ITP_PMODE CMC@ 1K_0402_1% 24 23 XDP_SPI_IO2 CMC@ 1K_0402_1% RC354 C CPU_XDP_TRST# XDP_TDI XDP_TMS PCH_JTAG_TCK XDP_TCK XDP_TDO PCH_JTAG_TCK XDP_TCK PCIRST# XDP_SPI_SI XDP_ITP_PMODE PCH_SPI_WP#_R 19 36 PCH_JTAG_TCK XDP_TCK CPU_XDP_TRST# INTEL_CMC_PRIMARY CONN@ B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 2017/01/06 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title CMC Conn Size R ev 1.0 LA-D751P Date: Document Number Tuesday, August 16, 2016 Sheet of 82 KQQ UH H H P00 C200 87 H 66 -e77i i ki a::: l yKHH k7 7i Si i CPU1C SKYLAKE_HALO BGA1440 CPU1 CPU1 S IC CL8066202194635 SR2FQ R0 2.6G FCBGA CPU1 S IC CL8066202194632 SR2FP R0 2.3G FCBGA SA000096Q1L Si5HR1@ CPU1 CPU1 C S IC CL8066202194635 SR2FQ R0 2.6G A31! SA000095Z2L Si7HR3@ PEG_CRX_TTX_P14 PEG_CRX_TTX_N14 PEG_CRX_TTX_P13 PEG_CRX_TTX_N13 PEG_CRX_TTX_P12 PEG_CRX_TTX_N12 PEG_CRX_GTX_P11 PEG_CRX_GTX_N11 PEG_CRX_GTX_P10 PEG_CRX_GTX_N10 PEG_CRX_GTX_P9 PEG_CRX_GTX_N9 PEG_CRX_GTX_P8 PEG_CRX_GTX_N8 PEG_CRX_GTX_P7 PEG_CRX_GTX_N7 PEG_CRX_GTX_P6 PEG_CRX_GTX_N6 PEG_CRX_GTX_P5 PEG_CRX_GTX_N5 PEG_CRX_GTX_P4 PEG_CRX_GTX_N4 PEG_CRX_GTX_P3 PEG_CRX_GTX_N3 PEG_CRX_GTX_P2 PEG_CRX_GTX_N2 PEG_CRX_GTX_P1 PEG_CRX_GTX_N1 PEG_CRX_GTX_P0 PEG_CRX_GTX_N0 CPU1 S IC CL8066202194632 SR2FP R0 2.3G A31! SA000096Q2L Si5HR3@ U P C H e k a l y::: bKHH a7 7i i Ki PEG_RCOMP Trace width=12 mils Spacing=15 mils Max length= 400 mils +VCCIO E25 D25 PEG_CRX_TTX_P14 PEG_CRX_TTX_N14 E24 F24 PEG_CRX_TTX_P13 PEG_CRX_TTX_N13 E23 D23 PEG_CRX_TTX_P12 PEG_CRX_TTX_N12 E22 F22 PEG_CRX_GTX_P11 PEG_CRX_GTX_N11 E21 D21 PEG_CRX_GTX_P10 PEG_CRX_GTX_N10 E20 F20 PEG_CRX_GTX_P9 PEG_CRX_GTX_N9 E19 D19 PEG_CRX_GTX_P8 PEG_CRX_GTX_N8 E18 F18 PEG_CRX_GTX_P7 PEG_CRX_GTX_N7 D17 E17 PEG_CRX_GTX_P6 PEG_CRX_GTX_N6 F16 E16 PEG_CRX_GTX_P5 PEG_CRX_GTX_N5 D15 E15 PEG_CRX_GTX_P4 PEG_CRX_GTX_N4 F14 E14 PEG_CRX_GTX_P3 PEG_CRX_GTX_N3 D13 E13 PEG_CRX_GTX_P2 PEG_CRX_GTX_N2 F12 E12 PEG_CRX_GTX_P1 PEG_CRX_GTX_N1 D11 E11 PEG_CRX_GTX_P0 PEG_CRX_GTX_N0 F10 E10 PEG_RCOMP G2 PEG_RXP[0] PEG_RXN[0] PEG_TXP[0] PEG_TXN[0] PEG_RXP[1] PEG_RXN[1] PEG_TXP[1] PEG_TXN[1] PEG_RXP[2] PEG_RXN[2] PEG_TXP[2] PEG_TXN[2] PEG_RXP[3] PEG_RXN[3] PEG_TXP[3] PEG_TXN[3] PEG_RXP[4] PEG_RXN[4] PEG_TXP[4] PEG_TXN[4] PEG_RXP[5] PEG_RXN[5] PEG_TXP[5] PEG_TXN[5] PEG_RXP[6] PEG_RXN[6] PEG_TXP[6] PEG_TXN[6] PEG_RXP[7] PEG_RXN[7] PEG_TXP[7] PEG_TXN[7] PEG_RXP[8] PEG_RXN[8] PEG_TXP[8] PEG_TXN[8] PEG_RXP[9] PEG_RXN[9] PEG_TXP[9] PEG_TXN[9] PEG_RXP[10] PEG_RXN[10] PEG_TXP[10] PEG_TXN[10] PEG_RXP[11] PEG_RXN[11] PEG_TXP[11] PEG_TXN[11] PEG_RXP[12] PEG_RXN[12] PEG_TXP[12] PEG_TXN[12] PEG_RXP[13] PEG_RXN[13] PEG_TXP[13] PEG_TXN[13] PEG_RXP[14] PEG_RXN[14] PEG_TXP[14] PEG_TXN[14] PEG_RXP[15] PEG_RXN[15] PEG_TXP[15] PEG_TXN[15] B25 A25 PEG_CTX_TRX_P15 PEG_CTX_TRX_N15 B24 C24 PEG_CTX_TRX_P14 PEG_CTX_TRX_N14 B23 A23 PEG_CTX_TRX_P13 PEG_CTX_TRX_N13 B22 C22 PEG_CTX_TRX_P12 PEG_CTX_TRX_N12 B21 A21 PEG_CTX_GRX_P11 PEG_CTX_GRX_N11 CC24 CC12 0.22U_0201_6.3V 0.22U_0201_6.3V PEG_CTX_C_GRX_P11 PEG_CTX_C_GRX_N11 B20 C20 PEG_CTX_GRX_P10 PEG_CTX_GRX_N10 CC23 CC11 0.22U_0201_6.3V 0.22U_0201_6.3V PEG_CTX_C_GRX_P10 PEG_CTX_C_GRX_N10 B19 A19 PEG_CTX_GRX_P9 PEG_CTX_GRX_N9 CC22 CC10 0.22U_0201_6.3V 0.22U_0201_6.3V PEG_CTX_C_GRX_P9 PEG_CTX_C_GRX_N9 B18 C18 PEG_CTX_GRX_P8 PEG_CTX_GRX_N8 CC21 CC9 0.22U_0201_6.3V 0.22U_0201_6.3V PEG_CTX_C_GRX_P8 PEG_CTX_C_GRX_N8 A17 B17 PEG_CTX_GRX_P7 PEG_CTX_GRX_N7 CC20 CC8 0.22U_0201_6.3V 0.22U_0201_6.3V PEG_CTX_C_GRX_P7 PEG_CTX_C_GRX_N7 C16 B16 PEG_CTX_GRX_P6 PEG_CTX_GRX_N6 CC19 CC7 0.22U_0201_6.3V 0.22U_0201_6.3V PEG_CTX_C_GRX_P6 PEG_CTX_C_GRX_N6 A15 B15 PEG_CTX_GRX_P5 PEG_CTX_GRX_N5 CC18 CC6 0.22U_0201_6.3V 0.22U_0201_6.3V PEG_CTX_C_GRX_P5 PEG_CTX_C_GRX_N5 C14 B14 PEG_CTX_GRX_P4 PEG_CTX_GRX_N4 CC17 CC5 0.22U_0201_6.3V 0.22U_0201_6.3V PEG_CTX_C_GRX_P4 PEG_CTX_C_GRX_N4 A13 B13 PEG_CTX_GRX_P3 PEG_CTX_GRX_N3 CC16 CC4 0.22U_0201_6.3V 0.22U_0201_6.3V PEG_CTX_C_GRX_P3 PEG_CTX_C_GRX_N3 C12 B12 PEG_CTX_GRX_P2 PEG_CTX_GRX_N2 CC15 CC3 0.22U_0201_6.3V 0.22U_0201_6.3V PEG_CTX_C_GRX_P2 PEG_CTX_C_GRX_N2 A11 B11 PEG_CTX_GRX_P1 PEG_CTX_GRX_N1 CC14 CC2 0.22U_0201_6.3V 0.22U_0201_6.3V PEG_CTX_C_GRX_P1 PEG_CTX_C_GRX_N1 C10 B10 PEG_CTX_GRX_P0 PEG_CTX_GRX_N0 CC13 CC1 0.22U_0201_6.3V 0.22U_0201_6.3V PEG_CTX_C_GRX_P0 PEG_CTX_C_GRX_N0 B8 A8 DMI_CTX_PRX_P0 DMI_CTX_PRX_N0 C6 B6 DMI_CTX_PRX_P1 DMI_CTX_PRX_N1 B5 A5 DMI_CTX_PRX_P2 DMI_CTX_PRX_N2 D4 B4 DMI_CTX_PRX_P3 DMI_CTX_PRX_N3 PEG_CTX_TRX_P15 PEG_CTX_TRX_N15 PEG_CTX_TRX_P14 PEG_CTX_TRX_N14 PEG_CTX_TRX_P13 PEG_CTX_TRX_N13 PEG_CTX_TRX_P12 PEG_CTX_TRX_N12 D PEG_CTX_C_GRX_P11 PEG_CTX_C_GRX_N11 PEG_CTX_C_GRX_P10 PEG_CTX_C_GRX_N10 PEG_CTX_C_GRX_P9 PEG_CTX_C_GRX_N9 PEG_CTX_C_GRX_P8 PEG_CTX_C_GRX_N8 PEG_CTX_C_GRX_P7 PEG_CTX_C_GRX_N7 PEG_CTX_C_GRX_P6 PEG_CTX_C_GRX_N6 PEG_CTX_C_GRX_P5 PEG_CTX_C_GRX_N5 PEG_CTX_C_GRX_P4 PEG_CTX_C_GRX_N4 PEG_CTX_C_GRX_P3 PEG_CTX_C_GRX_N3 PEG_CTX_C_GRX_P2 PEG_CTX_C_GRX_N2 PEG_CTX_C_GRX_P1 PEG_CTX_C_GRX_N1 PEG_CTX_C_GRX_P0 PEG_CTX_C_GRX_N0 > e s r Xe Tv Ue PR G< SA000097D2L Si7KR3@ > e s Xr e Rv Ue PR G< S IC CL8066202194730 SR2FL R0 2.7G A31! PEG_CRX_TTX_P15 PEG_CRX_TTX_N15 X> Te s ar r e ev de l aR C< X> Re s ar r e ev de l aR C< SA000095Z1L Si7HR1@ PEG_CRX_TTX_P15 PEG_CRX_TTX_N15 X T t l o> be r s er de nv ue hR T< SA000097D1L Si7KR1@ X R t l o> b e rs er de nv ue hR T< S IC CL8066202194730 SR2FL R0 2.7G BGA D C PEG_RCOMP RC2 24.9_0402_1% DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 D8 E8 DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 E6 F6 DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 D5 E5 DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 J8 J9 DMI_RXP[0] DMI_RXN[0] DMI_TXP[0] DMI_TXN[0] DMI_RXP[1] DMI_RXN[1] DMI_TXP[1] DMI_TXN[1] DMI_RXP[2] DMI_RXN[2] DMI_TXP[2] DMI_TXN[2] DMI_RXP[3] DMI_RXN[3] DMI_TXP[3] DMI_TXN[3] CPU1 DMI_CTX_PRX_P0 DMI_CTX_PRX_N0 DMI_CTX_PRX_P1 DMI_CTX_PRX_N1 DMI_CTX_PRX_P2 DMI_CTX_PRX_N2 DMI_CTX_PRX_P3 DMI_CTX_PRX_N3 OF 14 @ SKL-H_BGA1440 S IC A31 CL8067702869810 QL2X A0 2.7G FCBGA 1440 SA0000A130L Ki7KES@ CPU1 CPU1D B S IC A31 CL8067702869811 QL3X A0 2.4G BGA 1440 SA0000A150L Ki75ES@ CPU_DP1_P0 CPU_DP1_N0 CPU_DP1_P1 CPU_DP1_N1 CPU_DP1_P2 CPU_DP1_N2 CPU_DP1_P3 CPU_DP1_N3 CPU_DP1_AUXP CPU_DP1_AUXN CPU_DP2_P0 CPU_DP2_N0 CPU_DP2_P1 CPU_DP2_N1 CPU_DP2_P2 CPU_DP2_N2 CPU_DP2_P3 CPU_DP2_N3 CPU_DP2_AUXP CPU_DP2_AUXN CPU_DP1_P0 CPU_DP1_N0 CPU_DP1_P1 CPU_DP1_N1 CPU_DP1_P2 CPU_DP1_N2 CPU_DP1_P3 CPU_DP1_N3 K36 K37 J35 J34 H37 H36 J37 J38 CPU_DP1_AUXP CPU_DP1_AUXN D27 E27 CPU_DP2_P0 CPU_DP2_N0 CPU_DP2_P1 CPU_DP2_N1 CPU_DP2_P2 CPU_DP2_N2 CPU_DP2_P3 CPU_DP2_N3 H34 H33 F37 G38 F34 F35 E37 E36 CPU_DP2_AUXP CPU_DP2_AUXN F26 E26 C34 D34 B36 B34 F33 E33 C33 B33 A27 B27 SKYLAKE_HALO BGA1440 DDI1_TXP[0] DDI1_TXN[0] DDI1_TXP[1] DDI1_TXN[1] DDI1_TXP[2] DDI1_TXN[2] DDI1_TXP[3] DDI1_TXN[3] EDP_TXP[0] EDP_TXN[0] EDP_TXP[1] EDP_TXN[1] EDP_TXN[2] EDP_TXP[2] EDP_TXN[3] EDP_TXP[3] DDI1_AUXP DDI1_AUXN EDP_AUXP EDP_AUXN DDI2_TXP[0] DDI2_TXN[0] DDI2_TXP[1] DDI2_TXN[1] DDI2_TXP[2] DDI2_TXN[2] DDI2_TXP[3] DDI2_TXN[3] EDP_DISP_UTIL EDP_RCOMP D29 E29 F28 E28 B29 A29 B28 C28 CPU_EDP_TX0P CPU_EDP_TX0N CPU_EDP_TX1P CPU_EDP_TX1N CPU_EDP_TX2N CPU_EDP_TX2P CPU_EDP_TX3N CPU_EDP_TX3P C26 B26 CPU_EDP_AUX CPU_EDP_AUX# A33 D37 T1 PAD~D CPU_EDP_TX0P CPU_EDP_TX0N CPU_EDP_TX1P CPU_EDP_TX1N CPU_EDP_TX2N CPU_EDP_TX2P CPU_EDP_TX3N CPU_EDP_TX3P CPU_EDP_AUX CPU_EDP_AUX# TP@ EDP_RCOMP B +VCCIO EDP_RCOMP Trace width=20 mils Spacing=25 mils Max length=100 mils RC30 24.9_0402_1% DDI2_AUXP DDI2_AUXN DDI3_TXP[0] DDI3_TXN[0] DDI3_TXP[1] DDI3_TXN[1] DDI3_TXP[2] DDI3_TXN[2] DDI3_TXP[3] DDI3_TXN[3] PROC_AUDIO_CLK PROC_AUDIO_SDI PROC_AUDIO_SDO DDI3_AUXP DDI3_AUXN G27 G25 G29 CPU_DISPA_SDI_R OF 14 @ SKL-H_BGA1440 CPU_DISPA_BCLK CPU_DISPA_SDO CPU_DISPA_SDI RC66 20_0402_5% A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title CPU(1/7) DMI,PEG,DDI,EDP Size Document Number Rev 1.0 LA-D751P Date: Wednesday, August 24, 2016 Sheet of 82 D D Interleave CPU1A DDR_A_D[0 63] DDR_A_MA[0 13] DDR_A_DQS#[0 7] DDR_A_DQS[0 7] DDR_B_D[0 63] DDR_B_MA[0 13] DDR_B_DQS#[0 7] DDR_B_DQS[0 7] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 C B SKYLAKE_HALO BA2 BA1 AY4 AY5 BA5 BA4 AY1 AY2 DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15] DDR0_DQ[16]/DDR0_DQ[32] DDR0_DQ[17]/DDR0_DQ[33] DDR0_DQ[18]/DDR0_DQ[34] DDR0_DQ[19]/DDR0_DQ[35] DDR0_DQ[20]/DDR0_DQ[36] DDR0_DQ[21]/DDR0_DQ[37] DDR0_DQ[22]/DDR0_DQ[38] DDR0_DQ[23]/DDR0_DQ[39] DDR0_DQ[24]/DDR0_DQ[40] DDR0_DQ[25]/DDR0_DQ[41] DDR0_DQ[26]/DDR0_DQ[42] DDR0_DQ[27]/DDR0_DQ[43] DDR0_DQ[28]/DDR0_DQ[44] DDR0_DQ[29]/DDR0_DQ[45] DDR0_DQ[30]/DDR0_DQ[46] DDR0_DQ[31]/DDR0_DQ[47] DDR0_DQ[32]/DDR1_DQ[0] DDR0_DQ[33]/DDR1_DQ[1] DDR0_DQ[34]/DDR1_DQ[2] DDR0_DQ[35]/DDR1_DQ[3] DDR0_DQ[36]/DDR1_DQ[4] DDR0_DQ[37]/DDR1_DQ[5] DDR0_DQ[38]/DDR1_DQ[6] DDR0_DQ[39]/DDR1_DQ[7] DDR0_DQ[40]/DDR1_DQ[8] DDR0_DQ[41]/DDR1_DQ[9] DDR0_DQ[42]/DDR1_DQ[10] DDR0_DQ[43]/DDR1_DQ[11] DDR0_DQ[44]/DDR1_DQ[12] DDR0_DQ[45]/DDR1_DQ[13] DDR0_DQ[46]/DDR1_DQ[14] DDR0_DQ[47]/DDR1_DQ[15] DDR0_DQ[48]/DDR1_DQ[32] DDR0_DQ[49]/DDR1_DQ[33] DDR0_DQ[50]/DDR1_DQ[34] DDR0_DQ[51]/DDR1_DQ[35] DDR0_DQ[52]/DDR1_DQ[36] DDR0_DQ[53]/DDR1_DQ[37] DDR0_DQ[54]/DDR1_DQ[38] DDR0_DQ[55]/DDR1_DQ[39] DDR0_DQ[56]/DDR1_DQ[40] DDR0_DQ[57]/DDR1_DQ[41] DDR0_DQ[58]/DDR1_DQ[42] DDR0_DQ[59]/DDR1_DQ[43] DDR0_DQ[60]/DDR1_DQ[44] DDR0_DQ[61]/DDR1_DQ[45] DDR0_DQ[62]/DDR1_DQ[46] DDR0_DQ[63]/DDR1_DQ[47] DDR0_CKP[0] DDR0_CKN[0] DDR0_CKN[1] DDR0_CKP[1] DDR0_CLKP[2] DDR0_CLKN[2] DDR0_CLKP[3] DDR0_CLKN[3] DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3] DDR0_CS#[0] DDR0_CS#[1] DDR0_CS#[2] DDR0_CS#[3] DDR0_ODT[0] DDR0_ODT[1] DDR0_ODT[2] DDR0_ODT[3] DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0] DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1] DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0] DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16] DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14] DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15] DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0] DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1] DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2] DDR0_MA[3] DDR0_MA[4] DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5] DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6] DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7] DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8] DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9] DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10] DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11] DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12] DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13] DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1] DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT# DDR0_PAR DDR0_ALERT# DDR0_DQSN[0] DDR0_DQSN[1] DDR0_DQSN[2]/DDR0_DQSN[4] DDR0_DQSN[3]/DDR0_DQSN[5] DDR0_DQSP[4]/DDR1_DQSP[0] DDR0_DQSP[5]/DDR1_DQSP[1] DDR0_DQSP[6]/DDR1_DQSP[4] DDR0_DQSP[7]/DDR1_DQSP[5] DDR0_DQSP[0] DDR0_DQSP[1] DDR0_DQSP[2]/DDR0_DQSP[4] DDR0_DQSP[3]/DDR0_DQSP[5] DDR0_DQSN[4]/DDR1_DQSN[0] DDR0_DQSN[5]/DDR1_DQSN[1] DDR0_DQSN[6]/DDR1_DQSN[4] DDR0_DQSN[7]/DDR1_DQSN[5] DDR0_ECC[0] DDR0_ECC[1] DDR0_ECC[2] DDR0_ECC[3] DDR0_ECC[4] DDR0_ECC[5] DDR0_ECC[6] DDR0_ECC[7] SKYLAKE_HALO CPU1B BGA1440 BR6 BT6 BP3 BR3 BN5 BP6 BP2 BN3 BL4 BL5 BL2 BM1 BK4 BK5 BK1 BK2 BG4 BG5 BF4 BF5 BG2 BG1 BF1 BF2 BD2 BD1 BC4 BC5 BD5 BD4 BC1 BC2 AB1 AB2 AA4 AA5 AB5 AB4 AA2 AA1 V5 V2 U1 U2 V1 V4 U5 U4 R2 P5 R4 P4 R5 P2 R1 P1 M4 M1 L4 L2 M5 M2 L5 L1 DDR0_DQSP[8] DDR0_DQSN[8] AG1 AG2 AK1 AK2 AL3 AK3 AL2 AL1 M_CLK_DDR0 M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR1 AT1 AT2 AT3 AT5 DDR_CKE0_DIMMA DDR_CKE1_DIMMA AD5 AE2 AD2 AE5 DDR_CS0_DIMMA# DDR_CS1_DIMMA# AD3 AE4 AE1 AD4 M_ODT0 M_ODT1 AH5 AH1 AU1 DDR_A_BS0 DDR_A_BS1 DDR_A_BG0 AH4 AG4 AD1 AH3 AP4 AN4 AP5 AP2 AP1 AP3 AN1 AN3 AT4 AH2 AN2 AU4 AE3 AU2 AU3 DDR_A_RAS# DDR_A_WE# DDR_A_CAS# DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_BG1 DDR_A_ACT# AG3 AU5 DDR_A_PAR DDR_A_ALERT# BR5 BL3 BG3 BD3 AB3 V3 R3 M3 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 BP5 BK3 BF3 BC3 AA3 U3 P3 L3 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 BGA1440 BT11 BR11 BT8 BR8 BP11 BN11 BP8 BN8 BL12 BL11 BL8 BJ8 BJ11 BJ10 BL7 BJ7 BG11 BG10 BG8 BF8 BF11 BF10 BG7 BF7 BB11 BC11 BB8 BC8 BC10 BB10 BC7 BB7 AA11 AA10 AC11 AC10 AA7 AA8 AC8 AC7 W8 W7 V10 V11 W11 W10 V7 V8 R11 P11 P7 R8 R10 P10 R7 P8 L11 M11 L7 M8 L10 M10 M7 L8 AW11 AY11 AY8 AW8 AY10 AW10 AY7 AW7 AY3 BA3 DDR1_DQ[0]/DDR0_DQ[16] DDR1_DQ[1]/DDR0_DQ[17] DDR1_DQ[2]/DDR0_DQ[18] DDR1_DQ[3]/DDR0_DQ[19] DDR1_DQ[4]/DDR0_DQ[20] DDR1_DQ[5]/DDR0_DQ[21] DDR1_DQ[6]/DDR0_DQ[22] DDR1_DQ[7]/DDR0_DQ[23] DDR1_DQ[8]/DDR0_DQ[24] DDR1_DQ[9]/DDR0_DQ[25] DDR1_DQ[10]/DDR0_DQ[26] DDR1_DQ[11]/DDR0_DQ[27] DDR1_DQ[12]/DDR0_DQ[28] DDR1_DQ[13]/DDR0_DQ[29] DDR1_DQ[14]/DDR0_DQ[30] DDR1_DQ[15]/DDR0_DQ[31] DDR1_DQ[16]/DDR0_DQ[48] DDR1_DQ[17]/DDR0_DQ[49] DDR1_DQ[18]/DDR0_DQ[50] DDR1_DQ[19]/DDR0_DQ[51] DDR1_DQ[20]/DDR0_DQ[52] DDR1_DQ[21]/DDR0_DQ[53] DDR1_DQ[22]/DDR0_DQ[54] DDR1_DQ[23]/DDR0_DQ[55] DDR1_DQ[24]/DDR0_DQ[56] DDR1_DQ[25]/DDR0_DQ[57] DDR1_DQ[26]/DDR0_DQ[58] DDR1_DQ[27]/DDR0_DQ[59] DDR1_DQ[28]/DDR0_DQ[60] DDR1_DQ[29]/DDR0_DQ[61] DDR1_DQ[30]/DDR0_DQ[62] DDR1_DQ[31]/DDR0_DQ[63] DDR1_DQ[32]/DDR1_DQ[16] DDR1_DQ[33]/DDR1_DQ[17] DDR1_DQ[34]/DDR1_DQ[18] DDR1_DQ[35]/DDR1_DQ[19] DDR1_DQ[36]/DDR1_DQ[20] DDR1_DQ[37]/DDR1_DQ[21] DDR1_DQ[38]/DDR1_DQ[22] DDR1_DQ[39]/DDR1_DQ[23] DDR1_DQ[40]/DDR1_DQ[24] DDR1_DQ[41]/DDR1_DQ[25] DDR1_DQ[42]/DDR1_DQ[26] DDR1_DQ[43]/DDR1_DQ[27] DDR1_DQ[44]/DDR1_DQ[28] DDR1_DQ[45]/DDR1_DQ[29] DDR1_DQ[46]/DDR1_DQ[30] DDR1_DQ[47]/DDR1_DQ[31] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63] DDR1_CKP[0] DDR1_CKN[0] DDR1_CKN[1] DDR1_CKP[1] DDR1_CLKP[2] DDR1_CLKN[2] DDR1_CLKP[3] DDR1_CLKN[3] DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3] DDR1_CS#[0] DDR1_CS#[1] DDR1_CS#[2] DDR1_CS#[3] DDR1_ODT[0] DDR1_ODT[1] DDR1_ODT[2] DDR1_ODT[3] DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16] DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14] DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15] DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0] DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1] DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0] DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0] DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1] DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2] DDR1_MA[3] DDR1_MA[4] DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5] DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6] DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7] DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8] DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9] DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10] DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11] DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12] DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13] DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1] DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT# DDR1_PAR DDR1_ALERT# DDR1_DQSN[0]/DDR0_DQSN[2] DDR1_DQSN[1]/DDR0_DQSN[3] DDR1_DQSN[2]/DDR0_DQSN[6] DDR1_DQSN[3]/DDR0_DQSN[7] DDR1_DQSN[4]/DDR1_DQSN[2] DDR1_DQSN[5]/DDR1_DQSN[3] DDR1_DQSN[6] DDR1_DQSN[7] DDR1_DQSP[0]/DDR0_DQSP[2] DDR1_DQSP[1]/DDR0_DQSP[3] DDR1_DQSP[2]/DDR0_DQSP[6] DDR1_DQSP[3]/DDR0_DQSP[7] DDR1_DQSP[4]/DDR1_DQSP[2] DDR1_DQSP[5]/DDR1_DQSP[3] DDR1_DQSP[6] DDR1_DQSP[7] DDR1_ECC[0] DDR1_ECC[1] DDR1_ECC[2] DDR1_ECC[3] DDR1_ECC[4] DDR1_ECC[5] DDR1_ECC[6] DDR1_ECC[7] DDR1_DQSP[8] DDR1_DQSN[8] AM9 AN9 AM8 AM7 AM11 AM10 AJ10 AJ11 M_CLK_DDR2 M_CLK_DDR#2 M_CLK_DDR#3 M_CLK_DDR3 AT8 AT10 AT7 AT11 DDR_CKE2_DIMMB DDR_CKE3_DIMMB AF11 AE7 AF10 AE10 DDR_CS2_DIMMB# DDR_CS3_DIMMB# AF7 AE8 AE9 AE11 M_ODT2 M_ODT3 C AH10 AH11 AF8 DDR_B_RAS# DDR_B_WE# DDR_B_CAS# AH8 AH9 AR9 AJ9 DDR_B_MA0 AK6 DDR_B_MA1 AK5 DDR_B_MA2 AL5 DDR_B_MA3 AL6 DDR_B_MA4 AM6 DDR_B_MA5 AN7 DDR_B_MA6 AN10 DDR_B_MA7 AN8 DDR_B_MA8 AR11 DDR_B_MA9 AH7 DDR_B_MA10 AN11 DDR_B_MA11 AR10 DDR_B_MA12 AF9 DDR_B_MA13 AR7 AT9 AJ7 AR8 DDR_B_BS0 DDR_B_BS1 DDR_B_BG0 DDR_B_BG1 DDR_B_ACT# DDR_B_PAR DDR_B_ALERT# BP9 BL9 BG9 BC9 AC9 W9 R9 M9 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 BR9 BJ9 BF9 BB9 AA9 V9 P9 L9 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 B AW9 AY9 DDR CHANNEL B DDR CHANNEL A RH148 RH149 RH150 1 121_0402_1% DDR_RCOMP0 75_0402_1% DDR_RCOMP1 100_0402_1% DDR_RCOMP2 OF 14 @ SKL-H_BGA1440 G1 H1 J2 DDR_RCOMP[0] DDR_RCOMP[1] DDR_RCOMP[2] OF 14 @ DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ BN13 BP13 BR13 +V_DDR_REFA_R +V_DDR_REFB_R SKL-H_BGA1440 DDR_RCOMP0 : DDR_RCOMP1 : DDR_RCOMP2 : Trace width=12~15 mils Spacing=20 mils Max length= 500 mils A Compal Electronics, Inc Compal Secret Data Security Classification Issued Date A 2016/01/06 Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title CPU(2/7) DDR4 Size Document Number Rev 1.0 LA-D751P Date: Tuesday, August 16, 2016 Sheet of 82 +VCCST RH163 RH156 RH164 D @ 1K_0402_5% H_THERMTRIP# 51_0402_5% XDP_PREQ# 1K_0402_5% H_VCCST_PWRGD RH151 100_0402_1% VR_SVID_DATA RH152 56.2_0402_1% VR_SVID_ALERT# 1K_0402_5% H_PROCHOT# SKYLAKE_HALO CPU1E B31 A32 PCH_CPU_BCLK_P PCH_CPU_BCLK_N PCH_CPU_PCIBCLK_P PCH_CPU_PCIBCLK_N CPU_24MHZ_P CPU_24MHZ_N D35 C36 E31 D31 BGA1440 BCLKP BCLKN CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] PCI_BCLKP PCI_BCLKN CLK24P CLK24N +VCCSTG RH165 VR_SVID_ALERT# VR_SVID_CLK VR_SVID_DATA H_PROCHOT# VR_SVID_ALERT# RH153 220_0402_5% VR_SVID_DATA H_PROCHOT# RH158 499_0402_1% BH31 BH32 BH29 BR30 DDR_VTT_PG_CTRL PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS 1: Normal Operation; Lane # socket pin map definition CFG2 * definition matches RH184 H_VCCST_PWRGD H_CPUPWRGD PLTRST_CPU# H_PM_SYNC_R H_PM_DOWN H_PECI H_THERMTRIP# RH154 0:Lane Reversed CFG2 H_VCCST_PWRGD 1K_0402_5% RH155 RH519 BT13 60.4_0402_1% H13 BT31 BP35 BM34 BP31 BT34 J31 20_0402_5% H_THERMTRIP# PROC_DETECT# @ 0_0402_5% BR33 BN1 BM30 VIDALERT# VIDSCK VIDSOUT PROCHOT# DDR_VTT_CNTL CFG[17] CFG[16] CFG[19] CFG[18] VCCST_PWRGD BPM#[0] BPM#[1] BPM#[2] BPM#[3] PROCPWRGD RESET# PM_SYNC PM_DOWN PECI THERMTRIP# PROC_TDO PROC_TDI PROC_TMS PROC_TCK PROC_TRST# PROC_PREQ# PROC_PRDY# SKTOCC# PROC_SELECT# CATERR# CFG2 CFG4 CFG5 CFG6 CFG7 BN23 BP23 BP22 BN22 BR27 BT27 BM31 BT30 XDP_BPM#0 XDP_BPM#1 BT28 BL32 BP28 BR28 XDP_TDO XDP_TDI XDP_TMS PCH_JTAG_TCK BP30 BL30 BP27 CPU_XDP_TRST# XDP_PREQ# XDP_PRDY# BT25 CFG_RCOMP CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG17 CFG16 CFG19 CFG18 T112 T113 PAD~D PAD~D D @ @ XDP_TDO XDP_TDI XDP_TMS PCH_JTAG_TCK CPU_XDP_TRST# XDP_PREQ# XDP_PRDY# CFG_RCOMP BN25 BN27 BN26 BN28 BR20 BM20 BT20 BP20 BR23 BR22 BT23 BT22 BM19 BR19 BP19 BT19 C C OF 14 @ RH59 49.9_0402_1% SKL-H_BGA1440 Display Port Presence Strap : Disabled; No Physical Display Port attached to Embedded Display Port CFG4 +1.2V_DDR UC1 * : Enabled; An external Display Port device is connected to the Embedded Display Port CFG4 RH185 2 1K_0402_5% @ CH197 0.1U_0402_10V7K VCC NC A Y GND DDR_VTT_PG_CTRL H_VCCST_PWRGD H_CPUPWRGD PLTRST_CPU# 74AUP1G07GW_TSSOP5 +3VS CH193 0.1U_0402_16V7K~D ESD@ CH194 0.1U_0402_16V7K~D ESD@ CH195 0.1U_0402_16V7K~D ESD@ PCIE Port Bifurcation Straps RH525 330K_0402_5% 11: (Default) x16 - Device functions and disabled B 10: x8, x8 - Device function enabled ; function disabled 01: Reserved - (Device function disabled ; function enabled) 00: x8,x4,x4 - Device functions and enabled * SM_PG_CTRL RH489 PCH_SPI_SI_R 1K_0402_5% PCH_SYS_PWROK_XDP B RH489,RH493 close to UH4 RH186 1K_0402_5% CFG6 RH187 1K_0402_5% +3V_PCH +3VALW RH493 2.2K_0402_5% PCH_SYS_PWROK_XDP CFG5 +3VS CFG[6:5] RH5 1K_0402_5% 2 RH2 10K_0402_5% PEG DEFER TRAINING RH188 @ 0: PEG Wait for BIOS for training CFG7 SYS_RESET# 1 +VCCSTG CH174 0.1U_0402_10V * PBTN_OUT# 1: (Default) PEG Train immediately following xxRESETB de assertion 1K_0402_5% RH494 CMC@ 51_0402_5% XDP_TMS RH495 CMC@ 51_0402_5% XDP_TDI RH496 51_0402_5% XDP_TDO @ CH175 0.1U_0402_10V CFG7 A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title CPU(3/7) CFG,XDP Size Document Number Rev 1.0 LA-D751P Date: Tuesday, August 16, 2016 Sheet of 82 D D +VCC_CORE +VCC_CORE CPU1J SKYLAKE_HALO BGA1440 BJ17 BJ19 BJ20 BK17 BK19 BK20 BL16 BL17 BL18 BL19 BL20 BL21 BM17 BN17 CPU1G SKYLAKE_HALO BGA1440 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC V32 V33 V34 V35 V36 V37 V38 W13 W14 W29 W30 W31 W32 W35 W36 W37 W38 Y29 Y30 Y31 Y32 Y33 Y34 Y35 Y36 L14 P29 P30 P31 P32 P33 P34 P35 P36 R13 R31 R32 R33 R34 R35 R36 R37 R38 T29 T30 T31 T32 T35 T36 T37 T38 U29 U30 U31 U32 U33 U34 U35 U36 V13 V14 V31 P14 SKYLAKE_HALO CPU1K BGA1440 @ PAD~D @ @ PAD~D PAD~D D1 E1 E3 E2 T41 BR1 BT2 T43 T44 BN35 J24 H24 BN33 BL34 N29 R14 AE29 AA14 A36 A37 PCH_TRIGGER CPU_TRIGGER RH167 RH192 30_0402_5% 30_0402_5% H23 J23 F30 E30 B30 C30 G3 J3 BR35 BR31 BH30 RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD_TP RSVD RSVD RSVD VSS RSVD RSVD RSVD RSVD RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD PROC_TRIGIN PROC_TRIGOUT VSS RSVD RSVD RSVD_TP RSVD_TP RSVD RSVD RSVD RSVD RSVD RSVD RSVD NCTF NCTF NCTF NCTF NCTF NCTF RSVD RSVD RSVD BM33 BL33 T66 T67 PAD~D PAD~D @ @ BJ14 BJ13 T68 T69 PAD~D PAD~D @ @ BJ16 BK16 T73 T74 PAD~D PAD~D @ @ BK24 BJ24 T75 T76 PAD~D PAD~D @ @ BJ18 BL15 BM16 BK21 BJ21 BL22 BM22 BT17 BR17 BP15 BR15 BT15 BK18 BJ34 BJ33 T81 T82 PAD~D PAD~D @ @ T85 PAD~D @ T88 T89 PAD~D PAD~D @ @ BP16 BR16 BT16 G13 AJ8 BL31 B2 B38 BP1 BR2 C1 C38 BN15 BM15 BP17 BN16 BM14 BL14 BJ35 BJ36 11 OF 14 @ SKL-H_BGA1440 RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD C VCCOPC_SENSE VSSOPC_SENSE RSVD RSVD VCCEOPIO VCCEOPIO VCCEOPIO RSVD RSVD RSVD VCCEOPIO_SENSE VSSEOPIO_SENSE RSVD RSVD VCC_OPC_1P8 VCC_OPC_1P8 RSVD RSVD B +VCC_CORE AT13 AW13 AU13 AY13 RH197 100_0402_1% RH166 RH57 RH58 AG37 AG38 VCCSENSE VSSSENSE 1 @ @ @ 49.9_0402_1% 49.9_0402_1% 49.9_0402_1% BT29 BR25 BP25 ZVM# MSM# ZVM2# MSM2# OPC_RCOMP OPCE_RCOMP OPCE_RCOMP2 10 OF 14 @ SKL-H_BGA1440 VCC_SENSE VSS_SENSE BJ23 BJ26 BJ27 BK23 BK26 BK27 BL23 BL24 BL25 BL26 BL27 BL28 BM24 BK28 BJ28 B VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC C AA13 AA31 AA32 AA33 AA34 AA35 AA36 AA37 AA38 AB29 AB30 AB31 AB32 AB35 AB36 AB37 AB38 AC13 AC14 AC29 AC30 AC31 AC32 AC33 AC34 AC35 AC36 AD13 AD14 AD31 AD32 AD33 AD34 AD35 AD36 AD37 AD38 AE13 AE14 AE30 AE31 AE32 AE35 AE36 AE37 AE38 AF35 AF36 AF37 AF38 K13 K14 L13 N13 N14 N30 N31 N32 N35 N36 N37 N38 P13 VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC VCCOPC OF 14 SKL-H_BGA1440 @ RH466 100_0402_1% A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 2017/01/06 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title CPU(4/7) +VCC_CORE,RSVD Size Rev 1.0 LA-D751P Date: Document Number Tuesday, August 16, 2016 Sheet 10 of 82 +3V3_SYS +1.0VS_VGAP TDC 1A Peak Current 1.4A OCP current 6A FSW=1MHz TYP MAX Choke DCR 0.045mohm , 0.070mohm PR821 10K_0402_5% PEX_VDD_ENP PR802 1M_0402_1% C 13 15 EN NC ILMT NC BYP NC PAD @ Rup FB_1.0VS_VGAP 17 10 12 16 21 @EMI@ PR803 4.7_0603_5% SNB_1.0VS_VGAP SY8286RAC_QFN20_3X3 @EMI@ PC802 680P_0402_50V7K VCC 14 +1.0VS_VGAP PR804 21.5K_0402_1% GND 1UH_PCMB042T-1R0MS_4.5A_20% 20 FB C +3VALW 0_0402_5% 11 LX GND 19 PC816 22U_0603_6.3V6M PR801 GND PL800 PC805 22U_0603_6.3V6M 18 NVVDD2_PGOOD PC801 0.1U_0402_16V7K LX LX_1.0VS_VGAP IN PC808 0.1U_0603_25V7K PC804 22U_0603_6.3V6M 0_0402_5% LX PR806 0_0603_5% 2 PEX_VDD_EN BS IN @ PR823 IN 0_0402_5% PC809 330P_0402_50V7K PG D Rdown PR8217 IN PR805 @ 31.6K_0402_1% NVVDD2_EN PC800 2 2 JUMP_43X39 PC803 10U_0805_25V6K~D B+ +1.0VS_VGA_PGOOD PU800 2.2U_0402_16V6K PJ800 @ Input 0.7A D PC815 22U_0603_6.3V6M PR812 @ 0_0402_5% (1+Rup/Rdown) Vout=0.6V* PJP801 @ +3VALW 2 +PEX_VDD PC817 1U_0603_6.3V6M JUMP_43X79 @ PR813 0_0402_5% +1.0VS_VGAP B B A A Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 Issued Date Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_+1.0VS_VGA Size Rev 0.3 LA-D751P Date: Document Number Tuesday, August 16, 2016 Sheet 68 of 82 470K_0402_5%_B25/50 4700K PC6008 0.1U_0402_10V6K 16 15 GPU_PH4 Fsw=300kHz 5VCC 5VCC 5VCC PR6035 2.2_0603_1% +5VS 請 教 A U TO PHASE的 的 設 定 PHASE 5VCC +5VS 2 0_0402_5% PR6062 0_0402_5% PR6060 PR6059 0_0402_5% 0_0402_5% PR6058 PR6057 8.2K_0402_5% PR6056 8.2K_0402_5% 0_0402_5% PR6067 @ GPU_LPC GPU_PROG5 @ A Cold Boot = 4-phase Warm Boot = 4-phase Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 Issued Date Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_VGA_UP9511P Size Document Number Rev 0.3 LA-D751P Date: @ GPU_PROG4 @ @ GPU_PROG3 @ @ 20.5K_0402_1% PR6064 0_0402_5% PR6065 0_0402_5% PR6066 0_0402_5% @ A PR6048 51K_0402_5% GPU_PWM4 G2G3@ PR6055 0_0402_5% PR6051 10K_0402_5% GPU_PWM3 PR6050 36K_0402_5% GPU_PWM2 @ PR6054 0_0402_5% 2 B 0_0402_5% @ PR6049 0_0402_5% 2 UP9511PQGJ_VQFN40_5X5 GPU_PWM1 PR6046 43K_0402_5% PWM1 @ PR6043 1 11 PR6047 10K_0402_5% 12 13 14 GPU_PROG6 GPU_PH3 PR6052 10K_0402_5% 17 GPU_PH2 18 GPU_PH1 @ PR6031 0_0402_5% 19 C PR6038 33K_0402_5% ISEN1 PWM2 PWM3 PWM4 PWM3 PWM2 10 PWM4 PWM5 PWM6 PWM7 PWM8 NTC_Lb @ CSNSUM PW M1 REFIN NVVDD1 TDC 121A Peak Current 280A OCP=314A GPU_PROG2 CSPSUM CSNSUM 5VCC C PWMVID 的 RC BOM 請 根 據GPU's 據 GPU's config 設 定 PH6000 21 22 CSPSUM 24 23 APL2 APL1 ISEN8 VID 2 G2G3@ PR6004 20K_0402_1% PR6002 20K_0402_1% 0.1U_0402_25V6 PC6001 @ PR6005 0_0402_5% PR6007 12.4K_0402_1% GPU_PROG1 IMON PGOOD FBRTN NVVDD_ISUMN4 GPU_PROG2 0_0402_5% NVVDD_ISUMN3 GPU_PROG1 NVVDD_VID GPU_PROG5 ISEN7 PC6016 25 PSI PC6015 @ PR6044 4700P_0402_50V7K @ PR6018 0_0402_5% ISEN6 PR6061 R5 R2PR6063 NVVDD1_PGOOD VINMON EN PR6041 0_0402_5% PR6042 100K_0402_5% SS ISEN5 @ 27 LPC R4 28 ISEN4 R3 NVVDD_ISUMN2 PR6026 2.2K_0402_1% PR6027 2.2K_0402_1% ISEN2 PR6028 2K_0402_1% ISEN3 G2G3@ PR6030 2K_0402_1% ISEN4 G2G3@ PR6032 ISEN5 G1@ PR6070 100K_0402_5% 100K_0402_5% 20 GND 4.32K_0402_1% +3VS EAP APL4 FSW PR6040 @ PR6039 0_0402_5% ISEN3 R1 layout 上 : 請 將 RSE N1 ~ 放 靠 近 C o n t r o l l e r REFADJ 41 NVVDD_ISUMN1 40 REFADJ 1_0402_1% 1_0402_1% 1_0402_1% 1_0402_1% 39 NTC_La PC6006 0.12U_0402_10V6K PR6020 499_0402_1% 的 compon en t D @ PC6004 0.1U_0402_25V6 APL3 GPU_VID PR6045 COMP 38 PR6037 0_0402_5% 29 COMP 37 layout 上 : 請 將 Tota l DC R sensin g 放 靠 近Control 近 Control le r @ PC6003 0.1U_0402_25V6 ISEN2 30K_0402_5% GPU_PSI ISEN1 GPU_PROG6 NVVDD_PSI 36 @ PR6036 PQ8203A DMN53D0LDW-7 2N SOT363-6 NVVDD1_ENP 0_0402_5% NVVDD_ISUMP4 PC6014 1U_0402_6.3V6K @ +1.8VS 35 GPU_LPC @ PR6012 FBRTN 0.01U_0402_16V 0_0402_5% B 34 GPU_PROG4 NVVDD_ISUMP3 PR6010 PR6011 PR6013 G2G3@ PR6014 0_0402_5% 0_0402_5% FB 33 GPU_PROG3 NVVDD1_EN +3VS 0_0402_5% PR6022 10K_0402_5% 43,46,49> 32 FBRTN PQ8203B DMN53D0LDW-7 2N SOT363-6 PR6034 1 +3VALW 31 NVVDD_ISUMP2 NTC_La NTC_Lb @PR6008 @PR6009 2 REFIN FBRTN PR6069 0.1U_0402_25V6 PC6009 @ 0.1U_0402_25V6 PR6024 1K_0402_1% PR6029 100_0402_5% @ PC6011 309_0402_1% 16.5K_0402_1% @ PR6025 @ 0_0402_5% PU6000 PR6053 PR6068 @ 0_0402_5% 6.19K_0402_1% NVVDD_VSS_SENSE @ 0.1U_0402_25V6 0.1U_0402_25V6 PC6012 C PC6010 @ PR6023 100_0402_5% +NVVDD1 @ PC6007 0.1U_0402_25V6 @ PR6021 0_0402_5% NVVDD_VCC_SENSE 30 0_0402_5% SS @ PR6019 0.015U_0402_16V7K 1 @ PR6016 0_0402_5% PR6017 2.4K_0402_1% @ @ VINMON 2 0_0402_5% PC6005 1 PC6017 @ 0.1U_0402_25V6 @ PR6015 2 EAP PC6002 0.01U_0402_16V7K 10K_0402_5% D 26 PR6000 LLTH G2G3@ PR6006 91K_0402_1% 19.1K_0402_1% 12.4K_0402_1% G1@ PR6001 20K_0402_1% VREF PR6007 PC6000 0.1U_0402_25V6 1 NVVDD_ISUMP1 PR6003 20K_0402_1% NVVDD_B+ OCP setting PR6007 Tuesday, August 16, 2016 Sheet 69 of 82 GPU_B+ PR6101 4 3 0.005_2512_1% A NVVDD_B+ 0.005_2512_1% NVVDD1 TDC 121A Peak Current 280A OCP=280A 10 11 12 13 14 A +5VS PR6103 PW M ZCD_EN# VCIN CGND BOOT NC PHASE VIN VIN PGND SW SW SW SW CGND GL DSBL# THW n VDRV PGND GL SW SW SW SW SW SW SW 28 27 26 25 24 23 22 21 20 19 18 17 16 15 10K_0402_1% PR6106 2.2_0603_1% GPU_PH1 PL6100 GPU_PH1 PR6108 2.2_0603_1% SIC632CDT1GE3_POWERPAK31_5X5 +NVVDD1 0.22UH_MMD12DZNR22MEX_40A_20% 1 + + GPU_SNB1 2 PC6112 33U_D2_25VM_R40M PC6111 10U_0805_25V6K~D PC6110 10U_0805_25V6K~D CSSN_NVVDD @ PR6107 0_0402_5% PC6102 PC6109 10U_0805_25V6K~D PC6107 10U_0805_25V6K~D EMI@ PC6106 2200P_0402_50V7K EMI@ PC6105 0.1U_0402_25V6 EMI@ PC6104 1000P_0402_50V7K EMI@ PC6100 1U_0402_25V6K PU6100 0.1U_0603_50V7K B CSSP_NVVDD 0_0402_5% CSSN_B+ PC6103 1U_0603_16V7 PC6101 1U_0603_16V7 PR6104 1K_0402_1% +5VS NVVDD_B+ CSSP_B+ GPU_PWM1 @ PR6105 0_0402_5% @ PR6102 +5VS PC6113 3300P_0805_50V7K NVVDD_ISUMP1 NVVDD_ISUMN1 470U_D2_2VM_R4.5M~D PC6108 PR6100 B+ B 0_0402_5% +5VS PR6110 C 10K_0402_1% GPU_PH2 PL6101 GPU_PH2 PR6115 2.2_0603_1% SIC632CDT1GE3_POWERPAK31_5X5 0.22UH_MMD12DZNR22MEX_40A_20% NVVDD_ISUMP2 GPU_SNB2 D NVVDD_ISUMN2 D Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 Issued Date Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_+NVVDD1 Size Document Number Rev 0.3 LA-D751P Date: 1 + + +NVVDD1 470U_D2_2VM_R4.5M~D PC6124 PR6113 2.2_0603_1% 2 PC6123 33U_D2_25VM_R40M PC6126 10U_0805_25V6K~D 0.1U_0603_50V7K 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0_0402_5% PC6115 PC6121 10U_0805_25V6K~D PC6125 10U_0805_25V6K~D 1 EMI@ PC6120 2200P_0402_50V7K EMI@ PC6119 0.1U_0402_25V6 EMI@ PC6118 1000P_0402_50V7K @ PR6114 CGND GL DSBL# THW n VDRV PGND GL SW SW SW SW SW SW SW PC6127 3300P_0805_50V7K EMI@ PC6117 1U_0402_25V6K 1 PW M ZCD_EN# VCIN CGND BOOT NC PHASE VIN VIN PGND SW SW SW SW PC6116 1U_0603_16V7 NVVDD_B+ PC6114 1U_0603_16V7 0_0402_5% +5VS 10 11 12 13 14 GPU_PWM2 @ PR6112 PU6101 PR6111 1K_0402_1% C PC6122 10U_0805_25V6K~D @ PR6109 +5VS Tuesday, August 16, 2016 Sheet 70 of 82 +5VS +5VS PR6201 10K_0402_1% GPU_PH3 PL6200 GPU_PH3 PR6206 2.2_0603_1% SIC632CDT1GE3_POWERPAK31_5X5 0.22UH_MMD12DZNR22MEX_40A_20% + + +NVVDD1 GPU_SNB3 NVVDD_ISUMP3 NVVDD_ISUMN3 470U_D2_2VM_R4.5M~D PC6207 PR6204 2.2_0603_1% 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PC6212 33U_D2_25VM_R40M PC6211 10U_0805_25V6K~D PC6210 10U_0805_25V6K~D PC6209 10U_0805_25V6K~D PC6208 10U_0805_25V6K~D 1 EMI@ PC6206 2200P_0402_50V7K EMI@ PC6205 0.1U_0402_25V6 EMI@ PC6204 1000P_0402_50V7K 0.1U_0603_50V7K CGND GL DSBL# THW n VDRV PGND GL SW SW SW SW SW SW SW PC6213 3300P_0805_50V7K EMI@ PC6200 1U_0402_25V6K 0_0402_5% PC6202 PW M ZCD_EN# VCIN CGND BOOT NC PHASE VIN VIN PGND SW SW SW SW PC6203 1U_0603_16V7 C 10 11 12 13 14 @ PR6205 PC6201 1U_0603_16V7 0_0402_5% +5VS NVVDD_B+ PU6200 PR6202 1K_0402_1% GPU_PWM3 @ PR6203 0_0402_5% D @ PR6200 D C 0_0402_5% +5VS B PR6211 G2G3@ 2.2_0603_1% GPU_PH4 G2G3@ PL6201 PR6213 G2G3@ 2.2_0603_1% SIC632CDT1GE3_POWERPAK31_5X5 +NVVDD1 0.22UH_MMD12DZNR22MEX_40A_20% + + GPU_SNB4 2 NVVDD_ISUMP4 NVVDD_ISUMN4 470U_D2_2VM_R4.5M~D G2G3@ PC6221 GPU_PH4 PC6226 33U_D2_25VM_R40M 10K_0402_1% G2G3@ G2G3@ PC6225 10U_0805_25V6K~D G2G3@ PC6224 10U_0805_25V6K~D G2G3@ PC6223 10U_0805_25V6K~D G2G3@ PC6222 10U_0805_25V6K~D 2 0_0402_5% G2G3@EMI@ PC6220 2200P_0402_50V7K G2G3@EMI@ PC6219 0.1U_0402_25V6 G2G3@EMI@ PC6218 1000P_0402_50V7K 0.1U_0603_50V7K CGND GL DSBL# THW n VDRV PGND GL SW SW SW SW SW SW SW PC6227 G2G3@ 3300P_0805_50V7K G2G3@EMI@ PC6217 1U_0402_25V6K PR6212 G2G3@ 0_0402_1% PC6215 G2G3@ PW M ZCD_EN# VCIN CGND BOOT NC PHASE VIN VIN PGND SW SW SW SW 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PC6216 G2G3@ 1U_0603_16V7 NVVDD_B+ PC6214 G2G3@ 1U_0603_16V7 @ PR6210 +5VS PR6208 G2G3@ PU6201 GPU_PWM4 B 10 11 12 13 14 G2G3@ PR6209 G2G3@ 1K_0402_1% 2 @ PR6207 +5VS A A Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 Issued Date Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_+NVVDD1 Size Rev 0.3 LA-D751P Date: Document Number Tuesday, August 16, 2016 Sheet 71 of 82 GPU_B+ NVVDDS_B+ PR6401 0.005_2512_1% PR6400 A PC6422 10U_0805_25V6K~D PC6421 10U_0805_25V6K~D EMI@ PC6420 2200P_0402_50V7K EMI@ PC6419 0.1U_0402_25V6 EMI@ PC6418 1000P_0402_50V7K EMI@ PC6417 1U_0402_25V6K NVVDDS_B+ 470U_D2_2VM_R4.5M~D PC6425 1 + S2 S2 S2 + PC6433 33U_D2_25VM_R40M PC6432 10U_0805_25V6K~D PC6436 10U_0805_25V6K~D EMI@ PC6431 2200P_0402_50V7K EMI@ PC6430 0.1U_0402_25V6 EMI@ PC6435 1000P_0402_50V7K AON6992_DFN5X6D-8-7 EMI@ PC6429 1U_0402_25V6K 2 D1 G1 D2/S1 G2 S2 S2 S2 G2 D2/S1 PQ6403 +NVVDD2 PL6401 0.22UH_MMD-10DZ-R22MES1L_35A_20% NVVDDS_VSS_SENSE NVVDDS_SNB2 + NVVDDS_VCC_SENSE PR6427 2 PC6441 100_0402_5% PC6440 3300P_0805_50V7K 470U_D2_2VM_R4.5M~D PC6438 PR6424 2.2_0603_1% 1 PR6435 100K_0402_5% @ +NVVDD2 100_0402_5% 1 NVVDDS_LG2 PR6425 Avoid high dV/dt 2 S2 S2 S2 G2 AON6992_DFN5X6D-8-7 D1 G1 AON6992_DFN5X6D-8-7 S2 S2 PC6428 3300P_0805_50V7K 2 @ PR6422 0_0402_5% @ PR6421 0_0402_5% PR6420 D1 @ 2 D1 G1 S2 G2 @ PR6432 0_0402_5% NVVDDS_SW2 PQ6402 AON6992_DFN5X6D-8-7 PC6434 47P_0402_50V8J G1 @ 100K_0402_5% PR6433 2 NVVDDS_HG2 1 4700P_0402_50V7K PC6439 C @ PR6431 0_0402_5% PR6414 @ 49.9_0603_1% 0.01U_0402_16V NVVDDS_SNB1 PC6445 22U_0603_6.3V6M PC6426 PR6409 2.2_0603_1% 51.1K_0402_1% 1000P_0402_25V8J PC6427 OCP & FS setting PR6426 20.5K_0402_1% PL6400 0.22UH_MMD-10DZ-R22MES1L_35A_20% PR6434 100K_0402_5% @ 1500P_0402_50V7K 1 PR6411 NVVDD2_PGOOD R2 C 2 16 PHASE2 17 VREF NVVDDS_COMP +NVVDD2 B NVVDDS_VREF @ 11 D2/S1 NVVDDS_LG1 NVVDDS_HG2 46.4K_0402_1% 309_0402_1% PC6437 PR6418 12 PC6444 22U_0603_6.3V6M PR6423 PR6408 10K_0402_5% 13 PR6419 +3V3_SYS NVVDDS_BST2 PR6415 10K_0402_5% R5 14 D2/S1 PQ6401 @ 0.1U_0603_16V R4 16.5K_0402_1% PR6417 4.32K_0402_1% PR6416 15 FBRTN FB NVVDDS_VIDBUF 6.19K_0402_1% 18 COMP VID OCS/CB PSI B R3 PGOOD Avoid high dV/dt R1 PVCC GND EN LGATE2 19 21 UGATE2 0_0402_5% NVVDDS_VID LGATE1 NVVDD2_PSI @ PR6412 BOOT2 UGATE1 PQ6400 CSSN_NVVDDS 10 @ PC6415 0.22U_0603_25V7K PU6400 UP1666QQKF_WQFN20_3X3 PR6407 2.2_0603_1% BOOT1 84.5K_0402_1% PR6406 0_0402_5% NVVDD2_EN 0_0402_5% PR6413 NVVDDS_PSI 0_0402_5% 46> PR6410 @ PC6442 22U_0603_6.3V6M @ NVVDDS_BST1 NVVDDS_HG1 NVVDDS_SW1 PR6430 @ 100K_0402_5% @ PR6428 0_0402_5% CSSP_NVVDDS PC6443 22U_0603_6.3V6M +1.8VS TPAD NVVDD2_EN 20 PC6423 0.22U_0603_25V7K REFADJ @ PR6429 0_0402_5% NVVDDS_SW2 PR6405 2.2_0603_1% NVVDDS_HG1 NVVDDS_LG2 NVVDDS_SW1 2 @ 0_0402_5% NVVDDS_LG1 REFIN PR6404 100K_0402_1% PR6403 NVVDD1_PGOOD PHASE1 PR6436 30K_0402_5% @ PC6416 2 2.2_0603_1% 1 +5VS +3V3_SYS 4.7U_0603_6.3V A C Place close to GPU NVVDD2 TDC 37A Peak Current 84A OCP=108A TYP MAX H/S Rds(on):6.7mohm ,8.5mohm L/S Rds(on):2mohm ,2.5mohm D D Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_+NVVDD2 Size Document Number Rev 0.3 LA-D751P Date: Tuesday, August 16, 2016 Sheet 72 of 82 PR8211 PR8211 +1.35VS_VGAP Vout = 1.55V TDC 25.9A Peak Current 37A OCP current 44.4A FSW=400kHz TYP H/S Rds(on):6.7mohm L/S Rds(on):1.8mohm PR8211 D 34.8K_0402_1% SAMSUNG@ PJP8200@ +1.35VS_B+ 34.8K_0402_1%30K_0402_1% G3@ +5VALW MIRCON@ 2 GPU_B+ PGOOD PWR_VGA_CORE_LGATE1 14 8.66K_0402_1% PWR_VGA_CORE_UGATE2 15 PC8213 PR8207 0.22U_0603_25V7K PWR_VGA_CORE_BOOT22 2.2_0603_5% 1PWR_VGA_CORE_BOOT2_1 16 PWR_VGA_CORE_PHASE2 17 PWR_VGA_CORE_LGATE2 G1 G2 19 S2 PWR_VGA_CORE_PHASE1 S2 20 S2 PC8206 PR8205 0.22U_0603_25V7K PWR_VGA_CORE_BOOT12 2.2_0603_5% 1PWR_VGA_CORE_BOOT1_1 LGATE1 UGATE2 PR8208 10K_0402_1% BOOT2 REFIN PHASE2 REFADJ LGATE2 VREF 11 SS VSNS 12 PR8209 100_0402_5% EMI@ PC8220 1000P_0402_50V7K + C Pl8201 S COIL 0.47UH +-20% PCMB063T-R47MS 18A +1.35VS_VGAP G2 PR8210@EMI@ 4.7_1206_5% S2 S2 S2 PJP8201 2 +1.35VS_VGA JUMP_43X118 @ PJP8202 2 JUMP_43X118 @ PC8219@EMI@ 680P_0402_50V7K OPS PR8218 68.1K_0402_1% @ PR8215 52.3K_0402_1% RT8812AGQW-GP PR8220 PR8214 PC8222 B @ 0.1U_0402_25V6 0_0402_5% G1G2@ 1 MEM_VDD_CTL 10K_0402_5% PQ8202A DMN53D0LDW-7 2N SOT363-6 +3VALW PQ8202B DMN53D0LDW-7 2N SOT363-6 @ PR8211 34.8K_0402_1% 2 G3@ @ PC8216 47P_0402_50V8J RGND PC8218 0.1U_0402_25V6 GND 10 + D2/S1 21 PC8215 0.1U_0402_25V6 PC8217 2200P_0402_50V7K PWR_VGA_CORE_SS 1 VID 0_0402_5% FBVDD/Q_EN PR8206 PQ8201 AON6992 2N DFN5X6D G1 @ PC8211 0.1U_0402_25V6 @ PR8216 PSI FBVDD_PSI 0_0402_5% C PHASE1 +3VS EN PC8210@EMI@ 680P_0402_50V7K 10U_0805_25V6K~D PC8214 @ PR8219 D1 +1.35VS_VGA_PGOOD FBVDD/Q_ENP EMI@ PC8221 1U_0402_25V6K PR8204@EMI@ 4.7_1206_5% 100K_0402_1% MAX ,8.5mohm ,2.3mohm +1.35VS_VGAP BOOT1 PWR_VGA_CORE_UGATE1 PC8208 220U_D2 SX_2VY_R9M 13 PC8207 220U_D2 SX_2VY_R9M UGATE1 10U_0805_25V6K~D PC8212 PR8203 Pl8200 S COIL 0.47UH +-20% PCMB063T-R47MS 18A 2 TON +1V8_AON D2/S1 +1.35VS_B+ PR8202 383K_0402_1% PWR_VGA_CORE_TON 0.1U_0402_25V6 PR8201 2.2_0402_1% PC8200 2.2U_0603_16V6K PVCC PU8200 D1 PC8205 1PWR_VGA_CORE_TON_1 1 MIRCON@ 18 SAMSUNG@ 10U_0805_25V6K~D PC8204 RT8812_PVCC 52.3K_0402_1% 68.1K_0402_1% 10U_0805_25V6K~D PC8203 PR8200 2.2_0603_5% PQ8200 AON6992 2N DFN5X6D PR8215 PR8215 EMI@PC8202 0.1U_0402_25V6 2 EMI@PC8201 2200P_0402_50V7K JUMP_43X39 D FB_VDDQ_SENSE B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_+1.55VRAM Size R ev 0.3 LA-D751P Date: Document Number Tuesday, August 16, 2016 Sheet 73 of 82 PC6414 10U_0603_6.3V6M PC6413 10U_0603_6.3V6M 2 2 2 1 1 1 2 2 1 1 470U_D2_2VM_R4.5M~D PC6391 470U_D2_2VM_R4.5M~D PC6390 470U_D2_2VM_R4.5M~D PC6389 470U_D2_2VM_R4.5M~D PC6388 PC6401 10U_0603_6.3V6M PC6412 10U_0603_6.3V6M PC6411 10U_0603_6.3V6M PC6410 10U_0603_6.3V6M PC6409 10U_0603_6.3V6M PC6408 10U_0603_6.3V6M PC6407 10U_0603_6.3V6M PC6406 10U_0603_6.3V6M PC6405 10U_0603_6.3V6M PC6400 10U_0603_6.3V6M PC6399 10U_0603_6.3V6M PC6398 10U_0603_6.3V6M PC6397 10U_0603_6.3V6M PC6396 10U_0603_6.3V6M PC6395 10U_0603_6.3V6M PC6394 10U_0603_6.3V6M PC6393 10U_0603_6.3V6M PC6404 10U_0603_6.3V6M PC6403 10U_0603_6.3V6M PC6402 10U_0603_6.3V6M PC6387 4.7U_0603_6.3V6K 2 1 PC6386 4.7U_0603_6.3V6K PC6385 4.7U_0603_6.3V6K PC6384 4.7U_0603_6.3V6K PC6383 4.7U_0603_6.3V6K PC6382 4.7U_0603_6.3V6K PC6381 4.7U_0603_6.3V6K PC6380 4.7U_0603_6.3V6K 470U_D2_2VM_R4.5M~D PC6363 2 2 2 2 1 1 1 1 PC6360 47U_0805_6.3V6M PC6373 47U_0805_6.3V6M PC6372 22U_0805_6.3VAM PC6371 22U_0805_6.3VAM PC6370 22U_0805_6.3VAM PC6359 22U_0805_6.3VAM PC6369 1U_0402_6.3V6K PC6368 1U_0402_6.3V6K PC6367 1U_0402_6.3V6K PC6366 1U_0402_6.3V6K PC6358 1U_0402_6.3V6K PC6365 1U_0402_6.3V6K PC6392 10U_0603_6.3V6M PC6362 10U_0603_6.3V6M PC6377 10U_0603_6.3V6M PC6376 10U_0603_6.3V6M PC6361 10U_0603_6.3V6M PC6375 4.7U_0603_6.3V6K PC6374 4.7U_0603_6.3V6K 2 2 2 2 2 PC6357 1U_0402_6.3V6K PC6356 1U_0402_6.3V6K PC6355 1U_0402_6.3V6K PC6354 1U_0402_6.3V6K PC6353 1U_0402_6.3V6K PC6352 1U_0402_6.3V6K PC6351 1U_0402_6.3V6K PC6350 1U_0402_6.3V6K PC6349 1U_0402_6.3V6K PC6348 1U_0402_6.3V6K PC6347 1U_0402_6.3V6K PC6346 1U_0402_6.3V6K PC6345 1U_0402_6.3V6K PC6379 4.7U_0603_6.3V6K PC6378 47U_0805_6.3V6M PC6364 1U_0402_6.3V6K 1 PC6343 1U_0402_6.3V6K PC6342 1U_0402_6.3V6K PC6341 1U_0402_6.3V6K PC6340 1U_0402_6.3V6K PC6339 1U_0402_6.3V6K PC6338 1U_0402_6.3V6K PC6337 1U_0402_6.3V6K 1 PC6336 1U_0402_6.3V6K 2 2 2 2 PC6335 1U_0402_6.3V6K PC6334 1U_0402_6.3V6K PC6333 1U_0402_6.3V6K PC6332 1U_0402_6.3V6K PC6331 1U_0402_6.3V6K PC6330 1U_0402_6.3V6K PC6329 1U_0402_6.3V6K PC6328 1U_0402_6.3V6K PC6327 1U_0402_6.3V6K PC6326 1U_0402_6.3V6K PC6325 1U_0402_6.3V6K PC6324 1U_0402_6.3V6K PC6323 1U_0402_6.3V6K PC6344 1U_0402_6.3V6K 2 PC6321 1U_0402_6.3V6K PC6320 1U_0402_6.3V6K PC6319 1U_0402_6.3V6K PC6318 1U_0402_6.3V6K PC6317 1U_0402_6.3V6K PC6316 1U_0402_6.3V6K PC6315 1U_0402_6.3V6K 1 PC6314 1U_0402_6.3V6K PC6313 1U_0402_6.3V6K PC6312 1U_0402_6.3V6K PC6311 1U_0402_6.3V6K PC6310 1U_0402_6.3V6K PC6309 1U_0402_6.3V6K PC6308 1U_0402_6.3V6K PC6307 1U_0402_6.3V6K PC6306 1U_0402_6.3V6K PC6305 1U_0402_6.3V6K PC6304 1U_0402_6.3V6K PC6303 1U_0402_6.3V6K PC6302 1U_0402_6.3V6K PC6301 1U_0402_6.3V6K PC6322 1U_0402_6.3V6K + 82 of 74 Sheet Tuesday, August 16, 2016 Date: Rev 0.3 Document Number Size PWR_VGA DECOUPLING LA-D751P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title 2017/01/06 Deciphered Date 2016/01/06 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 1uF_0402 X 16 PC6300 1U_0402_6.3V6K 2 2 1 B B + + + + C 2 2 C 1 1 D D +NVVDDS 470uF X 47uF_0805 X 10uF_0603 X +NVVDD2 +NVVDD 470uF X 47uF_0805 X 22uF_0603 X 10uF_0603X 23 4.7uF_0603 X 1uF_0402 X 49 +NVVDD1 A A 97.6K_0402_1% PC500 VR_SVID_DATA PC501 1 @ PR506 0_0402_5% @ PR504 0_0402_5% CPU_B+ PC502 0.1U_0402_25V6 2 PR503 100_0402_1% PR502 75_0402_1% 1 @ PR507 0_0402_5% @ PR509 0_0402_5% @ PR511 0_0402_5% @ +5VS D PC503 1U_0402_16V6K 49.9_0402_1% PR508 @ PR510 0_0402_5% 10_0402_1% PR512 2 PC504 0.22U_0603_25V7K 470K_0402_5%_B25/50 4700K +3VS PR515 1.91K_0402_1% 2 1000P_0402_50V7K 6800P_0402_25V7K @ PR520 IMVP_VR_ON 0_0402_5% @ PR523 1 2K_0402_1% 3.6K_0402_1% PR524 1.27K_0402_1% ISUMN_SA 0_0402_5% PU500 PC525 ISEN2_GT 2 PR530 3.6K_0402_1% 11K_0402_1% PR529 2 PC512 0.022U_0402_25V7K PC510 0.01UF_0402_25V7K 1U_0402_16V7K PC511 1 PR533 2.74K_0402_1% 2200P_0402_50V7K 680P_0402_50V7K PC521 0.022U_0402_25V7K 2 2 PR542 11K_0402_1% 2 1K_0402_1% VSSSENSE 6800P_0402_25V7K PR549 2K_0402_1% 2 4.87K_0402_1% PC538 1 PC536 68P_0402_50V8J PR551 2 PC533 470P_0402_50V7K PC534 0.01UF_0402_25V7K PR550 3.57K_0402_1% PC537 680P_0402_50V7K 1 PR546 1K_0402_1% 1 2 PR547 27.4K_0402_1% 1 PC5011 1000P_0402_50V7K 2 PC535 330P_0402_50V7K 1 PH504 470K_0402_5%_B25/50 4700K VCCSENSE PR545 12.4K_0402_1% ISUMP_VCORE 4.42K_0402_1% 10K +-5% 0402 B25/50 4250K PH503 PR544 2200P_0402_50V7K PR543 PC531 0.22U_0402_16V7K 0.022U_0402_25V7K 4700P_0402_16V7K PWM2_GT PC527 ISEN1_VCORE 2 ISUMN_VCORE 0.022U_0402_25V7K PC526 ISEN2_VCORE 383_0402_1% PC532 A A Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 Issued Date Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_VCORE_ISL95855 Size Document Number Re v 0.3 LA-D751P Date: PC515 0.01UF_0402_25V7K B 93.1K_0402_1% PR548 VCCSA_SENSE 0.022U_0402_25V7K ISEN1_GT VSSSA_SENSE PC514 1500P_0402_50V7K 4.53K_0402_1% PC522 2 2K_0402_1% PR536 PC524 ISEN3_VCORE PR532 316_0402_1% PC530 PWM1_GT FCCM_VCORE PC529 PR541 FCCM_GT PWM1_VCORE 294_0402_1% PC528 0.022U_0402_25V7K PWM2_VCORE PWM3_VCORE PR537 2200P_0402_50V7K PR540 EP C ISUMP_SA PC520 68P_0402_50V8J 1K_0402_1% 1U_0402_16V7K FCCM_SA 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1K_0402_1% PC523 1U_0402_16V7K B 49 PROG5 PWM_C FCCM_C ISUMN_C ISUMP_C RTN_C FB_C COMP_C IMON_C PWM3_A PWM2_A PWM1_A 2 PC517 0.033U_0402_16V7K ISUMN_GT PC518 PR538 1 PC516 0.15U_0402_16V7K 2 10K +-5% 0402 B25/50 4250K PH502 PR535 11K_0402_1% ISUMP_GT PR534 2.61K_0402_1% PC513 0.01UF_0402_25V7K PSYS IMON_B NTC_B COMP_B FB_B RTN_B ISUMP_B ISUMN_B ISEN1_B ISEN2_B FCCM_B PWM1_B 2 10 11 12 PC519 330P_0402_50V7K 2200P_0402_50V7K PWM_SA PR539 110K_0402_1% VSSGT_SENSE VR_ENABLE VR_READY VR_HOT# SCLK ALERT# SDA VCC VIN PROG1 PROG2 PROG3 PROG4 VCCGT_SENSE 10K +-5% 0402 B25/50 4250K PH501 PR528 48.7K_0402_1% PWM2_B IMON_A NTC_A COMP_A FB_A RTN_A ISUMP_A ISUMN_A ISEN1_A ISEN2_A ISEN3_A FCCM_A PR531 2.94K_0402_1% PC509 ISL95829HRTZ-T_TQFN48_6X6 0_0402_5% PR527 I_SYS @ PR526 C 48 47 46 45 44 43 42 41 40 39 38 37 PR525 1K_0402_1% PC508 470P_0402_50V7K 2 VR_PWRGD PR522 PC507 2 PR521 PC506 68P_0402_50V8J PR518 110K_0402_1% PC505 1 PR517 28K_0402_1% 2 PC5010 1000P_0402_50V7K 1 PR514 12.4K_0402_1% PR513 27.4K_0402_1% 330P_0402_50V7K PR519 169K_0402_1% PR516 16.9K_0402_1% VR_SVID_CLK VR_SVID_ALERT# PH500 2 PR500 PR501 45.3_0402_1% +VCCST D VR_HOT# 47P_0402_50V8J~D 1_0402_5% PR505 Tuesday, August 16, 2016 Sheet 75 of 82 +VCC_CORE TDC PL2 :56A Peak Current 68A OCP Current 81.6A DCR 0.66mohm +/-7% Load Line 1.8mV/A Input Current: 8.2A 1.5V*56A/0.85/12V=8.2 PC5005 PR558 100K_0402_1% ISEN1_VCORE CORE_V2N 1 @ PR561 100K_0402_1% ISUMN_VCORE PC5006 C PR567 3.65K_0603_1% @EMI@ PC556 33P_0603_50V8J SIC632CDT1GE3_POWERPAK31_5X5 PL502 0.15UH_PCME064T-R15MS0R667_36A_20% CORE_V2N 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PR568 100K_0402_1% 2 CGND GL DSBL# THWn VDRV PGND GL SW SW SW SW SW SW SW ISEN2_VCORE CORE_V1N CORE_V3N @ PR570 100K_0402_1% @ PR571 100K_0402_1% PC5007 EMI@PC5018 1000P_0402_50V7K CGND GL DSBL# THWn VDRV PGND GL SW SW SW SW SW SW SW 28 27 26 25 24 23 22 21 20 19 18 17 16 15 10K_0402_1% PWM ZCD_EN# VCIN CGND BOOT NC PHASE VIN VIN PGND SW SW SW SW 1U_0402_6.3V6K B PR577 3.65K_0603_1% PL503 0.15UH_PCME064T-R15MS0R667_36A_20% PR578 100K_0402_1% 2 SIC632CDT1GE3_POWERPAK31_5X5 @EMI@ PC564 33P_0603_50V8J ISUMP_VCORE EMI@PC5017 1U_0402_25V6K EMI@ PC563 2200P_0402_50V7K 1 2 EMI@ PC562 0.1U_0402_25V6 PC561 10U_0805_25V6K PC560 10U_0805_25V6K PU504 10 11 12 13 14 1_0402_5% CORE_V3N PC558 0.22U_0603_16V7K PR574 4.7_0603_1% PC559 10U_0805_25V6K 2 @ PR573 0_0402_5% @ PR576 0_0402_5% FCCM_VCORE PR5019 PWM3_VCORE 1_0402_5% @EMI@ PR575 10_1206_5% 1 PC557 1U_0402_6.3V6K PR5020 +5VS B PR5030 PWM ZCD_EN# VCIN CGND BOOT NC PHASE VIN VIN PGND SW SW SW SW C PR569 10_0402_1% EMI@PC5016 1000P_0402_50V7K EMI@PC5015 1U_0402_25V6K EMI@ PC555 2200P_0402_50V7K 1 EMI@ PC554 0.1U_0402_25V6 PC553 10U_0805_25V6K PC552 10U_0805_25V6K PU503 10 11 12 13 14 1U_0402_6.3V6K ISUMP_VCORE PC550 0.22U_0603_16V7K PR564 4.7_0603_1% 1U_0402_6.3V6K PC551 10U_0805_25V6K 2 @ PR566 0_0402_5% FCCM_VCORE 2 1_0402_5% 10K_0402_1% PWM2_VCORE PR5029 @EMI@ PR565 10_1206_5% 1 PR5011 PC549 @ PR563 0_0402_5% PR5004 1_0402_5% +5VS 要 要 PR5 69 pi n 要 要 PR5 79 pi n 要 要 PR5 59 pi n @ PR560 100K_0402_1% @ ISUMP_VCORE pin1 pin1 pin1 2 CORE_V3N PR560,PR581 PR561,PR571 PR570,PR580 CORE_V1N PR557 3.65K_0603_1% SIC632CDT1GE3_POWERPAK31_5X5 ISUMN_VCORE EMI@PC5014 1000P_0402_50V7K EMI@PC5013 1U_0402_25V6K EMI@ PC547 2200P_0402_50V7K 1 2 EMI@ PC546 0.1U_0402_25V6 + PC545 10U_0805_25V6K 2 PC544 10U_0805_25V6K + PC543 10U_0805_25V6K 1 100U_25V_M PC542 100U_25V_M PC539 FBMA-L11-453215800LMA90T_2P +VCC_CORE PL501 0.15UH_PCME064T-R15MS0R667_36A_20% ISEN3_VCORE CORE_V1N @ PR580 100K_0402_1% @ PR581 100K_0402_1% CORE_V2N 4.7_0603_1% 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D PR579 10_0402_1% CGND GL DSBL# THWn VDRV PGND GL SW SW SW SW SW SW SW ISUMN_VCORE PL500 PWM ZCD_EN# VCIN CGND BOOT NC PHASE VIN VIN PGND SW SW SW SW 1U_0402_6.3V6K PR559 10_0402_1% PR554 EMI@ PU502 10 11 12 13 14 1_0402_5% PC541 0.22U_0603_16V7K 1U_0402_6.3V6K @ PR556 0_0402_5% FCCM_VCORE PR5028 @EMI@ PC548 @EMI@ PR555 33P_0603_50V8J 10_1206_5% 2 PR599 PWM1_VCORE @ PR552 0_0402_5% 10K_0402_1% PR553 PC540 CPU_B+ B+ 1_0402_5% +5VS PR562 20M_0402_5% D A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_VCORE_+VCC_CORE Size Date: Document Number LA-D751P Tuesday, August 16, 2016 Sheet 76 of Re v 0.3 82 Input Current: 5.7A 1.5V*39A/0.85/12V=5.7 +VCC_GT TDC PL2 :39A Peak Current 54A OCP Current 64.8A DCR 0.66mohm +/-7% Load Line 2.65mV/A PC5008 PR5031 PU507 2 ISEN1_GT @ PR589 100K_0402_1% GT_V2N 1 @EMI@ PC570 ISUMP_GT @ 要 要 PR5 88 pi n2 要 要 PR5 97 pi n2 pin1 pin1 PR587 100K_0402_1% PR586 3.65K_0603_1% PR589 PR598 PL505 0.15UH_PCME064T-R15MS0R667_36A_20% GT_V1N SIC632CDT1GE3_POWERPAK31_5X5 EMI@PC5020 1000P_0402_50V7K EMI@PC5019 1U_0402_25V6K EMI@ PC572 2200P_0402_50V7K 1 EMI@ PC571 0.1U_0402_25V6 PC569 10U_0805_25V6K~D PC568 10U_0805_25V6K~D PC565 10U_0805_25V6K~D 0.22U_0603_16V7K PR583 4.7_0603_1% D +VCCGT PR588 10_0402_1% CPU_B+ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CGND GL DSBL# THWn VDRV PGND GL SW SW SW SW SW SW SW PC567 2 PR572 20M_0402_5% PWM ZCD_EN# VCIN CGND BOOT NC PHASE VIN VIN PGND SW SW SW SW @EMI@ PR584 1 10 11 12 13 14 1U_0402_6.3V6K 4.7_1206_5% @ PR585 0_0402_5% PR5021 FCCM_GT 1_0402_5% 10K_0402_1% 1_0402_5% @ PR590 0_0402_5% PWM1_GT 680P_0603_50V7K 1 PC566 1U_0402_6.3V6K D PR5022 +5VS ISUMN_GT PC5009 PR5032 +5VS 4.7_1206_5% PR596 100K_0402_1% PR595 3.65K_0603_1% 2 ISEN2_GT @ PR598 100K_0402_1% GT_V1N ISUMN_GT 1 ISUMP_GT @EMI@ PC580 SIC632CDT1GE3_POWERPAK31_5X5 PL506 0.15UH_PCME064T-R15MS0R667_36A_20% GT_V2N +VCC_SA TDC PL2 :10A Peak Current 11A OCP Current 13.2A DCR 7.4mohm typ Load Line 9.1mV/A PR597 10_0402_1% 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CGND GL DSBL# THWn VDRV PGND GL SW SW SW SW SW SW SW C 680P_0603_50V7K EMI@PC5022 1000P_0402_50V7K EMI@PC5021 1U_0402_25V6K EMI@ PC579 2200P_0402_50V7K 1 EMI@ PC578 0.1U_0402_25V6 PC577 10U_0805_25V6K~D PC576 10U_0805_25V6K~D PWM ZCD_EN# VCIN CGND BOOT NC PHASE VIN VIN PGND SW SW SW SW PU510 10 11 12 13 14 0.22U_0603_16V7K PR592 4.7_0603_1% PC575 10U_0805_25V6K~D PR5023 @ PR594 0_0402_5% FCCM_GT PC574 B 1U_0402_6.3V6K @ PR591 0_0402_5% 2 PWM2_GT 10K_0402_1% @EMI@ PR593 1 1_0402_5% PC573 1U_0402_6.3V6K PR5024 C 1_0402_5% Input Current: 1.0A 1.05V*10A/0.85/12V=1.0 B SIC531CDT1GE3_POWERPAK22_4X3 FCCM_SA @ PR5006 CPU_B+ 0_0402_5% 2 PC586 0.22U_0603_16V7K PR5005 1_0603_5% ZCD_EN# VCIN CGND BOOT PHASE VIN PGND CGND PWM VDRV PGND GL VSWH 13 12 11 10 @ PR5001 0_0402_5% PWM_SA +VCCSA PL508 0.47UH_PCMB053T-R47MS_12A_20% PR5027 10_0402_1% PR5003 3.65K_0603_1% 1_0402_5% PR5026 ISUMP_SA ISUMN_SA A PR582 20M_0402_5% 680P_0603_50V7K @EMI@ PC587 2 4.7U_0402_6.3V6M +5VS PC5002 4.7U_0402_6.3V6M PC588 1_0402_5% 4.7_1206_5% PR5025 @EMI@ PR5002 EMI@PC5024 1000P_0402_50V7K EMI@PC5023 1U_0402_25V6K PC585 10U_0805_25V6K PC584 10U_0805_25V6K EMI@ PC581 2200P_0402_50V7K PC583 10U_0805_25V6K EMI@ PC582 0.1U_0402_25V6 PU511 @ Compal Electronics, Inc Compal Secret Data Security Classification Issued Date A 2016/01/06 Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_VCORE_+VCCGT,+VCCSA Size Document Number Rev 0.3 LA-D751P Date: Tuesday, August 16, 2016 Sheet 77 of 82 A 2 B 2 Issued Date C 2 PC1215 1U_0201_6.3V6M PC1216 1U_0201_6.3V6M PC1217 1U_0201_6.3V6M PC1218 1U_0201_6.3V6M Security Classification 2016/01/06 1 Deciphered Date D 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 1 Compal Secret Data Size Date: 1 1 Tuesday, August 16, 2016 E Sheet 78 of PC1235 1U_0201_6.3V6M PC1234 1U_0201_6.3V6M PC1233 1U_0201_6.3V6M 1 1 1 1 1 1 Document Number LA-D751P 82 PC1198 1U_0201_6.3V6M PC1197 1U_0201_6.3V6M PC1196 1U_0201_6.3V6M PC1195 1U_0201_6.3V6M PC1194 1U_0201_6.3V6M PC1193 1U_0201_6.3V6M PC1192 1U_0201_6.3V6M PC1191 1U_0201_6.3V6M PC1190 1U_0201_6.3V6M PC1189 1U_0201_6.3V6M PC1188 1U_0201_6.3V6M PC1187 1U_0201_6.3V6M PC1186 1U_0201_6.3V6M PC1185 1U_0201_6.3V6M 1 1 1 1 1 1 1 1 1 1 PC1160 1U_0201_6.3V6M PC1159 1U_0201_6.3V6M PC1158 1U_0201_6.3V6M PC1157 1U_0201_6.3V6M PC1156 1U_0201_6.3V6M PC1155 1U_0201_6.3V6M PC1154 1U_0201_6.3V6M PC1153 1U_0201_6.3V6M PC1152 1U_0201_6.3V6M PC1151 1U_0201_6.3V6M PC1150 1U_0201_6.3V6M PC1149 1U_0201_6.3V6M PC1148 1U_0201_6.3V6M PC1147 1U_0201_6.3V6M PC1146 1U_0201_6.3V6M PC1145 1U_0201_6.3V6M PC1144 1U_0201_6.3V6M PC1143 1U_0201_6.3V6M PC1142 1U_0201_6.3V6M PC1141 1U_0201_6.3V6M 1 1 1 1 1 1 PC1122 10U_0402_6.3V6M PC1121 10U_0402_6.3V6M PC1120 10U_0402_6.3V6M PC1119 10U_0402_6.3V6M PC1118 10U_0402_6.3V6M PC1117 10U_0402_6.3V6M PC1116 10U_0402_6.3V6M PC1115 10U_0402_6.3V6M PC1114 10U_0402_6.3V6M 2 1 1 1 1 1 1 PC1096 10U_0402_6.3V6M PC1095 10U_0402_6.3V6M PC1094 10U_0402_6.3V6M PC1093 10U_0402_6.3V6M PC1092 10U_0402_6.3V6M PC1091 10U_0402_6.3V6M PC1090 10U_0402_6.3V6M PC1089 10U_0402_6.3V6M PC1088 10U_0402_6.3V6M PC1087 10U_0402_6.3V6M 2 1 1 1 1 2 1 1 1 1 PC1008 220U_D7_2VM_R6M PC1009 220U_D7_2VM_R6M PC1014 47U_0603_6.3V6M PC1013 47U_0603_6.3V6M PC1012 47U_0603_6.3V6M PC1011 47U_0603_6.3V6M PC1010 220U_D7_2VM_R6M 1 1 PC1070 10U_0402_6.3V6M PC1069 10U_0402_6.3V6M 2 1 1 1 PC1044 1U_0201_6.3V6M PC1043 1U_0201_6.3V6M PC1042 1U_0201_6.3V6M PC1041 10U_0402_6.3V6M PC1040 10U_0402_6.3V6M PC1039 10U_0402_6.3V6M 2 PC1019 10U_0402_6.3V6M 1 PC1038 10U_0402_6.3V6M 2 PC1018 47U_0805_6.3V6M PC1037 10U_0402_6.3V6M PC1036 10U_0402_6.3V6M PC1017 220U_D2_2.5VY_R9M PC1016 47U_0603_6.3V6M PC1007 220U 2.5V Y D2 ESR9M H1.9 SX PC1068 10U_0402_6.3V6M PC1035 22U_0603_6.3V6M PC1034 22U_0603_6.3V6M PC1033 22U_0603_6.3V6M PC1032 22U_0603_6.3V6M PC1031 22U_0603_6.3V6M PC1030 22U_0603_6.3V6M PC1029 22U_0603_6.3V6M PC1028 22U_0603_6.3V6M PC1015 47U_0603_6.3V6M 1 PC1067 10U_0402_6.3V6M PC1066 10U_0402_6.3V6M PC1065 10U_0402_6.3V6M PC1064 10U_0402_6.3V6M PC1063 10U_0402_6.3V6M PC1062 10U_0402_6.3V6M 2 PC1058 10U_0402_6.3V6M PC1061 10U_0402_6.3V6M PC1057 10U_0402_6.3V6M PC1060 10U_0402_6.3V6M 2 PC1056 10U_0402_6.3V6M PC1059 10U_0402_6.3V6M PC1084 10U_0402_6.3V6M PC1086 10U_0402_6.3V6M 2 PC1083 10U_0402_6.3V6M PC1085 10U_0402_6.3V6M PC1111 1U_0201_6.3V6M PC1113 10U_0402_6.3V6M 2 PC1110 1U_0201_6.3V6M PC1112 10U_0402_6.3V6M 1 D PC1232 1U_0201_6.3V6M PC1184 1U_0201_6.3V6M PC1140 1U_0201_6.3V6M 2 PC1109 1U_0201_6.3V6M PC1082 10U_0402_6.3V6M PC1055 10U_0402_6.3V6M +VCCSA PC1231 1U_0201_6.3V6M PC1230 1U_0201_6.3V6M PC1229 1U_0201_6.3V6M PC1228 1U_0201_6.3V6M PC1183 1U_0201_6.3V6M 1 PC1137 1U_0201_6.3V6M PC1139 1U_0201_6.3V6M 2 1 1 PC1227 1U_0201_6.3V6M PC1182 1U_0201_6.3V6M 1 PC1136 1U_0201_6.3V6M PC1138 1U_0201_6.3V6M 2 PC1135 1U_0201_6.3V6M PC1108 1U_0201_6.3V6M PC1081 10U_0402_6.3V6M PC1054 10U_0402_6.3V6M + 1 PC1181 1U_0201_6.3V6M 1 1 1 2 PC1226 1U_0201_6.3V6M PC1225 1U_0201_6.3V6M PC1224 1U_0201_6.3V6M 1 PC1180 1U_0201_6.3V6M 2 PC1134 1U_0201_6.3V6M PC1107 1U_0201_6.3V6M PC1080 10U_0402_6.3V6M PC1053 10U_0402_6.3V6M PC1027 22U_0603_6.3V6M C 1 PC1175 1U_0201_6.3V6M PC1179 1U_0201_6.3V6M 2 1 1 PC1006 47U_0603_6.3V6M PC1005 47U_0805_6.3V6M VCC_GT 220uF X4 47uF_0805 X 22uF_0603 X 10uF_0402 X 35 1uF_0201 X 68 PC1223 1U_0201_6.3V6M PC1222 1U_0201_6.3V6M PC1221 1U_0201_6.3V6M PC1220 1U_0201_6.3V6M 1 PC1174 1U_0201_6.3V6M PC1178 1U_0201_6.3V6M 2 PC1133 1U_0201_6.3V6M PC1106 1U_0201_6.3V6M PC1079 10U_0402_6.3V6M PC1052 10U_0402_6.3V6M PC1026 22U_0603_6.3V6M PC1004 47U_0603_6.3V6M +VCCGT 1 PC1173 1U_0201_6.3V6M PC1177 1U_0201_6.3V6M 2 1 1 PC1025 22U_0603_6.3V6M PC1003 47U_0603_6.3V6M +VCC_CORE PC1219 1U_0201_6.3V6M 1 PC1172 1U_0201_6.3V6M PC1176 1U_0201_6.3V6M 2 PC1171 1U_0201_6.3V6M PC1132 1U_0201_6.3V6M PC1105 1U_0201_6.3V6M PC1078 10U_0402_6.3V6M PC1051 10U_0402_6.3V6M PC1024 22U_0603_6.3V6M PC1002 220U 2.5V Y D2 ESR9M H1.9 SX + 1 PC1213 1U_0201_6.3V6M 1 1 PC1050 10U_0402_6.3V6M PC1023 22U_0603_6.3V6M PC1000 220U_D7_2VM_R6M PC1001 220U 2.5V Y D2 ESR9M H1.9 SX 2 PC1212 1U_0201_6.3V6M PC1170 1U_0201_6.3V6M PC1131 1U_0201_6.3V6M PC1104 1U_0201_6.3V6M PC1077 10U_0402_6.3V6M PC1049 10U_0402_6.3V6M PC1022 22U_0603_6.3V6M PC1021 22U_0603_6.3V6M + 1 PC1211 1U_0201_6.3V6M 1 PC1076 10U_0402_6.3V6M PC1048 10U_0402_6.3V6M PC1047 10U_0402_6.3V6M 1 2 PC1210 1U_0201_6.3V6M PC1169 1U_0201_6.3V6M PC1130 1U_0201_6.3V6M PC1103 1U_0201_6.3V6M PC1075 10U_0402_6.3V6M PC1074 10U_0402_6.3V6M PC1046 10U_0402_6.3V6M + 1 PC1209 1U_0201_6.3V6M 1 PC1102 1U_0201_6.3V6M PC1101 1U_0201_6.3V6M PC1073 10U_0402_6.3V6M 2 PC1208 1U_0201_6.3V6M PC1168 1U_0201_6.3V6M PC1129 1U_0201_6.3V6M PC1128 1U_0201_6.3V6M PC1100 1U_0201_6.3V6M PC1072 10U_0402_6.3V6M 1 + 1 PC1207 1U_0201_6.3V6M PC1167 1U_0201_6.3V6M 2 PC1127 1U_0201_6.3V6M PC1099 1U_0201_6.3V6M 2 PC1020 22U_0603_6.3V6M B PC1206 1U_0201_6.3V6M PC1166 1U_0201_6.3V6M 2 PC1126 1U_0201_6.3V6M PC1098 1U_0201_6.3V6M 1 1 PC1205 1U_0201_6.3V6M PC1165 1U_0201_6.3V6M 2 PC1125 1U_0201_6.3V6M 2 PC1045 10U_0402_6.3V6M PC1204 1U_0201_6.3V6M PC1164 1U_0201_6.3V6M PC1163 1U_0201_6.3V6M PC1124 1U_0201_6.3V6M 1 VCC_CORE 220uF X3 47uF_0805 X 22uF_0603 X 10uF_0402 X 28 1uF_0201 X 63 PC1214 1U_0201_6.3V6M PC1203 1U_0201_6.3V6M PC1202 1U_0201_6.3V6M 1 2 PC1071 10U_0402_6.3V6M 2 PC1162 1U_0201_6.3V6M 1 + PC1201 1U_0201_6.3V6M 2 PC1097 1U_0201_6.3V6M PC1238 1U_0201_6.3V6M PC1200 1U_0201_6.3V6M 1 2 PC1123 1U_0201_6.3V6M + 1 PC1237 1U_0201_6.3V6M 2 PC1161 1U_0201_6.3V6M 1 2 + PC1199 1U_0201_6.3V6M PC1236 1U_0201_6.3V6M A E VCC_SA 220uF X1 47uF_0805 X 10uF_0402 X 1uF_0201 X Title PWR-CPU DECOUPLING Compal Electronics, Inc R ev 0.3 @ 10K_0402_5% VCCIO_PGOOD 15 BYP NC 10 12 16 21 PC599 22U_0603_6.3V6M PC598 22U_0603_6.3V6M PC597 22U_0603_6.3V6M PC596 22U_0603_6.3V6M 17 D +VCCIOP PR5014 10_0402_1% NC PR5009 4.7_1206_5% @EMI@ 14 NC ILMT 20 PL509 1UH_PCMB042T-1R0MS_4.5A_20% PC818 330P_0402_50V7K VCC EN FB 19 GND LX_VCCIO LX PC591 680P_0603_50V7K @EMI@ Rup SY8286RAC_QFN20_3X3 PR5012 @ PR5017 0_0402_5% @ PR5018 0_0402_5% VSSIO_SENSE Rdown PR5033 @ 0_0402_5% @ PR5034 0_0402_5% C C VCCIO_SENSE 21K_0402_1% PR5015 35.7K_0402_1% 1 LX GND BST_VCCIO PC593 0.1U_0603_25V7K 2 +3VALW IN PAD PC5003 1U_0603_6.3V6M PR5008 13 1M_0402_1% PC590 0.22U_0402_10V6K @ LX GND 11 +3VALW BS IN PR5010 0_0603_5% SNB_VCCIO 0_0402_5% IN PG PC807 IN 2.2U_0402_16V6K 1 @ PR5007 +VCCIO @ PU509 18 SUSP# PJP505 2 JUMP_43X118 +VCCIOP EMI@PC5026 1000P_0402_50V7K D EMI@PC5025 1U_0402_25V6K 2 JUMP_43X39 10U_0805_25V6K PC592 1 +3VS B+_VCCIO EMI@ PC594 0.1U_0402_25V6 1 EMI@ PC589 2200P_0402_50V7K B+ PR5016 PJP504 @ +VCCIOP (0.95V) TDC 3.85 A Peak Current 5.5 A OCP Current A Fix by IC TYP MAX Choke DCR 24.0mohm , 27.0mohm B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/01/06 Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_+VCCIO Size Document Number Rev 0.3 LA-D751P Date: Tuesday, August 16, 2016 Sheet 79 of 82 Power block CPU OTP Page 61 Turn Off D Input Switch DC IN D Always B+ +3VALWP: TDC:10.01A +5VALWP: TDC:10.77A TPS51225CRUKR Page 62 CHARGER CC:5.5A CV:17.7V BQ24780S +5VALW Page 63 +1.2VP/+0.6VSP:TDC:8.88A/1.47A RT8207MZQW SYSON Page 64 Page 62 C Battery C PCH_PWR_EN +1.0VALWP: TDC:9.41A TPS51212DSCR Page 66 GPU_PGOOD +1.05VSP: TDC:2A SY8032ABC Page 67 PM_SLP_S4# 3V3_MAIN_EN B 2.5V_MEMP: TDC:0.27A SY8003DFC +VGA_CORE TDC:85A RT8813AGQW B Page 68 FBVDD_EN +1.35VRAM: TDC:18A TPS51212DSCR Page 69 SUSP# +VCCIO: TDC:3.74A RT6220AHGQUF +VCC_CORE TDC: 39A +VCCGT TDC:56A +VCCSA TDC:10A ISL95855HRTZ IMVP_VR_ON Page 65 Page 74 Page 71,72,73 A A 2016/01/06 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2017/01/06 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_POWER BLOCK DIAGRAM Size R ev 0.3 LA-D751P Date: Document Number Tuesday, August 16, 2016 Sheet 80 of 82 V ersion Change L ist ( P I R L ist ) I t e m P a g e# D T it le D ate R eq u est O w n er Page I ssu e D escrip t io n S o lu tio n D escrip t io n R ev 69 VGA_UP9511P 2016/03/28 Compal_PWR For EE request to fine tune power sequence 64 +1.2VP/+0.6VSP 2016/03/28 Compal_PWR Add component for XMP 69 VGA_UP9511P 2016/03/30 Compal_PWR For EE request to fine tune power sequence Change PR6069&PR6036 pin from +3V3_SYS to +3VALW 0.2 69 VGA_UP9511P 2016/04/01 Compal_PWR For EE request to fine tune power sequence Change PR6033 connect to NVVDD_EN 0.2 72 2016/04/01 Compal_PWR For EE request to fine tune power sequence Change PR6402 connect to NVVDD_EN 0.2 73 2016/04/11 Compal_PWR For NV request Change +3VS to +1.8V_AON +NVVDD2 +1.35VS_VGAP Change PR6020 from 100 Ohm to 500 Ohm Change PR6007 from 5.1k Ohm to 13.3k Ohm D 0.2 Change PR213 from 20k Ohm to 60.4k Ohm 0.2 0.2 C C 64 +1.2VP/+0.6VSP 2016/04/11 Compal_PWR Add component for XMP Add PR212 to 1k Ohm Add PC217 to 0.1uF Add PQ202 MOS 0.2 73 +1.35VS_VGAP 2016/04/11 Compal_PWR For BOM control 0.2 68 +1VS_VGAP 2016/04/11 Compal_PWR For +1VS_VGAP OCP setting Add Add Add Add PR8211 PR8211 PR8215 PR8215 of of of of 34.8k Ohm for SAMSUNG@ 30k Ohm for MIRCON@ 52.3k Ohm for SAMSUNG@ 68.1k Ohm for MIRCON@ Change PL800 from 1UH_MAMK2520T1R0M_3.1A to 1UH_PCMB042T-1R0MS_4.5A 0.2 B B A A 2016/01/06 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2017/01/06 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_PIR1 Size R ev 0.3 LA-D751P Date: Document Number Tuesday, August 16, 2016 Sheet 81 of 82 V ersion Change L ist ( P I R L ist ) I t e m P a g e# T it le D ate R eq u est O w n er Page I ssu e D escrip t io n S o lu tio n D escrip t io n R ev D D 10 75 11 62 12 68 VCORE_ISL95829 CHARGER +1.0VS_VGAP 2016/05/18 Compal_PWR For CPU_VCORE setting Change PC507 from 680pF to 1000pF Change PC517 from 0.047uF to 0.068uF Change PR548 from 95.3kohm to 105kohm 2016/05/18 Compal_PWR For CHARGER ILIM setting Change PR710 from 2kohm to 5.11kohm Change PR711 from 2.43kohm to 3.16kohm 0.3 2016/05/18 Compal_PWR Add component for +1.0VS_VGAP_EN Add PR801 for 0ohm 0.3 0.3 C C 13 69 14 73 15 62 VGA_UP9511P Change PQ8203 from TR DMN66D0LDW-7 2N SOT363-6 to TR DMN53D0LDW-7 2N SOT363-6 2016/05/18 Compal_PWR For VGA_UP9511P_EN +1.55VRAM 2016/06/20 Compal_PWR Add component for +1.55VRAM CHARGER 2016/06/20 Compal_PWR For charger setting 0.3 Add PR8219 or 0ohm 0.4 Add PQ701,PQ702,PQ707,PQ708,PQ703 of AON7506_DFN33-8-5 for X76@ 0.4 B B A A 2016/01/06 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2017/01/06 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_PIR2 Size R ev 0.3 LA-D751P Date: Document Number Tuesday, August 16, 2016 Sheet 82 of 82 ... 99 10 1 10 3 10 5 10 7 10 9 11 1 11 3 11 5 11 7 11 9 12 1 12 3 12 5 12 7 12 9 13 1 13 3 13 5 13 7 13 9 14 1 14 3 14 5 14 7 14 9 15 1 15 3 15 5 15 7 15 9 16 1 16 3 16 5 16 7 16 9 17 1 17 3 17 5 17 7 17 9 18 1 18 3 18 5 18 7 18 9 19 1 19 3 19 5... 91 93 95 97 99 10 1 10 3 10 5 10 7 10 9 11 1 11 3 11 5 11 7 11 9 12 1 12 3 12 5 12 7 12 9 13 1 13 3 13 5 13 7 13 9 14 1 14 3 14 5 14 7 14 9 15 1 15 3 15 5 15 7 15 9 16 1 16 3 16 5 16 7 16 9 17 1 17 3 17 5 17 7 17 9 18 1 18 3 18 5 18 7 18 9... 80 82 84 86 88 90 92 94 96 98 10 0 10 2 10 4 10 6 10 8 11 0 11 2 11 4 11 6 11 8 12 0 12 2 12 4 12 6 12 8 13 0 13 2 13 4 13 6 13 8 14 0 14 2 14 4 14 6 14 8 15 0 15 2 15 4 15 6 15 8 16 0 16 2 16 4 16 6 16 8 17 0 17 2 17 4 17 6 17 8 18 0