A B C D E 1 Compal Confidential 2 DH53F MB Schematic Document LA-F991P 3 Rev : 1.C 2018.02.13 4 Compal Secret Data Security Classification 2017/07/20 Issued Date Deciphered Date 2018/07/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Cover Sheet Size Document Number Custom DH53F M/B Date: A B C D Compal Electronics, Inc Rev 1.A LA-F991P Tuesday, February 13, 2018 Sheet E of 73 A B C HDMI Conn D E eDP Fan Control*2 page 50 Interleaved Memory page 38 eDP HDMI x lanes Nvidia N17E-G1 with gDDR5 x6 PEG x16 8GT/s NGFF page 41 page 39 WLAN PCIE 2.0 5GT/s PCIE 3.0 x4 8GT/s Port 9-12 USB port port 15 CoffeeLake H PROCESSOR BGA1440 (42X28) (CFL-H_6+2) Processor page 25~36 260 pin DDR4-SO-DIMM X1 Memory BUS page 37 page 23 BANK 0, 1, 2, Dual Channel 260pin DDR4-SO-DIMM X1 1.2V DDR4 2400/2666 page 24 BANK 4, 5, 6, page 07~14 X4 DMI USB 3.0 conn x1 USB 3.0 x2 Type-C CMOS Camera USB (port 1) USB (port 2) USB (port 5) Flexible IO page 40 page 38 PCIE 2.0 5GT/s SATA3.0 Cannonlake PCH - H FCBGA(25X24) USBx8 Finger_Print USB (port 8) 6.0 Gb/s port 14 page 50 port 48MHz LAN(GbE) SATA Re-Driver Realtek 8411H PARADE PS8527 874pin FCBGA HD Audio page 46 page 44,45 page 37 3.3V 24MHz page 15~22 Card Reader RJ45 conn SATA HDD Conn HDA Codec ALC255 LPC/eSPI BUS page 42 3 CLK=24MHz ENE KB9022/9032 page 32 page 47 TPM page 43 page 49 Int Speaker SPI RTC CKT Sub Board page 42 page 21 LS-E921P HS/B page Touch Pad page 48 UAJ on Sub/B page 48 Int.KBD PS2 / I2C SPI ROM x1 48 Power On/Off CKT page 50 Int DMIC on Sub/B page 17 LS-F992P USB2/B page page 49 page 49 48 DC/DC Interface CKT page 51 4 Power Circuit DC/DC page 52~69 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2017/07/20 Deciphered Date 2018/07/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D R ev 1.A DH53F M/B LA-F991P Date: A Block Diagrams Size Document Number Custom Tuesday, February 13, 2018 Sheet E of 73 A B C Board ID Table for AD channel Vcc Ra Board ID 1 10 11 12 13 14 15 16 17 18 19 3.3V +/- 5% 100K +/- 5% Rb 12K +/- 1% 15K +/- 1% 20K +/- 1% 27K +/- 1% 33K +/- 1% 43K +/- 1% 56K +/- 1% 75K +/- 1% 100K +/- 1% 130K +/- 1% 160K +/- 1% 200K +/- 1% 240K +/- 1% 270K +/- 1% 330K +/- 1% 430K +/- 1% 560K +/- 1% 750K +/- 1% NC V BID 0.347 0.423 0.541 0.691 0.807 0.978 1.169 1.398 1.634 1.849 2.015 2.185 2.316 2.395 2.521 2.667 2.791 2.905 3.000 V V V V V V V V V V V V V V V V V V V V BID typ 0.000 V 0.345 V 0.430 V 0.550 V 0.702 V 0.819 V 0.992 V 1.185 V 1.414 V 1.650 V 1.865 V 2.031 V 2.200 V 2.329 V 2.408 V 2.533 V 2.677 V 2.800 V 2.912 V 3.000 V V BID max 0.300 V 0.360 V 0.438 V 0.559 V 0.713 V 0.831 V 1.006 V 1.200 V 1.430 V 1.667 V 1.881 V 2.046 V 2.215 V 2.343 V 2.421 V 2.544 V 2.687 V 2.808 V 2.919 V EC 0x00 0x14 0x1F 0x26 0x31 0x3B 0x46 0x55 0x65 0x77 0x88 0x97 0xA5 0xB0 0xB8 0xC0 0xCA 0xD5 0xDE 0xF1 AD - 0x13 - 0x1E - 0x25 - 0x30 - 0x3A - 0x45 - 0x54 - 0x64 - 0x76 - 0x87 - 0x96 - 0xA4 - 0xAF - 0xB7 - 0xBF - 0xC9 - 0xD4 - 0xDD - 0xF0 - 0xFF Device Touch Panel TM-P2969-001 (Touch Pad) SB8787-1200 (Touch Pad) DIMM1 DIMM2 LIS3DHTR(G-sensor) N17E-G1 (VGA) EC CC controller 179F TMS PCH_SMBCLK (+3VS) PCH_SML1CLK (+3VS) BQ24780 (Charger IC) BATTERY PACK EC_SMB_CK1 (+3VLP) Address(7 bit) SLP_S3# SLP_S4# SLP_S5# reserved 0x30 0x9E 0x12 0x16 +V +VS Clock ON ON ON HIGH HIGH HIGH ON S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF Item BOM Structure Unpop @ Connector CONN@ UMA only UMA@ CMC CMC@ dGPU VGA@ DIS@ DIS only TPM TPM@ For Acer IOAC IOAC@ No Acer IOAC NIOAC@ 28P@ 28P keyboard connector 32P@ 32P keyboard connector FP@ Finger Print Finger Print for ESD FPESD@ PBA PBA@ TMS@ Thermal sensor LAN LDO mode LDO@ LAN Switch mode SWR@ G-Sensor GSEN@ EMI requirement EMI@ @EMI@ EMI require reserve ESD requirement ESD@ EMI require reserve @ESD@ CNVi CNVI@ UART debug UART@ Codec ALC255 255@ Codec ALC256 256@ Codec ALC256 for ESD 256ESD@ Codec ALC256 for EMI 256EMI@ GPK@ G-PAK for GPU sequence NGPK@ DIS for GPU sequence W/ SATA re-driver SATARD@ W/O SATA re-driver NORD@ PCH@ PCH i5@/i7@ CPU Read +VALW S0 (Full ON) BOM Structure Table BOM Option Table Address(8bit) Write BOARD ID Table SIGNAL STATE I2C Address Table I2C_0 (+3VS) I2C_1 (+3VS) E Power State BUS D Board ID 10 11 12 13 PCB Revision 0.1 / 28P 0.2 / 28P 1.0 / 28P 1.C / 28P 0.1 / 32P 0.2 / 32P 1.0 / 32P 1.C / 32P Voltage Rails Power Plane Description +RTCVCC RTC Battery Power ON S3 ON ON S5 ON +19V_VIN Adapter power supply N/A N/A N/A N/A +12.6V_BATT Battery power supply N/A N/A N/A N/A +19VB AC or battery power rail for power circuit N/A N/A N/A N/A +3VLP +19VB to +3VLP power rail for suspend power ON ON ON ON +5VALW +5V Always power rail ON ON ON +3VALW System +3VALW always on power rail ON ON ON ON ON* +3VALW_DSW +3VALW power for PCH DSW rails ON ON ON ON +3VALW_PCH_PRIM +3VALW power for PCH power rails ON ON ON ON* +3VALW_SPI +3VALW_PRIM supply for the SPI IO ON ON ON ON S0 S4 +1.05VALW +1.05V Always power rail ON ON ON ON +1.2V_VDDQ DDR4 +1.2V power rail ON ON OFF OFF +1.05V_VCCST Sustain voltage for processor in Standby modes ON ON OFF OFF +5VS System +5V power rail ON OFF OFF OFF +3VS System +3V power rail ON OFF OFF OFF +1.05VS_VCCSTG +1.05VALW_PRIM Gated version of VCCST ON OFF OFF OFF +0.6VS_VTT DDR +0.6VS power rail for DDR terminator ON OFF OFF OFF +VCC_CORE Core voltage for CPU ON OFF OFF OFF +VCC_GT Sliced graphics power rail ON OFF OFF OFF +VCCIO CPU IO +0.95VS power rail ON OFF OFF OFF +VCC_SA System Agent power rail ON OFF OFF OFF +1.8VSDGPU_AON +1.8VS power rail for GPU(AON rails) ON OFF OFF OFF +1.8VSDGPU_MAIN +1.8VS power rail for GPU GC6 ON OFF OFF OFF +VGA_CORE Core voltage for VGA (merge core & core_s) ON OFF OFF OFF +1.35VSDGPU +1.35VS power rail for GPU ON OFF OFF OFF +1.0VSDGPU +1.0VS power rail for GPU ON OFF OFF OFF +1.8VALW System +1.8VALW always on power rail ON ON ON ON* Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF BOM table 43 Level 431AB2BOL05~08 431AB2BOL53_54 431AB1BOL67 X4EAB2BO001 X4EAB2BO051 X76730BOL56 X76730BOL57 X76730BOL58 Description BOM Structure ALT GROUP PARTS N17E6G SAM 256M32 DH7VF ALT GROUP PARTS N17E6G HYN 256M32 DH7VF ALT GROUP PARTS N17E6G MIC 256M32 DH7VF Compal Secret Data Security Classification Issued Date 2017/07/20 Deciphered Date 2018/07/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom B C D R ev 1.A DH53F M/B LA-F991P Date: A Compal Electronics, Inc Notes List Tuesday, February 13, 2018 Sheet E of 73 EN:DGPU_PWR_EN +1.8VSDGPU_AON UG27 DC_IN PL101 PJP101 +19V_VIN AC CONN GPU +1.8VSDGPU_MAIN EN:1.8VSDGPU_MAIN_EN EN : 1VSDGPU_EN +12.6V_BATT+ +12.6V_BATT +1.0VSDGPUP BATTERY PL201,PL202 +1.0VSDGPU +19VB PU301 CHARGER +19VB RS1 +VCC_CORE DIMM1 PL8101,PL8306,PL8305,PL8106 DIMM2 PCH +1.8V_PHVLDO +1.8VALWP EN:VR_ON UQ1 PQ8105 PU8106 R19 RH100 +VCC_GT PL8107 U5 +3VS_WLAN UM1 JNGFF1 +3V_LAN UL2 +3VALW_DSW +VCC_SA PL8301 +19VB EN:DRON +3VALW_PCH_PRIM RH97 EN:3V_EN RH101 +3VALW_HDA UK1 +3V_PTP EC,LID C WLAN CARD (IOAC) UF1 LAN +3VALW_SPI UH3 SPI +1.2V PCH JTP1 TP CPU UK2 JEP1 +FP_VCC +3VS_TPM WLAN JSSD1 SSD U5 TPM +TS_PWR JEDP1 TS UX1 +LCDVDD JEDP1 PANEL C 1.8VSDGPU_MAIN_EN +3VSDGPU GPU +3VS_DVDDIO FP JNGFF1 RX6 UG20 +1.2V_VDDQ PJ501 +3VS_SSD_NGFF R20 RK14 JPC1,C2 THERMAL SENSOR +3VS_WLAN RM11 +3VLP +1.2V_VDDQ_CPU G-SENSOR RM1 RH98 +3VALW PJ401 PU401 TPM RZ1 PCH RH99 CPU SATA Re-driver UO1 +3VALW_TPM CPU PCH +3VS JPQ1 UL1 EN:SYSON D RH100 DDR4 PU7105 PQ8301 CODEC +1.8VALW_PRIM +1.8VALW PJ7107 +2.5V PJ7103 PU7102 CPU EN:DRON +19VB RA3 +3.3V_CC IMVP8 PU8102 PU8103 PU8104 PU8105 GPU +1.8VDDA UQ2 GPU PJ1802 PU1801 PJP201 D +1.8VS RA2 +3VS_DVDDIO CODEC +3VS_DVDD CODEC JDIMM1,2 +19VB +0.6V_DDRB_VREFCA PU501 RA4 RD19,21,20 EN:SM_PG_CTRL +0.6VSP +0.6V_B_VREFDQ CPU +3VS_DIMMA +0.6VS_VTT PJ502 PU601 +3VS_DVDD DIMM RH92 +1.05VALW_PCH_PRIM RH93 +1.05VALW _VCCMPHY PCH +1.05VALW_PCH PCH PCH +1.05VALW +1.05VALWP PJ601 +19VB RH94 EN:+3VALW +1.05VALW_VCCAZPLL RH102 RH103 RH105 +19VB PU7201 +1.0VS_VCCIOP +VCCIO PJ7201 CPU PCH PCH PCH +1.05VALW_VCCAMPHYPLL +1.05VALW _XTAL UQ2 RQ5 +1.05V_VCCST UC4 RQ6 +1.05VS_VCCSTG CPU EN:SUSP# RK15 B B +5V_CC US2 +USB3_VCCC US11 PU402 +USB_VCCA JUSB1 US12 JTYPEC1 Type C Conn USB3.0 Conn +5VALWP PJ402 +19VB +5VALW JPQ2 UQ1 +5VS JIO2,3 RF4 +VCC_FAN1 FAN1 RF6 +VCC_FAN2 FAN2 USB/B FPC BTB CONN +VDDA UA1 CODEC U4 +5VS_BL JBL1 KB BackLight UO2 +5VS_HDD JHDD1 HDD JHDMI1 HDMI JPA1 +19VB PL1303 PR1301 +19VB_GPU PR1302 EN:NVVDD1_EN +19VB_NVVDD PL1304 PR1402 EN:NVVDD2_EN +19VB_NVVDDS GPU +NVVDD1 PU1302 PQ1401 A PJ1701 PL1351 PL1401 +NVVDD2 UY2 GPU RX7 +HDMI_5V_OUT +TS_PWR JEDP1 TP A GPU EN:1.35VSDGPU_EN +1.35VSDGPU +19VB_1.35VSDGPUP PQ1701 +19VB LX1 +INVPWR_B+ JEDP1 PANEL Compal Secret Data Security Classification Issued Date 2017/07/20 Deciphered Date 2018/07/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Power Map Number Re v 1.A DH53F M/B LA-F991P Date: Compal Electronics, Inc Size Document Custom Tuesday, February 13, 2018 Sheet of 73 DH53F_EVT Power Sequence Power On BIOS : 0.05 AC mode S3 S3 Resume Power Off Plug in +3VLP D +3VLP D EC_ON EC_ON +5VALW +5VALW → ON/OFFBTN# ON/OFFBTN# +3VALW → 90.77ms → 8.969s +3VALW +1.8VALW → 92.67ms → 8.97s +1.8VALW +1.05ALW → 93.73ms → 8.97S +1.05ALW → 8.497S EC_RSMRST# → 8.497S PBTN_OUT# → EC_RSMRST# 21.45ms → PBTN_OUT# ← 20ms → ← 130.8ms → 17.32ms → 17.36ms → 439.9us PM_SLP_S4# → 291.9us PM_SLP_S3# PM_SLP_S4# C → 291us PM_SLP_S3# → → 20.16ms SYSON 4.993us SYSON → 302.5us → 76.22us +1.05V_VCCST → 752.8us → 496.3us +1.2V_VDDQ → 985us → +1.05V_VCCST +1.2V_VDDQ +2.5V 1.587ms +2.5V → 9.797ms SUSP# → 8.607us → → 682.5us → → 926us → → 670.8us → → 438us → +1.05VS_VCCSTG +VCCIO → 13.77us 44.84us 637.6us 516.2us +5VS 5.065ms +3VS +1.8VS 4.447ms 8.64us → → 679.3us → → 929.5us → → 677.4us → → 419.9us → 20.55ms → 9.382us → → 20.5ms → 9.78us → SM_PG_CTRL → → 4us +0.6VS_VTT → VR_ON → +VCCS_A → 10.15ms PCH_PWROK → 120.9ms SYS_PWROK → 20.38ms → 74.13us → → 87.21us → PLT_RST# → → 136.8ms 83.73us +VCC_CORE 6.655s → → 560.8ms +VCC_GT +3VS +1.8VS 2.786ms EC_VCCST_PG 9.764us SM_PG_CTRL VR_ON 46.27us +VCC_SA → 74.07us PCH_PWROK → 87.14us SYS_PWROK PLT_RST# 1.614ms → 139.6ms → 1.419s B +0.6VS_VTT 724us 28.57us → → 1.339ms +5VS 4.683ms → 1.776ms 121.3ms +VCCIO 659.4us → 9.604ms +1.05VS_VCCSTG 646.6us 9.275us → 20.41ms → 43.75us SUSP 53.92us → → 4us → 28.72us → 1.773ms 19.97ms 2.089ms → 20.53ms 13.75us → → EC_VCCST_PG → 32.21ms → → → B C +VCC_CORE 84.98us +VCC_GT 1.837s A A Compal Secret Data Security Classification Issued Date 2017/07/20 Deciphered Date 2018/07/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom R ev 1.A DH53F M/B LA-F991P Date: Compal Electronics, Inc Power Map Tuesday, February 13, 2018 Sheet of 73 2.2K 2.2K +3VALW_PCH_PRIM 2.2K +3VS PCH_SMBCLK 2.2K +3VS D_CK_SCLK 2N7002DW PCH_SMBDATA PCH_SML0CLK 499 PCH_SML0DATA 499 2.2K D_CK_SDATA SO-DIMM A & B G-Sensor D CannonLake-H PCH 2.2K +3VALW_PCH_PRIM D +3VALW_PCH_PRIM PCH_SML1CLK +3VSDGPU 1.8K +1.8VSDGPU_MAIN I2CC_SCL_R N17E-G1 VGA_SMB_DA2 I2CC_SCL PJT138KA I2CC_SDA_R I2CC_SCL Current Sensor 4.7K 2.2K KB9022 1.8K VGA_SMB_CK2 PJT138KA PCH_SML1DATA 1.8K +1.8VSDGPU_AON +1.8VSDGPU_MAIN 2.2K 2.2K 1.8K +1.8VSDGPU_AON 2.2K +3VLP_EC 100 ohm EC_SMB_CK1-1 EC_SMB_DA1 100 ohm EC_SMB_DA1-1 ohm ohm EC_SMB_CK1_CHGR BATTERY EC_SMB_DA1_CHGR CONN 2N7002DW USB CC EJ179F 2.2K Charger +3VS 2.2K 2N7002DW C +3.3V_CC 4.7K +3.3V_CC EC_SMB_CK1 +3VS THERMAL SENSOR C B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2017/07/20 Deciphered Date 2018/07/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title N17E-GDDR5_D Size Document Number Rev 1.A DH53F M/B LA-F991P Date: Tuesday, February 13, 2018 Sheet of 73 A B C D E CO-LAY FOR VGA OUTPUT GPU_EDP_TXP0 GPU_EDP_TXN0 GPU_EDP_TXP1 GPU_EDP_TXN1 GPU_EDP_TXP2 GPU_EDP_TXN2 GPU_EDP_TXP3 GPU_EDP_TXN3 GPU_EDP_AUXP GPU_EDP_AUXN RG203 RG204 RG205 RG206 RG207 RG208 RG209 RG210 1 1 1 1 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% GPU_EDP_TXP0_R GPU_EDP_TXN0_R GPU_EDP_TXP1_R GPU_EDP_TXN1_R GPU_EDP_TXP2_R GPU_EDP_TXN2_R GPU_EDP_TXP3_R GPU_EDP_TXN3_R RG211 RG212 1 DIS@ 0_0201_5% DIS@ 0_0201_5% GPU_EDP_AUXP_R GPU_EDP_AUXN_R 2 2 2 2 TC21 TC22 TC23 TC24 TC25 TC26 TC27 TC28 @ @ @ @ @ @ @ @ TC29 @ TC30 @ CFL-H UC1D K36 K37 J35 J34 H37 H36 J37 J38 D27 E27 H34 H33 F37 G38 F34 F35 E37 E36 ZZZ PCB@ F26 E26 DAZ29000103 PCB DH53F LA-F991P LS-F992P/E921P C34 D34 B36 B34 F33 E33 C33 B33 A27 B27 DDI1_TXP_0 DDI1_TXN_0 DDI1_TXP_1 DDI1_TXN_1 DDI1_TXP_2 DDI1_TXN_2 DDI1_TXP_3 DDI1_TXN_3 EDP_TXP_0 EDP_TXN_0 EDP_TXP_1 EDP_TXN_1 EDP_TXP_2 EDP_TXN_2 EDP_TXP_3 EDP_TXN_3 DDI1_AUXP DDI1_AUXN EDP_AUXP EDP_AUXN DDI2_TXP_0 DDI2_TXN_0 DDI2_TXP_1 DDI2_TXN_1 DDI2_TXP_2 DDI2_TXN_2 DDI2_TXP_3 DDI2_TXN_3 EDP_DISP_UTIL DISP_RCOMP D29 E29 F28 E28 A29 B29 C28 B28 EDP_TXP0 EDP_TXN0 EDP_TXP1 EDP_TXN1 EDP_TXP2 EDP_TXN2 EDP_TXP3 EDP_TXN3 C26 B26 EDP_AUXP EDP_AUXN EDP_TXP0 EDP_TXN0 EDP_TXP1 EDP_TXN1 EDP_TXP2 EDP_TXN2 EDP_TXP3 EDP_TXN3 EDP_AUXP EDP_AUXN eDP +VCCIO A33 DP_RCOMP D37 RC1 24.9_0402_1% Trace Width/Space: 15 mil/ 20 mil Max Trace Length: 600 mil DDI2_AUXP DDI2_AUXN DDI3_TXP_0 DDI3_TXN_0 DDI3_TXP_1 DDI3_TXN_1 DDI3_TXP_2 DDI3_TXN_2 DDI3_TXP_3 DDI3_TXN_3 DDI3_AUXP DDI3_AUXN PROC_AUDIO_CLK PROC_AUDIO_SDI ofPROC_AUDIO_SDO 13 G27 G25 G29 CPU_DISPA_SDI RC2 20_0402_5% CPU_DISPA_BCLK_R CPU_DISPA_SDO_R CPU_DISPA_SDI_R CPU_DISPA_BCLK_R CPU_DISPA_SDO_R CPU_DISPA_SDI_R CFL-H_BGA1440 @ Coffee Lake-H CPU SKU UC1 UC1 CFL-H_BGA1440 S IC CL8068403373522 SR3Z0 U0 2.3G ABO! SA0000BPJ40 i5@ CFL-H_BGA1440 S IC CL8068403359524 SR3YY U0 2.2G ABO! SA0000BPZ40 i7@ 4 Compal Secret Data Security Classification 2017/07/20 Issued Date Deciphered Date 2018/07/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom B C D Rev 1.A DH53F M/B LA-F991P Date: A Compal Electronics, Inc CFL-H(1/8)DDI/eDP Tuesday, February 13, 2018 Sheet E of 73 A B C D E CHANNEL-A Interleaved Memory CFL-H UC1A DDR CHANNEL A DDR_A_D[0 63] DDR4(IL)/LP3-DDR4(NIL) DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 BR6 BT6 BP3 BR3 BN5 BP6 BP2 BN3 BL4 BL5 BL2 BM1 BK4 BK5 BK1 BK2 BG4 BG5 BF4 BF5 BG2 BG1 BF1 BF2 BD2 BD1 BC4 BC5 BD5 BD4 BC1 BC2 AB1 AB2 AA4 AA5 AB5 AB4 AA2 AA1 V5 V2 U1 U2 V1 V4 U5 U4 R2 P5 R4 P4 R5 P2 R1 P1 M4 M1 L4 L2 M5 M2 L5 L1 BA2 BA1 AY4 AY5 BA5 BA4 AY1 AY2 For ECC DIMM LP3/DDR4 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3 DDR0_DQ_8/DDR0_DQ_8 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3 DDR0_DQ_13/DDR0_DQ_13 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3 DDR0_DQ_18/DDR0_DQ_34 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3 DDR0_DQ_23/DDR0_DQ_39 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR0_DQ_27/DDR0_DQ_43 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR0_DQ_31/DDR0_DQ_47 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 DDR0_DQ_34/DDR1_DQ_2 DDR0_CAB_5/DDR0_MA_2 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_3/DDR0_MA_8 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 DDR0_DQ_42/DDR1_DQ_10 DDR0_CAB_7/DDR0_MA_10 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 DDR0_DQ_44/DDR1_DQ_12 DDR0_CAA_6/DDR0_MA_12 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT# DDR0_DQ_48/DDR1_DQ_32 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT# DDR0_DQ_51/DDR1_DQ_35 DDR4(IL)/LP3-DDR4(NIL) DDR0_DQ_52/DDR1_DQ_36 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 DDR0_DQ_57/DDR1_DQ_41DDR0_DQSN_4/DDR1_DQSN_0 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 DDR0_DQ_59/DDR1_DQ_43DDR0_DQSN_6/DDR1_DQSN_4 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5 DDR0_DQ_61/DDR1_DQ_45 DDR0_DQ_62/DDR1_DQ_46DDR0_DQSP_0/DDR0_DQSP_0 DDR0_DQ_63/DDR1_DQ_47DDR0_DQSP_1/DDR0_DQSP_1 DDR0_DQSP_2/DDR0_DQSP_4 LP3/DDR4 DDR0_DQSP_3/DDR0_DQSP_5 NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 NC/DDR0_ECC_1 DDR0_DQSP_5/DDR1_DQSP_1 NC/DDR0_ECC_2 DDR0_DQSP_6/DDR1_DQSP_4 NC/DDR0_ECC_3 DDR0_DQSP_7/DDR1_DQSP_5 NC/DDR0_ECC_4 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 NC/DDR0_ECC_6 DDR0_DQSN_8/DDR0_DQSN_8 OF 13 NC/DDR0_ECC_7 AG1 AG2 AK2 AK1 AL3 AK3 AL2 AL1 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 AT1 AT2 AT3 AT5 DDR_A_CKE0 DDR_A_CKE1 AD5 AE2 AD2 AE5 DDR_A_CS#0 DDR_A_CS#1 AD3 AE4 AE1 AD4 DDR_A_ODT0 DDR_A_ODT1 AH5 AH1 AU1 DDR_A_BA0 DDR_A_BA1 DDR_A_BG0 AH4 AG4 AD1 DDR_A_MA16_RAS# DDR_A_MA14_W E# DDR_A_MA15_CAS# AH3 AP4 AN4 AP5 AP2 AP1 AP3 AN1 AN3 AT4 AH2 AN2 AU4 AE3 AU2 AU3 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_BG1 DDR_A_ACT# AG3 AU5 DDR_A_PAR DDR_A_ALERT# BR5 BL3 BG3 BD3 AA3 U3 P3 L3 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 BP5 BK3 BF3 BC3 AB3 V3 R3 M3 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 AY3 BA3 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_A_CKE0 DDR_A_CKE1 DDR_A_CS#0 DDR_A_CS#1 DDR_A_ODT0 DDR_A_ODT1 DDR_A_BA0 DDR_A_BA1 DDR_A_BG0 DDR_A_MA16_RAS# DDR_A_MA14_W E# DDR_A_MA15_CAS# DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_BG1 DDR_A_ACT# DDR_A_PAR DDR_A_ALERT# DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 For ECC DIMM CFL-H_BGA1440 @ 4 Compal Secret Data Security Classification 2017/07/20 Issued Date Deciphered Date 2018/07/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title CFL-H(2/8)DIMMA Size Document Number Custom B C D Rev 1.A DH53F M/B LA-F991P Date: A Compal Electronics, Inc Tuesday, February 13, 2018 Sheet E of 73 A B C D E CHANNEL-B Interleaved Memory CFL-H UC1B DDR_B_D[0 63] DDR CHANNEL B DDR4(IL)/LP3-DDR4(NIL) DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 BT11 BR11 BT9 BR8 BP11 BN11 BP8 BN8 BL12 BL11 BL8 BJ8 BJ11 BJ10 BL7 BJ7 BG11 BG10 BG8 BF8 BF11 BF10 BG7 BF7 BB11 BC11 BB8 BC8 BC10 BB10 BC7 BB7 AA11 AA10 AC11 AC10 AA7 AA8 AC8 AC7 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 W8 W7 V10 V11 W11 W10 V7 V8 R11 P11 P7 R8 R10 P10 R7 P8 L11 M11 L7 M8 L10 M10 M7 L8 AW11 AY11 AY8 AW8 AY10 AW10 AY7 AW7 For ECC DIMM RC3 RC4 RC5 121_0402_1% SM_RCOMP0 75_0402_1% SM_RCOMP1 100_0402_1% SM_RCOMP2 1 Trace Width/Space: 15 mil/ 25 mil Max Trace Length: 500 mil G1 H1 J2 LP3/DDR4 DDR1_DQ_0/DDR0_DQ_16 DDR1_DQ_1/DDR0_DQ_17 DDR1_DQ_2/DDR0_DQ_18 DDR1_DQ_3/DDR0_DQ_19 DDR1_DQ_4/DDR0_DQ_20 DDR1_DQ_5/DDR0_DQ_21 DDR1_DQ_6/DDR0_DQ_22 DDR1_DQ_7/DDR0_DQ_23 DDR1_DQ_8/DDR0_DQ_24 DDR1_DQ_9/DDR0_DQ_25 DDR1_DQ_10/DDR0_DQ_26 DDR1_DQ_11/DDR0_DQ_27 DDR1_DQ_12/DDR0_DQ_28 DDR1_DQ_13/DDR0_DQ_29 DDR1_DQ_14/DDR0_DQ_30 DDR1_DQ_15/DDR0_DQ_31 DDR1_DQ_16/DDR0_DQ_48 DDR1_DQ_17/DDR0_DQ_49 DDR1_DQ_18/DDR0_DQ_50 DDR1_DQ_19/DDR0_DQ_51 DDR1_DQ_20/DDR0_DQ_52 DDR1_DQ_21/DDR0_DQ_53 DDR1_DQ_22/DDR0_DQ_54 DDR1_DQ_23/DDR0_DQ_55 DDR1_DQ_24/DDR0_DQ_56 DDR1_DQ_25/DDR0_DQ_57 DDR1_DQ_26/DDR0_DQ_58 DDR1_DQ_27/DDR0_DQ_59 DDR1_DQ_28/DDR0_DQ_60 DDR1_DQ_29/DDR0_DQ_61 DDR1_DQ_30/DDR0_DQ_62 DDR1_DQ_31/DDR0_DQ_63 DDR1_DQ_32/DDR1_DQ_16 DDR1_DQ_33/DDR1_DQ_17 DDR1_DQ_34/DDR1_DQ_18 DDR1_DQ_35/DDR1_DQ_19 DDR1_DQ_36/DDR1_DQ_20 DDR1_DQ_37/DDR1_DQ_21 DDR1_DQ_38/DDR1_DQ_22 DDR1_DQ_39/DDR1_DQ_23 DDR1_CKP_0/DDR1_CKP_0 DDR1_CKN_0/DDR1_CKN_0 DDR1_CKP_1/DDR1_CKP_1 DDR1_CKN_1/DDR1_CKN_1 NC/DDR1_CKP_2 NC/DDR1_CKN_2 NC/DDR1_CKP_3 NC/DDR1_CKN_3 DDR1_CKE_0/DDR1_CKE_0 DDR1_CKE_1/DDR1_CKE_1 DDR1_CKE_2/DDR1_CKE_2 DDR1_CKE_3/DDR1_CKE_3 DDR1_CS#_0/DDR1_CS#_0 DDR1_CS#_1/DDR1_CS#_1 NC/DDR1_CS#_2 NC/DDR1_CS#_3 DDR1_ODT_0/DDR1_ODT_0 NC/DDR1_ODT_1 NC/DDR1_ODT_2 NC/DDR1_ODT_3 DDR1_CAB_3/DDR1_MA_16 DDR1_CAB_2/DDR1_MA_14 DDR1_CAB_1/DDR1_MA_15 DDR1_CAB_4/DDR1_BA_0 DDR1_CAB_6/DDR1_BA_1 DDR1_CAA_5/DDR1_BG_0 DDR1_CAB_9/DDR1_MA_0 DDR1_CAB_8/DDR1_MA_1 DDR1_CAB_5/DDR1_MA_2 NC/DDR1_MA_3 NC/DDR1_MA_4 DDR1_CAA_0/DDR1_MA_5 DDR1_CAA_2/DDR1_MA_6 DDR1_CAA_4/DDR1_MA_7 DDR4(IL)/LP3-DDR4(NIL) DDR1_DQ_40/DDR1_DQ_24 DDR1_CAA_3/DDR1_MA_8 DDR1_DQ_41/DDR1_DQ_25 DDR1_CAA_1/DDR1_MA_9 DDR1_DQ_42/DDR1_DQ_26 DDR1_CAB_7/DDR1_MA_10 DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 DDR1_DQ_44/DDR1_DQ_28 DDR1_CAA_6/DDR1_MA_12 DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13 DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT# DDR1_DQ_48/DDR1_DQ_48 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT# DDR1_DQ_51/DDR1_DQ_51 DDR4(IL)/LP3-DDR4(NIL) DDR1_DQ_52/DDR1_DQ_52 DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 DDR1_DQ_55/DDR1_DQ_55DDR1_DQSN_2/DDR0_DQSN_6 DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 DDR1_DQ_57/DDR1_DQ_57DDR1_DQSN_4/DDR1_DQSN_2 DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 DDR1_DQ_59/DDR1_DQ_59DDR1_DQSN_6/DDR1_DQSN_6 DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7 DDR1_DQ_61/DDR1_DQ_61 DDR1_DQ_62/DDR1_DQ_62DDR1_DQSP_0/DDR0_DQSP_2 DDR1_DQ_63/DDR1_DQ_63DDR1_DQSP_1/DDR0_DQSP_3 DDR1_DQSP_2/DDR0_DQSP_6 LP3/DDR4 NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7 NC/DDR1_ECC_5 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8 DDR_RCOMP_0 DDR_RCOMP_1 DDR_RCOMP_2 OF 13 DDR_VREF_CA DDR0_VREF_DQ DDR1_VREF_DQ AM9 AN9 AM7 AM8 AM11 AM10 AJ10 AJ11 DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1 AT8 AT10 AT7 AT11 DDR_B_CKE0 DDR_B_CKE1 AF11 AE7 AF10 AE10 DDR_B_CS#0 DDR_B_CS#1 AF7 AE8 AE9 AE11 DDR_B_ODT0 DDR_B_ODT1 AH10 AH11 AF8 DDR_B_MA16_RAS# DDR_B_MA14_W E# DDR_B_MA15_CAS# AH8 AH9 AR9 DDR_B_BA0 DDR_B_BA1 DDR_B_BG0 AJ9 AK6 AK5 AL5 AL6 AM6 AN7 AN10 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 AN8 AR11 AH7 AN11 AR10 AF9 AR7 AT9 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_BG1 DDR_B_ACT# AJ7 AR8 DDR_B_PAR DDR_B_ALERT# BN9 BL9 BG9 BC9 AC9 W9 R9 M9 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 BP9 BJ9 BF9 BB9 AA9 V9 P9 L9 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 AW9 AY9 DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1 DDR_B_CKE0 DDR_B_CKE1 DDR_B_CS#0 DDR_B_CS#1 DDR_B_ODT0 DDR_B_ODT1 DDR_B_MA16_RAS# DDR_B_MA14_W E# DDR_B_MA15_CAS# DDR_B_BA0 DDR_B_BA1 DDR_B_BG0 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_BG1 DDR_B_ACT# DDR_B_PAR DDR_B_ALERT# DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 For ECC DIMM BN13 BP13 BR13 +0.6V_VREFCA +0.6V_B_VREFDQ +0.6V_VREFCA +0.6V_B_VREFDQ CFL-H_BGA1440 @ Compal Secret Data Security Classification 2017/07/20 Issued Date Deciphered Date 2018/07/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D CFL-H(3/8)DIMMB Size Document Number Custom Rev 1.A DH53F M/B LA-F991P Date: A Compal Electronics, Inc Tuesday, February 13, 2018 Sheet E of 73 A B C D E PEG&DMI To DGPU PEG Lane Reversed CC6 CC8 VGA@ VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P15 PEG_CRX_GTX_N15 E25 D25 PEG_CRX_C_GTX_P14 PEG_CRX_C_GTX_N14 CC10 VGA@ CC12 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P14 PEG_CRX_GTX_N14 E24 F24 PEG_CRX_C_GTX_P13 PEG_CRX_C_GTX_N13 CC14 VGA@ CC15 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P13 PEG_CRX_GTX_N13 E23 D23 PEG_CRX_C_GTX_P12 PEG_CRX_C_GTX_N12 CC3 VGA@ CC17 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P12 PEG_CRX_GTX_N12 E22 F22 E21 D21 PEG_CRX_C_GTX_P11 PEG_CRX_C_GTX_N11 CC19 VGA@ CC21 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P11 PEG_CRX_GTX_N11 PEG_CRX_C_GTX_P10 PEG_CRX_C_GTX_N10 CC5 VGA@ CC23 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P10 PEG_CRX_GTX_N10 E20 F20 PEG_CRX_C_GTX_P9 PEG_CRX_C_GTX_N9 CC25 VGA@ CC27 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P9 PEG_CRX_GTX_N9 E19 D19 PEG_CRX_C_GTX_P8 PEG_CRX_C_GTX_N8 CC29 VGA@ CC31 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P8 PEG_CRX_GTX_N8 E18 F18 PEG_CRX_C_GTX_P7 PEG_CRX_C_GTX_N7 CC33 VGA@ CC35 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P7 PEG_CRX_GTX_N7 D17 E17 PEG_CRX_C_GTX_P6 PEG_CRX_C_GTX_N6 CC37 VGA@ CC39 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P6 PEG_CRX_GTX_N6 F16 E16 PEG_CRX_C_GTX_P5 PEG_CRX_C_GTX_N5 CC41 VGA@ CC43 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P5 PEG_CRX_GTX_N5 D15 E15 PEG_CRX_C_GTX_P4 PEG_CRX_C_GTX_N4 CC45 VGA@ CC47 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P4 PEG_CRX_GTX_N4 F14 E14 PEG_CRX_C_GTX_P3 PEG_CRX_C_GTX_N3 CC49 VGA@ CC51 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P3 PEG_CRX_GTX_N3 D13 E13 F12 E12 UC1C PEG_CRX_C_GTX_P15 PEG_CRX_C_GTX_N15 To DGPU PEG Lane Reversed CFL-H PEG_CRX_C_GTX_P2 PEG_CRX_C_GTX_N2 CC53 VGA@ CC55 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P2 PEG_CRX_GTX_N2 PEG_CRX_C_GTX_P1 PEG_CRX_C_GTX_N1 CC57 VGA@ CC59 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P1 PEG_CRX_GTX_N1 D11 E11 PEG_CRX_C_GTX_P0 PEG_CRX_C_GTX_N0 CC61 VGA@ CC63 VGA@ 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K PEG_CRX_GTX_P0 PEG_CRX_GTX_N0 F10 E10 PEG_RXP_0 PEG_RXN_0 PEG_TXP_0 PEG_TXN_0 PEG_RXP_1 PEG_RXN_1 PEG_TXP_1 PEG_TXN_1 PEG_RXP_2 PEG_RXN_2 PEG_TXP_2 PEG_TXN_2 PEG_RXP_3 PEG_RXN_3 PEG_TXP_3 PEG_TXN_3 PEG_RXP_4 PEG_RXN_4 PEG_TXP_4 PEG_TXN_4 PEG_RXP_5 PEG_RXN_5 PEG_TXP_5 PEG_TXN_5 PEG_RXP_6 PEG_RXN_6 PEG_TXP_6 PEG_TXN_6 PEG_RXP_7 PEG_RXN_7 PEG_TXP_7 PEG_TXN_7 PEG_RXP_8 PEG_RXN_8 PEG_TXP_8 PEG_TXN_8 PEG_RXP_9 PEG_RXN_9 PEG_TXP_9 PEG_TXN_9 PEG_RXP_10 PEG_RXN_10 PEG_TXP_10 PEG_TXN_10 PEG_RXP_11 PEG_RXN_11 PEG_RXP_12 PEG_RXN_12 PEG_RXP_13 PEG_RXN_13 PEG_RXP_14 PEG_RXN_14 PEG_RXP_15 PEG_RXN_15 PEG_TXP_11 PEG_TXN_11 PEG_TXP_12 PEG_TXN_12 PEG_TXP_13 PEG_TXN_13 PEG_TXP_14 PEG_TXN_14 PEG_TXP_15 PEG_TXN_15 B25 A25 PEG_CTX_GRX_P15 0.22U_0201_6.3V6K PEG_CTX_GRX_N15 0.22U_0201_6.3V6K 2 1VGA@ CC7 1VGA@ CC9 B24 C24 PEG_CTX_GRX_P14 0.22U_0201_6.3V6K PEG_CTX_GRX_N14 0.22U_0201_6.3V6K 2 1VGA@ CC11 1VGA@ CC13 B23 A23 PEG_CTX_GRX_P13 0.22U_0201_6.3V6K PEG_CTX_GRX_N13 0.22U_0201_6.3V6K 2 1VGA@ CC1 1VGA@ CC2 B22 C22 PEG_CTX_GRX_P12 0.22U_0201_6.3V6K PEG_CTX_GRX_N12 0.22U_0201_6.3V6K 2 1VGA@ CC16 1VGA@ CC18 B21 A21 PEG_CTX_GRX_P11 0.22U_0201_6.3V6K PEG_CTX_GRX_N11 0.22U_0201_6.3V6K 2 1VGA@ CC20 1VGA@ CC4 B20 C20 PEG_CTX_GRX_P10 0.22U_0201_6.3V6K PEG_CTX_GRX_N10 0.22U_0201_6.3V6K 2 1VGA@ CC22 1VGA@ CC24 B19 A19 PEG_CTX_GRX_P9 PEG_CTX_GRX_N9 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC26 1VGA@ CC28 B18 C18 PEG_CTX_GRX_P8 PEG_CTX_GRX_N8 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC30 1VGA@ CC32 A17 B17 PEG_CTX_GRX_P7 PEG_CTX_GRX_N7 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC34 1VGA@ CC36 C16 B16 PEG_CTX_GRX_P6 PEG_CTX_GRX_N6 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC38 1VGA@ CC40 A15 B15 PEG_CTX_GRX_P5 PEG_CTX_GRX_N5 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC42 1VGA@ CC44 C14 B14 PEG_CTX_GRX_P4 PEG_CTX_GRX_N4 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC46 1VGA@ CC48 A13 B13 PEG_CTX_GRX_P3 PEG_CTX_GRX_N3 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC50 1VGA@ CC52 C12 B12 PEG_CTX_GRX_P2 PEG_CTX_GRX_N2 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC54 1VGA@ CC56 A11 B11 PEG_CTX_GRX_P1 PEG_CTX_GRX_N1 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC58 1VGA@ CC60 C10 B10 PEG_CTX_GRX_P0 PEG_CTX_GRX_N0 0.22U_0201_6.3V6K 0.22U_0201_6.3V6K 2 1VGA@ CC62 1VGA@ CC64 B8 A8 DMI_CTX_PRX_P0 DMI_CTX_PRX_N0 C6 B6 DMI_CTX_PRX_P1 DMI_CTX_PRX_N1 B5 A5 DMI_CTX_PRX_P2 DMI_CTX_PRX_N2 D4 B4 DMI_CTX_PRX_P3 DMI_CTX_PRX_N3 PEG_CTX_C_GRX_P15 PEG_CTX_C_GRX_N15 PEG_CTX_C_GRX_P14 PEG_CTX_C_GRX_N14 PEG_CTX_C_GRX_P13 PEG_CTX_C_GRX_N13 PEG_CTX_C_GRX_P12 PEG_CTX_C_GRX_N12 PEG_CTX_C_GRX_P11 PEG_CTX_C_GRX_N11 PEG_CTX_C_GRX_P10 PEG_CTX_C_GRX_N10 PEG_CTX_C_GRX_P9 PEG_CTX_C_GRX_N9 PEG_CTX_C_GRX_P8 PEG_CTX_C_GRX_N8 PEG_CTX_C_GRX_P7 PEG_CTX_C_GRX_N7 PEG_CTX_C_GRX_P6 PEG_CTX_C_GRX_N6 PEG_CTX_C_GRX_P5 PEG_CTX_C_GRX_N5 PEG_CTX_C_GRX_P4 PEG_CTX_C_GRX_N4 PEG_CTX_C_GRX_P3 PEG_CTX_C_GRX_N3 PEG_CTX_C_GRX_P2 PEG_CTX_C_GRX_N2 PEG_CTX_C_GRX_P1 PEG_CTX_C_GRX_N1 PEG_CTX_C_GRX_P0 PEG_CTX_C_GRX_N0 +VCCIO RC6 24.9_0402_1% PEG_RCOMP G2 PEG_RCOMP Trace Width/Space: 15 mil/ 15 mil Max Trace Length: 600 mil To PCH DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 DMI_CRX_PTX_P0 DMI_CRX_PTX_N0 D8 E8 DMI_CRX_PTX_P1 DMI_CRX_PTX_N1 E6 F6 DMI_CRX_PTX_P2 DMI_CRX_PTX_N2 D5 E5 DMI_CRX_PTX_P3 DMI_CRX_PTX_N3 J8 J9 DMI_RXP_0 DMI_RXN_0 DMI_TXP_0 DMI_TXN_0 DMI_RXP_1 DMI_RXN_1 DMI_TXP_1 DMI_TXN_1 DMI_RXP_2 DMI_RXN_2 DMI_TXP_2 DMI_TXN_2 DMI_RXP_3 DMI_RXN_3 OF 13 DMI_TXP_3 DMI_TXN_3 DMI_CTX_PRX_P0 DMI_CTX_PRX_N0 DMI_CTX_PRX_P1 DMI_CTX_PRX_N1 DMI_CTX_PRX_P2 DMI_CTX_PRX_N2 DMI_CTX_PRX_P3 DMI_CTX_PRX_N3 To PCH CFL-H_BGA1440 @ 4 Compal Secret Data Security Classification 2017/07/20 Issued Date Deciphered Date 2018/07/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title B C D PEG/DMI Size Document Number Custom Rev 1.A DH53F M/B LA-F991P Date: A Compal Electronics, Inc Tuesday, February 13, 2018 Sheet E 10 of 73 @EMI@ PR7203 4.7_1206_5% @EMI@ PC7203 680P_0402_50V7K SNB_+VCCIOP @ PJ7201 +1.0VS_VCCIOP 1 2 +VCCIO JUMP_43X118 +VCCIOP_EN 11 +VCCIOP_ILMT 13 15 PC7209 1U_0402_6.3V6K NC ILMT NC BYP NC PAD 10 12 PC7218 2.2U_0402_6.3V6M @ FB = 0.6V Rup 21 Pin BYP is for CS Common NB can delete +3VALW and PC15 VCCIO_SENSE_R VR_ON @ PR7207 0_0402_5% SUSP# PR7208 1K_0402_5% PC7214 22U_0603_6.3V6M PR7209 @ 0_0402_5% VCCIO_SENSE PR7210 @ 0_0402_5% VSSIO_SENSE VCCIO_SENSE VSSIO_SENSE C VR_ON check delay time with HW 2 +VCCIOP_EN SUSP# PC7201 0.1U_0402_25V6 PR7201 1M_0402_5% +VCCIOP_ILMT @ PR7217 0_0402_5% Vout=0.6V* (1+Rup/Rdown) =0.6*(1+(12k/20.5k)) OVP=0.95V*115%=1.0925V Vout=0.951 V 2% PR7218 12K_0402_1% +VCCIOP_LDO_3V @ PR7213 0_0402_5% Note:Iload(max)=5.5A IOCP=7A~8A(typ) @ 16 SY8288RAC_QFN20_3X3 C PC7212 22U_0603_6.3V6M @ 1 +VCCIOP_LDO_3V PC7211 22U_0603_6.3V6M VCC EN +VCCIOP_FB 17 PC7206 22U_0603_6.3V6M GND 14 Ipeak=5.5A, Iocp:6.6A +1.0VS_VCCIOP PC7205 22U_0603_6.3V6M FB 20 LX GND PL7202 0.68UH_7.9A_20%_5X5X3_M 19 PC7204 22U_0603_6.3V6M GND LX PC7202 0.1U_0603_25V7K 2 IN 2+VCCIOP_BST_R +VCCIOP_LX Rdown +3VALW LX PR7202 +VCCIOP_BST PR7212 10_0402_1% 18 IN BS PG IN Imax=3.85A, IN PR7214 D Choke 0.68uH SH00000Z300 (Common Part) (Size:4.85 x 4.7 x 2.8 mm) (DCR:11m~12m) 1K_0402_1% 0_0603_5% PR7215 20.5K_0402_1% 2 @EMI@ PC7217 0.1U_0402_25V6 1 JUMP_43X79 EMI@ PC7207 2200P_0402_50V7K 1 +19VB @ PU7201 +VCCIOP_B+ @ PJ7202 PC7208 10U_0805_25V6K D PC7219 330P_0402_50V7K @EMI@ PL7201 HCB2012KF-121T50_0805 B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/11/03 Deciphered Date 2017/06/14 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title DH53F M/B LA-F991P Size C Date: Document Number Rev 1.A 1.0VS_VCCIO Tuesday, February 13, 2018 Sheet 59 of 73 +19VB_CPU for ICCMAX=2.2V 76A for +19VB_CPU EMI@ PL8102 FBMA-L11-201209-800LMA50T ICCMAX=2.2V +VREF 47 ISENA1P ISENA1N 1 2 D1 G1 PR8183 PC8140 200_0402_1% 0.47U_0402_6.3V6K 2 @ PR8185 0_0402_5% B Ta=70=>Id=30A Rdson=2.8~3.5 mohm AISP3 AVcore3 BOOST_VCC4 PR8192 PC8150 2.2_0603_1% 0.1U_0603_25V7K 2BOOST_VCC4_R 1 PC8148 PC8149 EMI@ EMI@ PC8147 Ta=70=>Id=17.5A Rdson=8.2~10.5 mohm G1 VCC_UG4 VCC_PHASE4 D1 AON6962_DFN5X6D-8-7 RT9610CGQW_WDFN8_2X2 1U_0201_6.3V6K PL8107 0.15UH_MMD06CZER15MG_37A_20% VCCGT_PHASE1 D2/S1 S2 AON6962_DFN5X6D-8-7 RT9610CGQW_WDFN8_2X2 1U_0201_6.3V6K A EN4 PR8197 PC8159 200_0402_1% 0.47U_0402_6.3V6K 2 @ PR8199 0_0402_5% 0_0402_5% @ Ta=70=>Id=30A Rdson=2.8~3.5 mohm S2 VCCGT_LG1 S2 RTCPU_PS4 2 G1 D1 LGATE GND VCCGT_PHASE1 @EMI@ PR8194 4.7_1206_5% SNUB_VCC4 @EMI@ PC8160 680P_0603_50V8J PR8198 +VCC_GT VCC PGND G2 PHASE EN VCCGT_UG1 UGATE PWM VCC_LG4 S2 Ta=70=>Id=17.5A Rdson=8.2~10.5 mohm BOOT PL8106 0.15UH_MMD06CZER15MG_37A_20% VCC_PHASE4 D2/S1 PR8195 200_0402_1% LGATE GND VCC PGND S2 PHASE EN S2 UGATE PWM G2 PC8157 BOOT +5VALW max:3.5mOhm L/S AON6314 Rds(on) :typ:2.8mOhm, Idsm(TA=25)=37A, Idsm(TA=70)=30A EN4 1 2 1 PR8193 5.1_0402_1% PC8155 PC8156 EMI@ EMI@ PQ8104 AISP4 AVcore4 @EMI@ PR8201 4.7_1206_5% PR8202 182_0402_1% 1 EN3 0_0402_5% @ 2200P_0402_50V7K PC8154 0.1U_0402_25V6 PC8153 10U_0805_25V6K PC8152 10U_0805_25V6K 2 2 RTCPU_PS4 +3VALW PC8146 10U_0805_25V6K 10U_0805_25V6K S2 S2 RT9610CGQW_WDFN8_2X2 PQ8105 PC8161 @EMI@ PR8181 4.7_1206_5% @ PU8106 +5VALW PR8160 200_0402_1% 2 AON6962_DFN5X6D-8-7 +19VB_CPU PR8196 PC8158 2.2_0603_1% 0.1U_0603_25V7K BOOST_VCCGT1 2BOOST_VCCGT1_R PL8305 0.15UH_MMD06CZER15MG_37A_20% VCC_PHASE3 D2/S1 @EMI@ PC8141 680P_0603_50V8J H/S AON6380 Rds(on) :typ:8.2mOhm, max:10.5mOhm Idsm(TA=25)=22A, Idsm(TA=70)=17.5A S2 1U_0201_6.3V6K +19VB_CPU EN5 S2 S2 D1 G1 VCC_PHASE3 VCC_LG3 PU8105 S2 G2 1 LGATE GND VCC PGND VCC_UG3 S2 EN G2 PHASE UGATE PWM SNUB_VCC3 Ta=70=>Id=30A Rdson=2.8~3.5 mohm D1 G1 PC8139 BOOT PR8182 200_0402_1% 2 CPU_SVID_DAT_R PR8200 5.1_0402_1% AVcore2 Ta=70=>Id=17.5A Rdson=8.2~10.5 mohm EN3 PR8179 5.1_0402_1% CPU_SVID_ALERT#_R RTCPU_PWMA1 AISP2 PQ8103 PU8104 1 2 PR8174 PC8135 2.2_0603_1% 0.1U_0603_25V7K 2BOOST_VCC3_R CPU_SVID_CLK_R C @ PR8164 0_0402_5% PC8132 PC8133 EMI@ EMI@ PR8173 10_0603_1% BOOST_VCC3 2.2U_0402_6.3V6M 0.1U_0402_25V6 45.3_0402_1% 100_0402_1% AVGT1 PC8136 PC8131 PC8130 AISPGT1 PR8171 680_0402_1% PC8143 PC8151 PC8124 0.47U_0402_6.3V6K 2 Ta=70=>Id=30A Rdson=2.8~3.5 mohm 2 10_0402_1% PR8161 200_0402_1% +19VB_CPU 2 0_0402_5% PR8191 @EMI@ PR8158 4.7_1206_5% 0_0402_5% @ PR8180 100K_0402_1% PR8190 SDIO_CPU EN2 2200P_0402_50V7K ALERT_CPU @ 2 0.1U_0402_25V6 49.9_0402_1% @EMI@ PC8125 680P_0603_50V8J 10U_0805_25V6K PR8189 PR8188 RT9610CGQW_WDFN8_2X2 10U_0805_25V6K SCLK_CPU 2 ENABLE Upper Threshold > 0.8V Lower Threshold < 0.3V 100_0402_1% PR8186 @ PR8187 AON6962_DFN5X6D-8-7 PR8184 PR96and PR98 pull high resistor are pop at the end of VR SVID Other VR is unpop B VCC_LG2 RTCPU_PWMA1 VCCCORE_VR_PWRGD confirm with power sequence, it need behind +5VS @RF@ PC8142 2.2P_0402_50V8C SNUB_VCC2 RTCPU_PS4 +5VALW +1.05V_VCCST D2/S1 48 PWMA3 PL8306 0.15UH_MMD06CZER15MG_37A_20% VCC_PHASE2 PR8163 AVcore4 +5VALW Reserved for RF Team Request VCC_PHASE2 1U_0201_6.3V6K PC8138 68P_0402_50V8J VCC_UG2 2 +VCC_GT PC8137 330P_0402_50V8J AVcore3 PR8178 100_0402_1% LGATE GND ISENA2P PR8162 680_0402_1% VCC PGND 38 37 ISENA2N ISENA3P 36 41 ISENA3N 40 VCC 29 RTCPU_ISENA1N 39 VCCCORE_VR_PWRGD RTCPU_VCC 54 FBA COMPA 35 RTCPU_FBA RTCPU_COMPA 34 NC AISP4 RTCPU_ISEN4N PR8159 680_0402_1% PHASE EN RTCPU_VCC RTCPU_VCC AISP3 RTCPU_ISEN3N UGATE PWM S2 PC8123 BOOT +5VALW AVcore2 EN2 S2 PR8152 680_0402_1% PR8151 5.1_0402_1% G2 AVcore1 PR8150 680_0402_1% 46 PWMA2 Ta=70=>Id=17.5A Rdson=8.2~10.5 mohm AISP2 RTCPU_ISEN2N AVcore1 PQ8102 2200P_0402_50V7K PGOOD COMP PR8144 PC8122 2.2_0603_1% 0.1U_0603_25V7K 2BOOST_VCC2_R PU8103 AISP1 RTCPU_ISEN1N @ PR8131 0_0402_5% AISP1 PWMA1 PR8176 16.9K_0402_1% 2 BOOST_VCC2 PC8121 PC8117 EMI@ EMI@ 1 1U_0201_6.3V6K PC8120 PC8119 PC8115 Ta=70=>Id=30A Rdson=2.8~3.5 mohm RTCPU_PWM4 ISEN4N PC8134 0.1U_0402_25V6 D PC8113 0.47U_0402_6.3V6K 2 PR8125 200_0402_1% +19VB_CPU 2 RTCPU_PWM3 50 ISEN4P VSEN @ PR8170 0_0402_5% RTCPU_PWM2 53 ISEN3N RTCPU_DVD PR8172 100K_0402_1% 51 ISEN2P VSENA +19VB_CPU PR8177 10K_0402_1% 0_0402_5% @ EN1 SETA2 FB PR8123 200_0402_1% 1 GND RTCPU_VSENA @EMI@ PC8114 680P_0603_50V8J ISEN2N 10 RT9610CGQW_WDFN8_2X2 0.1U_0402_25V6 VCCGT_SENSE RTCPU_PWM1 ISEN1N SETA1 @EMI@ PR8121 4.7_1206_5% 1U_0201_6.3V6K 10U_0805_25V6K VR_ON SET3 11 AON6962_DFN5X6D-8-7 10U_0805_25V6K @ PR8175 0_0402_5% 52 ISEN1P SET2 RTCPU_FB PC8127 82P_0402_50V8J PR8169 510K_0402_1% +VCC_CORE PR8167 23.2K_0402_1% PC8126 330P_0402_50V8J VCC_LG1 30 NC SET1 DVD PR8166 10K_0402_1% PR8168 100_0402_1% 1 PS4 45 @ PR8165 0_0402_5% VCCSENSE 2 32 13 27 EN PWM4 28 RTCPU_VSEN PR8130 0_0402_5% RGND RGNDA 24 25 VCLK VDIO ALERT 23 16 NC VR_HOT IBIAS PWM3 RT3607CE RTCPU_COMP +VCC_CORE PL8101 0.15UH_MMD06CZER15MG_37A_20% VCC_PHASE1 D2/S1 PR8114 5.76K_0402_1% PR8128 0_0402_5% PR8124 100K_0402_1% RTCPU_IBIAS 31 21 22 VREF IMONA PWM2 TONSETA 12 PGND LGATE GND PR8120 0_0402_5% RTCPU_PS4 PU8101 TONSET C RTCPU_VSEN VCC RT3607CEGQW_WQFN56_6X6 ISEN3P RTCPU_VSEN VSSSENSE EN VCC_PHASE1 PR8129 RTCPU_EN VSSGT_SENSE_R VSSSENSE_R @ Choke 0.15uH SH00000X700 (Size:6.59 x 6.6 x 3.0 mm) (DCR:0.9m +-7%) SNUB_VCC1 SCLK_CPU SDIO_CPU ALERT_CPU NC RTCPU_VSENA 33 RTCPU_VSENA PHASE VR_HOT# PWM1 RTCPU_SETA2 19 @ 2 PR8105 4.02K_0402_1% 2 @ PWM VCC_UG1 1K_0402_1% 26 PR8113 1.8K_0402_1% 42 20 @ PR8122 PR8126 100_0402_1% NC RTCPU_SETA1 18 PC8112 UGATE 17 +5VALW EN1 15 +1.05V_VCCST PR8112 5.1_0402_1% 2 14 RTCPU_SET2 RTCPU_SET3 1 PR8104 7.5K_0402_1% RTCPU_SET1 IMON 57 49 GND PR8135 10K_0402_1% PR8140 2K_0402_1% PR8148 402_0402_1% PR8156 412_0402_1% PR8157 PR8149 300_0402_1% 3.16K_0402_1% 2 1 RTCPU_PS4 TSEN PR8134 13.3K_0402_1% PR8147 768_0402_1% 1 PR8155 0_0402_5% 43 TSENA PR8133 13.3K_0402_1% PR8138 26.7K_0402_1% PR8141 PR8136 8.2K_0402_1% 5.1K_0402_1% 2 PR8132 3.01K_0402_1% PR8143 0_0402_5% PR8146 3.4K_0402_1% PR8145 1.02K_0402_1% 1 PR8154 0_0402_5% PR8153 0_0402_5% @ 55 RTCPU_TONSETA PR8115 100_0402_1% BOOT 2200P_0402_50V7K @ RTCPU_TONSET Ta=70=>Id=17.5A Rdson=8.2~10.5 mohm 0.1U_0402_25V6 RTCPU_SET1 RTCPU_SET2 RTCPU_SET3 RTCPU_SETA1 RTCPU_SETA2 PR8111 0_0402_5% 10U_0805_25V6K @ PR8139 0_0402_5% 56 PR8142 0_0402_5% 44 @ +VREF @ VSSGT_SENSE +19VB EMI@ PL8103 FBMA-L11-201209-800LMA50T PQ8101 @ 10U_0805_25V6K PR8137 24.9_0402_1% +VREF PR8101 PC8101 2.2_0603_1% 0.1U_0603_25V7K 2BOOST_VCC1_R PU8102 PC8111 0.47U_0402_16V4Z RTCPU_TONSET PR8119 57.6K_0402_1% 2 RTCPU_TONSETA BOOST_VCC1 + 10K_0402_1%_B25/50 3370K NTCGT1N PR8127 1_0402_1% Core offset function disable, GT offset function disable, PSYS disable PR8118 57.6K_0402_1% 2 SETA2 Ramp=133%, DVIDW=9us, QRT=25mV, QRW=44% PR8117 442K_0402_1% SETA1 ICCMAX=32A, OCP=120%, DVIDT=60mV SET3 Zero LL disable, VR address Core=0, GT=1 PR8116 402K_0402_1% SET2 Ramp=133%, DVIDW=9us, QRT=25mV, QRW=44% PH8104 PR8110 220K_0402_5%_B25/50 4700K 8.66K_0402_1% RTCPU_TSENA RTCPU_TSENA_R PH8103 PR8109 220K_0402_5%_B25/50 4700K 8.66K_0402_1% RTCPU_TSEN RTCPU_TSEN_R 1 PR8108 2.2_0402_1% 1 PR8107 2.2_0402_1% SET1 ICCMAX=128A, OCP=120%, DVIDT=35.7mV PH8101 100K_0402_1%_B25/50 4250K NTC1N PR8106 100_0402_1% 2200P_0402_50V7K Fs=400k, LL=2.1m for GT D 0.22U_0402_25V6K PH8102 NTCGT1P PC8106 PC8107 EMI@ EMI@ 0.1U_0402_25V6 0.22U_0402_25V6K Fs=400k, LL=1.8m for Core PC8110 8.45K_0402_1% NTC1P PC8105 10U_0805_25V6K PC8109 +19VB_CPU 10U_0805_25V6K +19VB_CPU PR8103 30.1_0402_1% PC8108 100U_25V_NC_6.3X6 PC8104 confirm with power sequence, it need behind +5VS PR8102 +VREF 90A A SNUB_VCCGT1 @EMI@ PC8162 680P_0603_50V8J PR8204 EN5 RTCPU_PS4 0_0402_5% @ PR8203 PC8163 182_0402_1% 0.47U_0402_6.3V6K 2 @ PR8205 0_0402_5% AISPGT1 AVGT1 Compal Secret Data Security Classification Issued Date 2016/07/18 Deciphered Date 2017/06/14 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title RT3607CE Size Document Number Custom Tuesday, February 13, 2018 Date: Rev 1.A Sheet 60 of 73 PR902 and PR904 pull high resistor are pop at the end of VR SVID Other VR is unpop +1.05V_VCCST SVID_ALERT# pull high resistor is at HW side Confirm HW side Don't double pull high +1.05V_VCCST @ PR8302 D confirm with power sequence, it need behind +5VS D @ PR8339 @ PR8341 0_0402_5% 1 PR8310 59K_0402_1% 23 FB_VCCSA 24 RGND_VCCSA 22 VSEN UGATE 1.1K PR832 10K BOOST_VCCSA EMI@ PC8308 2200P_0402_50V7K @EMI@ PC8307 0.1U_0402_25V6 10U_0805_25V6K PC8305 665 PR830 243 549 PR831 10K 1K +VCC_SA 29 S2 S2 C 10K(3370K) 1K(3650K) 576_0603_1% PC8310 0.47U_0402_6.3V6K PR8336 PR8337 255_0402_1% 10K_0402_1% 2AVcore1_NTC @ PR8340 0_0201_5% 2AVcore1_NTC_R PH8301 10K_0402_1%_B25/50 3370K ISEN1P For NTC trace routing only 20 ISEN1N 37.4K D1 D1 D1 G1 LG_VCCSA UG_VCCSA 40.2K 604 PQ8301 AONH36334_DFN3X3A8-10 PR8331 LX_VCCSA S2 AISP1_R 10 PR833 PR828 B +5VALW AISP1_VCCSA AVcore1_VCCSA PC8319 0.1U_0402_25V6 36.3 PC8318 2.2U_0603_10V6K 21 DRVEN PC8317 1U_0201_6.3V6K 15 PVCC 12 2 Local sense, for debug only PR8349 22_0402_1% PR8348 100K_0402_5% Confirm HW side Don't double pull high VCC +VCC_VCCSA1 VCCSA_VR_PWRGD LG_VCCSA PL8301 0.24UH_22A_20%_ 7X7X3_M LX_VCCSA 10 RGND @ PC8315 0.1U_0402_25V6 @ PC8316 0.1U_0402_25V6 11 D1 FB 0_0402_5% D2/S1 COMP PR8346 14 G2 PWM BOOT COMP_VCCSA 73.2K PH802 SET3 @ VSSSA_SENSE 2 SET2 VR_READY PR8347 100_0402_1% B LX_VCCSA SET1 PHASE 25 10U_0805_25V6K PC8304 1 2 PSYS LGATE VSEN_VCCSA 68.1K PR841 UG_VCCSA 26 ISEN 27 PR813 COMP PU8301 GND @ PC8313 0.1U_0402_25V6 VR_ON RT3601EAGQW_WQFN28_4X4 28 PC8314 100P_0402_50V8J high > 0.7V, Low < 0.3V PR8301 2.2_0603_5% BOOST_VCCSA 2BOOST_VCCSA_R SET1_VCCSA SET2_VCCSA SET3_VCCSA @ PR8342 PR8343 PR8344 PR8345 0_0402_5% 10K_0402_1% 300_0402_1% 47.5K_0402_1% 2 2 PC8312 330P_0402_50V8J PR8321 EN: 0_0402_5% 0.1U_0402_25V6 EN SDIO_VCCSA ALERT#_VCCSA VDIO VCLK ALERT# VCLK_VCCSA VREF_VCCSA 17 VREF VIN @ PC8306 VCCSA_VR_EN PC8301 0.22U_0402_16V7K 19 VRHOT# 13 Choke 7x7x4 7x7x3 Size and DCR 0.67m +-5%0.9m +-5% IMON 18 TSEN_VCCSA 16 PR8322 2.2_0805_1% CPU_SVID_DAT_R +19VB_CPU IMON +19VB_CPU PR8311 10_0402_1% PR8316 2.4K_0402_1% IMON_VCCSA PR8314 200_0402_1% Vboot=0V CPU_SVID_ALERT#_R 1_0402_1% TSEN PR8315 7.32K_0402_1% PR8312 10K_0402_1% PR8318 2K_0402_1% PR8319 22K_0402_1% PR8320 22.6K_0402_1% PR8326 0_0402_5% PR8317 3.6K_0402_1% PR8325 300_0402_1% PR8324 120_0402_1% PR8313 48.7K_0402_1% TSEN_VCCSA_R 2 PSYS_VCCSA 0_0402_5% CPU_SVID_CLK_R @ PR8308 0_0402_5% AVcore1_VCCSA VCCSA_SENSE PR8306 49.9_0402_1% PR8307 PH8302 100K_0402_1%_B25/50 4250K AISP1_VCCSA PR8303 45.3_0402_1% @EMI@ PC8311 @EMI@ PR8330 680P_0402_50V7K 4.7_1206_5% SNUB_VCCSA PR8335 100_0402_1% +VCC_SA @ VR_HOT# 90 degreeC ALERT# 87.3 degreeC PC8309 0.22U_0402_25V6K PR8334 PR8329 2.2K_0402_1% 7.68K_0402_1% 2 Local sense, for debug only Trace is form output cap that is near choke PR8333 PR8328 300_0402_1% 20K_0402_1% 2 PR8332 PR8327 100_0402_1% 1.78K_0402_1% 2 C VREF_VCCSA SET1 connect to 5V is into test mode The output is 1.05V PR8309 PR8305 14K_0402_1% 30.9K_0402_1% 2 VREF_VCCSA PR8304 100_0402_1% VR2_HOT# PC8302 0.47U_0402_6.3V6K PC8303 0.1U_0402_25V6 2 1K_0402_5% +3VALW +5VALW VCCSENSE and VSSSENSE need have a 100ohm at HW Side A A Compal Secret Data Security Classification Issued Date 2011/06/13 Deciphered Date 2012/06/13 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title RT3601EA VCC_SA Size Document Number Custom Date: Rev 1.A Tuesday, February 13, 2018 Sheet 61 of 73 D C B A 2 2 2 1 2 PC9067 22U_0603_6.3V6M PC9039 22U_0603_6.3V6M PC9009 22U_0603_6.3V6M PC9003 220U_D2_2V_Y PC9093 22U_0603_6.3V6M PC9125 1U_0201_6.3V6M PC9115 1U_0201_6.3V6M PC9094 22U_0603_6.3V6M PC9068 22U_0603_6.3V6M PC9040 22U_0603_6.3V6M PC9010 22U_0603_6.3V6M PC9004 220U_D2_2V_Y PC9142 1U_0201_6.3V6M 2 PC9130 1U_0201_6.3V6M PC9131 1U_0201_6.3V6M PC9132 1U_0201_6.3V6M PC9095 22U_0603_6.3V6M PC9117 1U_0201_6.3V6M 2 @ PC9096 22U_0603_6.3V6M PC9118 1U_0201_6.3V6M PC9069 22U_0603_6.3V6M PC9070 22U_0603_6.3V6M @ PC9097 22U_0603_6.3V6M 2 PC9074 22U_0603_6.3V6M PC9122 1U_0201_6.3V6M PC9073 22U_0603_6.3V6M PC9121 1U_0201_6.3V6M PC9072 22U_0603_6.3V6M PC9120 1U_0201_6.3V6M PC9071 22U_0603_6.3V6M PC9119 1U_0201_6.3V6M 1 PC9075 22U_0603_6.3V6M PC9123 1U_0201_6.3V6M PC9076 22U_0603_6.3V6M 2 PC9098 1U_0201_6.3V6M 2 PC9099 1U_0201_6.3V6M PC9078 1U_0201_6.3V6M 2 PC9080 1U_0201_6.3V6M PC9042 22U_0603_6.3V6M PC9043 22U_0603_6.3V6M PC9044 22U_0603_6.3V6M PC9045 22U_0603_6.3V6M PC9046 22U_0603_6.3V6M PC9047 22U_0603_6.3V6M PC9048 22U_0603_6.3V6M PC9049 22U_0603_6.3V6M PC9050 22U_0603_6.3V6M PC9051 22U_0603_6.3V6M PC9052 22U_0603_6.3V6M PC9011 22U_0603_6.3V6M PC9005 220U_D2_2V_Y PC9012 22U_0603_6.3V6M 2 PC9013 22U_0603_6.3V6M 2 2 2 PC9019 22U_0603_6.3V6M PC9020 22U_0603_6.3V6M PC9021 22U_0603_6.3V6M PC9006 220U_D2_2V_Y PC9022 22U_0603_6.3V6M 2 Security Classification Issued Date 2 @ PC9106 1U_0201_6.3V6M PC9084 1U_0201_6.3V6M PC9085 1U_0201_6.3V6M @ PC9107 1U_0201_6.3V6M PC9086 1U_0201_6.3V6M PC9054 22U_0603_6.3V6M PC9055 22U_0603_6.3V6M PC9056 22U_0603_6.3V6M @ PC9057 22U_0603_6.3V6M @ PC9058 22U_0603_6.3V6M PC9007 220U_D2_2V_Y PC9023 22U_0603_6.3V6M PC9024 22U_0603_6.3V6M PC9025 22U_0603_6.3V6M PC9026 22U_0603_6.3V6M PC9027 22U_0603_6.3V6M PC9028 22U_0603_6.3V6M NA 2 PC9134 1U_0201_6.3V6M 1 Title @ PC9137 1U_0201_6.3V6M @ PC9138 1U_0201_6.3V6M PC9110 22U_0603_6.3V6M PC9111 22U_0603_6.3V6M PC9112 22U_0603_6.3V6M PC9113 22U_0603_6.3V6M PC9087 22U_0603_6.3V6M PC9088 22U_0603_6.3V6M PC9089 22U_0603_6.3V6M PC9090 22U_0603_6.3V6M PC9091 22U_0603_6.3V6M PC9092 22U_0603_6.3V6M Sheet 62 of Compal Electronics, Inc DH53F M/B LA-F991P Tuesday, February 13, 2018 Size Document Number Custom Date: @ PC9136 1U_0201_6.3V6M @ @ PC9135 1U_0201_6.3V6M 2 PC9109 22U_0603_6.3V6M Total VCCSA Output Capacitor: 4+6 X 22uF_0603 X 1uF_0201 @ 2014/07/04 PC9108 22U_0603_6.3V6M +VCC_SA Compal Secret Data Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC @ PC9105 1U_0201_6.3V6M PC9083 1U_0201_6.3V6M 3 @ PC9104 1U_0201_6.3V6M PC9082 1U_0201_6.3V6M PC9053 22U_0603_6.3V6M Total VCCGT Output Capacitor: X 330uF 5+13 X 22uF_0603_X5R 12 X 1uF_0201 @ PC9103 1U_0201_6.3V6M + PC9081 1U_0201_6.3V6M 1 PC9156 22U_0603_6.3V6M 2 @ PC9102 1U_0201_6.3V6M PC9155 22U_0603_6.3V6M PC9018 22U_0603_6.3V6M PC9154 22U_0603_6.3V6M PC9017 22U_0603_6.3V6M PC9153 22U_0603_6.3V6M PC9016 22U_0603_6.3V6M PC9152 22U_0603_6.3V6M PC9015 22U_0603_6.3V6M PC9151 22U_0603_6.3V6M PC9014 22U_0603_6.3V6M PC9150 22U_0603_6.3V6M 1 @ PC9101 1U_0201_6.3V6M + PC9079 1U_0201_6.3V6M 2 @ PC9100 1U_0201_6.3V6M PC9077 1U_0201_6.3V6M PC9041 22U_0603_6.3V6M +VCC_GT PC9133 1U_0201_6.3V6M @ PC9148 1U_0201_6.3V6M PC9116 1U_0201_6.3V6M Total VCORE Output Capacitor:+VCC_GT X 330uF 23 +10 X 22uF_0603_X5R 24 X 1uF_0201 2 @ PC9147 1U_0201_6.3V6M PC9129 1U_0201_6.3V6M @ PC9146 1U_0201_6.3V6M 2 PC9128 1U_0201_6.3V6M @ PC9145 1U_0201_6.3V6M PC9127 1U_0201_6.3V6M @ PC9144 1U_0201_6.3V6M 2 @ PC9143 1U_0201_6.3V6M PC9126 1U_0201_6.3V6M 1 + PC9141 1U_0201_6.3V6M + PC9140 1U_0201_6.3V6M 1 PC9114 1U_0201_6.3V6M + PC9124 1U_0201_6.3V6M +VCC_CORE +VCC_CORE PC9139 1U_0201_6.3V6M 73 R ev 1.A D C B A B C D E @ PJ1701 JUMP_43X79 2 +19VB_1.35VSDGPUP G1 10U_0805_25V6K PC1705 Choke 1uH SH00000YE00 (Common Part) (Size:7.6 x 6.6 x mm) (DCR:6.7m~7.4m) +1.35VSDGPU PL1701 1UH_11A_20%_7X7X3_M PSI LGATE1 20 LX1_1.35VSDGPUP 19 LGATE1_1.35VSDGPUP PR1706 2.2_0603_1% BST1_1.35VSDGPUP_R G2 S2 PC1707 0.22U_0603_25V7K PR1704 EMI@ 4.7_1206_5% BST1_1.35VSDGPUP PC1708 EMI@ 680P_0402_50V7K 1 PR1710 1K_0402_1% 0.1U_0402_25V6 1.35VSDGPUP_VREF UGATE2 VREF BOOT2 14 8.25K_0402_1% HGATE2_1.35VSDGPUP 15 BST2_1.35VSDGPUP 16 LX2_1.35VSDGPUP 17 LGATE2_1.35VSDGPUP IOCP PR1711 2.2_0603_1% BST2_1.35VSDGPUP_R PC1714 0.22U_0603_25V7K PC1015.2的GND 單單 單 vi a 下下 R3 OPS PC1720 0.1U_0402_25V6 0_0402_5% MEM_VDD_CTL PR1720 PQ1703B DMN53D0LDW-7 2N SOT363-6 PQ1703A DMN53D0LDW-7 2N SOT363-6 10K_0402_5% 1 Common part SGA0000BT00 G2 S2 PR1714 EMI@ 4.7_1206_5% PC1719 EMI@ 680P_0402_50V7K The GND trace need close to PR1719 + GPU pin E51 or F52 Differential with FB_VDDQ_SENSE FB_VDDQ_SENSE +3VALW PL1702 1UH_11A_20%_7X7X3_M PR1716 0_0402_5% RT8812AGQW-GP D2/S1 + PC1717 47P_0402_50V8J 10 RGND PR1717 0_0402_5% P5@ PR1723 68.1K_0402_1% 1 PR1715 35.7K_0402_1% P55@ PR1718 52.3K_0402_1% P55@ 2 P5@ PR1722 30.9K_0402_1% GND @ G1 FB_VDDQ_SENSE_R 1 21 R2 Choke 1uH SH00000YE00 (Common Part) (Size:7.6 x 6.6 x mm) (DCR:6.7m~7.4m) 12 VSNS PC1718 0.1U_0402_25V6 SS 2 PR1713 100_0402_5% D1 LGATE2 S2 REFADJ S2 PHASE2 PR1712 10K_0402_1% REFIN R1 1.35VSDGPUP_VREF_SS 11 PC1716 2200P_0402_50V7K PC1715 0.1U_0402_25V6 @ PC1721 680P_0402_50V7K @ PR1721 49.9_0402_1% 1 VID + @ PR1709 10U_0805_25V6K PC1713 1.35VSDGPU_EN 10U_0805_25V6K PC1712 0_0402_5% PC1711 PQ1702 AON6962 2N DFN5X6D @ PR1708 100K_0402_5% PR1707 2 @ +3VS PC1722 220U_D2 SX_2VY_R9M PHASE1 PC1709 220U_D2 SX_2VY_R9M EN HGATE1_1.35VSDGPUP S2 BOOT1 S2 UGATE1 PGOOD +19VB_GPU TON 13 1.35VSDGPU_EN_R D1 10K_0402_5% 1.35VSDGPU_PG 1.35VSDGPUP_TON D2/S1 +3VS PR1705 PR1703 383K_0402_1% PVCC +19VB_1.35VSDGPUP PU1701 Frequency 0.1U_0402_25V6 PR1702 2.2_0402_1% PC1701 2.2U_0603_16V6K 18 PC1706 1.35VSDGPUP_TON_R 1 RT8812_PVCC 10U_0805_25V6K PC1704 PQ1701 AON6962 2N DFN5X6D PR1701 2.2_0603_5% EMI@ PC1703 0.1U_0402_25V6 2 EMI@ PC1702 2200P_0402_50V7K +5VALW PC1710 220U_D2 SX_2VY_R9M A R1 R2 Hynix@ Samsung@ 10 35.7 10 35.7 R3 Vout NA 52.3 1.55 1.352 0.8% 0.7% NA 68.1 1.5 1.36 0.7% 0.74% Micron@ 10 10 30.9 30.9 +1.35VSDGPUP Vout = 1.35V TDC = 16.9A Peak Current = 24.2A OCP=36.3A FSW=400kHz DaulMOS AON6992 TYP MAX H/S Rds(on) = 6.8mohm ,8.6mohm L/S Rds(on) = 2.0mohm ,2.5mohm 4 Compal Secret Data Security Classification Issued Date 2016/11/03 Deciphered Date 2017/06/14 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc VRAM Size Document Number Custom R ev 1.A DH53F M/B LA-F991P Date: Tuesday, February 13, 2018 Sheet 63 of 73 A B C D @ PJ1802 JUMP_43X79 2 +1.0VSDGPUP PC1801 22U_0603_6.3V6M PU1801 SY8032ABC_SOT23-6 2 PC1806 0.1U_0402_16V7K @ PC1805 22U_0603_6.3V6M PR1803 13.7K_0402_1% 1VSDGPU_EN_R PR1805 1M_0402_1% +1.0VSDGPUP Rup EMI@ PR1802 4.7_0603_5% PC1804 22U_0603_6.3V6M 1 LX_1.0VSDGPUP 2 EN PC1803 22U_0603_6.3V6M FB LX GND PG 1VSDGPU_EN PR1804 0_0402_5% PR1801 10K_0402_5% IN +3VALW PC1802 68P_0402_50V8J VIN_1.0VSDGPUP 1VSDGPU_PG Imax= 0.7A, Ipeak= 1.1A PL1801 1UH_2.8A_30%_4X4X2_F @ PJ1801 JUMP_43X79 2 SNUB_1.0VSDGPUP +3VALW Choke 1uH SH00000YG00 (Common Part) (Size:3.8 x 3.8 x 1.9 mm) (DCR:20m~25m) VFB=0.6V Vout=0.6V* (1+Rup/Rdown) =0.6V* (1+13.7/20) Vout=1.011V FB_1.0VSDGPUP Rdown EMI@ PC1807 680P_0402_50V7K 1 +1.0VSDGPU PR1806 20K_0402_1% VIN_1.0VSDGPUP E Note: When design Vin=5V, please stuff snubber to prevent Vin damage 2 3 4 Compal Secret Data Security Classification Issued Date 2016/11/03 Deciphered Date 2017/06/14 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size C Date: A B C D Compal Electronics, Inc 1.05VSDGPU Document Number Rev 1.A DH53F M/B LA-F991P Tuesday, February 13, 2018 Sheet E 64 of 73 +19VB_NVVDD 10K_0402_5% PC1217 @ 0.1U_0402_25V6 PC1202 1 PR1205 0_0402_5% NTC_La NTC_Lb @PR1208 @PR1209 2 @ PR1212 0_0402_5% GPU_PROG2 Close to PL1301 33 PR1225 PR1226 PR1227 PR1264 ISEN1 ISEN2 12 ISEN3 11 ISEN4 10 5VCC PR1231 2.2_0603_1% +5VS PWM1 PR1239 0_0402_5% GPU_PWM1 +5VS 0_0402_5% @ @ PR1257 PR1255 0_0402_5% GPU_LPC PR1248 10K_0402_5% PR1244 51K_0402_5% GPU_PROG5 PR1247 100K_0402_5% GPU_PROG4 2 PR1243 100K_0402_5% GPU_PROG3 @ PR1246 36K_0402_5% GPU_PWM3 GPU_PROG2 GPU_PROG1 0_0402_5% GPU_PWM2 PR1250 0_0402_5% PR1252 8.2K_0402_5% PWM3 PR1245 PC1216 FBRTN 請 教 A U TO PHASE的 PHASE的 設 定 5VCC 20.5K_0402_1% C Fsw=300kHz GPU_PH3 5VCC 2 GPU_PH2 PWM2 PR1249 2 0_0402_5% PR1256 PR1240 4700P_0402_50V7K PC1215 2 GPU_PH1 0.01U_0402_16V R5 R2PR1258 NVVDD1_PG 2.2K_0402_1% 2.2K_0402_1% 2K_0402_1% 100K_0402_5% GPU_PROG6 14 13 PR1234 33K_0402_5% TSEN 15 VRHOT_L ISEN1N layout 上 : 請 將 RSE N1 ~ 放 靠 近 C o n t r o l l e r B GPU_PROG6 REFIN 16 ISEN1P VSEN FB COMP VIN PR1241 PH1201 PC1209 0.1U_0402_10V6K SVT EPAD 17 18 VDDIO VSEN_NB_IN SET1 EN NVVDD1 TDC = 60A Peak Current = 127A OCP = 165A NTC_Lb 470K_0402_5%_B25/50 4700K GPU_PROG1 VINMON GPU_PROG5 19 20 S5_OUT 21 22 PGOOD PR1238 100K_0402_5% NVVDD1_VID FBA IMON PR1237 0_0402_5% LDO_OUT 24 NC R4 @ VCC VREF_PINSET R3 @ 23 LDO_VIN LGATE 4.32K_0402_1% +3VS MUX_CTRL PW ROK PU1201 UP9511QQKI_WQFN32_4X4 R1 For N17E-G1, TDP 60.2W C SVD SVC REFADJ @ PR1235 0_0402_5% 1 PR1219 1K_0402_1% PHASE PVCC @ GPU_VID PR1233 0_0402_5% UGATE 309_0402_1% 16.5K_0402_1% NVVDD1_PSI BOOT 30K_0402_5% PQ1201B DMN53D0LDW-7 2N SOT363-6 PR1230 1 32 2 31 GPU_PSI PR1236 @ +1.8VS PR1232 0_0402_5% PQ1201A DMN53D0LDW-7 2N SOT363-6 B 30 NVVDD1_ENP NVVDD1_EN +3VS 29 GPU_LPC PR1263 10K_0402_5% @ 28 NVVDD_ISUMN3 PC1214 1U_0402_6.3V6K 27 GPU_PROG4 FBRTN 26 GPU_PROG3 PR1228 100_0402_5% +3VALW 25 RGND 0.1U_0402_25V6 PR1223 1K_0402_1% FBRTN PR1224 @ 0_0402_5% NVVDD1_VSS_SENSE 0.1U_0402_25V6 PC1211 C @ PC1212 NTC_La PC1207 0.1U_0402_10V6K @ PR1262 @ 0_0402_5% NVVDD_ISUMN2 @ PC1205 0.1U_0402_25V6 CSPSUM PR1222 100_0402_5% +NVVDD1 COMP 6.19K_0402_1% 0_0402_5% 0_0402_5% PR1220 NVVDD1_VCC_SENSE @ PC1208 0.1U_0402_25V6 PR1217 0_0402_5% EAP 1 2 PC1206 PR1216 PR1218 0.015U_0402_16V7K 2.4K_0402_1% 2 PR1221 0_0402_5% @ PC1204 0.1U_0402_25V6 PR1215 0_0402_5% SS PR1214 0_0402_5% Close to PU1201 NVVDD_ISUMN1 CSNSUM 2 的 compon en t D PR1210 1_0402_1% PR1211 1_0402_1% PR1213 1_0402_1% 0_0402_5% 0_0402_5% layout 上 : 請 將 Tota l DC R sensin g 放 靠 近Control 近 Control le r PC1203 0.01U_0402_16V7K PR1242 43K_0402_5% NVVDD_ISUMP3 D @ 0.1U_0402_25V6 PR1201 PR1207 for OCP setting @ PR1207 22.1K_0402_1% 2 PR1206 91K_0402_1% NVVDD_ISUMP2 PR1251 8.2K_0402_5% PC1201 0.1U_0402_25V6 NVVDD_ISUMP1 PR1204 20K_0402_1% PR1203 20K_0402_1% PR1202 20K_0402_1% A A PWMVID 的 RC BOM 請 根 據GPU's 據 GPU's config 設 定 Cold Boot = 4-phase Warm Boot = 4-phase Compal Electronics, Inc Compal Secret Data Security Classification 2016/11/03 Issued Date Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_VGA_UP9511P Size Rev 1.A DH53F M/B LA-F991P Date: Document Number Sheet Tuesday, February 13, 2018 65 of 73 +19VB PR1301 EMI@ PL1304 FBMA-L11-201209-800LMA50T PR1302 4 3 0.005_1206_1% +19VB_NVVDD NVVDD (NVVDD1) Vboot=0.8V TDC=60A Peak Current=127A OCP=165A FSW=300kHz Dr.MOS SIC632 TYP MAX H/S Rds(on) = 4.8mohm ,5.76mohm L/S Rds(on) = 1.3mohm ,1.56mohm 0.005_1206_1% CSSP_B+ PC1303 0_0402_5% +5VS A PR1304 10K_0402_1% PW M ZCD_EN# VCIN CGND BOOT NC PHASE VIN VIN PGND SW SW SW SW CGND GL DSBL# THW n VDRV PGND GL SW SW SW SW SW SW SW 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PR1307 2.2_0603_1% Choke 0.22uH SH00000QZ00 GPU_PH1 PL1301 0.22UH_MMD-10DZ-R22MES1L 35A_20% GPU_PH1 +NVVDD1 B EMI@ PR1309 4.7_1206_5% NVVDD_ISUMP1 NVVDD_ISUMN1 GPU_SNB1 PC1327 10U_0805_25VAK PC1326 10U_0805_25VAK SIC632CDT1GE3_POWERPAK31_5X5 PC1311 10U_0805_25VAK PC1310 10U_0805_25VAK PC1309 10U_0805_25VAK PC1308 10U_0805_25VAK EMI@ PC1307 2200P_0402_50V7K @EMI@ PC1306 0.1U_0402_25V6 @ CSSN_NVVDD 1 0_0402_5% @ PR1306 PC1302 1U_0603_16V7 PR1308 0.1U_0603_25V7K B PC1304 1U_0603_16V7 10 11 12 13 14 +5VS +19VB_NVVDD CSSP_NVVDD PU1301 PR1305 1K_0402_1% GPU_PWM1 CSSN_B+ 0_0402_5% @ PR1303 +5VS +19VB_GPU EMI@ PL1303 FBMA-L11-201209-800LMA50T A EMI@ PC1312 680P_0402_50V7K 0_0402_5% +5VS PC1314 0_0402_5% 0.1U_0603_25V7K CGND GL DSBL# THW n VDRV PGND GL SW SW SW SW SW SW SW 28 27 26 25 24 23 22 21 20 19 18 17 16 15 C 10K_0402_1% PR1314 2.2_0603_1% PL1302 0.22UH_MMD-10DZ-R22MES1L 35A_20% GPU_PH2 SIC632CDT1GE3_POWERPAK31_5X5 +NVVDD1 EMI@ PR1316 4.7_1206_5% PC1323 10U_0805_25VAK NVVDD_ISUMP2 GPU_SNB2 PC1322 10U_0805_25VAK EMI@ PC1319 2200P_0402_50V7K @EMI@ PC1318 0.1U_0402_25V6 @ Choke 0.36uH SH00000R500 (Size:13.5 x 12.5 x 2.8 mm) (DCR:1.5m~1.8m) GPU_PH2 +19VB_NVVDD PR1311 PW M ZCD_EN# VCIN CGND BOOT NC PHASE VIN VIN PGND SW SW SW SW PC1315 1U_0603_16V7 PR1315 PC1313 1U_0603_16V7 0_0402_5% +5VS 10 11 12 13 14 GPU_PWM2 @ PR1313 PU1302 PR1312 1K_0402_1% C @ PR1310 +5VS EMI@ PC1324 680P_0402_50V7K NVVDD_ISUMN2 D D Compal Electronics, Inc Compal Secret Data Security Classification 2016/11/03 Issued Date Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_+NVVDD1 Size Rev 1.A DH53F M/B LA-F991P Date: Document Number Sheet Tuesday, February 13, 2018 66 of 73 +5VS +5VS PR1355 2.2_0603_1% GPU_PH3 GPU_PH3 PL1351 0.22UH_MMD-10DZ-R22MES1L 35A_20% +NVVDD1 SIC632CDT1GE3_POWERPAK31_5X5 PC1361 10U_0805_25VAK EMI@ PR1357 4.7_1206_5% C @ NVVDD_ISUMP3 EMI@ PC1362 680P_0402_50V7K NVVDD_ISUMN3 GPU_SNB3 PC1360 10U_0805_25VAK 0.1U_0603_25V7K CGND GL DSBL# THW n VDRV PGND GL SW SW SW SW SW SW SW PC1353 0_0402_5% PC1359 10U_0805_25VAK PC1358 10U_0805_25VAK EMI@ PC1357 2200P_0402_50V7K @EMI@ PC1356 0.1U_0402_25V6 @ PW M ZCD_EN# VCIN CGND BOOT NC PHASE VIN VIN PGND SW SW SW SW 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PC1354 1U_0603_16V7 PR1356 PC1352 1U_0603_16V7 0_0402_5% +5VS +19VB_NVVDD C 10 11 12 13 14 GPU_PWM3 PR1352 10K_0402_1% PU1351 PR1353 1K_0402_1% @ PR1354 0_0402_5% D @ PR1351 D B B A A Compal Electronics, Inc Compal Secret Data Security Classification 2016/11/03 Issued Date Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_+NVVDD1 Size Rev 1.A DH53F M/B LA-F991P Date: Document Number Sheet Tuesday, February 13, 2018 67 of 73 A PC1417 10U_0805_25VAK PC1416 10U_0805_25VAK PC1407 10U_0805_25VAK PC1406 10U_0805_25VAK D1 G1 S2 G2 S2 S2 D1 S2 S2 D2/S1 Choke 0.22uH SH000011H00 (Size:7*7*4 mm) DCR 0.97 PL1401 NVVDDS_LG1 0.22UH_24A_+-20%_7X7X4_M PR1429 100K_0402_5% @ RT@ PR1433 2.2_0805_5% EMI@ PR1408 4.7_1206_5% NVVDDS_SNB1 +NVVDD2 100_0402_5% PR1423 1 1 1 @ PR1421 0_0402_5% B +NVVDD2 AON6962_DFN5X6D-8-7 PC1412 @ 47P_0402_50V8J PQ1402 1 2 @ PR1420 0_0402_5% G1 G2 2 @ PQ1401 D2/S1 PR1413 @ 49.9_0603_1% @ PR1414 0_0402_5% EMI@ PC1405 2200P_0402_50V7K @EMI@ PC1404 0.1U_0402_25V6 2 0_0603_5% 93.1K_0402_1% AON6962_DFN5X6D-8-7 S2 16 PHASE2 PR1432 PR1427 NVVDDS_HG1 NVVDDS_SW1 CSSN_NVVDDS 51.1K_0402_1% 1000P_0402_25V8J RT@ PC1418 1U_0603_25V6K EMI@ PC1411 680P_0402_50V7K OCP & FS setting NVVDD2_VCC_SENSE NVVDD2_VSS_SENSE Avoid high dV/dt 20.5K_0402_1% UPI@ PC1409 11 RT@ PR1434 432K_0402_1% CSSP_NVVDDS UPI@ PR1410 NVVDDS_COMP 12 PIN12 RT:93.1K OCP=37A OCP=[[(10uA*93.1k)/12/2.5m]+(12A/2)]*1phase=37A RT@ PR1422 NVVDD2_PG 13 UPI@ PR1418 45.3K_0402_1% 309_0402_1% 2 C PC1414 4700P_0402_50V7K PR1424 14 +19VB_NVVDD R2 C 18 NVVDDS_VREF R5 PC1413 1500P_0402_50V7K PR1417 16.5K_0402_1% PR1416 4.32K_0402_1% PR1415 6.19K_0402_1% NVVDDS_VIDBUF R4 17 FB B R3 PVCC GND VID Avoid high dV/dt R1 LGATE2 20 19 LGATE1 COMP 0_0402_5% 0.005_1206_1% PR1407 10K_0402_5% 15 FBRTN PSI OCS/CB PGOOD VREF NVVDD2_VID UGATE2 EN UGATE1 NVVDD2_PSI_R PR1411 PU1401 UP1666QQKF_WQFN20_3X3 10 +19VB_NVVDDS +3VS BOOT2 REFIN 0_0402_5% TPAD UPI@ BOOT1 REFADJ @ PR1412 10K_0402_1% PHASE1 21 NVVDDS_HG1 NVVDD2_EN PU1401 RT@ RT8816AGQW_WQFN20_3X3 2 1 NVVDDS_BST1 1 PR1405 2.2_0603_1% PR1409 NVVDD1_PSI PR1402 PC1408 0.22U_0603_25V7K +1.8VS PR1406 20K_0402_1% +19VB_GPU @ PR1431 30K_0402_1% NVVDDS_SW1 PR1404 100K_0402_1% 6,65> NVVDDS_LG1 PC1401 @ PR1430 30K_0402_5% NVVDD2_EN PR1401 2.2_0603_1% +5VS +3VS 4.7U_0402_6.3V6M A PC1415 0.01U_0402_16V PR1425 100_0402_5% NVVDDS (NVVDD2) Vboot=0.8V TDC=18A Peak Current=30.7A OCP=37A FSW=350kHz DaulMOS AON6962 TYP MAX H/S Rds(on) = 6.8mohm ,8.6mohm L/S Rds(on) = 2.0mohm ,2.5mohm Close to PU1201 PIN9 UPI:OCP & FS setting RT:Switching frequency setting:(Ton pin) Fsw=(Vin-0.5)/(2*Vin*432K*3.2p) =352Khz C D D Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2016/11/03 Deciphered Date 2017/01/06 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PWR_+NVVDD2 Size Document Number Rev 1.A DH53F M/B LA-F991P Date: Tuesday, February 13, 2018 Sheet 68 of 73 1 2 1 1 PC1557 22U_0603_6.3V6M PC1556 22U_0603_6.3V6M 2 PC1547 22U_0603_6.3V6M PC1555 22U_0603_6.3V6M 2 PC1554 22U_0603_6.3V6M 2 1 1 PC1553 22U_0603_6.3V6M 2 PC1552 22U_0603_6.3V6M 2 1 1 PC1546 22U_0603_6.3V6M 2 2 PC1571 10U_0603_6.3V6M PC1570 10U_0603_6.3V6M PC1569 10U_0603_6.3V6M PC1580 10U_0603_6.3V6M PC1575 10U_0603_6.3V6M PC1574 10U_0603_6.3V6M PC1573 10U_0603_6.3V6M PC1572 10U_0603_6.3V6M PC1568 10U_0603_6.3V6M PC1566 10U_0603_6.3V6M PC1565 10U_0603_6.3V6M PC1579 10U_0603_6.3V6M PC1578 10U_0603_6.3V6M PC1577 10U_0603_6.3V6M @ PC1567 10U_0603_6.3V6M PC1551 1U_0402_6.3V6K PC1550 1U_0402_6.3V6K PC1549 1U_0402_6.3V6K PC1576 10U_0603_6.3V6M 2 PC1629 22U_0603_6.3V6M PC1625 22U_0603_6.3V6M PC1624 22U_0603_6.3V6M PC1623 22U_0603_6.3V6M PC1622 10U_0603_6.3V6M PC1621 10U_0603_6.3V6M PC1620 10U_0603_6.3V6M PC1619 10U_0603_6.3V6M PC1543 1U_0402_6.3V6K PC1545 1U_0402_6.3V6K PC1544 1U_0402_6.3V6K PC1542 1U_0402_6.3V6K PC1541 1U_0402_6.3V6K PC1540 1U_0402_6.3V6K PC1539 1U_0402_6.3V6K PC1538 1U_0402_6.3V6K PC1537 1U_0402_6.3V6K PC1536 1U_0402_6.3V6K PC1535 1U_0402_6.3V6K PC1534 1U_0402_6.3V6K PC1533 1U_0402_6.3V6K PC1532 1U_0402_6.3V6K PC1548 1U_0402_6.3V6K 2 2 1 PC1615 1U_0402_6.3V6K PC1614 1U_0402_6.3V6K PC1613 1U_0402_6.3V6K PC1612 1U_0402_6.3V6K PC1611 1U_0402_6.3V6K PC1610 1U_0402_6.3V6K PC1530 1U_0402_6.3V6K PC1529 1U_0402_6.3V6K PC1528 1U_0402_6.3V6K PC1527 1U_0402_6.3V6K PC1526 1U_0402_6.3V6K PC1525 1U_0402_6.3V6K PC1524 1U_0402_6.3V6K PC1523 1U_0402_6.3V6K PC1522 1U_0402_6.3V6K PC1521 1U_0402_6.3V6K PC1520 1U_0402_6.3V6K PC1519 1U_0402_6.3V6K PC1518 1U_0402_6.3V6K PC1517 1U_0402_6.3V6K PC1531 1U_0402_6.3V6K PC1616 1U_0402_6.3V6K C PC1516 1U_0402_6.3V6K +NVVDD2 220uF X 560uF X 22uF_0603 X (unpop 2) 10uF_0603 X 1uF_0402 X 16 2 PC1609 1U_0402_6.3V6K PC1608 1U_0402_6.3V6K PC1607 1U_0402_6.3V6K PC1606 1U_0402_6.3V6K PC1605 1U_0402_6.3V6K PC1604 1U_0402_6.3V6K PC1603 1U_0402_6.3V6K PC1602 1U_0402_6.3V6K PC1601 1U_0402_6.3V6K PC1515 1U_0402_6.3V6K PC1514 1U_0402_6.3V6K PC1513 1U_0402_6.3V6K PC1512 1U_0402_6.3V6K PC1511 1U_0402_6.3V6K PC1510 1U_0402_6.3V6K PC1509 1U_0402_6.3V6K PC1508 1U_0402_6.3V6K PC1507 1U_0402_6.3V6K PC1506 1U_0402_6.3V6K PC1505 1U_0402_6.3V6K PC1504 1U_0402_6.3V6K PC1503 1U_0402_6.3V6K PC1502 1U_0402_6.3V6K PC1501 1U_0402_6.3V6K 73 of 69 Sheet Tuesday, February 13, 2018 Date: Rev 1.A Document Number Size PWR_VGA DECOUPLING DH53F M/B LA-F991P THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title 2017/01/06 Deciphered Date 2016/11/03 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification @ @ @ @ @ +NVVDD2 A A B +NVVDD2 220uF X 560uF X 47uF_0805 X 22uF_0603 X (unpop 2) 10uF_0603 X 1uF_0402 X 16 B PC1626 220U_D2 SX_2VY_R9M PC1627 220U_D2 SX_2VY_R9M PC1628 220U_D2 SX_2VY_R9M PC1592 220U_D2 SX_2VY_R9M @ +NVVDD1 220uF X 330uF X 560uF X 22uF_0603 X 10uF_0603X 11(unpop 5) 1uF_0402 X 49 D PC1593 330U_2.5V_ESR17M_6.3X4.5 PC1594 330U_2.5V_ESR17M_6.3X4.5 PC1591 220U_D2 SX_2VY_R9M PC1590 220U_D2 SX_2VY_R9M PC1589 220U_D2 SX_2VY_R9M PC1588 220U_D2 SX_2VY_R9M 2 D +NVVDD1 220uF X 560uF X 47uF_0805 X 22uF_0603 X 10uF_0603X 11(unpop 5) 1uF_0402 X 49 C 1 +NVVDD2 220uF X 560uF X 47uF_0805 X 22uF_0603 X 10uF_0603 X 4.7uF_0603 X 1uF_0402 X 16 +NVVDD1 + + + + + + + +NVVDD1 220uF X 560uF X 47uF_0805 X 22uF_0603 X 10uF_0603X 23 4.7uF_0603 X 1uF_0402 X 49 SF000006S00 SF-OS CON Cap Common + + + 1 1 1 +NVVDD2 Common part SGA0000BT00 Common part SGA0000BT00 +NVVDD1 5 Version change list (P.I.R List) Item Fixed Issue Page of for PWR Reason for change Down Size 0.1 02 Down Size & NVVDDS IC COLAY 0.1 C 03 0.1 CPU TEST B down size &CHANGE VGA IC 04 0.2 Unpop reduce charger IC loss extra circuit Unpop GPIO12& PROCHOT synchronous circuit 05 Modify List Rev PG# D 01 A 0.2 Date PQ311,PQ312: AON6366E 1N DFN5X6-8SB00001D800->AON7380_DFN3X3-8-5SB00001GM00 PC302,PC303,PC310,PC311,PC312: 10U_0603_25V6MSE00000X200->10U_0805_25V6KSE00000QK00 PC323: 10U_0603_25V6MSE00000X200->Del PC315,PC1312,PC1324,PC1362,PC1411: 680P_0603_50V7KSE025681K80->680P_0402_50V7KSE074681K80 10/26 PC412,PC426,PC602,PC7203,PC8311: 680P_0603_50V7KSE025681K80->680P_0402_50V7KSE074681K80Unpop PC102: 100P 50V J NPO 0603SE024101J80->100P 50V J NPO 0402SE071101J80 PC104: 1000P 50V K X7R 0603SE025102K80->1000P 50V K X7R 0402SE074102K80 PQ1401: AON6962_DFN5X6D-8-7SB00001ID00->Unpop PU1201 _UP9511PQGJ_VQFN40_5X5_SA00009SW00_->_UPI9511QQKI WQFN 32P _SA0000BK300 A 11/08 PC8317,PC509,PC517_1U_0402_10V6K_SE00000QL10_->_1U 6.3V K X5R 0201_SE00000YB00 PC8112,PC8115,PC8123,PC8139,PC8157,PC8161_1U_0402_25V6K_SE000010V00_->_1U 6.3V K X5R 0201_SE00000YB00 PQ307_ LMUN5113T1G PNP SOT323-3_SB000013X00_->_Unpop PQ308 _ LMUN5236T1G NPN SOT323-3_SB000011K00_->_Unpop PQ313 _2N7002KDW 2N SOT-363-6_SB00000EO00_->_Unpop A 11/15 PQ314_RUM001L02 1N VMT3_SB000012900_->_Unpop PR340 _10K_0402_1%_SD034100280_->_Unpop PR327 _0_0603_5%_SD013000080_->_Unpop PR326 _0_0603_5%_SD013000080_->_SMT PR310 _51.1K_0402_1%_SD034511280_->_52.3K_0402_1%_SD034523280 PC1709 _220U_D2 SX_2VY_R9M _SGA0000BT00_->_Unpop PC8147 _10U_0805_25V6K_SE00000QK00_->_Unpop Issued Date Compal Secret Data 2016/11/03 2017/06/14 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc Size Document Number Custom R ev 1.A DH53F M/B LA-F991P Tuesday, February 13, 2018 Sheet 70 of C B A PIR Date: D A PR1301,PR1302,PR1402: 0.005_2512_1%SD000016U00->0.005_1206_1%SD000017R00 PC1410: 0.1U_0603_16VSE026104K80->Del PR1432: Add->93.1K_0402_1%SD034931280 PR1410: 51.1K_0402_1%SD034511280->un pop PC1409: 1000P_0402_25V8JSE068102J80->un pop PU1401: UP1666QQKF_WQFN20_3X3SA00009SX00 -> RT8816AGQW_WQFN20_3X3 SA00009WE00 10/26 A PR1414: 10K_0402_5%SD028100280->0_0402_5%SD028000080 PR1418: 45.3K_0402_1%SD034453280->un pop PR1419: 84.5K_0402_1%SD034845280->Del PR1433: Add->2.2_0805_5%SD002220B80 PC1418: Add->1U_0603_25V6KSE000006900 PR1434: Add->432K_0402_1%SD034432380 PC8134: 0.1U_0402_50V7KSE074104K80->0.1U_0402_25V6SE00000G880 PU501 _RT8207PGQW_WQFN20_3X3 _-> _RT8207PGQW_WQFN20_3X3-S PH8103,PH8104_150K_0402_5%_B25/50 4500K_SL200002K00_->_S THERM_ 220K +-5% 0402 B25/50 4700K_SL200002I00 PR8110, PR8109 _8.87K_0402_1%_SD034887180_->_8.66K_0402_1%_SD034866180 PR8118, PR8119 _93.1K_0402_1%_SD034931280_->_57.6K_0402_1%_SD034576280 PC8113,PC8124,PC8140,PC8159,PC8163 _0.47U_0402_16V4Z_SE000002F80_->_0.47U_0402_6.3V6K_SE124474K80 PC8310 _0.47U_0402_25V6K_SE00000WA00_->_0.47U_0402_6.3V6K_SE124474K80 PR8114 _6.81K_0402_1%_SD034681180_->_5.76K_0402_1%_SD034576180 PR8113 _2.49K_0402_1%_SD034249180_->_1.8K_0402_1%_SD00000R580 PR8117 _560K_0402_1%_SD034560380_->_442K_0402_1%_SD034442300 PR8116 _510K_0402_1%_SD00000RK80_->_402K_0402_1% _SD034402380 PR8141 _100_0402_1%_SD034100080_->_8.2K_0402_1%_SD000004100 PR8149 _1.05K_0402_1%_SD00000J480_->_3.16K_0402_1%_SD000006580 PR8176 _20K_0402_1%_SD034200280_->_16.9K_0402_1%_SD034169280 PR8310 _63.4K_0402_1%_SD03463K280_->_59K_0402_1%_SD034590280 PR8319 _24.9K_0402_1%_SD034249280_->_22K_0402_1%_SD034220280 PR8325 _0_0402_5%_SD028000080_->_300_0402_1%_SD034300080 A 10/26 PR8328 _22K_0402_1%_SD034220280_->_20K_0402_1%_SD034200280 PR8333 _680_0402_1%_SD034680080_->_300_0402_1%_SD034300080 PC8312_270P_0402_50V7K_SE074271K80_->_330P_0402_50V8J_SE000006I80 PR8331 _470_0603_1%_SD014470080_->_576_0603_1%_SD014576080 PR8336 _42.2_0402_1%_SD00000ZN00_->_255_0402_1% _SD034255080 PC9110 PC9108 _22U_0603_6.3V6M_SE00000M000_->_unpop PC9112 PC9113_unpop _->_22U_0603_6.3V6M_SE00000M000 PC8126,PC8137 _330P_0402_25V8J_SE00000FD80_->_330P_0402_50V8J_SE000006I80 PR8134 _121K_0402_1%_SD034121380_->_13.3K_0402_1%_SD034133280 PR8138 _49.9K_0402_1%_SD034499280_->_26.7K_0402_1%_SD034267280 PR8147 _3.32K_0402_1%_SD034332180_->_768_0402_1% _SD00000TT80 PR8173 _0_0603_5%_SD013000080_->_10_0603_1%_SD014100A80 Security Classification Phase 73 Version change list (P.I.R List) Item Page of for PWR Fixed Issue 01 Rev 02 Date 1.0 material shortage 1.0 PC313,PC314_1U_0402_16V6K_SE00000OU00_->_1U 6.3V K X5R 0201_SE00000YB00 PC1303,PC1314,PC1353,PC8101,PC8122,PC8135,PC8150,PC8158 _0.1U_0603_50V7K_SE025104K80_->_0.1U 25V K X7R 0603_SE042104K80 PC305,PC324 _0.1U_0402_25V7K_SE00000W210_->_0.1U_0402_25V6_SE00000G880 Acer SW2 design reserve 1.0 03 1.0 For 4S per cell 4.35V battery charger boost cap to 0.47uF but material shortage so down size 04 Modify List PG# PR326,PR304,PR314,PR316,PR317,PR322,PR333,PR334,PR8111,PR8120,PR8128,PR8129,PR8139,PR8142, PR8143,PR8153,PR8154,PR8155,PR8163,PR8165,PR8170,PR8175,PR8184,PR8190,PR8198,PR8204,PR8308, PR8339,PR8341,PR8342,PR8346,PR8326,PR1414_SD028000080 chage to _R-Short 0402 12/17 PR326 0_0603_5%_SD013000080 ->R-Short 0603_SD013000080 0ohm ->R-Short D 1.0 PR217 0_0402_5%_SD028000080(unpop) -> SMT 0402_SD028000080 PQ307 _LMUN5113T1G_SOT323-3_SB000013X00_->del PR327unpop_0_0603_5%_SD013000080_->del PR342Add _->_2M_0402_1%_SD034200480 PR343Add _100K_0402_1%_SD034100380 PQ315Add _2N7002KW_SOT323-3_SB00000ST00 Phase A.2 12/17 A.2 12/17 A.2 12/20 A.2 12/21 A.2 D PC309 _0.22U_0603_25V7K_SE000005Z80_->_0.47U_0402_16V4Z_SE000002F80 C C ACDET change 05 1.0 PR306 _392K_0402_1%_SD034392380_->_499K_0402_1%_SD034499380 PR310 _52.3K_0402_1%_SD034523280_->_66.5K_0402_1%_SD034665280 A.2 12/28 B B A A Compal Secret Data Security Classification Issued Date 2016/11/03 2017/06/14 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom R ev 1.A DH53F M/B LA-F991P Date: Compal Electronics, Inc PIR Tuesday, February 13, 2018 Sheet 71 of 73 A B C D Version change list (P.I.R List) Item 1 Page Title 46 19,36 41 42 48 11 43 Page of for HW Phase Rev Correct USB charger connection 1.Change RS15 connection to CHG_ILMSEL DVT 0.2 10/18 Placement 1.Remove RPH10, add RH197,RH198 2.UG27 source change to +1.8VALW for +1.8VSDGPU_AON/+1.8VSDGPU_MAIN DVT 0.2 10/18 For CNVI power rail 1.Co-lay RM46 for CNVI +3VALW power rail DVT 0.2 10/18 X1 code issue 1.LA1 change to SM01000NS00 DVT 0.2 10/18 redriver verify 1.Add one USB3.0 port to JIO3 DVT 0.2 Placement 10/21 Placement Change RM36,RM37,RM42,RM43 to 0402 size Change RH186,RH47,RH98~RH100,RH103,RH105,RD2,RD3,RD6,RD13,RD15,RD17,RM34,RM35 ,RM38,RM39,RS1,R19,R20,RQ5,RQ6,RQ9 to R-short Change RS8,RS10 to 1206 R-short Change RH97 to 0805 R-short DVT 0.2 ESD cap 10/21 Sourcer request 1.Change CC66,CC68 to SE074102K80 DVT 0.2 10/21 EC board ID 1.Change RB3 to 12kohm/28P@ and 160kohm/32P@ DVT 0.2 10/24 Sourcer request Change CA6,CA8,CA9,CA12,CA14,CA16,CA19,CC71~CC81,CC88~CC90,CG130,CG131 ,CG143~CG145,CG168,CG169,CG178~CG181,CG193,CG205~CG207,CG229,CG230,CG241,CG243 ,CG253~CG255,CG267~CG269,CG291,CG292,CG303~CG305,CX1,CX3 from 0402 to 0603 size DVT 0.2 USB Placement CNVI Material USB EC Date 10/18 Issue Description E Cap Solution Description 10 50 Screw hole 10/25 Screw hole 1.Change H21 footprint to H_6P0 DVT 0.2 11 48 USB EMI 10/25 EMI issue 1.Add LS11,LS12 DVT 0.2 12 41,43 CNVI 10/26 For CNVI power rail detect 1.Add net CNVI_DET#,RB78,RB79 DVT 0.2 13 46 USB 10/26 Correct USB charger connection 1.Correct USB2.0 connection for US12 DVT 0.2 14 42 DMIC 10/26 Acer request 1.Change JDMIC1 from 8pin to 4pin DVT 0.2 15 47 SATA 11/03 Co-layout 1.Co-lay JHDD3,CO14~CO17,RO21~EO24 DVT 0.2 16 44 SMBus 11/08 Co-layout 1.Co-lay RS114,RS115 DVT 0.2 17 49 SW 11/14 Remove debug SW 1.De-pop SW1 DVT 0.2 18 44 Type-C 11/14 CC logic control by EC SMBus 1.De-pop QS1,QS3,RS107,RS108,RS111 Pop RS114,RS115 DVT 0.2 19 16 Cap 11/14 by crystal vendor test result 1.Change CH7,CH8 to 10pF DVT 0.2 20 45 Cap 11/16 For shortage 1.Change CS84~CS87 to SE00000G880 DVT 0.2 21 43 CNVI 11/16 CNVI detect by SW 1.De-pop RB78 Pop RB79 DVT 0.2 22 43 CNVI 12/15 Remove CNVI detect 1.Remove RB78, RB79 and netname CNVI_DET# PVT 1.0 23 18 PECI 12/15 For PECI issue 1.De-pop RH41 PVT 1.0 24 50 BI SW 12/15 By customer request 1.De-pop SW2 PVT 1.0 25 43 EC 12/15 Update EC board ID 1.Change RB3 to 15kohm/28P@ and 200kohm/32P@ PVT 1.0 26 42 Inductor 12/15 Change source 1.Change LA1 to SM01000EE00 PVT 1.0 NPI 12/15 For NPI test 1.Change RB19,RC17,RG143,RG200,RG202,RH101,RH102,RH5,RH6,RH92,RH93,RH94,RH96 ,RM2,RS114,RS115,RB72,RB76,RL1,RL13,RQ2 to R-short PVT 1.0 4 27 Compal Secret Data Security Classification Issued Date 2016/07/18 Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom B C D R ev 1.A DH53F M/B LA-F991P Date: A Compal Electronics, Inc PIR-HW1 Tuesday, February 13, 2018 Sheet E 72 of 73 A B C D Version change list (P.I.R List) Item Page Title E Page of for HW Phase Rev 28 44 Type-C 12/18 Date Change current limit solution Issue Description 1.Change US2 to SA00006Y700 2.Add RS116,RS117,RS118 Reserve CS101 Solution Description PVT 1.0 29 43 EC 12/20 For PWR BATT_4S 1.Add net BATT_4S to EC pin89 PVT 1.0 30 41 WLAN 12/20 For CNVi BT_ON 1.Add RM47 PVT 1.0 31 21 PCH 12/20 For intel sensitive net 1.Pop CH29,CH34,CS100 PVT 1.0 32 45 Type-C 12/21 For intel new topology 1.Change RS64,RS65,RS74,RS76,RS82~RS85 to 0201 size 2.Add CS102~CS105,RS119~RS122 PVT 1.0 33 36 GPU 12/21 Fine tune GPU sequence 1.Change CG315 to 0.22uF, RG190 to 16.9k ohm, add RG225 PVT 1.0 34 20 12/28 For MB ID 1.De-pop RH86 Pop RH85,RH87 PVT 1.0 35 7,15 CPU,PCH 12/28 Update intel chip to QS PN 1.SA0000BPJ10 for i5@, SA0000BPI10 for i7@, SA0000BPF10 for PCH@ PVT 1.0 36 DAZ 12/28 Update MB DAZ PN 1.DAZ29000100 for PCB@ PVT 1.0 37 37 eDP 12/28 For eDP sequence 1.Pop RX1 PVT 1.0 38 18,39 PCIE 01/11 For IRST support issue 1.Change 2.Change 3.Change 4.Change PVT 1.C 39 45 Type-C 01/11 For intel new topology 1.Place CS58~CS61 close to connector and change net name PVT 1.C 40 43 EC 01/11 Update EC board ID 1.Change RB3 to 20kohm/28P@ and 240kohm/32P@ PVT 1.C 41 21 PCH 01/12 For layout routing 1.Change RH93 to 0ohm footprint PVT 1.C 42 45 Type-C 01/16 For intel new topology 1.Change CS58~CS61 to 0.22uF PVT 1.C 43 CPU,DAZ 01/27 Update CPU,DAZ PN 1.SA0000BPZ10 for i7@, DAZ29000103 for PCB@ PVT 1.C 44 7,15 CPU,PCH 02/13 Update CPU,PCH PN to MP PN 1.SA0000BPJ40 for i5@,SA0000BPZ40 for i7@,SA0000BVP10 for PCH@ Pre-MP 1.C PCIE port17~20 to port 9~12 for PCIE SSD SATA port0A to port4 for SATA HDD SSD_DEVSLP4 to SSD_DEVSLP1 SATA_GP4 to SATA_GP1 3 4 Compal Secret Data Security Classification Issued Date 2016/07/18 Deciphered Date 2016/11/10 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size Document Number Custom B C D R ev 1.A DH53F M/B LA-F991P Date: A Compal Electronics, Inc PIR-HW2 Tuesday, February 13, 2018 Sheet E 73 of 73 ... VCC98 VCC99 VCC100 VCC1 01 VCC102 VCC103 VCC104 VCC105 VCC106 VCC107 VCC108 VCC109 VCC 110 VCC 111 VCC 112 VCC 113 VCC 114 VCC 115 VCC 116 VCC 117 VCC 118 VCC 119 VCC120 VCC1 21 VCC122 VCC123 VCC124 OF 13 CFL-H_BGA1440... VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC 11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC 21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC 31 VCC32 VCC33 VCC34... VCCGT98 VCCGT99 VCCGT100 VCCGT1 01 VCCGT102 VCCGT103 VCCGT104 VCCGT105 VCCGT106 VCCGT107 VCCGT108 VCCGT109 VCCGT 110 VCCGT 111 VCCGT 112 VCCGT 113 VCCGT 114 VCCGT 115 VCCGT 116 VCCGT 117 VCCGT 118 VCCGT 119