A B C D E COMPAL CONFIDENTIAL MODEL NAME : ZAM81 PCB NO : LA-A913P BOM P/N : GPIO MAP: 3.1 Huston 15" DSC 2 Broadwell U 2013‐08‐20 REV : 0.1 (X00) @ : Nopop Component EMC@ : EMI, ESD and RF Component @EMC@ : EMI, ESD and RF Nopop Component XDP@ : XDP Component CONN@ : Connector Component 3 4 MB PCB Part Number Description DAA0007Y000 PCB 13N LA-A913P REV0 MB DSC DOCK DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT A B C D Title SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet E of 56 A B C D E Reverse Type Houston15 DSC Block Diagram VRAM DDR3 DDR3L-DIMM X2 BANK 0, 1, 2, NVIDIA Graphics N15S-GT/GM PAGE40~44 PAGE45~46 Memory BUS (DDR3L) PCIe x 4 PAGE 18 19 1333/1600MHz 1 USB2.0[4] eDP CONN Dual Lane eDP1.3 PAGE 23 PAGE 23 USB2.0[5] INTEL HDMI HDMI CONN HDMI Level Shifter PS8401A PAGE 24 PAGE 24 DDI1 USB2.0[1] BROADWELL ULT VGA PI3V713 PAGE 26 IDT VMM2320 VGA VGA SW PAGE 22 PAGE 26 USB POWER SHARE DOCKING USB2.0[3] DDI2 PAGE 25 USB2.0 SW NX3DV221GM USB2.0&3.0 SW USB3.0[1] PI3USB3102ZLEX DP PAGE 31 DP CONN PAGE 6~17 SD4.0 O2 Micro OZ777FJ2LN PAGE 29 PAGE 29 USB3.0/2.0 HD Audio I/F PCIE3 PCIE4 SATA2 HDA Codec ALC3235 WWAN/LTE PAGE 28 WLAN/BT/ WIGIG PAGE 30 PAGE 30 USB2.0[7] Transformer On Audio/B Trough eDP Cable PAGE 21 PAGE 7 LID switch SATA REPEATER PI3EQX6741STZDEX PAGE 39 SATA3 Conn PAGE 20 PAGE 20 USH CONN PAGE 27 PAGE 27 PAGE 35 CPU XDP Port PAGE 9 BC BUS Automatic Power Switch (APS)PAGE 9 KB/TP CONN SMSC KBC MEC5085 PAGE 37 FAN CONN PAGE 36 RJ45 PAGE 21 Single DMIC Discrete TPM AT97SC3205 USB2.0[2] WIGIG_DP PAGE 28 SMSC SIO ECE5048 Dig MIC 64M 4K sector W25Q32BVSSIQ Intel Clarkville I218LM PAGE 31 Universal Jack PAGE 21 W25Q64CVSSIQ PCIE6_0 USB3.0[2] PAGE 31 INT.Speaker SATA1 PCI Express BUS USB3.0 Redriver PS8713B PAGE 32 PAGE 21 32M 4K sector SW_USB2.0[0] SW_USB3.0[1] SPI DAI LAN SATA1 DOCK_USB2.0[0] DOCK_USB2.0[5] DOCK_USB3.0[3] PCIE1 LPC PAGE 27 USB3.0/2.0 DOCK_USB3.0[1] Trough eDP Cable USB3.0/2.0 PS PAGE 32 SW_USB2.0[3] USB3.0[4] PAGE 31 USB2.0[0] Card reader USB2.0[1]_PS PAGE 32 WIGIG_DP VGA PS8338B DP Sw DP Camera PAGE 23 TPS2544 USB VGA CONN LCD Touch Free Fall sensor PAGE 20 PAGE 36 PAGE 28 DC/DC Interface PAGE 38 Smart Card RFID Power On/Off SW & LED PAGE 39 USH BCM5882 TDA8034HN DELL CONFIDENTIAL/PROPRIETARY Fingerprint CONN FP_USB PAGE 29 A Compal Electronics, Inc USB2.0[6] PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT USH board B C D Title SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet E of 56 POWER STATES Signal SLP S3# SLP S4# SLP S5# SLP A# M PLANE SUS PLANE RUN PLANE S0 (Full ON) / M0 HIGH HIGH HIGH HIGH ON ON ON ON ON S3 (Suspend to RAM) / M3 LOW HIGH HIGH HIGH ON ON ON OFF OFF S4 (Suspend to DISK) / M3 LOW LOW HIGH HIGH ON ON OFF OFF OFF S5 (SOFT OFF) / M3 LOW LOW LOW HIGH ON ON OFF OFF OFF S3 (Suspend to RAM) / M-OFF LOW HIGH HIGH LOW ON OFF ON OFF OFF S4 (Suspend to DISK) / M-OFF LOW LOW HIGH LOW ON OFF OFF OFF OFF S5 (SOFT OFF) / M-OFF LOW LOW LOW LOW ON OFF OFF OFF OFF State D C ALWAYS PLANE PCIE CLOCKS USB3.0 power plane +3.3V_SUS +5V_RUN +3.3V_M +3.3V_M +3.3V_ALW +1.35V_MEM +3.3V_RUN +1.05V_M +1.05V_M +3.3V_ALW_PCH +0.675V_DDR_VTT +3.3V_RTC_LDO +1.05V_RUN DESTINATION USB3.0 JUSB1 >Rear left USB3.0 JUSB3 >Right PCIE USB3.0 MMI (CARD READER) PCIE USB3.0 JUSB2 >Rear Right PCIE LOM PCIE WLAN PCIE GPU/WIGIG PCIE PM TABLE +5V_ALW SATA (M-OFF) SATA WIGI/Express SATA mSATA/PCIE SATA HDD SATA DOCK D C +VCC_CORE DESTINATION USB PORT# State B S0 ON ON ON ON ON S3 ON ON OFF ON OFF S5 S4/AC ON OFF OFF ON OFF S5 S4/AC doesn't exist OFF OFF OFF OFF OFF BDW ULT need to update Power Status and PM Table USH JUSB1 JUSB3 WLAN + BT JUSB2 Touch Screen CAMERA USH WWAN BIO NA B A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Title SCHEMATICS,MB AA913 Size Document Number Rev A 4019RA Date: Thursday, November 14, 2013 Sheet of 56 RUN_ON MPHYP_PWR_EN TPS22965 (UZ7) SI3456 (QZ6) D D EN_INVPWR ADAPTER FDC654P (QV1) +BL_PWR_SRC +1.05V_RUN A_ON +1.05V_MODPHY SY8208DQNC +1.05V_M (PU300) +1.05V_PEX_VDD 3V3_MAIN_EN BATTERY +PWR_SRC 3V3_MAIN_EN TPS22965 (UV15) RT8813 +3.3V_RUN_GFX +GPU_CORE (PU600) ALWON TPS51285 (PU100) +5V_ALW C C CHARGER TPS51622 (PU500) H_VR_EN TPS22966 (UZ3) TPS22966 (UZ2) APL3512 (UV24) RUN_ON RUN_ON EN_LCDPWR 3.3V_WWAN_EN SIO_SLP_LAN# SUS_ON AUX_EN_WOWL TPS22966 (UZ8) USB_PWR_SHR_EN# USB_PWR_EN1# TPS2544 (UI3) TPS22966 (UZ9) USB_PWR_EN2# G547I2P81U (UI1) G547I2P81U (UI2) +1.35V_MEM DGPU_PWR_ON SI416 (QV83) +3.3V_M +0.675V_DDR_VTT +3.3V_WLAN +3.3V_ALW_PCH A +3.3V_LAN +3.3V_SUS +LCDVDD +3.3V_WWAN +3.3V_CAM +3.3V_RUN +5V_RUN 3.3V_CAM_EN# +VCC_CORE 0.675V_DDR_VTT_ON B SUS_ON B RT8207 (PU200) PCH_ALW_ON A_ON +3.3V_ALW LP2301ALT1G (QZ1) +5V_USB_CHG_PWR LP2301ALT1G (QV8) 3.3V_TS_EN DGPU_PWR_EN +USB_LEFT_PWR LP2301ALT1G (QV86) +USB_RIGHT_PWR +5V_TS +3.3V_GFX_AON A DELL CONFIDENTIAL/PROPRIETARY +1.35V_MEM_GFX Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Title SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet of 56 2.2K SMBUS Address [0x9a] +3.3V_ALW_PCH 2.2K AP2 MEM_SMBCLK AH1 MEM_SMBDATA 202 2N7002 DIMMA 200 2N7002 1K 202 BDW D +3.3V_ALW_PCH 1K AN1 AH3 AU3 31 LOM 53 SML1_SMBCLK 3A 28 SML0DATA AK1 SML1_SMBDATA A5 SML0CLK 2.2K XDP 51 2.2K +3.3V_ALW_PCH B6 10K 2.2K 2.2K +3.3V_ALW B4 DOCK_SMB_CLK 127 A3 DOCK_SMB_DAT 129 1A +3.3V_RUN 10K 3A 1A D DIMMB 200 G Sensor DOCKING C C 1B 1B 2.2K KBC 2.2K 1C 1C A56 B59 +3.3V_ALW 100 ohm PBAT_SMBCLK PBAT_SMBDAT BATTERY CONN 100 ohm 2.2K 2.2K A50 MEC 5085 1E B53 1E +3.3V_SUS M9 USH_SMBCLK L9 USH_SMBDAT USH B B 2B 2B 10K 10K B50 1G A47 1G +3.3V_ALW 11 CHARGER_SMBCLK 12 CHARGER_SMBDAT Charger 2D A A 2D 2.2K 2.2K 2A 2A B48 B49 DELL CONFIDENTIAL/PROPRIETARY +3.3V_RUN Compal Electronics, Inc D8 GPU_SMBDAT D9 GPU_SMBCLK GPU PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Title SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet of 56 DSC SATA port Service Mode Switch: Add a switch to ME_FWP signal to unlock the ME region and allow the entire region of the SPI flash to be updated using FPT +3.3V_ALW_PCH RC2 1K_0402_5% SW1 ME_FWP_EC ME_FWP 3 G2 G1 SATA1 PCB E-Dock HDD H12 UMA NA HDD H12 Entry E-Dock HDD H14 DSC M2 3042 SATA-Cache(no HCA) E-Dock HDD H14 UMA M2 3042 2nd PCIe Lane for PCIe Cache NA HDD H14D_En NA NA HDD H14U_En NA E-Dock HDD H15 DSC M2 3042 SATA-Cache(no HCA) E-Dock HDD H15 UMA M2 3042 2nd PCIe Lane for PCIe Cache NA HDD H15D_En NA NA HDD H15U_En NA SATA2/PCIE6 L1 SATA3/PCIE6 L0 ME_FWP PCH has internal 20K PD RC1 330K_0402_5% FLASH DESCRIPTOR SECURITY OVERRIDE ME_FWP=LOW → ENABLE ME (DEFAULT) ‐‐> Pin1 & Pin3 short =HIGH → DISABLE ME (ME can update) ‐‐> Pin2 & Pin3 short PCH_INTVRMEN INTVRMEN ‐ INTEGRATED SUS 1.05V VRM ENABLE High ‐ Enable Internal VRs Low ‐ Enable External VRs CC1 2 0_0402_5% @ RC4 YC1 32.768KHZ_12.5PF_Q13FC135000040 2 RC9 CC2 NA RC10 RC8 NA SATA2/PCIE6_L1 contact to WWAN M2 3030 WIGIG SATA3/PCIE6 L0 contact to WLAN M2 3042 (HCA & SATA-Cache) 2 20K_0402_5% 20K_0402_5% SATA_RN1/PERN6_L2 SATA_RP1/PERP6_L2 SATA_TN1/PETN6_L2 SATA_TP1/PETP6_L2 PCH_AZ_CODEC_SDIN0 ME_FWP RC11 PCH_AZ_BITCLK PCH_AZ_SYNC PCH_AZ_RST# PCH_AZ_CODEC_SDIN0 PCH_AZ_SDOUT 1K_0402_5% CMOS place near DIMM TPM setting CMOS_CLR1 Shunt Clear ME RTC Registers Shunt Clear CMOS Keep ME RTC Registers Open Keep CMOS +1.05V_M PCH_JTAG_TDI 51_0402_5% PCH_JTAG_TDO 51_0402_5% PCH_JTAG_TMS 51_0402_5% PCH_JTAG_JTAGX 1K_0402_1% RC15 RC16 @ RC18 @ RC21 AW8 AV11 AU8 AY10 AU12 AU11 AW10 AV10 AY8 CMOS setting Open SATA_RN0/PERN6_L3 SATA_RP0/PERP6_L3 SATA_TN0/PETN6_L3 SATA_TP0/PETP6_L3 RTC @ CMOS1 SHORT PADS~D 1U_0402_6.3V6K RC14 RTCX1 RTCX2 INTRUDER INTVRMEN SRTCRST RTCRST PCH_RTCRST# CC4 ME_CLR1 AW5 AY5 AU6 AV7 AV6 AU7 1U_0402_6.3V6K D contact to WWAN M2 3030 WIGIG contact to WLAN NA SATA2/PCIE6_L1 contact to WWAN M2 3030 WIGIG SATA3/PCIE6 L0 contact to WLAN M2 3042 (HCA & SATA-Cache) contact to WWAN M2 3030 WIGIG contact to WLAN contact to Express card Express card BDW_ULT_DDR3L UC1E INTRUDER# PCH_INTVRMEN SRTCRST# PCH_RTCRST# 18P_0402_50V8J contact to WWAN C PCH_RTCX2 1M_0402_5% CC3 B M2 3042 (HCA & SATA-Cache) PCH_RTCX1 18P_0402_50V8J +RTC_CELL PCH_RTCX1_R RC7 10M_0402_5% C M2 3042 2nd PCIe Lane for PCIe Cache SS3-CMFTQR9_3P +RTC_CELL SATA0 D PCH_JTAG_TRST# PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS PCH_JTAG_JTAGX PCH_JTAG_TRST# PCH_JTAG_TCK PCH_JTAG_TDI PCH_JTAG_TDO PCH_JTAG_TMS AU62 AE62 AD61 AE61 AD62 AL11 AC4 AE63 AV2 HDA_BCLK/I2S0_SCLK HDA_SYNC/I2S0_SFRM HDA_RST/I2S_MCLK AUDIO HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD HDA_SDO/I2S0_TXD HDA_DOCK_EN/I2S1_TXD HDA_DOCK_RST/I2S1_SFRM I2S1_SCLK SATA SATA_RN2/PERN6_L1 SATA_RP2/PERP6_L1 SATA_TN2/PETN6_L1 SATA_TP2/PETP6_L1 SATA_RN3/PERN6_L0 SATA_RP3/PERP6_L0 SATA_TN3/PETN6_L0 SATA_TP3/PETP6_L0 SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37 PCH_TRST PCH_TCK PCH_TDI PCH_TDO PCH_TMS RSVD RSVD JTAGX RSVD JTAG SATA_IREF RSVD RSVD SATA_RCOMP SATALED J5 H5 B15 A15 SATA_PRX_DKTX_N0_C SATA_PRX_DKTX_P0_C SATA_PTX_DKRX_N0_C SATA_PTX_DKRX_P0_C J8 H8 A17 B17 SATA_PRX_DTX_N1 SATA_PRX_DTX_P1 SATA_PTX_DRX_N1 SATA_PTX_DRX_P1 J6 H6 B14 C15 PCIE_PRX_SATATX_N6_L1 PCIE_PRX_SATATX_P6_L1 PCIE_PTX_SATARX_N6_L1 PCIE_PTX_SATARX_P6_L1 F5 E5 C17 D17 PCIE_PRX_WIGIGTX_N6_L0 PCIE_PRX_WIGIGTX_P6_L0 PCIE_PTX_WIGIGRX_N6_L0 PCIE_PTX_WIGIGRX_P6_L0 V1 U1 HDD_DET# V6 SATA2_PCIE6_L1 AC1mCARD_PCIE#_SATA A12 L11 K10 C12 U3 for DOCK SATA HDD for SATA‐CACHE (WWAN) for WIGIG (WLAN) MPCIE_RST# HDD_DET# SATA2_PCIE6_L1 mCARD_PCIE#_SATA B +PCH_ASATA3PLL SATA_COMP SATA_ACT# SATA_ACT# +3.3V_RUN RPC18 MMICLK_REQ# WIGIGCLK_REQ# PCH_GPIO52 10K_8P4R_5% BDW-ULT-DDR3L_BGA1168 OF 19 PCH_JTAG_TCK 51_0402_5% SATA Impedance Compensation +PCH_ASATA3PLL SATA_COMP 3.01K_0402_1% HDA for Codec CAD note: Place the resistor within 500 mils of the PCH. Avoid routing next to clock pins PCH_AZ_SDOUT 33_0402_5% PCH_AZ_SYNC RC20 33_0402_5% PCH_AZ_RST# RC22 33_0402_5% EMC@ PCH_AZ_BITCLK RC23 33_0402_5% RC19 PCH_AZ_CODEC_SYNC PCH_AZ_CODEC_RST# PCH_AZ_CODEC_BITCLK A CC5 @EMC@ 27P_0402_50V8J A PCH_AZ_CODEC_SDOUT DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Reserve for EMI RC17 Title SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet of 56 +3.3V_RUN +3.3V_ALW_PCH BDW_ULT_DDR3L LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3 LPC_LFRAME# PCH_SPI_CLK PCH_SPI_CS0# PCH_SPI_CS1# PCH_SPI_CS2# PCH_SPI_DO PCH_SPI_DIN PCH_SPI_DO2 PCH_SPI_DO3 PCH_SPI_CLK D AU14 AW12 AY12 AW11 AV12 PCH_SPI_CS2# PCH_SPI_DO PCH_SPI_DIN AA3 Y7 Y4 AC2 AA2 AA4 Y6 AF1 LAD0 LAD1 LAD2 LAD3 LFRAME LPC SMBUS SPI_CLK SPI_CS0 SPI_CS1 SPI_CS2 SPI_MOSI SPI_MISO SPI_IO2 SPI_IO3 SPI SMBALERT/GPIO11 SMBCLK SMBDATA SML0ALERT/GPIO60 SML0CLK SML0DATA SML1ALERT/PCHHOT/GPIO73 SML1CLK/GPIO75 SML1DATA/GPIO74 CL_CLK CL_DATA CL_RST C-LINK AN2 AP2 AH1 AL2 AN1 AK1 AU4 AU3 AH3 AF2 AD2 AF4 MEM_SMBCLK MEM_SMBDATA PCH_SMB_ALERT# MEM_SMBCLK SML0_SMBCLK SML0_SMBDATA SML1_SMBCLK SML1_SMBDATA SML0_SMBCLK SML0_SMBDATA PCH_GPIO73 SML1_SMBCLK SML1_SMBDATA PCH_CL_CLK1 PCH_CL_DATA1 PCH_CL_RST1# UC1G RPC14 DDR_XDP_WAN_SMBCLK SML1_SMBCLK MEM_SMBCLK MEM_SMBDATA SML1_SMBDATA QC1A DMN66D0LDW-7_SOT363-6 2.2K_0804_8P4R_5% MEM_SMBDATA DDR_XDP_WAN_SMBDAT SML0_SMBCLK 1K_0402_5% SML0_SMBDATA 1K_0402_5% QC1B DMN66D0LDW-7_SOT363-6 PCH_CL_CLK1 PCH_CL_DATA1 PCH_CL_RST1# 2 RC33 D RC34 +3.3V_SPI BDW-ULT-DDR3L_BGA1168 OF 19 64Mb Flash ROM SOFTWARE TAA SPI_CLK32 UC2 SPI_PCH_CS0# RC35 0_0402_5% SPI_PCH_DO2 RC38 33_0402_5% SPI_PCH_CS0#_R SPI_DIN64 SPI_PCH_DO2_64 2 2 @EMC@ @EMC@ CC10 RC62 33P_0402_50V8J 33_0402_5% @EMC@ @EMC@ CC9 RC61 33P_0402_50V8J 33_0402_5% SPI_PCH_DIN SPI_PCH_DO SPI_PCH_CLK SPI_PCH_DO3 1 SPI_PCH_DO2 1K_0402_5% SPI_PCH_DO3 1K_0402_5% RC29 RC31 VCC /HOLD(IO3) CLK DI(IO0) SPI_PCH_DO3_64 SPI_CLK64 SPI_DO64 W25Q64FVSSIQ_SO8 RPC11 C /CS DO(IO1) /WP(IO2) GND SPI_CLK64 +3.3V_SPI CC6 0.1U_0402_25V6 SPI_DIN64 SPI_DO64 SPI_CLK64 SPI_PCH_DO3_64 +3.3V_SPI 32Mb Flash ROM 33_0804_8P4R_5% CC7 0.1U_0402_25V6 UC3 RPC12 SPI_PCH_DO3 SPI_PCH_CLK SPI_PCH_DO SPI_PCH_DIN SPI_PCH_CS1# RC50 0_0402_5% SPI_PCH_DO2 RC55 33_0402_5% SPI_PCH_CS1#_R SPI_DIN32 SPI_PCH_DO2_32 SPI_PCH_DO3_32 SPI_CLK32 SPI_DO32 SPI_DIN32 /CS DO/IO1 /WP/IO2 GND VCC /HOLD/IO3 CLK DI/IO0 SPI_PCH_DO3_32 SPI_CLK32 SPI_DO32 W25Q32FVSSIQ_SO8 C 33_0804_8P4R_5% @EMC@ CC13 MMI ‐‐‐> Reserve for EMI CLK_PCIE_MMI# CLK_PCIE_MMI MMICLK_REQ# +3.3V_RUN +3.3V_RUN 10/100/1G LAN ‐‐‐> WLAN (NGFF1)‐‐‐> RPC6 LANCLK_REQ# mCARD_PCIE#_SATA MPCIE_RST# HDD_DET# GPU‐‐‐> WGIG‐‐‐> B PCIE1 H12 UMA SD card PCIE2 PCIE3 PCIE4 PCIE5 WLAN WIGIG NA LOM RC66 MMICLK_REQ# 10K_0402_5% CLK_PCIE_LAN# CLK_PCIE_LAN LANCLK_REQ# CLK_PCIE_WLAN# CLK_PCIE_WLAN WLANCLK_REQ# 10K_8P4R_5% PCB BDW_ULT_DDR3L UC1F CLK_PCIE_GFX# CLK_PCIE_GFX GFXCLK_REQ# +3.3V_RUN CLK_PCIE_WIGIG# CLK_PCIE_WIGIG WIGIGCLK_REQ# PCIE6 M2 3042 (HCA & SATA-Cache) H12 Entry SD card NA LOM WLAN WIGIG NA H14 DSC SD card NA LOM WLAN GPU WIGIG H14 UMA SD card NA LOM WLAN WIGIG M2 3042 (HCA & SATA-Cache) PCH_GPIO19 C43 C42 U2 B41 A41 Y5 LANCLK_REQ# C41 B42 AD1 WLANCLK_REQ# B38 C37 N1 A39 B39 U5 RC68 10K_0402_5% WIGIGCLK_REQ# B37 A37 T2 CLKOUT_PCIE_N0 CLKOUT_PCIE_P0 PCIECLKRQ0/GPIO18 XTAL24_IN XTAL24_OUT RSVD RSVD DIFFCLK_BIASREF CLKOUT_PCIE_N1 CLKOUT_PCIE_P1 PCIECLKRQ1/GPIO19 TESTLOW_C35 TESTLOW_C34 TESTLOW_AK8 TESTLOW_AL8 CLOCK CLKOUT_PCIE_N2 CLKOUT_PCIE_P2 PCIECLKRQ2/GPIO20 SIGNALS CLKOUT_PCIE_N3 CLKOUT_PCIE_P3 PCIECLKRQ3/GPIO21 CLKOUT_LPC_0 CLKOUT_LPC_1 CLKOUT_ITPXDP CLKOUT_ITPXDP_P CLKOUT_PCIE_N4 CLKOUT_PCIE_P4 PCIECLKRQ4/GPIO22 WLAN GPU WIGIG H14U_En SD card NA LOM WLAN WIGIG NA H15 DSC SD card NA LOM WLAN GPU WIGIG H15 UMA SD card NA LOM WLAN WIGIG M2 3042 (HCA & SATA-Cache) K21 M21 C26 CLK_BIASREF C35 C34 AK8 AL8 MCP_TESTLOW1 MCP_TESTLOW2 MCP_TESTLOW3 MCP_TESTLOW4 AN15 AP15 PCI_CLK_LPC_0 PCI_CLK_LPC_1 RC72 22_0402_5% H15U_En SD card NA NA LOM LOM WLAN WLAN GPU WIGIG EMC@ RC74 22_0402_5% PCI_CLK_LPC_1 EMC@ RC67 22_0402_5% EMC@ RC70 22_0402_5% CLK_PCI_SIO CLK_PCI_MEC CLK_PCI_LPDEBUG CLK_PCI_DOCK 1 1 2 2 RC240 RC241 RC242 RC243 RC69 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% LPC_0 LPC_1 SIO DOCK MEC DEBUG JSPI1 RC224 RC225 RC226 RC227 RC228 RC229 RC230 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 10 11 12 13 14 15 16 17 18 19 20 SPI_PCH_CS1# PCH_SPI_CS1# SPI_PCH_DO PCH_SPI_DO SPI_PCH_DIN PCH_SPI_DIN SPI_PCH_CLK PCH_SPI_CLK SPI_PCH_CS0# PCH_SPI_CS0# SPI_PCH_DO2 PCH_SPI_DO2 SPI_PCH_DO3 PCH_SPI_DO3 +3.3V_SPI RC231 0_0402_5% 21 22 10 11 12 13 14 15 16 17 18 19 20 GND1 GND2 TYCO_2-2041070-0 CONN@ WIGIG Express card MCP_TESTLOW1 MCP_TESTLOW2 MCP_TESTLOW3 MCP_TESTLOW4 B35 A35 +3.3V_M H15D_En SD card +PCH_VCCACLKPLL CLK_BIASREF 3.01K_0402_1% support SPI TPM A CC11 2 XTAL24_OUT_R 0_0402_5% 18P_0402_50V8J BDW-ULT-DDR3L_BGA1168 OF 19 PCI_CLK_LPC_0 EMC@ LOM @ RC65 B NA XTAL24_IN XTAL24_OUT YC2 24MHZ_12PF_X3G024000DC1H CLKOUT_PCIE_N5 CLKOUT_PCIE_P5 PCIECLKRQ5/GPIO23 H14D_En SD card A25 B25 PCI_CLK_LPC_1 12P_0402_50V8J PCIECLK for DSC 1 @EMC@ CC12 PCI_CLK_LPC_0 12P_0402_50V8J RC63 1M_0402_5% CC8 18P_0402_50V8J A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Title SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet of 56 D UC1C DDR_A_D[0 63] DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 C B AH63 AH62 AK63 AK62 AH61 AH60 AK61 AK60 AM63 AM62 AP63 AP62 AM61 AM60 AP61 AP60 AP58 AR58 AM57 AK57 AL58 AK58 AR57 AN57 AP55 AR55 AM54 AK54 AL55 AK55 AR54 AN54 AY58 AW58 AY56 AW56 AV58 AU58 AV56 AU56 AY54 AW54 AY52 AW52 AV54 AU54 AV52 AU52 AK40 AK42 AM43 AM45 AK45 AK43 AM40 AM42 AM46 AK46 AM49 AK49 AM48 AK48 AM51 AK51 SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 BDW_ULT_DDR3L SA_CLK#0 SA_CLK0 SA_CLK#1 SA_CLK1 SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3 SA_CS#0 SA_CS#1 SA_ODT0 SA_RAS SA_WE SA_CAS SA_BA0 SA_BA1 SA_BA2 SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15 DDR CHANNEL A SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7 SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7 SM_VREF_CA SM_VREF_DQ0 SM_VREF_DQ1 AU37 AV37 AW36 AY36 M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1 AU43 AW43 AY42 AY43 DDR_CKE0_DIMMA DDR_CKE1_DIMMA AP33 AR32 DDR_CS0_DIMMA# DDR_CS1_DIMMA# M_CLK_DDR#0 M_CLK_DDR0 M_CLK_DDR#1 M_CLK_DDR1 DDR_CKE0_DIMMA DDR_CKE1_DIMMA DDR_CS0_DIMMA# DDR_CS1_DIMMA# AP32 AY34 AW34 AU34 DDR_A_RAS# DDR_A_WE# DDR_A_CAS# AU35 AV35 AY41 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 AP49 AR51 AP51 DDR_A_RAS# DDR_A_WE# DDR_A_CAS# DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 DDR_A_MA[0 15] DDR_A_DQS#[0 7] DDR_A_DQS[0 7] +SM_VREF_CA +SM_VREF_DQ0 +SM_VREF_DQ1 BDW-ULT-DDR3L_BGA1168 OF 19 DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 AY31 AW31 AY29 AW29 AV31 AU31 AV29 AU29 AY27 AW27 AY25 AW25 AV27 AU27 AV25 AU25 AM29 AK29 AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26 AM26 AK25 AL25 AY23 AW23 AY21 AW21 AV23 AU23 AV21 AU21 AY19 AW19 AY17 AW17 AV19 AU19 AV17 AU17 AR21 AR22 AL21 AM22 AN22 AP21 AK21 AK22 AN20 AR20 AK18 AL18 AK20 AM20 AR18 AP18 D BDW_ULT_DDR3L UC1D DDR_B_D[0 63] SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 SB_CK#0 SB_CK0 SB_CK#1 SB_CK1 SB_CKE0 SB_CKE1 SB_CKE2 SB_CKE3 SB_CS#0 SB_CS#1 SB_ODT0 SB_RAS SB_WE SB_CAS SB_BA0 SB_BA1 SB_BA2 DDR CHANNEL B SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15 SB_DQSN0 SB_DQSN1 SB_DQSN2 SB_DQSN3 SB_DQSN4 SB_DQSN5 SB_DQSN6 SB_DQSN7 SB_DQSP0 SB_DQSP1 SB_DQSP2 SB_DQSP3 SB_DQSP4 SB_DQSP5 SB_DQSP6 SB_DQSP7 AM38 AN38 AK38 AL38 M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3 AY49 AU50 AW49 AV50 DDR_CKE2_DIMMB DDR_CKE3_DIMMB AM32 AK32 DDR_CS2_DIMMB# DDR_CS3_DIMMB# M_CLK_DDR#2 M_CLK_DDR2 M_CLK_DDR#3 M_CLK_DDR3 DDR_CKE2_DIMMB DDR_CKE3_DIMMB DDR_CS2_DIMMB# DDR_CS3_DIMMB# AL32 AM35 AK35 AM33 DDR_B_RAS# DDR_B_WE# DDR_B_CAS# AL35 AM36 AU49 DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_RAS# DDR_B_WE# DDR_B_CAS# DDR_B_BS0 DDR_B_BS1 DDR_B_BS2 DDR_B_MA[0 15] C DDR_B_DQS#[0 7] DDR_B_DQS[0 7] B BDW-ULT-DDR3L_BGA1168 OF 19 A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Title SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet of 56 @ RC77 2 0_0402_5% +3.3V_RUN B A UC5 TC7SH08FU_SSOP5~D O 4PCH_PLTRST#_EC PCH_PLTRST#_EC PM_APWROK SIO_SLP_A# PM_APWROK B +RTC_CELL O A PM_APWROK_R 1 SYS_RESET# @ UC4 74AHC1G09GW_TSSOP5 P PCH_PLTRST# O A P B G UC6 TC7SH08FU_SSOP5~D 1 ME_RESET# 8.2K_0402_5% RC81 @ RC82 @ RC80 +PCH_VCCDSW3_3 D DSWODVREN RC78 330K_0402_5% ME_SUS_PWR_ACK 10K_0402_5% SUSACK# 10K_0402_5% SUS_STAT#/LPCPD# 10K_0402_5% G G XDP_DBRESET# RC79 P +3.3V_ALW_PCH +3.3V_ALW2 +3.3V_RUN D RPC1 PCH_BATLOW# AC_PRESENT PCH_PCIE_WAKE# PM_LANPHY_ENABLE RC91 @ RC2191 @ RC87 @ RC88 @ RC89 @ RC2201 PLTRST_VMM2320# PLTRST_USH# PLTRST_MMI# PLTRST_LAN# PLTRST_GPU# 10K_8P4R_5% 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% DSWODVREN ‐ ON DIE DSW VR ENABLE PCH_PLTRST# HIGH = ENABLED (DEFAULT) LOW = DISABLED PCH_RSMRST#_Q 10K_0402_5% BDW_ULT_DDR3L UC1H SYSTEM POWER MANAGEMENT +3.3V_RUN PM_APWROK_R PCH_PLTRST# ME_RESET# 8.2K_0402_5% PCH_RSMRST#_Q ME_SUS_PWR_ACK SIO_PWRBTN# AC_PRESENT SIO_SLP_WLAN# PCH_RSMRST#_Q ME_SUS_PWR_ACK SIO_PWRBTN# AC_PRESENT PCH_BATLOW# SIO_SLP_S0# SIO_SLP_WLAN# +3.3V_RUN C AW6 AV4 AL7 AJ8 AN4 AF3 AM5 DSWVRMEN DPWROK WAKE CLKRUN/GPIO32 SUS_STAT/GPIO61 SUSCLK/GPIO62 SLP_S5/GPIO63 RSMRST SUSWARN/SUSPWRDNACK/GPIO30 PWRBTN ACPRESENT/GPIO31 BATLOW/GPIO72 SLP_S0 SLP_WLAN/GPIO29 UC7 XDP@ 14 TDO_XDP 0_0402_5% TDI_XDP_R 0_0402_5% RUNPWROK PCH_JTAG_TMS PCH_JTAG_TMS 12 TRST#_XDP 13 RUNPWROK RUNPWROK 10 RUNPWROK AJ6 AT4 AL5 AP4 AJ7 1B CPU_XDP_TDO 1OE 2A 2B CPU_XDP_TDI 3A 3B Place near JXDP1 CFG0 CFG1 CFG2 CFG3 11 4B 4OE CPU_XDP_TRST# RC5 need to close to JCPU1 GND 15 H_VCCST_PWRGD CFG2 CFG3 XDP_OBS0_R XDP_OBS1_R 3OE 4A CFG0 CFG1 CFG4 CFG5 CFG4 CFG5 CFG6 CFG6 1K_0402_5% CFG7 RC102 CFG7 XDP@ 1K_0402_5% H_CPUPWRGD @ RC103 H_VCCST_PWRGD_XDP SIO_PWRBTN# 74CBTLV3126BQ_DHVQFN14_2P5X3 PCH_JTAG_TRST# 0_0402_5% CPU_XDP_TRST# RC109 XDP@ PCH_JTAG_JTAGX 0_0402_5% CPU_XDP_TCLK RC112 XDP@ CPU_PWR_DEBUG# DDR_XDP_WAN_SMBDAT DDR_XDP_WAN_SMBCLK PCH_JTAG_TCK SYS_PWROK CPU_XDP_TCLK TDI_XDP_R RC118 @ 1 RC123 10K_0402_5% @EMC@ CC83 100P_0402_50V8J H_PROCHOT# PECI_EC RC121 DDR3_DRAMRST# DDR_PG_CTRL A D61 K61 N62 H_PROCHOT#_R 56_0402_5% K63 H_CPUPWRGD C61 SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 CAD Note: Avoid stub in the PWRGD path while placing resistors RC123 CFG17 CFG16 CFG8 CFG9 CFG8 CFG9 CFG10 CFG11 CFG10 CFG11 CFG19 CFG18 CFG19 CFG18 CFG12 CFG13 CFG12 CFG13 CFG14 CFG15 CFG14 CFG15 XDP_RST#_R XDP_DBRESET# TDO_XDP TRST#_XDP PCH_JTAG_TDI PCH_JTAG_TMS CFG3_R RC113 XDP@ RC106 XDP@ PCH_PLTRST#_EC 1K_0402_5% CFG3 1K_0402_5% +1.05V_RUN AU60 AV60 AU61 AV15 AV61 PROC_DETECT CATERR PECI PROCPWRGD SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 SM_DRAMRST SM_PG_CNTL1 @ RC117 XDP_DBRESET# 2 MISC PRDY PREQ PROC_TCK PROC_TMS PROC_TRST PROC_TDI PROC_TDO JTAG PROCHOT B CC21 XDP@ 0.1U_0402_25V6 H_CATERR# PECI_EC @ CC22 0.1U_0402_25V6 BDW_ULT_DDR3L UC1B EMI request add C Place near JXDP1.48 SYS_PWROK H_CPUPWRGD CFG17 CFG16 TDO_XDP 51_0402_5% XDP@ RC120 1K_0402_5% CPU_XDP_TCLK RC119 @ H_PROCHOT# GND1 OBSFN_C0 OBSFN_C1 GND3 OBSDATA_C0 OBSDATA_C1 GND5 OBSDATA_C2 OBSDATA_C3 GND7 OBSFN_D0 OBSFN_D1 GND9 OBSDATA_D0 OBSDATA_D1 GND11 OBSDATA_D2 OBSDATA_D3 GND13 ITPCLK/HOOK4 ITPCLK#/HOOK5 VCC_OBS_CD RESET#/HOOK6 DBR#/HOOK7 GND15 TD0 TRST# TDI TMS GND17 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 +3.3V_ALW_PCH @EMC@ CC20 22P_0402_50V8J SIO_SLP_S0# TDO_XDP RC115 @ PCH_JTAG_TCK 0_0402_5% SYS_RESET# SAMTE_BSH-030-01-L-D-A CONN@ 0_0402_5% PCH_JTAG_TDO 0_0402_5% GND0 OBSFN_A0 OBSFN_A1 GND2 OBSDATA_A0 OBSDATA_A1 GND4 OBSDATA_A2 OBSDATA_A3 GND6 OBSFN_B0 OBSFN_B1 GND8 OBSDATA_B0 OBSDATA_B1 GND10 OBSDATA_B2 OBSDATA_B3 GND12 PWRGOOD/HOOK0 HOOK1 VCC_OBS_AB HOOK2 HOOK3 GND14 SDA SCL TCK1 TCK0 GND16 2 B H_CATERR# 49.9_0402_1% H_PROCHOT# 62_0402_5% PCH_RTCRST# PCH_RTCRST# POWER_SW#_MB +1.05V_RUN 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 CPU_XDP_PREQ# CPU_XDP_PRDY# CPU_XDP_TMS reference Shark Bay ULT Validation Customer Debug Port Implementation Requirement Rev 1.0 @ RC114 RC116 10 11 12 13 14 15 16 17 18 GND GND JXDP1 2OE GND PAD +1.05V_VCCST SIO_SLP_S5# SIO_SLP_S4# SIO_SLP_A# +PCH_VCCDSW3_3 +1.05V_RUN 1A PCH_JTAG_TDI RC99 XDP@ PCH_JTAG_TDI CLKRUN# CLKRUN# SUS_STAT#/LPCPD# SUSCLK_R SUSCLK SIO_SLP_S5# @ @RC136 RC136 0_0402_5% SIO_SLP_S5# T8 PAD~D@ T9 PAD~D @ SIO_SLP_S4# SIO_SLP_S4# SIO_SLP_S3# SIO_SLP_S3# SIO_SLP_A# SIO_SLP_A# SIO_SLP_SUS# SIO_SLP_SUS# SIO_SLP_LAN# SIO_SLP_LAN# VCC RUNPWROK V5 AG4 AE6 AP5 10 11 12 13 14 15 16 17 18 19 20 SIO_SLP_S3# +PCH_VCCDSW3_3 CONN@ ACES_50506-01841-P01 @ CC19 0.1U_0402_25V6 RC98 XDP@ JAPS1 +3.3V_ALW_PCH PCH_DPWROK PCH_PCIE_WAKE# +1.05V_RUN @ CC18 0.1U_0402_25V6 PCH_JTAG_TDO DSWODVREN PCH_DPWROK PCH_PCIE_WAKE# BDW-ULT-DDR3L_BGA1168 OF 19 CC17 XDP@ 0.1U_0402_25V6 SLP_S4 SLP_S3 SLP_A SLP_SUS SLP_LAN AW7 AV5 AJ5 @ RC95 SUSACK SYS_RESET SYS_PWROK PCH_PWROK APWROK PLTRST SYS_PWROK RESET_OUT# AK2 AC3 AG2 AY7 AB5 AG7 SUSACK# SYS_RESET# SYS_PWROK SUSACK# THERMAL J62 K62 E60 E61 E59 F63 F62 CPU_XDP_PRDY# CPU_XDP_PREQ# CPU_XDP_TCLK CPU_XDP_TMS CPU_XDP_TRST# CPU_XDP_TDI CPU_XDP_TDO J60 H60 H61 H62 K59 H63 K60 J61 XDP_OBS0_R XDP_OBS1_R XDP_OBS2_R XDP_OBS3_R XDP_OBS4_R XDP_OBS5_R XDP_OBS6_R XDP_OBS7_R Place near JXDP1.47 +3.3V_RUN XDP_DBRESET# 1K_0402_5% +1.05V_RUN DDR3L PAD~D PAD~D PAD~D PAD~D PAD~D PAD~D T10 T11 T12 T13 T14 T15 @ RC124 @ RC125 @ RC126 CPU_XDP_TCLK 51_0402_5% CPU_XDP_TRST# 51_0402_5% CPU_XDP_TMS 51_0402_5% CPU_XDP_TDI 51_0402_5% CPU_XDP_PREQ# 51_0402_5% CPU_XDP_TDO 51_0402_5% PWR BPM#0 BPM#1 BPM#2 BPM#3 BPM#4 BPM#5 BPM#6 BPM#7 RC122 @ @ @ @ @ @ BDW-ULT-DDR3L_BGA1168 OF 19 RC127 RC128 @ RC129 A DDR3 COMPENSATION SIGNALS 200_0402_1% 121_0402_1% 100_0402_1% RC130 SM_RCOMP0 RC131 SM_RCOMP1 RC132 SM_RCOMP2 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc CAD Note: Trace width=12~15 mil, Spcing=20 mils Max trace length= 500 mil PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Title SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet of 56 D D BDW_ULT_DDR3L UC1A DDI1_LANE_N0 DDI1_LANE_P0 DDI1_LANE_N1 DDI1_LANE_P1 DDI1_LANE_N2 DDI1_LANE_P2 DDI1_LANE_N3 DDI1_LANE_P3 DDI2_LANE_N0 DDI2_LANE_P0 DDI2_LANE_N1 DDI2_LANE_P1 DDI2_LANE_N2 DDI2_LANE_P2 DDI2_LANE_N3 DDI2_LANE_P3 C54 C55 B58 C58 B55 A55 A57 B57 C51 C50 C53 B54 C49 B50 A53 B53 DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3 EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1 DDI EDP DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3 EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3 EDP_AUXN EDP_AUXP EDP_RCOMP EDP_DISP_UTIL C45 B46 A47 B47 EDP_CPU_LANE_N0 EDP_CPU_LANE_P0 EDP_CPU_LANE_N1 EDP_CPU_LANE_P1 EDP_CPU_LANE_N0 EDP_CPU_LANE_P0 EDP_CPU_LANE_N1 EDP_CPU_LANE_P1 COMPENSATION PU FOR eDP +VCCIOA_OUT C47 C46 A49 B49 EDP_COMP 24.9_0402_1% A45 B45 EDP_CPU_AUX# EDP_CPU_AUX D20 A43 EDP_COMP EDP_CPU_AUX# EDP_CPU_AUX RC133 CAD Note:Trace width=20 mils ,Spacing=25mil, Max length=100 mils C C BDW-ULT-DDR3L_BGA1168 OF 19 +3.3V_RUN RPC15 +3.3V_RUN 3.3V_TP_EN CAM_MIC_CBL_DET# USH_DET# PCH_GPIO69 BDW_ULT_DDR3L UC1I RPC2 CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT CPU_DPC_CTRLCLK CPU_DPC_CTRLDAT 10K_8P4R_5% RC134 DGPU_PWR_EN 10K_0402_5% 2 @ RC139 @ RC140 ENVDD_PCH 100K_0402_5% PCH_GPIO53 1K_0402_5% EDP_BIA_PWM PANEL_BKLEN ENVDD_PCH CONTACTLESS_DET# DGPU_PWROK HDD_FALL_INT PCH_GPIO80 @ T16 PAD~D TOUCHPAD_INTR# PCH_GPIO52 DGPU_PWR_EN EDP_BIA_PWM PANEL_BKLEN ENVDD_PCH DGPU_PWROK HDD_FALL_INT DGPU_PWR_EN PCH_GPIO53 B B8 A9 C6 U6 P4 N4 N2 AD4 U7 L1 L3 R5 L4 EDP_BKLCTL EDP_BKLEN EDP_VDDEN DDPB_CTRLCLK DDPB_CTRLDATA DDPC_CTRLCLK DDPC_CTRLDATA eDP SIDEBAND PIRQA/GPIO77 PIRQB/GPIO78 PIRQC/GPIO79 PIRQD/GPIO80 PME DISPLAY PCIE GPIO55 GPIO52 GPIO54 GPIO51 GPIO53 DDPB_AUXN DDPC_AUXN DDPB_AUXP DDPC_AUXP DDPB_HPD DDPC_HPD EDP_HPD B9 C9 D9 D11 CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT CPU_DPC_CTRLCLK CPU_DPC_CTRLDAT CPU_DPB_CTRLCLK CPU_DPB_CTRLDAT C5 B6 B5 A6 CPU_DPB_AUX# CPU_DPC_AUX# CPU_DPB_AUX CPU_DPC_AUX CPU_DPC_AUX# C8 A8 D6 DPB_HPD DPC_HPD EDP_CPU_HPD CPU_DPC_AUX 2.2K_0804_8P4R_5% DPB_HPD DPC_HPD EDP_CPU_HPD RPC20 CPU_DPB_AUX# CPU_DPB_AUX CPU_DPC_AUX CPU_DPC_AUX# B 100K_0804_8P4R_5% BDW-ULT-DDR3L_BGA1168 OF 19 EDP_CPU_HPD 100K_0402_5% DPC_HPD 100K_0402_5% RC141 RC142 A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Title SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet 10 of 56 PLACE BETWEEN GPU AND POWER SUPPLY UV1D AA22 AB23 AC24 AD25 AE26 AE27 +3.3V_GFX_AON G10 G12 G8 G9 FB_CAL_PD_VDDQ 40.2_0402_1% C24 RV44 42.2_0402_1% B25 RV43 51.1_0402_1% +1.35V_MEM_GFX +3.3V_RUN_GFX 2 2 C +3.3V_GFX_AON AB8 NC NC NC NC NC PEX_PLLVDD_1 PEX_PLLVDD_2 2 CV159 4.7U_0603_6.3V6K AA8 AA9 CV160 4.7U_0603_6.3V6K PEX_PLL_HVDD_1 PEX_PLL_HVDD_2 PEX_SVDD_3V3 J7 K7 K6 H6 J6 CV130 4.7U_0603_6.3V6K RV42 CV198 1U_0402_6.3V6K FB_CAL_TERM_GND D22 PLACE NEAR GPU CV164 4.7U_0603_6.3V6K 3V3_AON 3V3_AON VDD33_3 VDD33_4 CV64 0.1U_0402_10V7K IFPD_PLLVDD_2 NC IFPD_RSET NC D PLACE NEAR BGA T7 R7 U6 R6 CV199 1U_0402_6.3V6K POWER CV30 0.1U_0402_10V7K NC NC NC NC CV68 0.1U_0402_10V7K M7 N7 T6 P6 PLACE UNDER GPU FB_CAL_PU_GND C +1.05V_PEX_VDD CV36 22U_0603_6.3V6M NC NC NC NC NC PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 PEX_IOVDD_6 AA10 AA12 AA13 AA16 AA18 AA19 AA20 AA21 AB22 AC23 AD24 AE25 AF26 AF27 CV40 0.1U_0402_10V7K V7 W7 AA6 W6 Y6 PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8 PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11 PEX_IOVDDQ_12 PEX_IOVDDQ_13 PEX_IOVDDQ_14 CV16 10U_0603_6.3V6M FBVDDQ_01 FBVDDQ_02 FBVDDQ_03 FBVDDQ_04 FBVDDQ_05 FBVDDQ_06 FBVDDQ_07 FBVDDQ_08 FBVDDQ_09 FBVDDQ_10 FBVDDQ_11 FBVDDQ_12 FBVDDQ_13 FBVDDQ_14 FBVDDQ_AON FBVDDQ_AON FBVDDQ_AON FBVDDQ_AON FBVDDQ_19 FBVDDQ_20 FBVDDQ_21 FBVDDQ_22 FBVDDQ_23 FBVDDQ_24 FBVDDQ_25 FBVDDQ_26 FBVDDQ_27 CV65 4.7U_0603_6.3V6K CV161 0.1U_0402_10V7K CV163 0.1U_0402_10V7K CV168 1U_0402_6.3V6K CV165 1U_0402_6.3V6K CV24 4.7U_0603_6.3V6K CV47 4.7U_0603_6.3V6K CV39 10U_0603_6.3V6M CV43 22U_0603_6.3V6M PLACE UNDER GPU B26 C25 E23 E26 F14 F21 G13 G14 G15 G16 G18 G19 G20 G21 H24 H26 J21 K21 L22 L24 L26 M21 N21 R21 T21 V21 W21 CV211 1U_0402_6.3V6K I=2000mA PLACE NEAR GPU D PLACE NEAR BALLS PLACE NEAR GPU Part of +1.35V_MEM_GFX AA14 AA15 PLACE UNDER GPU PLACE NEAR GPU 2 CV135 4.7U_0603_6.3V6K CV205 1U_0402_6.3V6K CV63 0.1U_0402_10V7K GM108-ES-S-A1_FCBGA595 +1.05V_PEX_VDD B B A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Title SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet 42 of 56 Caps on Power Side 1UX4 4.7UX10 under GPU 4.7UX5 22UX1 47UX2 330UX2 near GPU D D UV1F +GPU_CORE VDD_001 VDD_002 VDD_003 VDD_004 VDD_005 VDD_006 VDD_007 VDD_008 VDD_009 VDD_010 VDD_011 VDD_012 VDD_013 VDD_014 VDD_015 VDD_016 VDD_017 VDD_018 VDD_019 VDD_020 POWER Part of K10 K12 K14 K16 K18 L11 L13 L15 L17 M10 M12 M14 M16 M18 N11 N13 N15 N17 P10 P12 +GPU_CORE VDD_041 VDD_040 VDD_039 VDD_038 VDD_037 VDD_036 VDD_035 VDD_034 VDD_033 VDD_032 VDD_031 VDD_030 VDD_029 VDD_028 VDD_027 VDD_026 VDD_025 VDD_024 VDD_023 VDD_022 VDD_021 V18 V16 V14 V12 V10 U17 U15 U13 U11 T18 T16 T14 T12 T10 R17 R15 R13 R11 P18 P16 P14 C C GM108-ES-S-A1_FCBGA595 B B A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Title SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet 43 of 56 FBA_D[0 63] FB_CLAMP FBA_CMD34 FBA_CMD35 3V3_MAIN_EN RV185 RV193 0_0402_5% +5V_ALW 0_0402_5% FBA_CLK1 FBA_CLK1_N FBA_WCK01 FBA_WCK01_N FBA_WCK23 FBA_WCK23_N FBA_WCK45 FBA_WCK45_N FBA_WCK67 FBA_WCK67_N N22 M22 ON1 VBIAS VOUT1 VOUT1 CT1 GND ON2 CT2 VIN2 VIN2 VOUT2 VOUT2 GPAD 14 13 +1.05V_PEX_VDD_UV15 12 CV139 0.1U_0402_10V7K CV140 470P_0402_50V7K 11 CV141 10 +3.3V_RUN_GFX_UV15 470P_0402_50V7K @ PJP30 +3.3V_RUN_GFX 15 TPS22966DPUR_SON14_2X3 3V3_MAIN_EN VIN1 VIN1 2 CLKA0 CLKA0# FBA_CLK0 FBA_CLK0_N 2 UV15 +3.3V_RUN D24 D25 PJP31 PAD-OPEN1x1m @ +1.05V_M CLKA1 CLKA1# PAD-OPEN1x1m B D18 C18 D17 D16 T24 U24 V24 V25 +1.35V_MEM_GFX +1.35V_MEM +5V_ALW 1 @ RV177 20K_0402_5% A RV209 10K_0402_5% BAT54CW_SOT323-3 @ CV366 100P_0402_50V8J 2 QV83 SI4164DY-T1-GE3_SO8~D DGPU_PWR_ON RV179 2.2M_0402_5% GPU_GC6_FB_EN QV84A DMN66D0LDW-7_SOT363-6 QV84B DMN66D0LDW-7_SOT363-6 RV178 100K_0402_5% DGPU_PWR_ON# DV7 CV365 10U_0603_6.3V6M +3.3V_ALW2 GM108-ES-S-A1_FCBGA595 DGPU_PWROK +1.35V_MEM_GFX F3 F22 J22 C +1.05V_PEX_VDD RV176 470K_0402_5% 1 60.4_0402_1% 60.4_0402_1% FB_DLLAVDD S DGPU_PWR_EN# FB_CLAMP_GPU 10K_0402_5% H22 FB_VREF_PROBE FBA_WP0 FBA_WP1 FBA_WP2 FBA_WP3 FBA_WP4 FBA_WP5 FBA_WP6 FBA_WP7 D G DGPU_PWR_EN 1 I=35mA D23 E19 C15 B16 B22 R25 W23 AB26 T26 D +1.35V_MEM_GFX @ RV46 @ RV130 PAD~D FBA_RN0 FBA_RN1 FBA_RN2 FBA_RN3 FBA_RN4 FBA_RN5 FBA_RN6 FBA_RN7 +3.3V_GFX_AON QV86 LP2301ALT1G_SOT23-3 RV48 @T95 FB_PLLAVDD_1 FB_PLLAVDD_2 F19 C14 A16 A22 P25 W22 AB27 T27 +5V_RUN FBA_RST @ B F16 P22 FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 +3.3V_RUN FBA_CMD5 RV119 FBA_WP[0 7] CV142 0.1U_0402_10V7K CV48 0.1U_0402_10V7K PLACE CLOSE to GPU FBA_CMD31 D19 D14 C17 C22 P24 W24 AA25 U25 FBA_WP[0 7] 2 CV45 0.1U_0402_10V7K CV133 0.1U_0402_10V7K CV32 22U_0603_6.3V6M FBA_DQS_WP0 FBA_DQS_WP1 FBA_DQS_WP2 FBA_DQS_WP3 FBA_DQS_WP4 FBA_DQS_WP5 FBA_DQS_WP6 FBA_DQS_WP7 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD0 T110 PAD~D@ FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 T111 PAD~D@ FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 T112 PAD~D@ RV118 FBA_CMD19 +FB_PLLAVDD FBA_DQS_RN0 FBA_DQS_RN1 FBA_DQS_RN2 FBA_DQS_RN3 FBA_DQS_RN4 FBA_DQS_RN5 FBA_DQS_RN6 FBA_DQS_RN7 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD3 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% CV363 0.1U_0402_25V6 PLACE UNDER GPU LV26 BLM18PG300SN1D_2P FBA_DQM0 FBA_DQM1 FBA_DQM2 FBA_DQM3 FBA_DQM4 FBA_DQM5 FBA_DQM6 FBA_DQM7 C27 C26 E24 F24 D27 D26 F25 F26 F23 G22 G23 G24 F27 G25 G27 G26 M24 M23 K24 K23 M27 M26 M25 K26 K22 J23 J25 J24 K27 K25 J27 J26 RV117 G +1.05V_PEX_VDD FBA_CMD0 FBA_CMD1 FBA_CMD2 FBA_CMD3 FBA_CMD4 FBA_CMD5 FBA_CMD6 FBA_CMD7 FBA_CMD8 FBA_CMD9 FBA_CMD10 FBA_CMD11 FBA_CMD12 FBA_CMD13 FBA_CMD14 FBA_CMD15 FBA_CMD16 FBA_CMD17 FBA_CMD18 FBA_CMD19 FBA_CMD20 FBA_CMD21 FBA_CMD22 FBA_CMD23 FBA_CMD24 FBA_CMD25 FBA_CMD26 FBA_CMD27 FBA_CMD28 FBA_CMD29 FBA_CMD30 FBA_CMD31 RV132 FBA_CMD18 D C FBA_D00 FBA_D01 FBA_D02 FBA_D03 FBA_D04 FBA_D05 FBA_D06 FBA_D07 FBA_D08 FBA_D09 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 S ODT CKE A13 A8 A6 A11 A5 A3 BA2 BA1 A12 A10 RAS# E18 F18 E16 F17 D20 D21 F20 E21 E15 D15 F15 F13 C13 B13 E13 D13 B15 C16 A13 A15 B18 A18 A19 C19 B24 C23 A25 A24 A21 B21 C20 C21 R22 R24 T22 R23 N25 N26 N23 N24 V23 V22 T23 U22 Y24 AA24 Y22 AA23 AD27 AB25 AD26 AC25 AA27 AA26 W26 Y25 R26 T25 N27 R27 V26 V27 W27 W25 FBA_CKE_H FBA_CMD2 QV87 L2N7002WT1G_SC-70-3 A13 A8 A6 A11 A5 A3 BA2 BA1 A12 A10 RAS# CAS# CS0# FBA_D0 FBA_D1 FBA_D2 FBA_D3 FBA_D4 FBA_D5 FBA_D6 FBA_D7 FBA_D8 FBA_D9 FBA_D10 FBA_D11 FBA_D12 FBA_D13 FBA_D14 FBA_D15 FBA_D16 FBA_D17 FBA_D18 FBA_D19 FBA_D20 FBA_D21 FBA_D22 FBA_D23 FBA_D24 FBA_D25 FBA_D26 FBA_D27 FBA_D28 FBA_D29 FBA_D30 FBA_D31 FBA_D32 FBA_D33 FBA_D34 FBA_D35 FBA_D36 FBA_D37 FBA_D38 FBA_D39 FBA_D40 FBA_D41 FBA_D42 FBA_D43 FBA_D44 FBA_D45 FBA_D46 FBA_D47 FBA_D48 FBA_D49 FBA_D50 FBA_D51 FBA_D52 FBA_D53 FBA_D54 FBA_D55 FBA_D56 FBA_D57 FBA_D58 FBA_D59 FBA_D60 FBA_D61 FBA_D62 FBA_D63 FBA_CKE_L FBA_DQM[0 7] RV181 100K_0402_5% CAS# FBA_DQM[0 7] Part of A14 RST A9 A7 A2 A0 A4 A1 BA0 WE# FBA_RN[0 7] RV114 10K_0402_5% ODT CKE A14 RST A9 A7 A2 A0 A4 A1 BA0 WE# CMD32 CMD33 CMD34 CMD35 CMD36 CMD37 CMD38 CMD39 CMD40 CMD41 CMD42 CMD43 CMD44 CMD45 CMD46 CMD47 CMD48 CMD49 CMD50 CMD51 CMD52 CMD53 CMD54 CMD55 CMD56 CMD57 CMD58 CMD59 CMD60 CMD61 CMD62 CMD63 CS0# FBA_ODT_H FBA_RN[0 7] MEMORY INTERFACE A D CMD0 CMD1 CMD2 CMD3 CMD4 CMD5 CMD6 CMD7 CMD8 CMD9 CMD10 CMD11 CMD12 CMD13 CMD14 CMD15 CMD16 CMD17 CMD18 CMD19 CMD20 CMD21 CMD22 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30 CMD31 FBA_ODT_L FBA_D[0 63] UV1B GDDR3L CMD Mapping Table DGPU_PWR_ON A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Title SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet 44 of 56 Memory Partition A - Upper 16 bits FBA_D[0 31] 256x16 DDR3L FBA_D[0 31] FBA_WP[0 3] FBA_WP[0 3] FBA_DQM[0 3] FBA_DQM[0 3] FBA_RN[0 3] FBA_RN[0 3] D D FBA_CMD3 J7 K7 K9 FBA_CMD2 FBA_CMD0 FBA_CMD30 FBA_CMD15 FBA_CMD13 K1 L2 J3 K3 L3 CLKA0 CLKA0# FBA_CMD3 RV145 162_0402_1% 2 2 PLACE UNDER DRAM VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 2 PLACE CLOSE DRAM GND FBA_CMD2 FBA_CMD0 FBA_CMD30 FBA_CMD15 FBA_CMD13 K1 L2 J3 K3 L3 FBA_WP0 FBA_WP3 F3 C7 FBA_DQM0 FBA_DQM3 E7 D3 FBA_RN0 FBA_RN3 G3 B7 FBA_CMD5 T2 FBA_ZQ1 L8 ADDRESS DATA J7 K7 K9 CK CK CKE B1 B9 D1 D8 E2 E8 F9 G1 G9 96-BALL SDRAM DDR3 H5TC4G63AFR-11C_FBGA96 ODT CS RAS CAS WE DQSL DQSU DML DMU VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS RESET ZQ D7 C3 C8 C2 A7 A2 B8 A3 FBA_D25 FBA_D29 FBA_D26 FBA_D28 FBA_D27 FBA_D30 FBA_D24 FBA_D31 C B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.35V_MEM_GFX VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ DQSL DQSU FBA_D1 FBA_D4 FBA_D3 FBA_D6 FBA_D0 FBA_D7 FBA_D2 FBA_D5 A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 2 2 PLACE UNDER DRAM 2 @ CV136 10U_0603_6.3V6M CLKA0 CLKA0# FBA_CMD3 BA0 BA1 BA2 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 CV187 1U_0402_6.3V6K M2 N8 M3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 NC DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 CV186 1U_0402_6.3V6K NC NC NC NCZQ1 FBA_CMD12 FBA_CMD27 FBA_CMD26 VREFCA VREFDQ CV179 1U_0402_6.3V6K ZQ A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 243_0402_1% RV152 J1 L1 J9 L9 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 CV132 1U_0402_6.3V6K L8 RESET FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4 FBA_CMD14 CV172 0.1U_0402_10V6K FBA_ZQ0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU M8 H1 CV174 0.1U_0402_10V6K T2 @ CV42 10U_0603_6.3V6M FBA_CMD5 243_0402_1% RV148 B G3 B7 CV184 1U_0402_6.3V6K FBA_CMD5 FBA_RN1 FBA_RN2 DML DMU 20130610 10U reserve CV183 1U_0402_6.3V6K FBA_DQM1 FBA_DQM2 A1 A8 C1 C9 D2 E9 F1 H2 H9 CV178 1U_0402_6.3V6K CV335 0.01U_0402_25V7K @ E7 D3 DQSL DQSU +FBA_VREF_CA0 +FBA_VREF_DQ0 +1.35V_MEM_GFX VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ CV131 1U_0402_6.3V6K F3 C7 FBA_WP1 FBA_WP2 CLKA0_C ODT CS RAS CAS WE B2 D9 G7 K2 K8 N1 N9 R1 R9 CV151 0.1U_0402_10V6K @ FBA_D17 FBA_D21 FBA_D18 FBA_D20 FBA_D19 FBA_D22 FBA_D16 FBA_D23 CV143 0.1U_0402_10V6K FBA_CMD2 FBA_CMD0 FBA_CMD30 FBA_CMD15 FBA_CMD13 80.6_0402_1% RV147 80.6_0402_1% RV146 @ CK CK CKE VDD VDD VDD VDD VDD VDD VDD VDD VDD D7 C3 C8 C2 A7 A2 B8 A3 CLKA0 CLKA0# BA0 BA1 BA2 FBA_D11 FBA_D13 FBA_D10 FBA_D15 FBA_D9 FBA_D14 FBA_D8 FBA_D12 Control & DQM M2 N8 M3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 20130610 10U reserve PLACE CLOSE DRAM GND FBA_CMD12 FBA_CMD27 FBA_CMD26 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 NC ADDRESS DATA N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 FBA_CMD12 FBA_CMD27 FBA_CMD26 FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4 FBA_CMD14 UV18 VREFCA VREFDQ POWER C M8 H1 Control & DQM FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4 FBA_CMD14 +FBA_VREF_CA0 +FBA_VREF_DQ0 POWER UV17 +FBA_VREF_CA0 +FBA_VREF_DQ0 J1 L1 J9 L9 NC NC NC NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B1 B9 D1 D8 E2 E8 F9 G1 G9 B 96-BALL SDRAM DDR3 H5TC4G63AFR-11C_FBGA96 SA00006E800 Link done SA00006E800 Link done 2 1.33K_0402_1% RV144 2 CV334 0.01U_0402_25V7K PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT +FBA_VREF_DQ0 1.33K_0402_1% RV112 CV326 0.01U_0402_25V7K 1.33K_0402_1% RV110 +FBA_VREF_CA0 A +1.35V_MEM_GFX 1.33K_0402_1% RV139 +1.35V_MEM_GFX DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc Title SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet 45 of 56 A Memory Partition A - Lower 16 bits FBA_D[32 63] 256x16 DDR3L FBA_D[32 63] FBA_WP[4 7] FBA_WP[4 7] FBA_DQM[4 7] FBA_DQM[4 7] FBA_RN[4 7] FBA_RN[4 7] D D FBA_CMD18 FBA_CMD16 FBA_CMD30 FBA_CMD15 FBA_CMD13 K1 L2 J3 K3 L3 J1 L1 J9 L9 NC NC NC NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ 2 PLACE UNDER DRAM K1 L2 J3 K3 L3 FBA_WP4 FBA_WP7 F3 C7 FBA_DQM4 FBA_DQM7 E7 D3 FBA_RN4 FBA_RN7 G3 B7 FBA_CMD5 T2 FBA_ZQ3 L8 ODT CS RAS CAS WE DQSL DQSU DML DMU VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS DQSL DQSU B1 B9 D1 D8 E2 E8 F9 G1 G9 96-BALL SDRAM DDR3 H5TC4G63AFR-11C_FBGA96 RESET ZQ FBA_D56 FBA_D60 FBA_D58 FBA_D61 FBA_D57 FBA_D63 FBA_D59 FBA_D62 C B2 D9 G7 K2 K8 N1 N9 R1 R9 +1.35V_MEM_GFX VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ PLACE CLOSE DRAM GND 1 243_0402_1% RV156 2 FBA_CMD18 FBA_CMD16 FBA_CMD30 FBA_CMD15 FBA_CMD13 CK CK CKE D7 C3 C8 C2 A7 A2 B8 A3 A1 A8 C1 C9 D2 E9 F1 H2 H9 A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 2 2 PLACE UNDER DRAM 2 @ CV158 10U_0603_6.3V6M J7 K7 K9 VDD VDD VDD VDD VDD VDD VDD VDD VDD FBA_D35 FBA_D37 FBA_D34 FBA_D39 FBA_D33 FBA_D38 FBA_D32 FBA_D36 CV215 1U_0402_6.3V6K ZQ CLKA1 CLKA1# FBA_CMD19 BA0 BA1 BA2 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 CV197 1U_0402_6.3V6K L8 RESET M2 N8 M3 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 NC DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 CV209 1U_0402_6.3V6K FBA_ZQ2 243_0402_1% RV155 B T2 FBA_CMD12 FBA_CMD27 FBA_CMD26 VREFCA VREFDQ CV173 1U_0402_6.3V6K FBA_CMD5 FBA_CMD5 DQSL DQSU N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 CV204 0.1U_0402_10V6K G3 B7 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4 FBA_CMD14 CV203 0.1U_0402_10V6K DML DMU @ CV15 10U_0603_6.3V6M CV218 0.01U_0402_25V7K @ A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 20130610 10U reserve CV196 1U_0402_6.3V6K FBA_RN6 FBA_RN5 DQSL DQSU +1.35V_MEM_GFX CV210 1U_0402_6.3V6K FBA_DQM6 FBA_DQM5 E7 D3 A1 A8 C1 C9 D2 E9 F1 H2 H9 CV208 1U_0402_6.3V6K F3 C7 CLKA1_C VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ CV170 1U_0402_6.3V6K FBA_WP6 FBA_WP5 ODT CS RAS CAS WE CV181 0.1U_0402_10V6K @ B2 D9 G7 K2 K8 N1 N9 R1 R9 CV180 0.1U_0402_10V6K FBA_CMD18 FBA_CMD16 FBA_CMD30 FBA_CMD15 FBA_CMD13 80.6_0402_1% RV154 80.6_0402_1% RV153 @ CK CK CKE FBA_D44 FBA_D40 FBA_D46 FBA_D41 FBA_D45 FBA_D43 FBA_D47 FBA_D42 M8 H1 ADDRESS DATA J7 K7 K9 VDD VDD VDD VDD VDD VDD VDD VDD VDD D7 C3 C8 C2 A7 A2 B8 A3 +FBA_VREF_CA1 +FBA_VREF_DQ1 POWER FBA_CMD19 FBA_CMD19 BA0 BA1 BA2 FBA_D52 FBA_D49 FBA_D53 FBA_D50 FBA_D54 FBA_D48 FBA_D55 FBA_D51 20130610 10U reserve PLACE CLOSE DRAM GND CLKA1 CLKA1# RV151 162_0402_1% ADDRESS DATA M2 N8 M3 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 E3 F7 F2 F8 H3 H8 G2 H7 CLKA1 CLKA1# FBA_CMD12 FBA_CMD27 FBA_CMD26 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 NC DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 FBA_CMD12 FBA_CMD27 FBA_CMD26 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 POWER C FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4 FBA_CMD14 UV20 VREFCA VREFDQ Control & DQM FBA_CMD9 FBA_CMD11 FBA_CMD8 FBA_CMD25 FBA_CMD10 FBA_CMD24 FBA_CMD22 FBA_CMD7 FBA_CMD21 FBA_CMD6 FBA_CMD29 FBA_CMD23 FBA_CMD28 FBA_CMD20 FBA_CMD4 FBA_CMD14 M8 H1 Control & DQM UV19 +FBA_VREF_CA1 +FBA_VREF_DQ1 J1 L1 J9 L9 NC NC NC NCZQ1 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B1 B9 D1 D8 E2 E8 F9 G1 G9 B 96-BALL SDRAM DDR3 H5TC4G63AFR-11C_FBGA96 SA00006E800 Link done SA00006E800 Link done +1.35V_MEM_GFX 1.33K_0402_1% RV150 20130606 reduce ??? 1.33K_0402_1% RV149 +1.35V_MEM_GFX 2 CV217 0.01U_0402_25V7K PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT +FBA_VREF_DQ1 1.33K_0402_1% RV143 CV216 0.01U_0402_25V7K 1.33K_0402_1% RV142 +FBA_VREF_CA1 A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc Title SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet 46 of 56 A +COINCELL COIN RTC Battery PR1 1K_0402_5% Z4012 +3.3V_RTC_LDO @ JRTC1 G G +COINCELL EMC@ PL1 FBMJ4516HS720NT_2P Primary Battery Connector PD3 +3.3V_ALW D PC1 1U_0603_10V4Z +PBATT PR2 10 PRP2 PBAT_SMBCLK_C PBAT_SMBDAT_C PBAT_PRES#_C PBAT_SMBDAT PBAT_SMBCLK 100K_0402_5% PBAT_PRES# PQ1 ME2301D-G 1P SOT-23-3 100_0804_8P4R_5% PD4 3 11 12 PC3 2200P_0402_50V7K 1 EMC@PL2 EMC@ PL2 FBMJ4516HS720NT_2P PBATT+_C BAS40CW SOT-323 @PBATT1 11 12 +RTC_CELL EMC@ PD2 TVNST52302AB0_SOT523-3 3 EMC@ PD1 TVNST52302AB0_SOT523-3 10 TYCO_2-1775293-2~D 1 D DOCK_SMB_ALERT# SDMK0340L-7-F_SOD323-2~D 2 TYU_TU1513WNV-100201J16 GND SLICE_BAT_PRES# PR6 0_0402_5% PC4 C C 1500P_0402_50V7K +3.3V_ALW EMC@ PL3 BLM15AG102SN1D_2P DOCK_PSID NO IN GPIO_PSID_SELECT PR8 2.2K_0402_5% PR9 33_0402_5% S G PR10 D NB_PSID PU1 PR7 0_0402_5% GND V+ +5V_ALW @ NB_PSID_TS5A63157 PQ2 FDV301N-G_SOT23-3 NC COM PS_ID TS5A63157DCKR_SC70-6~D +5V_ALW B 1 100K_0402_1% B C PQ3 MMST3904-7-F_SOT323~D B PR11 10K_0402_1% 2 E PR12 15K_0402_1% 1 @ PR13 PSID_DISABLE# 10K_0402_5% DC_IN+ Source PJP1 DCX124EK-7-F PNP/NPN_SC74-6~D PC10 10U_0805_25V6K SOFT_START_GC PR15 10K_0402_5% 100K_0402_5% PR14 AC_DIS PR18 1 5 PR17 PQ6A ACES_50299-0050N-001 PR16 +DCIN_JACK -DCIN_JACK 4.7K_0805_5% @ A @EMC@ PC11 0.1U_0603_25V7K EMC@ PC9 1000P_0603_50V7K GND GND 1M_0402_5% PQ6B @ PJPDC1 +DC_IN_SS PQ4 FDMC6679AZ_MLP8-5 PC5 0.022U_0805_50V7K EMC@ PL4 FBMJ4516HS720NT_2P DCX124EK-7-F PNP/NPN_SC74-6~D +DC_IN A 1M_0402_5% DELL CONFIDENTIAL/PROPRIETARY PAD-OPEN 1x3m Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet 47 of 56 A B C D E +3.3V_ALW2 +3.3V_RTC_LDO PR100 130K_0402_1% PR101 150K_0402_1% 3VALWP TDC 6.0 A Peak Current 8.6 A OCP Current 10.32 A TYP MAX H/S Rds(on) 24mohm , 30mohm L/S Rds(on) 13.5mohm , 16.5mohm Choke DCR 15.5mohm CAP ESR 18mohm FB_5V PC102 10U_0805_25V6K UG_5V 17 BST_5V 18 SW1 DRVL1 EN1 PC110 0.1U_0603_25V7K BST_5V_C SW1 EN 15 20 VIN 13 12 11 VREG5 SW2 DRVL2 PR109 2.2_0603_5% LG_3V LG_5V 4 +5V_ALW2 +3V5V_PWR_SRC PL102 3.3UH_6.3A_20% +5V_ALWP PC115 220U_6.3V_M 16 VBST2 VBST1 SW2 TPS51285BRUKR_QFN20_3X3 DRVH2 DRVH1 10 @EMC@ PR112 4.7_1206_5% UG_3V PR110 2.2_0603_5% BST_3V PC109 0.1U_0603_25V7K BST_3V_C + @EMC@ PC114 680P_0603_50V7K PR114 200_0402_1% VCLK 14 19 PGOOD SIS412DN-T1-GE3_POWERPAK8-5 PQ101 PGOOD_3V_5V 21 SI7716ADN-T1-GE3_POWERPAK8-5 PQ103 VO1 CS1 VFB1 VREG3 VFB2 CS2 PAD PQ100 SIS412DN-T1-GE3_POWERPAK8-5 EN2 SNUB_5V PR106 PC118 4.7U_0603_10V6K 2 EN PC117 0.1U_0603_25V7K + 100K_0402_1% PR107 PR108 0_0402_5% EN ALWON PR113 0_0402_5% +5V_ALWP PJP101 +5V_ALW 5VALWP TDC 3.5 A Peak Current 5.0 A OCP Current 6.0 A TYP MAX H/S Rds(on) 24mohm , 30mohm L/S Rds(on) 13.5mohm , 16.5mohm Choke DCR 25mohm CAP ESR 18mohm PAD-OPEN 1x3m PJP102 +3.3V_ALWP +3.3V_ALW PAD-OPEN 1x3m PC119 1U_0603_10V6K PC113 220U_6.3V_M @EMC@ PC111 @EMC@ PR111 680P_0603_50V7K 4.7_1206_5% SNUB_3V PL101 2.2UH_7.8A_20% +3.3V_ALWP PQ102 SI7716ADN-T1-GE3_POWERPAK8-5 PC101 10U_0805_25V6K +PWR_SRC @EMC@ PC105 2200P_0402_50V7K 2 PU100 PAD-OPEN 1x3m +3V5V_PWR_SRC 16.9K_0402_1% FB_3V +3.3V_ALW +3V5V_PWR_SRC PR104 100K_0402_1% PC100 4.7U_0603_10V6K 2 ALW_PWRGD_3V_5V PJP100 PR103 0_0402_5% PR105 30K_0402_1% @EMC@ PL100 1UH_PCMB053T-1R0MS_7A_20% PR102 200K_0402_1% @ 4 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D SCHEMATICS,MB AA913 Document Number Rev A 4019RA Thursday, November 14, 2013 Sheet E 48 of 56 0.675Volt +/‐ 5% TDC 0.7 A Peak Current 1.0 A OCP Current 1.2 A PJP200 1.35V_B+ BOOT_1.35V 0.22U_0603_16V7K S1/D2 PAD VTTGND PGND VTTSNS 20 VTT 19 VLDOIN 18 BOOT UGATE LGATE PU200 21 +V_DDR_REF CS_1.35V 13 PC209 1U_0603_10V6K G2 12 CS GND RT8207MZQW_WQFN20_3X3 VDDP VTTREF +V_DDR_REF PR202 +5V_ALW +1.35V_MEN_P C PC212 0.033U_0402_16V7K FB sense trace when FB pull down to GND FB PC211 1U_0603_10V6K VDDQ +5V_ALW VDD S3 11 S5 VDD_1.35V 5.1_0603_5% TON S2 14 S2 S2 D1 G1 PR201 6.04K_0402_1% 17 16 DL_1.35V PHASE PC204 SW_1.35V 15 PQ201 AON6932A_DFN5X6-8-7 @EMC@ PR203 4.7_1206_5% SNUB_1.35V +0.675V_P @EMC@ PC208 680P_0603_50V7K PC207 220U_D2_2VY_R17M + C +1.35V_MEN_P DH_1.35V Footprint use AON6932A PL200 1.0UH_PCMB104T-1R0MH_18A_20% +VLDOIN_1.35V PAD-OPEN1x1m 2 @EMC@ PC203 2200P_0402_50V7K PC201 10U_0805_25V6K PC200 10U_0805_25V6K @ +1.35V_MEN_P D PJP201 PR200 2.2_0603_5% PC205 22U_0805_6.3V6M PAD-OPEN 1x2m~D PGOOD 10 +PWR_SRC D PR205 8.06K_0402_1% 1.35V_FB PC213 100P_0402_50V8J PR206 1 PR208 0_0402_5% 0.675V_DDR_VTT_ON @ PC215 1U_0402_16V7K SIO_SLP_S3# 10K_0402_1% PR209 PR210 0_0402_5% @ PC214 1U_0402_16V7K SUS_ON 1M_0402_1% B +1.35V_MEM TDC 9.45 A Peak Current 13.5 A OCP Current 16.2 A TYP MAX H/S Rds(on) 6.7mohm , 8.5mohm L/S Rds(on) 2.4mohm , 3.2mohm Choke DCR 3.0mohm , 3.5mohm CAP ESR 17mohm SIO_SLP_S4# 1.35V_B+ S5_1.35V @ PR207 0_0402_5% B @ PR211 0_0402_5% +1.35V_MEN_P Mode S3 S5 +1.35V_MEN +V_DDR_REF +0.675V_P S5 L L off off off S3 L H on on off S0 H H on on on FB sense trace PJP203 1 2 JUMP_1x3m +1.35V_MEN_P A PJP202 PJP204 1 2 +0.675V_P +1.35V_MEM +0.675V_DDR_VTT A JUMP_1x3m PAD-OPEN1x1m DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet 49 of 56 D D PR301 0_0402_5% A_ON PR302 @ 0_0402_5% SIO_SLP_A# EN_+V1.05SP 1M_0402_1% PR303 PJP300 +1.05V_MP 1 +1.05V_M JUMP_43X118 @EMC@ PR305 @EMC@ PC301 4.7_1206_5% 680P_0603_50V7K SNB_1.05V PJP302 PU300 SY8208DQNC_QFN10_3X3 @ PR306 0_0402_5% B @ PC308 22U_0805_6.3VAM PR310 133K_0402_1% @ PR308 0_0402_5% C ILMT_1.05V +3.3V_ALW PC307 22U_0805_6.3VAM LDO PG FB_+V1.05SP BYP +1.05V_MP PC306 47U_0805_6.3V6M +3.3V_ALW PL301 0.68UH +-20% 7.9A ILMT FB ILMT_1.05V SW_+V1.05SP PC305 47U_0805_6.3V6M LX 10 GND PC302 PR312 0.1U_0603_25V7K 0_0603_5% 2BST_+V1.05SP_C BST_+V1.05SP PC304 330P_0402_50V7K BS PR309 1K_0402_5% EN PR307 100K_0402_1% IN PC310 4.7U_0603_6.3V6K C +V1.05SP_B+ 10U_0805_25V6K PC303 PAD-OPEN 1x2m~D @EMC@ PC300 2200P_0402_50V7K PC309 4.7U_0603_6.3V6K +PWR_SRC +1.05V_MEM TDC 6.5 A Peak Current 9.1 A OCP Current 11.0 A TYP MAX Choke DCR 13.0mohm , 14.0mohm B A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet 50 of 56 +3.3V_RUN D D +5V_ALW PJP400 PC400 1U_0402_6.3V6K PU400 PR402 1.54K_0402_1% +1.5V_RUN PAD-OPEN1x1m PC403 0.01U_0402_25V7K VIN PJP401 1.5VSP FB PC401 4.7U_0805_6.3V6K GND PC404 22U_0805_6.3V6M APL5930KAI-TRG_SO8 1 EN +1.5V_VIN PR403 1.74K_0402_1% C C @ PR401 47K_0402_5% 100K_0402_5% @EMC@ PC402 1U_0402_16V7K VOUT PR400 VIN VOUT POK +3.3V_RUN VCNTL PAD-OPEN1x1m +1.5V_RUN TDC 0.47 A Peak Current 0.67 A B B A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet 51 of 56 VREF PR504 +PWR_SRC PJP500 VBAT SLEWA THERM IMON OCP-I B-RAMP F-IMAX O-USR SKIP# PWM1 @ PR516 1.91K_0402_1% PR519 1_0603_5% +3.3V_RUN +3.3V_RUN PWM1 TPS51622RSM_QFN32_4X4 H_VR_READY VIDALERT_N PC509 1U_0603_10V7K +5V_RUN PR512 2.15K_0402_1% CSP1 PC511 0.1U_0402_25V6 VIDSCLK VIDALERT_N VCCSENSE from processor VIDSOUT VSSSENSE PR531 0_0402_5% PR515 3.01K_0402_1% 2 PR514 20K_0402_1% 1 PR529 110_0402_1% PR528 75_0402_1% 2 PR527 54.9_0402_1% B @ 2 VFB +1.05V_VCCST PR520 0_0402_5% H_PROCHOT# TI recommend 1nF 2SKIP# PC514 VIDSCLK 1 PR526 10_0603_1% +5V_ALW PC510 1U_0603_10V7K 2 PR534 0_0402_5% PC507 0.33U_0603_10V7K PC512 1500P_0402_50V7K 1 PR535 4.75K_0402_1% 2 VREF CSD97374CQ4M_SON8_3P5X4P5 PL500 0.15UH_PCME064T-R15MS0R667_36A_20% CORE_SW 47P_0402_50V8J PR523 10K_0402_5% VR_HOT# 4.87K_0402_1% 100P_0402_50V8J PC503 1000P_0402_50V7K C +VCC_CORE 1SKIP#1 PC502 0.068U_0402_16V7K PR521 1 PC505 1U_0603_10V6K @ PC506 PU501 PC504 PGND2 CORE_BOOT PWM BOOT VSW 0.1U_0402_25V6 PGND1 CORE_BOOT_R BOOT_R VDD PR517 VIN SKIP# 0_0603_5% PC513 0.068U_0402_16V7K PH501 10K_0402_1%_TSM0A103F34D1RZ DROP COMP VREF V5A GND VR_HOT# VCLK ALERT# GND 25 26 27 28 29 30 31 32 33 C PR539 0_0402_5% @ PR513 75_0402_1% @EMC@ PC508 680P_0603_50V7K CORE_SW_CSP @EMC@ PR522 4.7_1206_5% 1CORE_SNUB2 VR_ON SKIP# PWM1 PWM2 N/C PGOOD VDD VDIO VIDSOUT CSP1 CSN1 CSN2 CSP2 PU3 N/C GFB VFB VFB CSN1 17 18 19 20 21 22 23 24 H_VR_EN + 2 PU500 +3.3V_RUN +3.3V_RUN 0_0402_5% 16 15 14 13 12 11 10 CSP1 PR536 @EMC@ PC520 2200P_0402_50V7K 2 PC519 100U_D_20VM_R55M 10K_0402_5% GFB @EMC@ PL501 @EMC@PL501 FBMA-L11-453215-121LMA90T_2 PC518 10U_0805_25V6K PR511 PC517 10U_0805_25V6K 1 +VCC_PWR_SRC CORE_BOOT_C +VCC_PWR_SRC PAD-OPEN 4x4m PC516 10U_0805_25V6K 1 PC515 10U_0805_25V6K PR509 D 1 PR508 O-USR 100K_0402_1% PR507 150K_0402_1% 36.5K_0402_1% PR503 681K_0402_1% PR502 75_0402_1% PR501 365K_0402_1% PC500 2 F-IMAX 1 PR510 39K_0402_5%~N B-RAMP PR506 SLEWA @ OCP-I 39K_0402_1% D PC501 1U_0402_16V7K PR505 10K_0402_5% 2 @ PR500 75_0402_1% 4700P_0603_50V7K PH500 IMON 20K_0402_1% 100K_0402_1%_NCP15WF104F03RC B CSN1 PR532 0_0402_5% GFB CPU 15W TDC 10 A Peak Current 32 A OCP Current 38.4 A DC Load line ‐2.0 mV/A Icc_Dyn_VID1 27 A Choke DCR: 0.66m +‐7% ohm PH500 B Value : 4250k 1% PH501 B Value : 3370k 1% A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet 52 of 56 B I_ripple=(19-0.9)*0.9/ (304.89Khz*0.36u*19)=7.811A Vmin= Vvref*[Rref2/(Rref2+Rboot)]*[Rt/(Rref1+Rt)] Vmax=Vvref*Rref2/[(Rref1//Rrefadj)+Rboot+Rref2] Vout=Vmin+N*Vstep OCP=54A/2=27A per phase Ivalley=27A-7.811A/2=23.1A Vstep=(Vmax-Vmin)/Nmax PWM-VID Spec and component Values Config A Config B Config C Vmin 0.6V 0.6V 0.65V Vmax 1.2V 1.2V 1.15V Vboot 0.875V 0.9V 0.9V 6.25mV 6.25mV 25mV Voltage step Module model information: RT8813A_V1A for IC module RT8813A_V1B for SW module N of Voltage level 96 96 20 Rrefadj PR9 39K 20K 39K Rref1 PR5 39K 20K 30K Rboot PR8 1.5K 2K 3K PR10 30K 18K 24K PR12 1.5K 3K PC8 1.5nf 2.7nf Rref2=PR10+PR12 C L-side MOS:TPCA8057 Rds(on): 2.0mohm@Vgs=10V 2.6~3.2mohm@Vgs=4.5V Id :42A@Ta=25 degC H-side MOS:TPCA8065 Rds(on): 11.7mohm@Vgs=10V 9.4mohm@Vgs=4.5V Id :16A@Ta=25 degC Choke: 0.36uH (Size:10*10*4) Rdc=1.1mohm +-5% Heat Rating Current=30A Saturation Current=50A C=3*330uF (9mohm)=990uF Vripple=Iripple*ESR(min)=7.811A*3mohm=23.4mV 1.8nf @ PR601 1K_0402_5% PWM VID and Output voltage control 1.Boot mode 2.Standby mode (don't support) 3.Normal mode D Different VGA Chip (different EDP-Peak Current) need select different solution VGA Chip N14P-GV N14M-GS N14M-LP N14P-LP OpenVReg Configurations Config B Config B Config B Config B Config B Rated TDP Power at Tj=102C 18W 25W 18W 13W 18.9W 25W 25.6W 35.5W Boosted GPU Total at Tj=102C 25W 32W 25W 20W 23W N/A 30W 40W EDP-Continuous at Tj=102C 24A 32A 26A 22A 25A 27A 38A 45A EDP-Peak at Tj=102C 35A 55A 45A 35A 35A 40A 60A 75A Istep max (Evaluation) 15A 27A 25A 20A 14A 12A 31.5A 35A OCP Setting Current 42A 66A 54A 42A 42A 48A 72A 90A Rocset 8.96K 12.45K 10.7K 8.96K 8.96K 9.83K 8.3K N14P-GV2 N14P-GE Config B GPU_PWM_VID 2phase 1H1L 2phase 1H1L 2phase 1H1L 2phase 1H1L 2phase 1H1L 2phase 1H1L 2phase 1H2L 2phase 1H2L Polymer Cap (330uF) 6mohm * 9mohm * 9mohm * 6mohm * 6mohm * 6mohm * 6mohm * (L=0.22uH) 4.5mohm * (L=0.15uH) Or OSCON (390uF) 10mohm * 10mohm * 10mohm * 10mohm * 10mohm * 10mohm * Operation phase Number PSI Voltage setting phase with DEM 0V to 0.8V phase with CCM 1.2V to 1.8V Active phase with CCM 2.4V to 5.5V EMC@ PL600 HCB2012KF-121T50_0805 110C 113.4C 2 U2_PHASE2 U2_LGATE2 19 U2_PWM3 U2_PWM3 21 20 @ PC604 10U_0805_25V6K PC603 10U_0805_25V6K @EMC@ PR613 4.7_1206_5% U2_LGATE1 22 23 + + 2@ @EMC@ PC614 680P_0603_50V7K BOOT2 18 U2_BOOT2 RT8813AGQW_WQFN24_4X4 PC617 0.22U_0603_25V7K PQ601 CSD87351Q5D_SON8-7 PR620 18.7K_0402_1% 1 PC621 10U_0805_25V6K 2 1 +GPU_PWR_SRC PR618 4.7_0603_5% U2_BOOT21 PC620 10U_0805_25V6K PGOOD UGATE2 17 16 VCC/ISNE1 U2_LGATE1 PR615 8.87K_0402_1% BOOT1 EN UGATE1 PSI 1 @EMC@ PC602 2200P_0402_50V7K 1 U2_BOOT1 U2_UGATE1 GPU_EN GPU_VID GPU_PSI VID REFADJ U2_PHASE1 PL602 0.22UH_PCME064T-R22MS0R985_28A_20% U2_PHASE2_C U2_PHASE2 +5V_RUN DGPU_PWROK 106.38C LAGTE2 PHASE2 24 +GPU_CORE U2_LGATE2 @ PR623 10K_0603_5% 2 PC626 1U_0402_6.3V6K +GPU_CORE @EMC@ PR622 4.7_1206_5% PR620=13K PL601 0.22UH_PCME064T-R22MS0R985_28A_20% U2_PHASE1_C 103.1C @EMC@ PC625 680P_0603_50V7K T_max 100C +VGA_CORE EDP-Continuous 32 A EDP-Peak 60 A OCP 72 A CSD87351Q5D_SON8-7 Reserve Location T_typical 96.73C SS PC622 1U_0402_6.3V6K T_min PR620=18.7K PQ600 U2_UGATE1 GPU_SNUB2 PC605 0.22U_0603_25V7K U2_UGATE2 PH600 470K_0402_5%_TSM0B474J4702RE Thermal monitoring: (VGPU_VREF-VTSNS)/PR620=VTSNS/Rth VSNS PVCC U2_UGATE2 GPU_VREF PR617 100_0402_1% VSNS Soft-Start time (Internal) is 0.7ms (PC616 un-pop) Tss=(Css*Vrefin)/Iss+2.3ms =0.01U*0.9V/5uA+2.3ms=4.1ms (PC616 pop) RGND 25 @ PC616 0.01U_0402_25V7K 2 12 LGATE1 GND/PWM3 15 GPU_FB Switching frequency setting: Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p)=304.89Khz PHASE1 TON GPU_DSBL/ISEN1 GPU_COMP 0_0402_5% +GPU_CORE 10 11 @ PC615 47P_0402_50V8J VREF GND TALERT/ISEN2 PR616 TSNS/ISEN3 GPU_FBRTN PR614 100_0402_1% GPU_VDD_SENSE GPU_TON GPU_VREF @PC613 @PC613 0.01UF_0402_25V7K 14 REFIN 13 0_0402_5% GPU_TSNS/ISEN3 1 GPU_VSS_SENSE 3V3_MAIN_EN GPU_SNUB1 GPU_REFIN +PWR_SRC 2 PR606 4.7_0603_5% U2_BOOT1 U2_PHASE1 PU600 PR611 Pull high on HW side PR612 499K_0402_1% +GPU_PWR_SRC NULL PR625 1K_0402_5% GPU_REFADJ PR604 20K_0402_1% PC607 2700P_0402_50V7K PR610 0_0402_5% @ PC606 0.01U_0402_25V7K PR607 18K_0402_1% NVVDD_PSI 0_0402_5% PR603 2K_0402_5% NULL +GPU_PWR_SRC @EMC@ PC601 0.1U_0402_25V6 2 9.39K Recommendation PSI Pull high on HW side PR605 @ PC608 0.1U_0402_25V6 2 Config B 1 0_0402_5% PR600 20K_0402_1% N14P-GT Config B +3.3V_RUN PR602 PC600 1U_0402_6.3V6K N14P-GS PC611 330U_X_2VM_R6M Rt=Rrefadj // (Rboot+Rref2) PWM-VID Spec C Current Limit threshold setting Rocset= (Ivalley * Rds(on) + 40 mV) / 10uA Vboot=Vvref*Rref2/(Rref1+Rref2+Rboot) PC609 330U_X_2VM_R6M A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA D Sheet 53 of 56 A B C D EMC@ PL700 1UH_PCMB053T-1R0MS_7A_20% PR701 0.01_1206_1% +SDC_IN PC700 0.1U_0603_25V7K PAD-OPEN 4x4m D G PQ701 NTR4502PT1G_SOT23-3 D G PQ703A NTGD4161PT1G_TSOP6~D S S D GNDA_CHG ACP 13 CMPOUT 14 16 @ PR728 0_0402_5% /PROCHOT GND CMPIN NC +PWR_SRC PC708 22U_0805_25V6M PC707 22U_0805_25V6M PC705 10U_0805_25V6K PC704 10U_0805_25V6K PR707 100K_0402_1% 23 CHG_LGATE 22 +PWR_SRC /BATPRES CELL SRN /BATDRV PWPD BAT BQ24715URUYR_WQFN28_4x4 21 20 PJP701 19 PR722 4.02K_0402_1% 18 17 PQ704 CSD87351Q5D_SON8-7 PR723 10_0603_1% PC729 1U_0603_25V6K GNDA_CHG CHG_SW1 PAD-OPEN1x1m +VCHGR PR721 0.01_1206_1% 2.2UH_12A_20% 1 PL701 CMPOUT GNDA_CHG PR729 121K_0402_1% @ ISYS SRP 15 /BATPRES PC706 22U_0805_25V6M 1 PR706 100K_0402_1% 2 CSSN_1 ACN LODRV CHG_UGATE CHG_SW CMPIN 29 PBAT_PRES# PHASE 26 27 IADP HIDRV ACOK H_PROCHOT# PR725 100K_0402_1% SDA @EMC@ PR726 4.7_1206_5% BQ24770_REGN GNDA_CHG 10 PR712 2.2_0603_5% 25 CHG_SNUB I_SYS 0_0402_5% BTST PC726 0.1U_0402_25V6 PC727 0.1U_0402_25V6 @ PC728 0.1U_0402_25V6 GNDA_CHG PR717 @ 24 @EMC@ PC721 1000P_0603_50V7K V_SYS 0_0402_5% 0_0402_5% 0_0402_5% REGN ACDET IDCHG @ 1U_0603_10V6K CMSRC SCL PR716 PR718 PR720 PC720 100P_0402_50V8J 2 VCP PC719 100P_0402_50V8J PR715 121K_0402_1% PC718 100P_0402_50V8J 2 ACAV_IN DK_CSS_GC PC710 PC725 10U_0805_25V6K GNDA_CHG BQ24770_REGN Near PL701 PC724 10U_0805_25V6K CHARGER_SMBCLK PR709 0_0402_5% PC723 10U_0805_25V6K CHARGER_SMBDAT @EMC@ PC722 0.1U_0603_25V7K 12 0_0402_5% VCC DOCK_DCIN_IS- @EMC@ PC713 2200P_0402_50V7K 1 0.1U_0402_25V4Z~D PR714 PC712 0.047U_0603_25V7K~D ACDRV 28 +DCIN PC709 10U_0805_25V6K 2 PR710 294K_0402_1% GNDA_CHG PU700 BQ24770_REGN PC711 GNDA_CHG PR713 100K_0402_1% PC702 0.1U_0402_25V6 2 PC703 0.1U_0402_25V6 11 CHARGER_SMBCLK CHARGER_SMBDAT pull up 10K in HW side (R827 R828) PR711 49.9K_0402_1% PC701 1U_0603_25V6K PR708 10_1206_5% G SDMK0340L-7-F_SOD323-2~D +SDC_IN 0_0402_5% D PR703 10K_0402_5% DOCK_DCIN_IS+ PQ703B NTGD4161PT1G_TSOP6~D S PD702 PR705 BAT54CW_SOT323-3 +DC_IN_SS G PR704 0_0402_5% CSSP_1 PC717 22U_0805_25V6M PQ702 NTR4502PT1G_SOT23-3 PD701 S PC716 22U_0805_25V6M 2 0_0402_5% +DOCK_PWR_BAR 1 CSS_GC PC715 22U_0805_25V6M PR702 1 DC_BLOCK_GC 2 PJP700 @ PR700 TYP MAX H/S Rds(on) 7.4mohm , 8.8mohm L/S Rds(on) 2.6mohm , 3.1mohm Choke DCR 5.8mohm , 7.0mohm CHAGER_SRC @ 0_0402_5% +PWR_SRC_AC PC714 22U_0805_25V6M PQ700 SI4835DDY-T1-GE3_SO8 +DC_IN_SS GNDA_CHG GNDA_CHG GNDA_CHG BATDRV# +DC_IN PR737 649K_0402_1% CMPOUT PC737 100P_0402_50V8J PR738 3M_0402_5% CMPIN PR745 100K_0402_1% 1 2 ACAV_IN_NB PR743 0_0402_5% PC741 100P_0402_50V8J PR740 10K_0402_1% +3.3V_ALW 4 DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA D Sheet 54 of 56 DMN66D0LDW-7 2N_SOT363-6~D PQ807A 3301_DSCHRG_FET_GC PU804 TC7SH08FU_SSOP5~D DMN66D0LDW-7 2N_SOT363-6~D O A PR812 0_0402_5% DIS_BAT_PROCHOT# PQ806A B D PR814 330K_0402_5% +DOCK_PWR_BAR PC811 0.01U_0603_25V7K PBAT_PRES# P STSTART_DCBLOCK_GC PQ810 FDS6679AZ-G_SO8 SLICE_BAT_ON PR821 820_0603_5%~D 2 5 SLICE_BAT_ON G 0.47U_0805_25V6K FDS6679AZ-G_SO8 +3.3V_ALW PC805 0.1U_0402_10V7K PR811 0_0402_5% PC807 SLICE_BAT_PRES# DMN66D0LDW-7 2N_SOT363-6~D PQ807B 4 PR817 330K_0402_5% PQ806B 1 PD808 PDS5100H-13_POWERDI5-3 PQ812B DMN66D0LDW-7 2N_SOT363-6~D PBAT_PRES# PQ811 +PBATT PR816 100K_0402_5% PR810 100K_0402_5% DMN66D0LDW-7 2N_SOT363-6~D 2 +3.3V_ALW2 +3.3V_ALW /BATPRES +3.3V_ALW PR808 PQ833B +PWR_SRC_AC TC7SH08FU_SSOP5~D +3.3V_ALW PR803 100K_0402_5% DMN66D0LDW-7 2N_SOT363-6~D PQ833A O A DMN66D0LDW-7 2N_SOT363-6~D B SLICE_BAT_ON PR804 100K_0402_5% SLICE_BAT_PRES# PU801 +3.3V_ALW2 PQ812A DMN66D0LDW-7 2N_SOT363-6~D PR801 100K_0402_5% PR802 100K_0402_5% PC801 0.1U_0402_10V7K 100K_0402_5% PR815 10K_0402_5% 2 PR813 100K_0402_5% PD811 +NBDOCK_DC_IN_SS BATDRV# SDMK0340L-7-F_SOD323-2~D PQ800 SI4835DDY-T1-GE3_SO8 PQ809 SI4835DDY-T1-GE3_SO8 +3.3V_ALW Purpose: Trigger PROCHOT# when active battery is removed from system Allows EC to re-establish system performance for battery next in line +VCHGR D PD800 PDS5100H-13_POWERDI5-3 +PBATT_IN_SS PQ801 NTR4502PT1G_SOT23-3 +BATT_SUM PD807 SDMK0340L-7-F_SOD323-2~D P PD806 PDS5100H-13_POWERDI5-3 G PQ826 FDMC6679AZ_MLP8-5 +3.3V_ALW2 P SLICE_BAT_PRES# C +3.3V_ALW2 1 PR819 100K_0402_5% A D DOCK_DET# G PQ817 DMN65D8LW-7_SOT323-3 ACAV_IN# S PR820 0_0402_5% PR822 PR829 A PR825 0_0402_5% PR851 ACAV_IN 0_0402_5% 37 +3.3V_ALW2 TP 0_0402_5% ERC3 ERC2 CSS_GC DK_CSS_GC ACAV_IN_NB DOCK_AC_OFF_EC 1 PR837 100K_0402_5% PC814 0.1U_0402_10V7K PR850 0_0402_5% PR836 100K_0402_5% PR854 0_0402_5% +DC_IN_SS +PBATT O A SLICE_BAT_PRES# DOCK_DET# PR864 100K_0402_5% PU808 TC7SH08FU_SSOP5~D ACAV_IN# PR872 0_0402_5% 1M_0402_5% ACAV_IN +NBDOCK_DC_IN_SS +3.3V_ALW DOCK_DET# B SLICE_BAT_PRES# @ PR863 0_0402_5% CD3301BRHHR_QFN36_6X6~D PR859 0_0402_5% P33ALW PR858 +3.3V_ALW2 1 +3.3V_ALW2 S D 2 G 3 PR840 100K_0402_5% PQ831 DMN65D8LW-7_SOT323-3 PR852 0_0402_5% PQ822 NTR4502PT1G_SOT23-3 DK_AC_OFF_EN SL_BAT_PRES# +3.3V_ALW2 2 NTR4502PT1G_SOT23-3 PQ830 100K_0402_5% 0_0402_5% PR848 0_0402_5% 3301_ACAV_IN_NB DK_AC_OFF 27 26 25 24 23 22 21 20 19 PR857 EN_DOCK_PWR_BAR D S G PQ825 DMN65D8LW-7_SOT323-3 0_0402_5% A EN_DK_PWRBAR PC817 0.1U_0402_25V4Z~D A PC816 0.047U_0603_25V7M PC815 0.1U_0603_25V7K 10 11 12 13 14 15 16 17 18 PR855 P50ALW PBATT_OFF DK_AC_OFF_EN ACAV_IN_NB GND DK_AC_OFF_EN SL_BAT_PRES# BLKNG_MOSFET_GC NBDK_DCINSS SLICE_BAT_PRES# DC_BLOCK_GC DC_IN SS_GC ERC1 ACAVDK_SRC GND SDC_IN DC_BLK_GC ACAV_IN P33ALW2 0_0402_5% CD3301_SDC_IN ACAVIN P33ALW2 SLICE_BAT_ON PR849 P ERC1 G PR847 0_0402_5% 2 PR845 PD821 SDMK0340L-7-F_SOD323-2~D +SDC_IN PR844 PQ821B DMN66D0LDW-7 2N_SOT363-6~D 100K_0402_5% 10K_0402_5% CD_PBATT_OFF PD816 SDMK0340L-7-F_SOD323-2~D DMN65D8LW-7_SOT323-3 ACAV_DOCK_SRC# +5V_ALW BAT54CW_SOT323-3 PR834 G S B PQ828 PR842 0_0402_5% 2ACAVDK_SRC 100K_0402_5% PU800 DOCK_DET# DOCK_AC_OFF PR843 0_0402_5% D +NBDOCK_DC_IN_SS SLICE_BAT_PRES# PR861 0_0402_5% PQ821A DMN66D0LDW-7 2N_SOT363-6~D PR839 +PBATT P50ALW NC CHARGERVR_DCIN DC_IN_SS DK_PWRBAR GND NC BLK_MOSFET_GC DSCHRG_MOSFET_GC PBatt+ PR846 SOFT_START_GC PD815 CSS_GC DK_CSS_GC ERC3 ERC2 GND PWR_SRC SS_DCBLK_GC EN_DK_PWRBAR P33ALW +3.3V_ALW2 PR853 0_0402_5% PR838 0_0402_5% 36 35 34 33 32 31 30 29 28 PC813 0.1U_0603_50V4Z PD819 SDMK0340L-7-F_SOD323-2~D DOCK_SMB_ALERT# 47_0805_5%~D +DOCK_PWR_BAR PR841 0_0402_5% 3301_DSCHRG_FET_GC CD3301_DCIN 2 PR827 100K_0402_5% 2 DSCHRG_MOSFET_GC PR835 DC_IN_SS DK_PWRBAR +DC_IN_SS +DC_IN PR832 0_0402_5% PR831 0_0402_5% B +3.3V_ALW2 100K_0402_5% PQ813B DMN66D0LDW-7 2N_SOT363-6~D 3 100K_0402_5% S G PQ814 NTR4502PT1G_SOT23-3 1 10K_0402_5% AC_DIS D PQ832 DMN65D8LW-7_SOT323-3 PR826 G PR828 D SLICE_BAT_PRES# 1 G O SLICE_BAT_ON S PQ813A DMN66D0LDW-7 2N_SOT363-6~D PR823 100K_0402_5% B PR830 100K_0402_5% PD820 SDMK0340L-7-F_SOD323-2~D Purpose: Turn on the PQ817 for Slice battery discharge without AC exist 2 PQ818 PU807 TC7SH08FU_SSOP5~D PD814 SDMK0340L-7-F_SOD323-2~D SDMK0340L-7-F_SOD323-2~D PC812 0.1U_0402_10V7K DMN65D8LW-7_SOT323-3 PD813 0_0402_5% +3.3V_ALW2 +3.3V_ALW2 Vth=0.5‐1.5V G S P PR895 +3.3V_ALW PQ829 DMG2301U-7 1P SOT23-3 D PQ816 AO3418_SOT23-3 FDS6679AZ-G_SO8 B O A 10K_0402_5% PD810 SDMK0340L-7-F_SOD323-2~D B O 0.1U_0402_10V7K P 4 PU806 TC7SH08FU_SSOP5~D PQ815 PU805 TC7SH08FU_SSOP5~D PC810 1 1500P_0402_50V7K +3.3V_ALW2 G PR818 @ PC809 100K_0402_5% C Purpose: Turn on the PQ817 for primary or module bay battery to provide power to dock side without AC exist PC808 0.1U_0402_10V7K G @ STSTART_DCBLOCK_GC PR860 0_0402_5% 3301_PWRSRC PR874 1M_0402_5% +PWR_SRC_AC DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC ("DELL") THIS DOCUMENT MAY NOT BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL IN ADDITION, NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT Title SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet 55 of 56 +VCC_CORE D D 2 2 PC922 22U_0805_6.3V6M PC923 22U_0805_6.3V6M PC924 22U_0805_6.3V6M PC953 4.7U_0603_6.3V6K PC952 4.7U_0603_6.3V6K PC912 4.7U_0603_6.3V6K PC911 4.7U_0603_6.3V6K PC910 4.7U_0603_6.3V6K PC917 22U_0805_6.3V6M PC909 4.7U_0603_6.3V6K 1 PC916 22U_0805_6.3V6M PC908 4.7U_0603_6.3V6K 2 PC915 22U_0805_6.3V6M PC921 1U_0402_6.3V PC914 22U_0805_6.3V6M PC913 22U_0805_6.3V6M PC907 4.7U_0603_6.3V6K 2 PC920 1U_0402_6.3V 2 +GPU_CORE PC904 22U_0805_6.3V6M PC906 4.7U_0603_6.3V6K 2 PC903 22U_0805_6.3V6M PC919 1U_0402_6.3V 2 PC902 22U_0805_6.3V6M PC901 22U_0805_6.3V6M PC905 4.7U_0603_6.3V6K 2 PC900 22U_0805_6.3V6M PC918 1U_0402_6.3V 1 nVidia GB4-64 package Under GPU 4.7uF 0603 * 10 1uF 0402 * PC925 22U_0805_6.3V6M PC926 22U_0805_6.3V6M C C PC927 22U_0805_6.3V6M PC928 22U_0805_6.3V6M PC929 22U_0805_6.3V6M @ PC930 22U_0805_6.3V6M @ PC931 22U_0805_6.3V6M nVidia GB4-64 package Near GPU 47uF 0805 *1 22uF 0805 *1 4.7uF 0805 *5 @ PC946 22U_0805_6.3V6M PC942 4.7U_0805_6.3V6K PC937 4.7U_0805_6.3V6K PC936 4.7U_0805_6.3V6K PC935 4.7U_0805_6.3V6K 1 @ PC947 22U_0805_6.3V6M @ PC948 22U_0805_6.3V6M 1 PC934 4.7U_0805_6.3V6K @ PC943 22U_0805_6.3V6M @ PC951 4.7U_0805_6.3V6K PC933 22U_0805_6.3V6M 2 PC941 22U_0805_6.3V6M @ PC950 4.7U_0805_6.3V6K 1 @ 2 PC940 22U_0805_6.3V6M 1 @ PC932 47U_0805_6.3V6M 1 @ PC949 4.7U_0805_6.3V6K +GPU_CORE B B A A DELL CONFIDENTIAL/PROPRIETARY Compal Electronics, Inc Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC SCHEMATICS,MB AA913 Size Document Number Date: Thursday, November 14, 2013 Rev A 4019RA Sheet 56 of 56 ... DDI1_LANE_N0 DDI1_LANE_P0 DDI1_LANE_N1 DDI1_LANE_P1 DDI1_LANE_N2 DDI1_LANE_P2 DDI1_LANE_N3 DDI1_LANE_P3 DDI2_LANE_N0 DDI2_LANE_P0 DDI2_LANE_N1 DDI2_LANE_P1... VDD UL4 LAN_TX0+L +RSVD_VCC3P3_1 RL6 4.7K_0402_5% +3.3V_LAN +3.3V_LAN LAN_TX0-L LAN_TX1+L 15 19 29 LAN_TX1-L +0.9V_LAN LAN_TX2+L 47 46 37 LAN_TX2-L 10 LAN_TX3+L 11 LAN_TX3-L 12 +0.9V_LAN REGCTL_PNP10... close UL4 as possible UL1 1 +3.3V_LAN 39 30 21 14 4 38 37 SW_LAN_TX0+ SW_LAN_TX0- 34 33 SW_LAN_TX1+ SW_LAN_TX1- 29 28 SW_LAN_TX2+ SW_LAN_TX2- 25 24 D SW_LAN_TX3+ SW_LAN_TX3- 17 18 41 SW_ACTLED_YEL#