1104 compal la a041p

A B C D E Compal Confidential Model Name : SAGE 3G Compal Project Name : V1JB1 File Name : LA-A041P Compal Confidential 2 V1JB1 UMA M/B Schematics Document Intel Ivy/Sandy Bridge SFF BGA 1023p Processor /Panther Point 989p PCH / DDR3L Memory Down *8 2013-03-26 3 REV:2.0 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title Cover Page THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC V1JB1 M/B LA-A041P Schematic Date: A B C D Tuesday, March 26, 2013 Sheet E of 52 Rev 2.0 A B C D E DDRIII-ON BOARD Memory BUS(DDR3L) 1 Dual Channel Fan (PWM) Intel Ivy Bridge ULV eDP Conn page 34 page 22 Processor BGA1023 120MHz eDP page 11,12 page 4~10 HDMI Conn FDI x8 page 23 100MHz 100MHz 1GB/s x4 100MHz PCI-Express x (PCIE2.0 5GT/s) port port WLAN Realtek RTS5209 On Board WLAN/BT MD222 page 32 Intel Panther Point-M SATA x (GEN1 1.5GT/S ,GEN2 3GT/S) 100MHz PCH SMLink Camera1 JCMOS1(FRONT) Camera2 JCMOS2(REAR) Sub/Board USB port page 22 USB port 10 page 27 USB port 11 page 33 Ext USB3.0 JUSB1 BT - On Board WLAN 3G Module MU736 USB20 port USB30 port USB port USB port page 24 page 13~21 3.3V 24MHz HDA Codec ALC271X-VB6 SUB/B SPI Sub/Board page 25 SPI ROM (ME-2MB) page 13 PROX SENSOR STM8T143 Connect to page 31 page 27 989pin BGA mSATA Module page 24 Touch Screen JEDP1 3.3V 48MHz USBx14 HD Audio port 0,1 Card Reader DMI x4 2.7GT/s TMDS DDRIII-ON BOARD 1.35V DDR3L 1333 Sub/Board Int Speaker Phone Jack COM_MIC Int MIC Digital MIC page 33 LPC BUS 33MHz EC 3 HSPI RTC CKT ITE IT 8518 page SMLink1 page 13 Power On/Off CKT Sub/Board Sensor Hub STM32F page 30 page 29 DC/DC Interface CKT page 34 Power Circuit DC/DC page 35~46 I2C1 Sub/Board ALS CM3218 page 30 TPM SLB9655 page 26 28 WLAN Frequency : 802.11b/g/n : 2.412 ~ 2.4835 GHz 802.11a/n : 5.15 ~ 85GHz BT Frequency : 2.402~2.480 GHz USB Port SMBUS1 FSPI Battery Charger IC WWAN: WCDMA/HSDPA/HSUPA/HSPA+: 850 MHz/900 MHz/1700 MHz(AWS)/1900 MHz/2100 MHz GPRS/EDGE: 850 MHz/900 MHz/1800 MHz/1900 MHz GPS: L1 page 36, 37 ACCEL with E-COMPASS LSM303D GYRO L3GD20TR page 30 SPI ROM (BIOS+EC) (4MB)page 28 SMBUS2 Thermal Sensor page 11 page 30 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title Block Diagrams THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC V1JB1 M/B LA-A041P Schematic Date: A B C D Tuesday, March 26, 2013 Sheet E of 52 Rev 0.1 A B C D Voltage Rails Power Plane Description S1 S3 S5 VIN Adapter power supply (19V) N/A N/A N/A BATT+ Battery power supply (12.6V) N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF +VGFX_CORE Core voltage for UMA graphic ON OFF OFF +1.05VS_VTT +1.05VS_VTTP to +1.05VS_VTT switched power rail for CPU ON OFF OFF +1.05VS_PCH +1.05VS_VTT to +1.05VS_PCH power for PCH ON OFF OFF +1.35V +1.35VP to +1.35V power rail for DDR3L ON ON OFF +1.35VS +1.35V to +1.35VS switched power rail ON OFF OFF +0.675VS +0.675VSP to +0.675VS switched power rail for DDR3L terminator ON OFF OFF +1.5VS +1.5VSP to +1.5VS power rail for PCH ON OFF OFF +1.8VS (+5VALW or +3VALW) to 1.8VS switched power rail for PCH ON OFF OFF +3VALW +3VALWP to +3VALW always on power rail ON ON ON* +VCCSUS3_3 +3VALW to +VCCSUS3_3 power rail for PCH ON ON ON* +3VS +3VALW to +3VS power rail ON OFF OFF +5VALW +5VALWP to +5VALW always on power rail ON ON ON* +VALW +V +VS Clock HIGH HIGH HIGH HIGH ON ON ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Full ON +V5REF_SUS +5VALW to +V5REF_SUS power rail for PCH ON ON ON* +5VS +5VALW to +5VS switched power rail ON OFF OFF +VSB +VSBP to +VSB always on power rail for sequence control ON ON ON* +RTCVCC RTC power ON ON ON SLP_S1# SLP_S3# SLP_S4# SLP_S5# Vcc Ra/Rc/Re 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BOARD ID Table Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF EC SM Bus1 address Device Address Smart Battery 0001 011X b PCH SM Bus address Device EC SM Bus2 address Device Sensor HUB SM Bus address Address Device ChannelA A0 1010 000X Gyroscope ChannelB A4 1010 010X Address Address D1 1101 000X b D3 1101 001X b E-compass + G sensor 33 0011 001X b ALS sensor 21 0010 000X b BOM Config Board ID Note : USB Port Table USB 2.0 USB 1.1 Port UHCI1 Sensors List EHCI1 Function Gyroscope Accel+E-Compass Sensor Hub ALS Prox Device ST - L3GD20TR ST - LSM303DLHCTR ST - STM32F103RCY6TR Capella - CM3218 ST-STM8T143AU62TTRC06 UHCI2 UHCI3 UHCI4 EHCI2 UHCI5 UHCI6 10 11 12 13 External USB Port Sensor Hub Ext USB Connector 3G Module - MU736/ME906 Touch Screen BlueTooth(WLAN Module) Debug Port(Reserve) Camera(Front) Camera(Rear) BTO Item BOM Structure Unpop @ Connector CONN@ UMA UMA@ CPU IVB@ DDR3 DDR3@ DDR3L DDR3L@ On Board DRAM X76@ Dual Channel DDR 128@ eDP eDP@ PCH HM77@ Normal S3 S3@ Deep S3 DS3@ TPM TPM@ Non TPM SKU WOTPM@ Hall Sensor LID@ Foxconn MD222 FOXMD222@ Lite-On MD222 LIONMD222@ For EMI/RF(Pop) EMC@ For EMI/RF(Unpop) XEMC@ Sensor(Intel F/W) INTEL@ Sensor(ST F/W) ST@ 3G@ 3G SKU 3G SKU(EMC part) 3GEMC@ 2011/06/24 Compal Electronics, Inc Compal Secret Data Security Classification Issued Date BTO Option Table PCB Revision 0.1 0.2 0.3 1.0 2.0* UHCI0 Connect to Sensor Hub Sensor Hub PCH(USB P3) Sensor Hub EC Board ID / SKU ID Table for AD channel Board ID SIGNAL STATE E 2012/06/02 Deciphered Date Title Notes List THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E of 52 Rev 0.1 A B C D E +1.05VS_VTT PEG_ICOMPI and RCOMPO signals should be shorted and routed with - max length = 500 mils - typical impedance = 43 mohms R532 24.9_0402_1% 15 15 15 15 DMI_CRX_PTX_P0 DMI_CRX_PTX_P1 DMI_CRX_PTX_P2 DMI_CRX_PTX_P3 N3 P7 P3 P11 15 15 15 15 DMI_CTX_PRX_N0 DMI_CTX_PRX_N1 DMI_CTX_PRX_N2 DMI_CTX_PRX_N3 15 15 15 15 DMI_CTX_PRX_P0 DMI_CTX_PRX_P1 DMI_CTX_PRX_P2 DMI_CTX_PRX_P3 15 15 15 15 15 15 15 15 FDI_CTX_PRX_N0 FDI_CTX_PRX_N1 FDI_CTX_PRX_N2 FDI_CTX_PRX_N3 FDI_CTX_PRX_N4 FDI_CTX_PRX_N5 FDI_CTX_PRX_N6 FDI_CTX_PRX_N7 15 15 15 15 15 15 15 15 FDI_CTX_PRX_P0 FDI_CTX_PRX_P1 FDI_CTX_PRX_P2 FDI_CTX_PRX_P3 FDI_CTX_PRX_P4 FDI_CTX_PRX_P5 FDI_CTX_PRX_P6 FDI_CTX_PRX_P7 U7 W11 W1 AA6 W6 V4 Y2 AC9 U6 W10 W3 AA7 W7 T4 AA3 AC8 AA11 AC12 U11 15 FDI_INT R118 24.9_0402_1% Add eDP circuit W=4mil,S=15mil,L=500mil EDP_HPD# AF3 AD2 AG11 AG4 AF4 22 EDP_AUXN 22 EDP_AUXP AC3 AC4 AE11 AE7 22 EDP_TXN0 22 EDP_TXN1 AC1 AA4 AE10 AE6 22 EDP_TXP0 22 EDP_TXP1 R809 1K_0402_5% EDP_COMP EDP_HPD# DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] FDI0_TX#[0] FDI0_TX#[1] FDI0_TX#[2] FDI0_TX#[3] FDI1_TX#[0] FDI1_TX#[1] FDI1_TX#[2] FDI1_TX#[3] FDI0_TX[0] FDI0_TX[1] FDI0_TX[2] FDI0_TX[3] FDI1_TX[0] FDI1_TX[1] FDI1_TX[2] FDI1_TX[3] FDI0_FSYNC FDI1_FSYNC FDI_INT FDI0_LSYNC FDI1_LSYNC eDP_COMPIO eDP_ICOMPO eDP_HPD# eDP_AUX# eDP_AUX eDP +1.05VS_VTT AA10 AG8 15 FDI_LSYNC0 15 FDI_LSYNC1 W=12mil,S=15mil,L=500mil 22 EDP_HPD# K3 M7 P4 T3 15 FDI_FSYNC0 15 FDI_FSYNC1 eDP@ K1 M8 N4 R2 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] PCI EXPRESS GRAPHICS M2 P6 P1 P10 Intel(R) FDI +1.05VS_VTT eDP_COMPIO and ICOMPO signals should be shorted near balls and routed with typical impedance PEG NC G22 C23 D23 F21 H19 C17 K15 F17 F14 A15 J14 H13 M10 F10 D9 J4 F22 A23 D24 E21 G19 B18 K17 G17 E14 C15 K13 G13 K10 G10 D8 K4 IVY-BRIDGE_BGA1023 IVB@ CPU P/N: 1.I3-3217 SA00005L5C0:S IC AV8063801058401 SR0N9 L1 1.8G ABO! 2.I5-3317 SA00005K6B0:S IC AV8063801058002 SR0N8 L1 1.7G ABO! 3.I3-2365 SA000051H60:S IC AV8062701047904 SR0CV J1 1.4G ABO! 4 Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 Issued Date Deciphered Date 2012/06/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title PROCESSOR(1/7) DMI,FDI,PEG Size Document Number Custom Rev 0.1 V1JB1 M/B LA-A041P Schematic Date: Sheet W ednesday, March 13, 2013 E of 52 A B C D E 1 UCPU1B 17 H_SNB_IVB# Follow DG 1.2 & CRB1.0 C57 T1 @ PAD H_CATERR# C49 H_PECI A48 PROC_DETECT# @ 0.1U_0201_10V6K H_CPUPWRGD 10K_0402_5% H_CPUPWRGD Processor Pullups follow CRB1.0 R223 R220 +1.05VS_VTT 28 H_PECI 62_0402_5% H_PROCHOT# 28,36 H_PROCHOT# R216 56_0402_5% H_PROCHOT#_R D45 18 H_THRMTRIP# Follow DG 1.2 & CRB1.0 +3VS SAGE 3G P R227 43_0402_1% BUFO_CPU_RST# R80 18 H_CPUPWRGD UNCOREPWRGOOD: BUF_CPU_RST# 0_0402_5% H_CPUPWRGD_R B46 @ 除除CPU_CORE以以以以OK PM_DRAM_PWRGD_R G RESET#: C48 15 H_PM_SYNC R226 75_0402_5% BE45 都ok後後CPU做reset BUF_CPU_RST# SAGE 3G D44 +1.05VS_VTT CLK_CPU_DPLL 14 CLK_CPU_DPLL# 14 CLK_CPU_DPLL# R116 @ 1K_0402_5% CLK_CPU_DPLL R117 @ 1K_0402_5% SM_DRAMRST# BF44 BE43 BG43 SM_RCOMP0 R149 SM_RCOMP1 R486 SM_RCOMP2 R484 SM_DRAMRST# 2 140_0402_1% 25.5_0402_1% 200_0402_1% DDR3 Compensation Signals Trace:10mil ,Spacing:13mil, Max.Length:500mil PM_SYNC UNCOREPWRGOOD SM_DRAMPWROK SM_DRAMPWROK:DRAM power ok SN74LVC1G07DCKR_SC70-5 CLK_CPU_DPLL CLK_CPU_DPLL# AT30 THERMTRIP# TCK TMS TRST# C396 0.1U_0402_16V4Z Y A SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] +1.05VS_VTT U15 NC 17,26,28,31,32 PLT_RST# SM_DRAMRST# PRDY# PREQ# PROCHOT# PWR MANAGEMENT PECI Use open drain MOS: +1.05VS_VTT PH pop 75ohm series resister pop 43ohm Buffered reset to CPU C45 AG3 AG1 CLK_CPU_DMI 14 CLK_CPU_DMI# 14 Checklist1.0 P.64 Processor Graphis Disable Guide DIS only SKU or UMA eDP disable DPLL_REF_SSCLK PD 1K_5% to GND DPLL_REF_SSCLK# PH 1K_5% to +1.05VS_VTT RESET# JTAG & BPM C784 DPLL_REF_CLK DPLL_REF_CLK# J3 H2 CATERR# THERMAL 偵偵CPU有有有有 XBOX 三三三三 PROC_SELECT# BCLK BCLK# CLOCKS F49 DDR3 MISC 外外外 PCH->CPU UNCOREPWRGOOD: CORE OK SM_DRAMPWROK:DRAM power ok RESET#: ok CPU reset MISC 非 都 後後 做 PROC_SELECT# Future platforms,PH VCPLL and connect to PCH DF_TVS TDI TDO N53 N55 L56 L55 J58 XDP_TCK XDP_TMS XDP_TRST# @ PAD @ PAD @ PAD T2 T3 T4 M60 L59 XDP_TDI XDP_TDO @ PAD @ PAD T5 T6 K58 XDP_DBRESET# +3VS DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] XDP_DBRESET# R569 XDP_DBRESET# 15 G58 E55 E59 G55 G59 H60 J59 J61 1K_0402_5% CRB1.0 PH 1K +3VS Check list 1.0 PH 5K +3VS Check list 1.2 PH 10K +3VS Debug port DG1.1-1.2 50~5K ohm SAGE 3G C102 XEMC@ 100P_0402_50V8J For EMI IVY-BRIDGE_BGA1023 IVB@ 3 +3VALW Follow DG 1.2 & CRB1.0 1 C101 0.1U_0402_16V4Z +1.35VS R88 200_0402_5% 0_0402_5% R81 @ 0_0402_5% B A Y 15 PM_DRAM_PWRGD U5 @ P G 15 SYS_PWROK R82 2 28,42 VR_ON Use open drain MOS: +1.35VS PH pop 200ohm series resister pop 130ohm PM_SYS_PWRGD_BUF R97 130_0402_5% PM_DRAM_PWRGD_R MC74VHC1G09DFT2G_SC70-5 SAGE 3G 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title PROCESSOR(2/7) PM,XDP,CLK THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E of 52 Rev 0.1 A B C D UCPU1C UCPU1D 12 DDR_B_D[0 63] BD37 BF36 BA28 11 DDR_A_BS0 11 DDR_A_BS1 11 DDR_A_BS2 AT40 AU40 BB26 DDR_A_CLK1 DDR_A_CLK1# R263 75_0402_1% DDR_A_CKE1 11 SA_CS#[0] SA_CS#[1] BB40 BC41 DDR_A_CS0# 11 DDR_A_CS1# 11 SAGE 3G PVT SA_ODT[0] SA_ODT[1] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] SA_CAS# SA_RAS# SA_WE# AY40 BA41 DDR_A_ODT0 11 DDR_A_ODT1 11 AL11 AR8 AV11 AT17 AV45 AY51 AT55 AK55 DDR_A_DQS#0 DDR_A_DQS#1 DDR_A_DQS#2 DDR_A_DQS#3 DDR_A_DQS#4 DDR_A_DQS#5 DDR_A_DQS#6 DDR_A_DQS#7 DDR_A_DQS#[0 7] 11 AJ11 AR10 AY11 AU17 AW45 AV51 AT56 AK54 DDR_A_DQS0 DDR_A_DQS1 DDR_A_DQS2 DDR_A_DQS3 DDR_A_DQS4 DDR_A_DQS5 DDR_A_DQS6 DDR_A_DQS7 DDR_A_DQS[0 7] 11 BG35 BB34 BE35 BD35 AT34 AU34 BB32 AT32 AY32 AV32 BE37 BA30 BC30 AW41 AY28 AU26 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 DDR_A_MA[0 15] 11 BG39 BD42 AT22 12 DDR_B_BS0 12 DDR_B_BS1 12 DDR_B_BS2 AV43 BF40 BD45 12 DDR_B_CAS# 12 DDR_B_RAS# 12 DDR_B_WE# IVY-BRIDGE_BGA1023 IVB@ SB_CK[0] SB_CK#[0] SB_CKE[0] BA34 AY34 AR22 DDR_B_CLK0 12 DDR_B_CLK0# 12 DDR_B_CKE0 12 SB_CK[1] SB_CK#[1] SB_CKE[1] BA36 BB36 BF27 DDR_B_CLK1 DDR_B_CLK1# R264 75_0402_1% DDR_B_CKE1 12 SB_CS#[0] SB_CS#[1] BE41 BE47 DDR_B_CS0# 12 DDR_B_CS1# 12 SAGE 3G PVT SB_ODT[0] SB_ODT[1] SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] SB_BS[0] SB_BS[1] SB_BS[2] SB_CAS# SB_RAS# SB_WE# AT43 BG47 DDR_B_ODT0 12 DDR_B_ODT1 12 AL3 AV3 BG11 BD17 BG51 BA59 AT60 AK59 DDR_B_DQS#0 DDR_B_DQS#1 DDR_B_DQS#2 DDR_B_DQS#3 DDR_B_DQS#4 DDR_B_DQS#5 DDR_B_DQS#6 DDR_B_DQS#7 DDR_B_DQS#[0 7] 12 AM2 AV1 BE11 BD18 BE51 BA61 AR59 AK61 DDR_B_DQS0 DDR_B_DQS1 DDR_B_DQS2 DDR_B_DQS3 DDR_B_DQS4 DDR_B_DQS5 DDR_B_DQS6 DDR_B_DQS7 DDR_B_DQS[0 7] 12 BF32 BE33 BD33 AU30 BD30 AV30 BG30 BD29 BE30 BE28 BD43 AT28 AV28 BD46 AT26 AU22 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 DDR_B_MA[0 15] 12 Address 0~13:For 128*16 Address 0~14:For 256*16 Address 0~15:For 512*16 IVY-BRIDGE_BGA1023 IVB@ +1.35V Follow CRB1.0 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] DDR_A_CLK0 11 DDR_A_CLK0# 11 DDR_A_CKE0 11 AL4 AL1 AN3 AR4 AK4 AK3 AN4 AR1 AU4 AT2 AV4 BA4 AU3 AR3 AY2 BA3 BE9 BD9 BD13 BF12 BF8 BD10 BD14 BE13 BF16 BE17 BE18 BE21 BE14 BG14 BG18 BF19 BD50 BF48 BD53 BF52 BD49 BE49 BD54 BE53 BF56 BE57 BC59 AY60 BE54 BG54 BA58 AW59 AW58 AU58 AN61 AN59 AU59 AU61 AN58 AR58 AK58 AL58 AG58 AG59 AM60 AL59 AF61 AH60 AU36 AV36 AY26 SA_CK[1] SA_CK#[1] SA_CKE[1] SA_BS[0] SA_BS[1] SA_BS[2] BE39 BD39 AT41 11 DDR_A_CAS# 11 DDR_A_RAS# 11 DDR_A_WE# SA_CK[0] SA_CK#[0] SA_CKE[0] DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] DDR SYSTEM MEMORY A AG6 AJ6 AP11 AL6 AJ10 AJ8 AL8 AL7 AR11 AP6 AU6 AV9 AR6 AP8 AT13 AU13 BC7 BB7 BA13 BB11 BA7 BA9 BB9 AY13 AV14 AR14 AY17 AR19 BA14 AU14 BB14 BB17 BA45 AR43 AW48 BC48 BC45 AR45 AT48 AY48 BA49 AV49 BB51 AY53 BB49 AU49 BA53 BB55 BA55 AV56 AP50 AP53 AV54 AT54 AP56 AP52 AN57 AN53 AG56 AG53 AN55 AN52 AG55 AK56 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 DDR SYSTEM MEMORY B 11 DDR_A_D[0 63] E 通通DIMM做reset SAGE 3G DVT R66 1K_0402_5% CPU DIMM_DRAMRST#_R Q6 BSS138_NL_SOT23-3 SM_DRAMRST# D S SM_DRAMRST# G R79 4.99K_0402_1% 14 DRAMRST_CNTRL_PCH 28 DRAMRST_CNTRL_EC R413 DS3@ 0_0402_5% C78 047U_0402_16V7K SAGE 3G R63 1K_0402_5% DIMM_DRAMRST# 11,12 S0 DRAMRST_CNTRL_PCH hgih ,MOS ON SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH Dimm not reset S3 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# Low,DDR3 DRAMRST# HIGH Dimm not reset S4,S5 DRAMRST_CNTRL_PCH Low ,MOS OFF SM_DRAMRST# Low,DDR3 DRAMRST# Low Dimm reset Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC V1JB1 M/B LA-A041P Schematic Date: A B PROCESSOR(3/7) DDRIII C D Wednesday, March 13, 2013 Sheet E of 52 Rev 0.1 A B C D E Default "1",EDS R1.0 P.88 CFG Straps for Processor UCPU1E CFG2 +CPU_CORE CFG4 CFG5 CFG6 CFG7 1 R810 @ 49.9_0402_1% VCC_VAL_SENSE VSS_VAL_SENSE R812 @ 49.9_0402_1% H43 K43 VCC_VAL_SENSE VSS_VAL_SENSE H45 K45 VAXG_VAL_SENSE VSSAXG_VAL_SENSE +VGFX_CORE F48 PAD @ VCC_VAL_SENSE VSS_VAL_SENSE VAXG_VAL_SENSE VSSAXG_VAL_SENSE VCC_DIE_SENSE BCLK_ITP BCLK_ITP# RSVD30 RSVD31 RSVD32 RSVD33 RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39 RSVD40 RSVD41 RSVD42 RSVD43 RSVD44 RSVD45 N59 N58 CLK_RES_ITP 14 CLK_RES_ITP# 14 1: Normal Operation; Lane # definition matches socket pin map definition CFG2 * N42 L42 L45 L47 0:Lane Reversed CFG2 M13 M14 U14 W14 P13 R234 1K_0402_1% AT49 K24 eDP enable AH2 AG13 AM14 AM15 CFG4 * 1:Disable 0:Enable N50 T56 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] B50 C51 B54 D53 A51 C53 C55 H49 A55 H51 K49 K53 F53 G53 L51 F51 D52 L53 CFG0 PAD @ RESERVED T72 PEG Static Lane Reversal - CFG2 is for the 16x IVY-BRIDGE_BGA1023 IVB@ CFG4 DC_TEST_C4_D3 eDP@ R204 1K_0402_1% DC_TEST_A59_C59 A4 C4 D3 D1 A58 A59 C59 A61 C61 D61 BD61 BE61 BE59 BG61 BG59 BG58 BG4 BG3 BE3 BG1 BE1 BD1 DC_TEST_A61_C61 PCIE Port Bifurcation Straps DC_TEST_BE59_BE61 DC_TEST_BG59_BG61 CFG[6:5] (Default) 1x16 PCI Express *11: 10: 2x8 PCI Express 01: Reserved DC_TEST_BE3_BG3 00: 1x8,2x4 PCI Express DC_TEST_BE1_BG1 These pins are for solder joint reliability and non-critical to function For BGA only CFG6 CFG5 1 R813 @ 49.9_0402_1% RSVD8 RSVD9 RSVD10 RSVD11 RSVD12 RSVD13 RSVD14 RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 DC_TEST_A4 DC_TEST_C4 DC_TEST_D3 DC_TEST_D1 DC_TEST_A58 DC_TEST_A59 DC_TEST_C59 DC_TEST_A61 DC_TEST_C61 DC_TEST_D61 DC_TEST_BD61 DC_TEST_BE61 DC_TEST_BE59 DC_TEST_BG61 DC_TEST_BG59 DC_TEST_BG58 DC_TEST_BG4 DC_TEST_BG3 DC_TEST_BE3 DC_TEST_BG1 DC_TEST_BE1 DC_TEST_BD1 VSSAXG_VAL_SENSE BA19 AV19 AT21 BB21 BB19 AY21 BA22 AY22 AU19 AU21 BD21 BD22 BD25 BD26 BG22 BE22 BG26 BE26 BF23 BE24 R230 1K_0402_1% @ @ VAXG_VAL_SENSE RSVD6 RSVD7 H48 K48 R811 @ 49.9_0402_1% PEG DEFER TRAINING CFG7 R228 1K_0402_1% CRB1.0 P.12 1: (Default) PEG Train immediately following xxRESETB de assertion 0: PEG Wait for BIOS for training CFG7 R224 1K_0402_1% @ Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 Issued Date Deciphered Date 2012/06/02 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title PROCESSOR(4/7) RSVD,CFG Size Document Number Custom Rev 0.1 V1JB1 M/B LA-A041P Schematic Date: Sheet W ednesday, March 13, 2013 E of 52 A B C UCPU1F ULV SC/DC 33A D POWER E 8.5A +1.05VS_VTT VCCIO[1] VCCIO[3] VCCIO[4] VCCIO[5] VCCIO[6] VCCIO[7] VCCIO[8] VCCIO[9] VCCIO[10] VCCIO[11] VCCIO[12] VCCIO[13] VCCIO[14] VCCIO[15] VCCIO[16] VCCIO[17] VCCIO[18] VCCIO[19] VCCIO[20] VCCIO[21] VCCIO[22] VCCIO[23] VCCIO[24] VCCIO[25] VCCIO[26] VCCIO[27] VCCIO[28] VCCIO[29] INTEL Recommend VCCIO PD 0.9 330uF 1+1 10uF (0603) *5 1uF (0201) *16 +1.05VS_VTT AA14 AA15 AB17 AB20 AC13 AD16 AD18 AD21 AE14 AE15 AF16 AF18 AF20 AG15 AG16 AG17 AG20 AG21 AJ14 AJ15 330uF 10uF (0603) *5 1uF (0201) *10 +3VALW VCCIO_SEL For 2012 CPU support R521 10K_0402_5% +1.05VS_VTT A19 W16 W17 BC22 : +1.05VS_VTT 0: +1.0VS_VTT VCCIO_SEL R520 10K_0402_5% VCCIO_SEL * VCCIO50 VCCIO51 VCCIO[30] VCCIO[31] VCCIO[32] VCCIO[33] VCCIO[34] VCCIO[35] VCCIO[36] VCCIO[37] VCCIO[38] VCCIO[39] VCCIO[40] VCCIO[41] VCCIO[42] VCCIO[43] VCCIO[44] VCCIO[45] VCCIO[46] VCCIO[47] VCCIO[48] VCCIO[49] VCCIO_SEL_R @ 2 AF46 AG48 AG50 AG51 AJ17 AJ21 AJ25 AJ43 AJ47 AK50 AK51 AL14 AL15 AL16 AL20 AL22 AL26 AL45 AL48 AM16 AM17 AM21 AM43 AM47 AN20 AN42 AN45 AN48 R582 @ 0_0402_5% +1.05VS_VTT +1.05VS_VTT VCCPQE[1] VCCPQE[2] AM25 AN22 C951 1U_0402_6.3V6K R574 130_0402_5% VIDALERT# VIDSCLK VIDSOUT A44 B43 C44 R576 R577 R578 H_CPU_SVIDALRT# H_CPU_SVIDCLK H_CPU_SVIDDAT VR_SVID_ALRT# 42 VR_SVID_CLK 42 VR_SVID_DAT 42 +CPU_CORE VCC_SENSE VSS_SENSE F43 VCCSENSE_R G43 VSSSENSE_R R579 R581 0_0402_5% 0_0402_5% @ @ R588 100_0402_1% Place the PU,PD resistors close to CPU VCCSENSE 42 VSSSENSE 42 R107 AN16 AN17 10_0402_5% VCCIO_SENSE VSSIO_SENSE VCCIO_SENSE VCCIO_SENSE VSS_SENSE_VCCIO +1.05VS_VTT R589 100_0402_1% 40 Check List R1.5 VCCSENSE:100ohm ±1% pull-up to VCC near processor VSSSENSE:100ohm ±1% pull-down to GND near processor SENSE LINES 43_0402_1% 0_0402_5% 0_0402_5% @ @ SVID 2 Check List R1.5 VIDALERT#:75ohm ±5% pull-up to VCCIO close to IMVP7 VIDSCLK: 55ohm ±5% pull-up to VCCIO close to IMVP7 VIDSOUT: 130ohm ±5% pull-up to VCCIO close to CPU 130ohm ±5% pull-up to VCCIO close to IMVP7 SAGE 3G 1 VCC[1] VCC[2] VCC[3] VCC[4] VCC[5] VCC[6] VCC[7] VCC[8] VCC[9] VCC[10] VCC[11] VCC[12] VCC[13] VCC[14] VCC[15] VCC[16] VCC[17] VCC[18] VCC[19] VCC[20] VCC[21] VCC[22] VCC[23] VCC[24] VCC[25] VCC[26] VCC[27] VCC[28] VCC[29] VCC[30] VCC[31] VCC[32] VCC[33] VCC[34] VCC[35] VCC[36] VCC[37] VCC[38] VCC[39] VCC[40] VCC[41] VCC[42] VCC[43] VCC[44] VCC[45] VCC[46] VCC[47] VCC[48] VCC[49] VCC[50] VCC[51] VCC[52] VCC[53] VCC[54] VCC[55] VCC[56] VCC[57] VCC[58] VCC[59] VCC[60] VCC[61] VCC[62] VCC[63] VCC[64] VCC[66] VCC[67] VCC[68] VCC[69] VCC[70] VCC[71] VCC[72] VCC[73] VCC[74] VCC[75] VCC[76] QUIET RAILS A26 A29 A31 A34 A35 A38 A39 A42 C26 C27 C32 C34 C37 C39 C42 D27 D32 D34 D37 D39 D42 E26 E28 E32 E34 E37 E38 F25 F26 F28 F32 F34 F37 F38 F42 G42 H25 H26 H28 H29 H32 H34 H35 H37 H38 H40 J25 J26 J28 J29 J32 J34 J35 J37 J38 J40 J42 K26 K27 K29 K32 K34 K35 K37 K39 K42 L25 L28 L33 L36 L40 N26 N30 N34 N38 CORE SUPPLY INTEL Recommend VCC 3*330uF,12*22uF(0805),16*2.2uF(0402) PD0.9 PEG IO AND DDR IO +CPU_CORE R105 10_0402_5% IVY-BRIDGE_BGA1023 IVB@ Compal Electronics, Inc Compal Secret Data Security Classification Issued Date Should change to connect from power cirucit & layout differential with VCCIO_SENSE 2011/06/24 2012/06/02 Deciphered Date Title PROCESSOR(5/7) PWR,BYPASS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E of 52 Rev 0.1 B ULV SC/DC GT1: 18A GT2: 33A C1181 2 C1179 1U_0402_6.3V6K C1180 1U_0402_6.3V6K C607 330U_B2_2VM_R15M SGA00004700 1U_0402_6.3V6K 1 2 C997 10U_0603_6.3V6M C996 10U_0603_6.3V6M C995 10U_0603_6.3V6M INTEL Recommend VCCSA 1*330uF,5*10uF(0603) ,5*1uF(0402) PD0.9 1 2 + C599 330U_B2_2VM_R15M SGA00004700 C970 C987 C989 @ 2 @ 2 C990 C998 SAGE 3G C999 1 @ 2 C979 C978 Place BOT OUT Conn 6A L17 L21 N16 N20 N22 P17 P20 R16 R18 R21 U15 V16 V17 V18 V21 W20 VCCPLL[1] VCCPLL[2] VCCPLL[3] VCCSA[1] VCCSA[2] VCCSA[3] VCCSA[4] VCCSA[5] VCCSA[6] VCCSA[7] VCCSA[8] VCCSA[9] VCCSA[10] VCCSA[11] VCCSA[12] VCCSA[13] VCCSA[14] VCCSA[15] VCCSA[16] QUIET RAILS SENSE LINES VCCDQ[1] VCCDQ[2] AM28 AN26 SAGE 3G VDDQ_SENSE VSS_SENSE_VDDQ BC43 BA43 VCCSA_VID For 2012 future CPU VCCSA voltage select SAGE 3G VCCSA_SENSE VCCSA_VID[0] VCCSA_VID[1] U10 @ VCCSA_SENSE CPU EDS1.3 P.93 VCCSA_VID0 Must PD D48 D49 H_VCCSA_VID0 H_VCCSA_VID1 VCCSA T55 PAD H_VCCSA_VID0 H_VCCSA_VID1 VID0 VID1 Vout SNB IVB ULV 0 0.9V V V V 0.8V V V 0.725V X V V 1 0.675V X V V 41 41 R129 0_0402_5% @ 0.85V V IVY-BRIDGE_BGA1023 IVB@ VREF - 1.5V RAILS DDR3 GRAPHICS BB3 BC1 BC4 1.8V RAIL 1.2A SENSE LINES SAGE 3G +VCCSA + VAXG_SENSE VSSAXG_SENSE VCCSA VID lines +VCCSA C977 +1.35VS 10U_0603_6.3V6M Short for +1.35VS to +1.35V_CPU_VDDQ 10U_0603_6.3V6M INTEL Recommend VDDQ 1*330uF,8*10uF(0603) ,10*1uF(0402) PD0.9 10U_0603_6.3V6M C606 220U_B2_2.5VM_R15M SGA00004I00 @ R68 1K_0402_1% SAGE 3G AJ28 AJ33 AJ36 AJ40 AL30 AL34 AL38 AL42 AM33 AM36 AM40 AN30 AN34 AN38 AR26 AR28 AR30 AR32 AR34 AR36 AR40 AV41 AW26 BA40 BB28 BG33 R540 1K_0402_1% 5A VDDQ[1] VDDQ[2] VDDQ[3] VDDQ[4] VDDQ[5] VDDQ[6] VDDQ[7] VDDQ[8] VDDQ[9] VDDQ[10] VDDQ[11] VDDQ[12] VDDQ[13] VDDQ[14] VDDQ[15] VDDQ[16] VDDQ[17] VDDQ[18] VDDQ[19] VDDQ[20] VDDQ[21] VDDQ[22] VDDQ[23] VDDQ[24] VDDQ[25] VDDQ[26] C647 0.1U_0402_16V4Z 10U_0603_6.3V6M + C584 1U_0402_6.3V6K 100_0402_5% +1.8VS_VCCPLL R500 0_0805_5% @ SA_DIMM_VREFDQ SB_DIMM_VREFDQ SA_DIMM_VREFDQ SB_DIMM_VREFDQ @ R69 1K_0402_1% +V_SM_VREF BE7 BG7 10U_0603_6.3V6M 1 AY43 C985 1U_0402_6.3V6K F45 G45 R396 C583 1U_0402_6.3V6K +1.35VS R534 1K_0402_1% +1.35VS 42 VCC_AXG_SENSE 42 VSS_AXG_SENSE SM_VREF 100_0402_5% +1.8VS SAGE 3G VAXG[1] VAXG[2] VAXG[3] VAXG[4] VAXG[5] VAXG[6] VAXG[7] VAXG[8] VAXG[9] VAXG[10] VAXG[11] VAXG[12] VAXG[13] VAXG[14] VAXG[15] VAXG[16] VAXG[17] VAXG[18] VAXG[19] VAXG[20] VAXG[21] VAXG[22] VAXG[23] VAXG[24] VAXG[25] VAXG[26] VAXG[27] VAXG[28] VAXG[29] VAXG[30] VAXG[31] VAXG[32] VAXG[33] VAXG[34] VAXG[35] VAXG[36] VAXG[37] VAXG[38] VAXG[39] VAXG[40] VAXG[41] VAXG[42] VAXG[43] VAXG[44] VAXG[45] VAXG[46] VAXG[47] VAXG[48] VAXG[49] VAXG[50] VAXG[51] VAXG[52] VAXG[53] VAXG[54] VAXG[55] VAXG[56] 1U_0402_6.3V6K +VGFX_CORE R381 +V_SM_VREF should have 20 mil trace width 10U_0603_6.3V6M Check List R1.5 VCCAXG_SENSE:100ohm ±5% pull-up to VCC near processor VSSAXG_SENSE:100ohm ±5% pull-down to GND near processor J16 @ 2 JUMP_43X39 POWER 1U_0402_6.3V6K INTEL Recommend VCCPLL 1*330uF,2*1uF(0402) PD 0.9 E +1.35VS 1U_0402_6.3V6K AA46 AB47 AB50 AB51 AB52 AB53 AB55 AB56 AB58 AB59 AC61 AD47 AD48 AD50 AD51 AD52 AD53 AD55 AD56 AD58 AD59 AE46 N45 P47 P48 P50 P51 P52 P53 P55 P56 P61 T48 T58 T59 T61 U46 V47 V48 V50 V51 V52 V53 V55 V56 V58 V59 W50 W51 W52 W53 W55 W56 W61 Y48 Y61 1 UCPU1G D SA_DIMM_VREFDQ SB_DIMM_VREFDQ For Future CPU M3 support, Sandey bridge not support M3, Check list1.0 & CRB say can NC +VGFX_CORE SA RAIL INTEL Recommend VAXG 2*330uF,5*22uF(0805),6*10uF(0603),6*1uF(0402) PD 0.9 C A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title PROCESSOR(6/7) PWR THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E of 52 Rev 0.1 A B C D E UCPU1H UCPU1I A13 A17 A21 A25 A28 A33 A37 A40 A45 A49 A53 A9 AA1 AA13 AA50 AA51 AA52 AA53 AA55 AA56 AA8 AB16 AB18 AB21 AB48 AB61 AC10 AC14 AC46 AC6 AD17 AD20 AD4 AD61 AE13 AE8 AF1 AF17 AF21 AF47 AF48 AF50 AF51 AF52 AF53 AF55 AF56 AF58 AF59 AG10 AG14 AG18 AG47 AG52 AG61 AG7 AH4 AH58 AJ13 AJ16 AJ20 AJ22 AJ26 AJ30 AJ34 AJ38 AJ42 AJ45 AJ48 AJ7 AK1 AK52 AL10 AL13 AL17 AL21 AL25 AL28 AL33 AL36 AL40 AL43 AL47 AL61 AM13 AM20 AM22 AM26 AM30 AM34 VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29] VSS[30] VSS[31] VSS[32] VSS[33] VSS[34] VSS[35] VSS[36] VSS[37] VSS[38] VSS[39] VSS[40] VSS[41] VSS[42] VSS[43] VSS[44] VSS[45] VSS[46] VSS[47] VSS[48] VSS[49] VSS[50] VSS[51] VSS[52] VSS[53] VSS[54] VSS[55] VSS[56] VSS[57] VSS[58] VSS[59] VSS[60] VSS[61] VSS[62] VSS[63] VSS[64] VSS[65] VSS[66] VSS[67] VSS[68] VSS[69] VSS[70] VSS[71] VSS[72] VSS[73] VSS[74] VSS[75] VSS[76] VSS[77] VSS[78] VSS[79] VSS[80] VSS[81] VSS[82] VSS[83] VSS[84] VSS[85] VSS[86] VSS[87] VSS[88] VSS[89] VSS[90] VSS VSS[91] VSS[92] VSS[93] VSS[94] VSS[95] VSS[96] VSS[97] VSS[98] VSS[99] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] VSS[164] VSS[165] VSS[166] VSS[167] VSS[168] VSS[169] VSS[170] VSS[171] VSS[172] VSS[173] VSS[174] VSS[175] VSS[176] VSS[177] VSS[178] VSS[179] VSS[180] AM38 AM4 AM42 AM45 AM48 AM58 AN1 AN21 AN25 AN28 AN33 AN36 AN40 AN43 AN47 AN50 AN54 AP10 AP51 AP55 AP7 AR13 AR17 AR21 AR41 AR48 AR61 AR7 AT14 AT19 AT36 AT4 AT45 AT52 AT58 AU1 AU11 AU28 AU32 AU51 AU7 AV17 AV21 AV22 AV34 AV40 AV48 AV55 AW13 AW43 AW61 AW7 AY14 AY19 AY30 AY36 AY4 AY41 AY45 AY49 AY55 AY58 AY9 BA1 BA11 BA17 BA21 BA26 BA32 BA48 BA51 BB53 BC13 BC5 BC57 BD12 BD16 BD19 BD23 BD27 BD32 BD36 BD40 BD44 BD48 BD52 BD56 BD8 BE5 BG13 BG17 BG21 BG24 BG28 BG37 BG41 BG45 BG49 BG53 BG9 C29 C35 C40 D10 D14 D18 D22 D26 D29 D35 D4 D40 D43 D46 D50 D54 D58 D6 E25 E29 E3 E35 E40 F13 F15 F19 F29 F35 F40 F55 G51 G6 G61 H10 H14 H17 H21 H4 H53 H58 J1 J49 J55 K11 K21 K51 K8 L16 L20 L22 L26 L30 L34 L38 L43 L48 L61 M11 M15 VSS[181] VSS[182] VSS[183] VSS[184] VSS[185] VSS[186] VSS[187] VSS[188] VSS[189] VSS[190] VSS[191] VSS[192] VSS[193] VSS[194] VSS[195] VSS[196] VSS[197] VSS[198] VSS[199] VSS[200] VSS[201] VSS[202] VSS[203] VSS[204] VSS[205] VSS[206] VSS[207] VSS[208] VSS[209] VSS[210] VSS[211] VSS[212] VSS[213] VSS[214] VSS[215] VSS[216] VSS[217] VSS[218] VSS[219] VSS[220] VSS[221] VSS[222] VSS[223] VSS[224] VSS[225] VSS[226] VSS[227] VSS[228] VSS[229] VSS[230] VSS[231] VSS[232] VSS[233] VSS[234] VSS[235] VSS[236] VSS[237] VSS[238] VSS[239] VSS[240] VSS[241] VSS[242] VSS[243] VSS[244] VSS[245] VSS[246] VSS[247] VSS[248] VSS[249] VSS[250] VSS[251] VSS[252] VSS[253] VSS[254] VSS[255] VSS[256] VSS[257] VSS[258] VSS[259] VSS[260] VSS[261] VSS[262] VSS[263] VSS[264] VSS[265] VSS[266] VSS[267] VSS[268] VSS[269] VSS[270] VSS[271] VSS[272] VSS[273] VSS[274] VSS[275] VSS[276] VSS[277] VSS[278] VSS[279] VSS[280] VSS[281] VSS[282] VSS[283] VSS[284] VSS[285] VSS[286] VSS[287] VSS[288] VSS[289] VSS[290] VSS[291] VSS[292] VSS[293] VSS[294] VSS[295] VSS[296] VSS[297] VSS[298] VSS[299] VSS[300] VSS[301] VSS NCTF VSS_NCTF_1 VSS_NCTF_2 VSS_NCTF_3 VSS_NCTF_4 VSS_NCTF_5 VSS_NCTF_6 VSS_NCTF_7 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_10 VSS_NCTF_11 VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 M4 M58 M6 N1 N17 N21 N25 N28 N33 N36 N40 N43 N47 N48 N51 N52 N56 N61 P14 P16 P18 P21 P58 P59 P9 R17 R20 R4 R46 T1 T47 T50 T51 T52 T53 T55 T56 U13 U8 V20 V61 W13 W15 W18 W21 W46 W8 Y4 Y47 Y58 Y59 G48 A5 A57 BC61 BD3 BD59 BE4 BE58 BG5 BG57 C3 C58 D59 E1 E61 @ @ @ @ @ @ @ @ @ @ @ @ @ @ PAD T58 PAD T59 PAD T60 PAD T61 PAD T62 PAD T63 PAD T64 PAD T65 PAD T66 PAD T67 PAD T68 PAD T69 PAD T70 PAD T71 CR CheckList Rev1.5 IVY-BRIDGE_BGA1023 IVB@ IVY-BRIDGE_BGA1023 IVB@ 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title PROCESSOR(7/7) VSS THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E 10 of 52 Rev 0.1 PR402 499K_0402_1% BS PC429 PR414 0.01U_0402_25V4Z 1K_0402_5% 2 FB_3V PR401 BST_3V_1 BST_3V 2.2_0603_5% PC402 0.1U_0603_25V7K OUT PG LDO 5*5*3 D +3VALWP NW00 GND PL402 1UH_PCMB053T-1R0MS_7A_20% LX_3V +3VLP SY8208BQNC_QFN10_3X3 PR404 4.7_1206_5% PC410 4.7U_0603_6.3V6K PC411 680P_0402_50V7K 2 36 SPOK 10 LX PC406 1U_0603_25V6K ENM PR403 150K_0402_1% 1 B+ PC409 22U_0805_6.3VAM EN2 PC408 22U_0805_6.3VAM EN1 IN IN PC407 22U_0805_6.3VAM PC405 10U_0805_25V6K PC404 10U_0805_25V6K @ PC403 2200P_0402_50V7K PC401 0.1U_0603_25V7K D RF@ PC424 68P_0402_50V8J PU401 RF@ PC425 2200P_0402_50V7K PL401 HCB2012KF-121T50_0805 RF@ PC426 0.1U_0603_25V7K ENLDO_3V5V B+ C C B+ 5*5*3 NW00 PL404 1UH_PCMB053T-1R0MS_7A_20% 2 PR408 2.2K_0402_5% 28 EC_ON B @ PJ401 +3VALWP @ PD401 SBR2U30P1-7_POWERDI123-2 1 2 +3VALW JUMP_43X118 @ PJ402 @ PR409 0_0402_5% +5VALWP 1 2 +5VALW PC423 4.7U_0603_6.3V6K JUMP_43X118 @ PR411 402K_0402_1% 36 MAINPWON A PC420 22U_0805_6.3VAM PR406 4.7_1206_5% PC419 22U_0805_6.3VAM VL SY8208CQNC_QFN10_3X3 +5VALWP LX_5V PC418 22U_0805_6.3VAM LDO 10 PC416 0.1U_0603_25V7K BST_5V_1 RF@ PC427 68P_0402_50V8J OUT PG PR405 2.2_0603_5% 2 @ PR407 0_0402_5% VCC BST_5V B LX PC421 4.7U_0603_6.3V6K PC417 4.7U_0603_6.3V6K GND @ ENM PC422 680P_0402_50V7K BS EN1 EN2 ENM IN PC428 PR410 6800P_0402_25V7K 1K_0402_5% 2 FB_5V PU402 PC414 0.1U_0603_25V7K PC413 2200P_0402_50V7K PC415 10U_0805_25V6K PC412 10U_0805_25V6K PL403 HCB2012KF-121T50_0805 For EC use +3VALW, mark "@" if use +3VLP A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 Date of EOP Deciphered Date Title 3VALW/5VALW THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 SAGE 3G Date: Sheet 38 of 52 A +VTT_REFP PC501 2200P_0402_50V7K @ PC504 0.1U_0402_25V6 1 +1.35VP 1.5UH_MMD-06CZ-1R5M-V1_9A_20% PL502 PR503 4.7_1206_5% CS VDDP LG_1.35V 14 13 PQ502 PR504 18.7K_0402_1% 2 PGND 15 2 PHASE OVP=110%~120% LX_1.35V 16 UG_1.35V UGATE BST_1.35V 18 BOOT 17 LGATE VTTREF PC509 680P_0402_50V7K + PC508 330U_D2_2V_Y MDV1525URH_PDFN33-8-5 Rds=11.5mΩ(Typ) 14mΩ(Max) 12 11 PR505 5.1_0603_5% +1.35VP +5VALW PJ504 2 +1.35V JUMP_43X118 +3VALW VDD PR506 10K_0402_5% PC511 1U_0603_10V6K PGOOD 10 TON S5_1.35V PR507 680K_0402_1% S5 VDDQ S3 FB PC510 0.033U_0402_16V7K PC512 1U_0603_10V6K @ @ +0.675VSP PGOOD_1.35V PJ506 2 +0.675VS JUMP_43X79 @ PR508 0_0402_5% PR501 887K_0402_1% 1.35V_B+ DDR3L@ PR509 4.64K_0402_1% 2 1 PC513 0.1U_0402_16V4Z @ PC514 0.1U_0402_16V7K 1 1.35VP D PR510 FB=0.75V To GND = 1.5V To VDD = 1.35V SUSP G S3 S5 S0 Hi Hi On On S3 Lo Hi On On Lo Lo S PQ503 2N7002KW_SOT323-3 VTT_REFP 5.76K_0402_1% 34 SUSP S4/S5 prevent the switching too fast to short through RT8207MZQW_WQFN20_3X3 +1.35VP 28,34 SYSON STATE @ 19 20 GND B+ MDV1528URH_PDFN33-8-5 PR502 PC505 2.2_0603_5% 0.1U_0603_25V7K BST_1.35V-1 VTTSNS S3_1.35V 28,34,40,41 SUSP# VTTGND PQ501 2 PAD VLDOIN VTT PU501 21 PJ501 JUMP_43X118 1 2 PC507 10U_0805_25V6K PC506 10U_0805_25V6K RF@ PC516 68P_0402_50V8J 靠靠Output Cap PAD PJ503 @ JUMP_43X39 PC503 4.7U_0805_25V6-K PJ507 @ JUMP_43X39 PC502 4.7U_0805_25V6-K +1.35VP +1.35VS 2012/08/01 +0.675VSP @ 1.35V_B+ RF@ PC515 68P_0402_50V8J Ipeak=12.2A ; Imax=8.54A ;Iocp=14.64A Delta I=3.23=>1/2Delta I=1.62A (F=285K Hz) Rds(on)=14m ohm(max) ; Rds(on)=11.5m ohm(typical) Ilimit_min=(18.7K*10uA)/(14m)=13.36A Ilimit_max=(18.7K*10uA)/(11.5m)=16.26A Iocp=Ilimit+1/2Delta I =14.97~17.88A 0.675VSP On Off (Hi-Z) Off Off Off (Discharge) (Discharge) (Discharge) Note: S3 - sleep ; S5 - power off Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 Deciphered Date Date of EOP Title 1.5VP/0.75VSP/1.8VSP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 SAGE 3G Date: A Sheet 39 of 52 D D PR602 330K_0402_1% B+ PL602 0.68UH_PCMC063T-R68MN_15.5A_20% 2 PC612 22U_0805_6.3V6M PC611 22U_0805_6.3V6M PC610 22U_0805_6.3V6M PC609 22U_0805_6.3V6M 1 PR605 4.7_0805_5% PC608 22U_0805_6.3V6M 1 +3VALW SY8208DQNC_QFN10_3X3 PR608 10K_0402_1% PC622 1U_0402_16V7K PC607 22U_0805_6.3V6M LDO FB_+1.05VSP PG C @ PC614 680P_0402_50V7K @ PJ601 +1.05VS_VCCPP BYP 2 ILMT +1.05VS_VCCPP 5K80 SW_+1.05VSP @ PC613 0.1U_0402_16V7K RF@ PC620 2200P_0402_50V7K BST_+1.05VSP 10 7*7*3 FB PR606 1M_0402_1% PR601 PC601 0_0603_5% 0.1U_0603_25V7K 2 RF@ PC618 68P_0402_50V8J LX EN_+1.05VSP GND PC616 4.7U_0603_6.3V6K PC606 10U_0805_25V6K PC605 10U_0805_25V6K EN PC615 4.7U_0603_6.3V6K +3VS PC604 2200P_0402_50V7K @ PC603 0.1U_0402_25V6 RF@ PC621 68P_0402_50V8J 1 C IN BS RF@ PC619 68P_0402_50V8J 1 @ PR604 10K_0402_1% @ PC602 0.1U_0402_16V7K PU601 VFB=0.6V 1 2 +1.05VS_VTT JUMP_43X118 PR607 PL601 HCB2012KF-121T50_0805 +3VS SUSP# 28,34,39,41 @ PR603 1M_0402_1% PC617 220P_0402_50V8J 2 100K_0402_1% 41 VCCPPWRGOOD PR609 133K_0402_1% B PC623 PR610 @ 1000P_0402_50V7K @ 1.2K_0402_1% 2 B PR611 100_0402_1% VCCIO_SENSE A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 Date of EOP Deciphered Date Title 1.05VS_VTTP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 SAGE 3G Date: Sheet 40 of 52 +VCCSA_PWRGD 40 VCCPPWRGOOD PC711 1U_0603_6.3V6M @ PR704 0_0402_5% POK D1 VEN/MODE D0 @ PR703 0_0402_5% 2 1 G978F11U_SO8 @ PR705 0_0402_5% H_VCCSA_VID1 H_VCCSA_VID0 @ PR706 1K_0402_5% 0.9V RF@ PC726 68P_0402_50V8J Vo PC710 22U_0805_6.3V6M Vo VPP PC709 2200P_0402_50V7K 1 +5VALW VIN PC712 1U_0603_6.3V6M 2 PC708 22U_0805_6.3V6M 15,28 SA_PGOOD PR702 1K_0402_5% GND PC707 22U_0805_6.3V6M PU701 +3VS D +VCCSAP PR701 100K_0402_5% VCCSA Vout 0.9V 0.85V 0.775V 0.75V output voltage adjustable network PC706 0.1U_0402_16V7K 1 VID[1] 1 PC704 22U_0805_6.3V6M 2 PC705 22U_0805_6.3V6M +1.05VS_VTT @ PC703 0.1U_0603_25V7K PC702 2200P_0402_50V7K D PC701 22U_0805_6.3V6M RF@ PC725 68P_0402_50V8J VID [0] 0 1 @ PJ701 1 2 JUMP_43X39 @ PJ705 +VCCSAP 1 +VCCSA JUMP_43X39 C C +3VS @ PR707 0_0402_5% 2 PR716 10K_0402_1% +1.5VSP_ON PC718 22U_0805_6.3V6M @ FB_1.5VSP @ PR714 22K_0402_5% PC721 0.1U_0402_16V7K B PR715 22.6K_0402_1% 2 Rdown PC717 22U_0805_6.3V6M PR710 20K_0402_1% FB=0.8V 2 GND FB +1.5VSP RF@ PC727 68P_0402_50V8J 2 Note:Iload(max)=3A PC724 680P_0402_50V7K FB=0.6V 1 FB_1.8V EN POK PR711 1_0402_1% 28,34,39,40 SUSP# VOUT VOUT PC716 0.022U_0402_16V7K Rup VCNTL VIN VIN PR713 20K_0402_1% PC715 4.7U_0603_6.3V6K +1.8VSP 2 SY8003DFC_DFN8_2X2 1 NC LX_1.8V PGND LX RF@ PC728 68P_0402_50V8J EN IN PC723 22U_0805_6.3VAM JUMP_43X79PC719 22U_0805_6.3VAM PG 2 PU702 APL5930KAI-TRG_SO8 PC722 22U_0805_6.3VAM 2 @ PC713 1U_0402_6.3V6K Note:Iload(max)=3A PL701 1UH_PH041H-1R0MS_3.8A_20% PC720 68P_0402_50V8J 1 Note:Iload(max)=2.5A 1 PR709 1M_0402_5% +3VALW B FB PR712 4.7_0603_5% @ PJ702 PGND SGND 1 SUSP# 0.1U_0402_16V7K @ PC714 PU703 1 +1.8VSP_ON Vout=0.6V* (1+Rup/Rdown) @ +1.8VSP 1 Ien=10uA, Vth=0.3V, notice the res and pull high voltage from HW PJ704 2 +1.8VS JUMP_43X79 @ PJ703 +1.5VSP 2 +1.5VS JUMP_43X39 A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 Date of EOP Deciphered Date Title VCC_SAP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 SAGE 3G Date: Sheet 41 of 52 @ PC802 1000P_0402_50V7K 22 19 LGATE1 18 PHASE1 17 UGATE1 20 PR822 1_0603_5% +3VS VCCSENSE VSSSENSE 2 @ PR847 10_0402_1% PR816 1_0402_5% 1 56via PR843 1_0402_5% 3.65K_0603_1% PR842 VSUM- PC834 0.22U_0603_16V7K LGATE1 VSUM- +CPU_CORE SAGE 3G VSUM+ B PL804 0.24UH_FDUE0630J-H-R24M-P3_22A_20% PC836 680P_0402_50V7K 2 PR841 4.7_1206_5% PR840 2.2_0603_5% 1 BOOT1 B+ PC827 2200P_0402_50V7K 2 @ PC826 0.1U_0402_25V6 + RF@ PC845 68P_0402_50V8J PC841 33U_D2_25VM_R60M PC823 10U_0805_25V6K PC822 10U_0805_25V6K 2UGATE1-1 PQ803 MDV1525URH_PDFN33-8-5 1 UGATE1 PHASE1 PC837 0.1U_0402_16V7K @ PC838 330P_0402_50V7K PH804 2.61K_0402_1% 10K_0402_1%_ERTJ0EG103FA PR835 2 11K_0402_1% PR838 PC833 0.1U_0603_25V7K @ PC829 0.01UF_0402_25V7K 2 2 A @ PR846 10_0402_1% PC839 330P_0402_50V7K +CPU_CORE PR832 0_0603_5% Close Phase choke PC835 150P_0402_50V8J 2 PR845 130K_0402_1% PR836 511_0402_1% PC832 56P_0402_50V8 PC831 6800P_0402_25V7K PR834 42.2K_0402_1% PL802 HCB2012KF-121T50_0805 CPU_B+ PQ804 MDU1511RH_POWERDFN56-8-5 1.91K_0402_1% 1 PR844 1.91K_0402_1% PC814 10U_0805_25V6K PL801 HCB2012KF-121T50_0805 For17 W 1+1 CPU_CORE LL= -2.9mΩ, OCP ~40A GFX_CORE LL= -3.9mΩ, OCP ~34A 1 PR837 499_0402_1% BOOT1 PR831 +5VS PR839 649_0402_1% PC830 470P_0402_50V7K 2 2 VSUM+ PR833 2K_0402_1% VSUMG+ +5VS 21 VGATE 15 B PC828 470P_0402_50V7K C PC819 1U_0603_10V6K BOOT1 UGATE1 23 +VGFX_CORE OVP=VID +(120mV~ 200mV) 16 15 @ PR829 0_0402_5% 14 ISEN2 PGOOD PHASE1 COMP NTC FB LGATE1 42via PC817 1U_0603_10V6K PW M2 VR_HOT# 25 27 28 29 30 31 32 33 26 BOOTG PGOODG COMPG FBG RTNG ISUMNG UGATEG VDD ISL95833HRTZ-T_TQFN32_4X4 SDA ALERT# 24 1 PR828 3.83K_0402_1% 2 @ PC820 0.1U_0402_16V7K PR830 27.4K_0402_1% PR824 0_0402_5% PR825 130_0402_1% PR826 75_0402_5% PR827 54.9_0402_1% @ +1.05VS_VTT SDA @ PR823 0_0402_5% 28 VR_HOT# VCCP 13 LGATEG SCLK RTN ALERT# VR_ON 12 @ PR821 0_0402_5% @ PC818 47P_0402_50V8J PAD SCLK ISUMN 0_0402_5% 0_0402_5% 11 @ Rds(on)=2.7m-3.3m ohm LGATEG PHASEG ISUMP PR818 @ PR820 PHASEG NTCG 10 PH803 470K_0402_5%_ TSM0B474J4702RE 2 VR_SVID_DAT 1 NTCG ISEN1 28,5 VR_ON VR_SVID_CLK VR_SVID_ALRT# PR819 3.83K_0402_1% PH802 470K_0402_5%_ TSM0B474J4702RE C ISUMPG PU801 SAGE 3G PC816 680P_0402_50V7K 2 LGATEG PQ802 MDU1511RH_POWERDFN56-8-5 PR813 2.2_0603_5% UGATEG1 PR814 4.7_1206_5% PC815 0.22U_0603_16V7K 1 2 BOOTG BOOTG PR817 27.4K_0402_1% PL803 0.24UH_FDUE0630J-H-R24M-P3_22A_20% PHASEG VSUMG- UGATEG1-1 PC813 10U_0805_25V6K PR811 0_0603_5% UGATEG1 PR812 1.91K_0402_1% +3VS PR807 1.65K_0402_1% PR810= 24.9 Kohm==>Freq= 400KHz PR810 24.9K_0402_1% PC809 0.01UF_0402_25V7K @ PC812 1000P_0402_50V7K PC808 0.1U_0603_25V7K PR808 280_0402_1% D CPU_B+ PR815 3.65K_0603_1% VSUMG+ PR809 11K_0402_1% PR801 2.61K_0402_1% 1 PC801 0.1U_0402_16V7K 2 RF@ PC843 2200P_0402_50V7K PC807 150P_0402_50V8J PR805 137K_0402_1% RF@ PC844 68P_0402_50V8J PC806 PR806 2200P_0402_50V7K 649_0402_1% 2 VSUMG- PC805 470P_0402_50V7K 2 PR804 499_0402_1% PH801 10K_0402_1%_ERTJ0EG103FA PC804 68P_0402_50V8J PQ801 MDV1525URH_PDFN33-8-5 @ PR803 10_0402_1% D For ULV 17W 1+1 CPU_CORE LL= -2.9mΩ,Iocp_cpu=39.6A GFX_CORE LL= -4.6mΩ,Iocp_gfx=21.6A RF@ PC842 0.1U_0402_25V6 PC803 0.01UF_0402_25V7K 10_0402_1% 2 @ PR802 VCC_AXG_SENSE VSS_AXG_SENSE 1 +VGFX_CORE A @ PC840 0.01UF_0402_25V7K Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 Date of EOP Deciphered Date Title CPU_CORE/VGFX_CORE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 SAGE 3G Date: Sheet 42 of 52 Compal Secret Data Date of EOP 1 1 PC994 10U_0603_6.3V6M PC993 10U_0603_6.3V6M PC992 10U_0603_6.3V6M PC991 10U_0603_6.3V6M PC990 10U_0603_6.3V6M 2 PC995 330U_D2_2V_Y 1 1 PC989 10U_0603_6.3V6M PC988 10U_0603_6.3V6M PC987 10U_0603_6.3V6M PC986 10U_0603_6.3V6M PC985 10U_0603_6.3V6M PC956 1U_0402_6.3V6K PC957 1U_0402_6.3V6K PC958 1U_0402_6.3V6K PC959 1U_0402_6.3V6K PC960 1U_0402_6.3V6K PC961 1U_0402_6.3V6K PC962 1U_0402_6.3V6K PC963 1U_0402_6.3V6K PC964 1U_0402_6.3V6K PC965 1U_0402_6.3V6K PC966 1U_0402_6.3V6K PC967 1U_0402_6.3V6K PC968 1U_0402_6.3V6K PC972 1U_0402_6.3V6K PC973 1U_0402_6.3V6K PC974 1U_0402_6.3V6K PC975 1U_0402_6.3V6K PC976 1U_0402_6.3V6K PC977 1U_0402_6.3V6K PC978 1U_0402_6.3V6K PC979 1U_0402_6.3V6K PC980 1U_0402_6.3V6K PC981 1U_0402_6.3V6K PC982 1U_0402_6.3V6K PC983 1U_0402_6.3V6K PC984 1U_0402_6.3V6K PC969 330U_D2_2V_Y PC970 330U_D2_2V_Y PC971 330U_D2_2V_Y PC941 330U_D2_2V_Y PC942 330U_D2_2V_Y PC943 22U_0805_6.3V6M PC944 22U_0805_6.3V6M PC945 22U_0805_6.3V6M PC946 22U_0805_6.3V6M PC947 22U_0805_6.3V6M PC948 22U_0805_6.3V6M 1 1 1 PC933 10U_0603_6.3V6M PC932 10U_0603_6.3V6M PC931 10U_0603_6.3V6M PC930 10U_0603_6.3V6M PC929 10U_0603_6.3V6M PC928 10U_0603_6.3V6M 2 2 2 PC927 2.2U_0402_6.3V6M Deciphered Date 1 1 1 PC919 1U_0402_6.3V6K PC918 1U_0402_6.3V6K PC917 1U_0402_6.3V6K PC916 1U_0402_6.3V6K PC915 1U_0402_6.3V6K PC914 1U_0402_6.3V6K PC913 1U_0402_6.3V6K PC912 1U_0402_6.3V6K PC911 1U_0402_6.3V6K PC910 1U_0402_6.3V6K PC901 1U_0402_6.3V6K 2 2 2 2 PC909 2.2U_0402_6.3V6M 2011/06/24 + PC955 22U_0805_6.3V6M Issued Date 1 PC940 22U_0805_6.3V6M Security Classification + 2 PC926 2.2U_0402_6.3V6M ESR=9m ohm 1 PC954 22U_0805_6.3V6M + + PC953 22U_0805_6.3V6M 2 PC952 22U_0805_6.3V6M motherboard design (Gfx VR keeps VAXG from floating) if the VR is stuffed PC951 22U_0805_6.3V6M ‧ VAXG can be left floating in a common 2 PC939 22U_0805_6.3V6M ‧ Can connect to GND if motherboard only 2 PC938 22U_0805_6.3V6M 2 PC937 22U_0805_6.3V6M Vaxg PC936 22U_0805_6.3V6M 1 PC908 2.2U_0402_6.3V6M 2 PC950 22U_0805_6.3V6M 2 PC925 2.2U_0402_6.3V6M 1 PC907 2.2U_0402_6.3V6M PC924 2.2U_0402_6.3V6M 1 PC906 2.2U_0402_6.3V6M PC935 22U_0805_6.3V6M PC923 2.2U_0402_6.3V6M 1 PC905 2.2U_0402_6.3V6M ESR=9m ohm + PC922 2.2U_0402_6.3V6M C PC904 2.2U_0402_6.3V6M + PC921 2.2U_0402_6.3V6M 1 PC903 2.2U_0402_6.3V6M PC949 22U_0805_6.3V6M D PC934 22U_0805_6.3V6M PWR Rule 17W@ULV(CR BGA1023_GT2) CPU2.9m GFx3.9m CPU 330uF/9m *3, 22uF(0805) *12, 2.2uF(0402)*16 GFX 330uF/9m*2, 22uF(0805)*6, 10uF(0603)*6, 1uF(0402)*11 1.05V 330uF*2,10uF(0603)*10,1uF(0402)*26 PC920 2.2U_0402_6.3V6M B +VGFX_CORE PC902 2.2U_0402_6.3V6M +CPU_CORE For BOT side @ A Title Compal Electronics, Inc THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC SAGE 3G CPU_CORE_CAP Rev 1.0 Date: Sheet 43 of 52 D +CPU_CORE @ For TOP side C supports external graphics and if GFX VR is not stuffed in a common motherboard design, +1.05VS_VTT +CPU_CORE B ESR=9m ohm A SW 0.1U_0603_50V7K PC1403 2.2U_1206_50V7K @ PC1402 2.2U_1206_50V7K PC1408 VOUT 2.2U_1206_50V7K PR1401 1 +LG_VOUT D PC1401 S CER CAP 220P 50V J NPO 0603 PC1406 2 13 IFB5 14 15 FAULT IFB4 SW DCTRL 12 11 FB4 22 C DCTRL TPS61181ARTER_QFN16_3X3 FB3 22 CIN 62K_0402_1% PC1414 PR1409 B 10 IFB2 IFB3 IFB1 VO 100P_0402_50V8J @ PC1412 PC1411 1U_0805_50V7K VOUT GND ISET 100P_0402_50V8J @ PC1410 1 PR1408 VBAT 0.1U_0402_10V7K EN 1M_0402_1% 10K_0402_1% PGND PR1407 2 EN 16 17 TPAD 1 SW EN PU1401 C 28 BKOFF# 2.2U_1206_50V7K LL4148_LL34-2 2 PC1409 2 PR1406 100P_0402_50V8J DCTRL 10K_0402_1% PR1405 51_1206_5% PR1404 1M_0402_1% 16 INVTPWM PD1401 PR1403 0_0603_5% PR1402 100K_0402_5% PC1405 100P_0402_50V8J 1 0.1U_0603_50V7K PC1404 G D PD1402 SBR3U40P1-7_POWERDI123-2 4.7UH_PCMC063T-4R7MN_5.5A_20% PL1401 D S B+ PC1407 PQ1401 P5103EMG_SOT23-3 10_1206_1% IFB6 FB2 22 B FB1 22 @ PJ1401 GND GND_SIGNAL PAD-OPEN1x1m A A Compal Secret Data Security Classification Issued Date 2011/06/13 Deciphered Date 2012/06/13 Title Compal Electronics, Inc LED Converter THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Wednesday, March 13, 2013 Date: Rev 0.1 SAGE 3G Sheet 44 of 52 Version change list (P.I.R List) Item Fixed Issue Reason for change Rev PG# Modify List Design Change Design Change of IC Application 0.2 38 Add Add Add Add Design Change Design Change of IC Application 0.2 44 35 Add Adapter Detection Circuit Design Change of DC Jack Application Design Change Design Change of IC Application 0.2 42 Change Component Part Number Factory lack of material 0.2 44 Change Component Part Number Factory lack of material 0.2 Change Component Part Number X1 Code Design Change 1 Page 1of for PWR Date @PR410.@PR414 to SD028100180(S RES 1/16W 1K +-5% 0402) @PC429 to SE075472K80(S CER CAP 4700P 25V K X7R 0402) @PC428 to SE075472K80(S CER CAP 0.047U 25V K X7R 0402) PR412.@PR413.PR415 to SD028000080(S RES 1/16W +-5% 0402) Phase 2012/12/13 DVT Delete PC1413 2012/12/13 DVT Add Add Add Add 2012/12/13 DVT 2012/12/24 DVT Change PL1401 to SH000006J80 (S COIL 4.7UH +-20% PCMC063T-4R7MN 5.5A) 2012/12/24 DVT 42 Change PC841 to SGA00007I00 (S POLY C 33U 25V M D2 ESR60M TQC H1.9) 2012/12/26 DVT 0.2 44 Change PD1402 to SCS00005Y00 (S SCH DIO SBR3U40P1-7 POWERDI123-2) 2012/12/26 DVT Design Change of IC Application 0.3 38 Delete PR412.PR413.PR415 2012/01/29 PVT Design Change Design Change of IC Application 0.3 38 Change @PR410.@PR414.@PC428.@PC429 to PR410.PR414.PC428.PC429 2012/01/29 PVT 10 Design Change Design Change of IC Application 0.3 38 Change PC428 to SE075682K80(S CER CAP 6800P 25V K X7R 0402) Change PC429 to SE072103Z80(S CER CAP 01U 25V Z Y5V 0402) 2013/02/22 PVT 11 Design Change Design Change of Adapter Detection 0.4 37 Change PQ307 to SB000009Q80(S TR 2N7002KW 1N SOT323-3) Add PR325 to SD028100380(S RES 1/16W 100K +-5% 0402) 2013/02/23 Pre MP D 0.2 37 PR325 to SD028000080(S RES 1/16W +-5% 0402) PR321.PR323 to SD028100380(S RES 1/16W 100K +-5% 0402) PQ307 to SB201440000(S TR PDTA144EU PNP SOT323) PQ308 to SB301150200(S TR PDTC115EU NPN SOT323) Change PC831 to SE075682K80(S CER CAP 6800P 25V K X7R 0402) Change PC832 to SE071560J80(S CER CAP 56P 50V J NPO 0402) D C C B B A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 Deciphered Date Date of EOP Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC PIR (PWR) Rev 1.0 EG51_HX M/B LA-9491P Schematics Date: Sheet 45 of 52 VIN = B+ QFN10 +5VALW D Page 38 SUSP# LDO = +3VLP VIN = B+ (+VCCDSW3_3 = +3VLP) EC_ON QFN10 SYSON Page 38 WQFN20 ADAPTER +3VALW SUSP# PU703 SY8003DFC_2X2 DFN8 +1.35V PU601 SY8208DQNC_3X3 SUSP# +1.05VS_VCCP (+1.05VS_VTT) (+1.05VS_PCH) (VCCPPWRGOOD) C QFN10 BATTERY Page 40 VIN = B+ PU701 G978F11U TQFN32 SO8 QFN16 C SUSP Page 34 Q68 AP2301GN-HF POWERPAK8-5 Page 34 SOT23-3 +3VS +LG_VOUT (+INVPWR_B+) Page 44 PCH_PWR_EN# U21 SI7716ADN-T1-GE3 +1.35VS PU1401 TPS61181ARTER_3X3 BKOFF# +3VALW POWERPAK8-5 VIN = +5VS CHARGER Page 41 U12 SI7716ADN-T1-GE3 +CPU_CORE (VGATE) +VGFX_CORE Page 42 +VCCSA (SA_PGOOD) VIN = +1.05VS_VTT VCCPPWRGOOD SUSP PU801 ISL95833HRTZ-T_4X4 VR_ON +1.8VS Page 41 VIN = +3VALW +0.675VS Page 39 VIN = +5VALW B+ +1.5VS Page 41 VIN = +3VS PU501 RT8207MZQW_3X3 SUSP# PU702 APL5930KAI-TRG SO8 PU401 SY8208BQNC_3X3 MAINPWON (VIN) LDO = VL PU402 SY8208CQNC_3X3 D LED & LID +VCCSUS3_3 HUB_PWRGATE @SENSOR +3VALW (LED & LID) Page 33 VIN = B+ Page 20 +3V_SEN Page 30 AUDIO CODEC AOAC_ON @WIFI +3VS_WLAN B Page 24 +5VALW SUSP USB_EN# +3VS_WWAN Page 31 U22 SI7716ADN-T1-GE3 U17 AP2301MPG-13 Q64 AP2301GN-HF POWERPAK8-5 Page 34 MSO8 SOT23-3 +5VS +USB3_VCCA B +3VS (CAMERA) Page 27,33 TPM +3V_TPM Page 26 PCH_PWR_EN# Page 27 +3VS (MIC)Page 33 CAMERA mSATA +3VS_FULL Page 25 Page 20 PCH_ENVDD @LCD +LCDVDD Page 22 +V5REF_SUS AUDIO CODEC JIO1 (Audio) Page 33 +3VS_WWAN Page 31 WIFI (w/o IOAC) FAN A A +3VS_WLAN Page 24 +5VS (FAN) Page 29 EC HDMI +HDMI_5V_OUT Page 23 +3VS_CARD Page 32 +3VLP +3VALW_EC Page 28 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title POWER TREE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC V1JB1 M/B LA-A041P Schematic Date: Wednesday, March 13, 2013 Sheet 46 of 52 Rev 0.1 AC DC Adapter IN Battery_IN EC_ON (S5 enable) EC_ON (S5 enable) -8 -8 +3VALWP EN +5VALWP EN -7 LX D 3V BATT+ -3 -11 Switch MosFET LDO Charger VIN Switch MosFET B+ PGOOD +3VLP GPE0 SPOK VIN ON/OFF GPE4 PWR BTN GPB7 C GPI7 DPWROK -6 PCH_RSMRST# -1 VR_ON 10 GPJ3 GPD5 DRAMPWROK SLP_SUS# GPF1 GPE1 GPD0 GPE2 GPD1 GPJ1 SYSON SUSP# PM_DRAM_PWRGD PLTRST# KBC VO PWRBTN# -4 PBTN_OUT# +V5REF_SUS PLT_RST# 17 SLP_S4# KBC VO BUF_CPU_RST# RESET# B+ +5VS +5VALW +VSB VI EN KBC VO +5VS 10 VDD/VCCP VR_ON VR_ON KBC 14 SUSP SYSON SUSP# EN_S5 KBC PHASE EN_S3 +VSB VTT VLDOIN SUSP# EN KBC +VSB SUSP# VCCPPWRGOOD VI EN KBC KBC VO VI EN KBC VO VCCPPWRGOOD VI EN KBC VO PGOOD VI EN 15 B +1.35VS +1.5VS +1.05VS_VTT +3VALW SUSP# VGATE +3VS SW PGOOD A VO +3VS +1.05VS_VCCP (+1.05VS_VTT) (+1.05VS_PCH) KBC +VGFX_CORE SUSP -2 -2 PHASEG +CPU_CORE +1.35V +1.35V +0.675VS SVID PHASE1 PGOOD VI EN SUSP VDD/VDDP SVID_CLK/DATA/ALERT# +3VALW +1.35V +VCCSUS3_3 Buffer Y SLP_S3# +3VALW VI UNCOREPWRGOOD CPU P A B+ EN C 13 SVID +5VALW VI SM_DRAMPWROK +3VS +5VALW EN PM_DRAM_PWRGD_R A H_CPUPWRGD B+ PCH_PWR_EN# 12 AND Gate Y NC B -3 P B PWROK PCH_PWR_EN PM_SLP_S3# 16 PCH APWROK GPH0 PM_SLP_S4# +3VALW PROCPWRGD 11 PCH_PWROK AND Gate A Y SYS_PWROK RSMRST# SLP_SUS# -9 -1 PGOOD SYS_PWROK KBC SA_PGOOD LDO P DPWROK -5 VL +3VS -10 -2 B GPG2 5V -9 -1 EC_ON VCC D SW2 -8 +3VLP -7 LX SW2 VIN VO +VCCSA A SA_PGOOD +1.8VS Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title POWER TREE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC V1JB1 M/B LA-A041P Schematic Date: Wednesday, March 13, 2013 Sheet 47 of 52 Rev 0.1 A B C V1JV1 CLOCK MAP D XTAL 32.768K Hz E XTAL 25M Hz 1 RTCX1 RTCX2 WLAN MD222 CLK_PCIE_MINI1 CLK_PCIE_MINI1# 100MHz XTAL25_IN XTAL25_OUT CLKOUT_DP_P CLKOUT_DP_N CLKOUT_PCIE1P CLKOUT_PCIE1N CLKOUT_DMI_P CLKOUT_DMI_N Card Reader RTS5209 CLK_PCIE_CARD CLK_PCIE_CARD# 100MHz 120MHz CLK_CPU_DPLL CLK_CPU_DPLL# 100MHz CLK_CPU_DMI CLK_CPU_DMI# 33MHz CLK_PCI0 Panther Point-M CLKOUT_PCI0 HDA_BITCLK_AUDIO PCH HDA_BITCLK_PCH 24MHz CLKOUT_PCI2 PCH_SPI_CLK_0 33 Ohm PCH_SPI_CLK 33MHz CLK_PCI2 33MHz CLK_PCI1 22 Ohm TPM SLB9655 CLK_PCI_TXM CLKOUT_PCIE7P CLKOUT_PCIE7N CLKOUT_PCI1 2MB SPI ROM 22 Ohm CLK_PCI_LPBACK CLKIN_PCILOOPBACK 33 Ohm Ivy Bridge Intel CLKOUT_PCIE4P CLKOUT_PCIE4N Audio Codec AL271X CPU 22 Ohm CLK_PCI_LPC SPI_CLK 33 Ohm 3 PCH_SPI_CLK_1 LPCCLK HSCK CLK_PCI_LPC EC IT8518 4MB SPI ROM EC_SPICLK XTAL 32.768K Hz CK32K CK32KE FSCK 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title CLOCK MAP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E 48 of 52 Rev 0.1 A B C D E SMBUS Block Diagram 1 +3VS SDVO_SCLK SDVO_SDATA HDMI_SCLK HDMI_SDATA HDMI Connector I2C_SCL_GYRO I2C_SDA_GYRO +VCCSUS3_3 Intel Panther Point-M PCH I2C_1_SCL_SENSOR I2C_1_SDA_SENSOR ST Sensor HUB PCH_SMBCLK PCH_SMBDATA PCH_SML0CLK PCH_SML0DATA I2C_SCL_ACCEL I2C_SDA_ACCEL I2C_SCL_ALS I2C_SDA_ALS (USB interface) +3VS PCH_SML1CLK PCH_SML1DATA ST Gyroscope ST G-sensor+E-compass Capella Light sensor EC_SMB_CK2 EC_SMB_DA2 DDR Thermal sensor +3VS +3VS_LC EC_SMB_CK2 EC_SMB_DA2 ThunderBolt +3VALW_EC EC ITE 8518 TB_SMB_CK TB_SMB_DA Cactus - Ridge EC_SMCA EC_SMDA EC_SMB_CK1 EC_SMB_DA1 Battery EC SM Bus1 address Device Smart Battery XX XXXX XXXX b DCIN / Charge 13 0001 001X b PCH SM Bus address Device ST sensor HUB EC SM Bus2 address Address XX Device PCH SM Bus address(Link 1) Address Device XXXX XXXX b DDR Thermal sensor 99 Address Thunderbolt 29 0010 100X b(CIO P1) 2B 0010 101X b(CIO P2) 2D 0010 110X b(CIO P3) 2F 0010 111X b(CIO P4) Sensor HUB SM Bus address Device DCIN / charge Address 1001 101X b Address Gyroscope D1 1101 000X b D3 1101 001X b Security Classification E-compass + G sensor 33 0011 001X b Issued Date ALS sensor 21 0010 000X b Compal Electronics, Inc Compal Secret Data 2011/06/24 2012/06/02 Deciphered Date Title SMBUS Block Diagrams THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E 49 of 52 Rev 0.1 A B C D E V1JB1 SYSTEM Diagram 1 SYSTEM MB IO BOARD FPC between MB & IO Board JIO1 JIO1 Audio Codec Rear Camera ALS RTC Battery JSW1,JSW2 JWIN1 Wire between IO/B & WIN/B FFC between IO/B & SW/B ( FFC x ) 3 JWIN1 JSW1,JSW2 SWITCH BOARD ON/OFF BTN VOL UP/DOWN BTN POWER LED (BLUE/AMB) WIN BUTTON BOARD Window Home Key Reset BTN Prox Sensor 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 2012/06/02 Deciphered Date Title SYSTEM MAP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC V1JB1 M/B LA-A041P Schematic Date: A B C D Wednesday, March 13, 2013 Sheet E 50 of 52 Rev 0.1 V ersion Change L ist ( P I R L ist ) Item Page# D Title D ate R equest O w ner Page Issue D escription Solution D escription R ev DVT D 01 Add net " IO/B_DET" to detect IO/B - Avoid thermal sensor wrong action by remote mode cause system auto shut down 02 Add clips at ext USB area (RF requirement) 03 Move D_LOCK pull up resistor from IO/B to M/B side (Reserve function) 04 Move ON/OFFBTN# circuit from IO/B to M/B side(Sub/B just SW BTN only) 05 Change R960 to 8.2k ohm (Board ID update) 06 Change RP19, RP20 package to R_0402*8 (HDMI signal fine tune requirement) 07 Change C451,C450 BOM structure to XEMC@ 08 Delete R78 for Layout components reduce 09 Change SIM Card Connecotor as MOLEX_503960-0694 (ME requirement) 10 Change C548 to ohm resistor (3G power from +3VS, not +3VALW) 11 Base on crystal vender suggest, change C756, C757 to 15pF, C744 & C745 to 12pF PVT C 01 Add test point at CPU pin B22, A19, B14, A11, B10, B6 (DFB requirement) 02 Modify EC_RST# circuit for Reset Button (Dual Mosfet) 03 Add ODT1, CKE1, CS1# net to DDR for 8Gb DRAMs 04 Remove EC_ON, MAINPWON net from JIO1 (un-used net) 05 Change R960 to 18k ohm (Board ID update) 06 Change R185, R186, R720 to short pad 07 Change R637 to 33 ohm (3G PWR SEQ) 08 Reserve ohm resistor to GND for sensor PB13 as ST suggestion 09 Remove Screw "H18" (ME outline modify) 10 Unstuff 3G power switch circuit (un-used -> 3G power source tie to +3VS directly) 11 Add 3G@ BOM option for WiFi only sku 12 Change R499, R503, R504 from 10k to 100k for DS5 power consumption C R10 B 01 Change RP43 part number from SD302220A00(22 ohm) to SD309220A80 (22 ohm) for Green BOM request 02 Unstuff component of reserve circuit (un-used function) -> R503, Q7 (SIM_DET# to EC), R504 (EC_3G_ON_OFF#), R260, R311, R505, C407 (3G Ext RST#) 03 Change R960 to 33k ohm (Board ID update) 04 Unstuff R485 to avoid leakage to wlan module ( 3G provide power when S3/DS3) 05 Unstuff SW5 (for test phase only, MP remove) 06 Update PCB PN to R10 07 As source request (cancel vender-Cheng Hann), change below parts~ Change L23 PN from SM01000AX00 to SM01000EP00 Change L3, L4, L36, L38, L39, L40, L53, L68 PN from SM070001600 to SM070001E00 Change L52 PN from SM070001310 to SM070001E00 B R20 01 Add USB switch to 3G USB signals for avoid DS3 leakage 02 Delete Q7, R503 (un-used component) 03 Rename EC_SIM_DET# to EC_3G_PWR_EN# (correct net name to meet actual function) 04 Change EC GPD7 (U53.M12) to EC_3G_USB_ON for 3G USB switch 05 Change R960 to 56k ohm (Board ID update) 06 Update PCB PN to R20 A A Compal Secret Data Security Classification Issued Date 2011/06/13 2012/06/13 Deciphered Date Title Compal Electronics, Inc EE P.I.R THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 0.1 V1JB1 M/B LA-A041P Schematic Date: Tuesday, March 26, 2013 Sheet 51 of 52 A ZZZ1 C D E WLAN/BT Module PCB B LA-A041P MB Rev0: DAA0006P000 U1 PK29S004B00 S_W/L_MOD WCBN3501A W/BT MD222 ABO! LA-A041P MB Rev2: DAA0006P020 LA-A041P REV2 DAA0006P020 LIONMD222@ LA-A041P MB Rev1: DAA0006P010 W CBN3501A W /BT MD222 CPU UCPU1 UCPU1 S IC AV8063801058401 SR0N9 L1 1.8G ABO! I33217@ S IC AV8063801119500 SR0XF L1 1.9G ABO! I33227@ SA00005L5C0 SA00006D990 AV8063801119500 SR0XF L1 1.9G ABO! AV8063801058401 SR0N9 L1 1.8G ABO! UCPU1 UCPU1 S IC AV8063801058002 SR0N8 L1 1.7G ABO! I53317@ S IC AV8063801129900 SR0XL L1 1.8G ABO! I53337@ SA00005K6B0 SA00006D860 AV8063801129900 SR0XL L1 1.8G ABO! AV8063801058002 SR0N8 L1 1.7G ABO! 2 UCPU1 UCPU1 S IC AV8062701313000 SR0U3 J1 1.4G ABO! I32365M@ S IC AV8062701313100 SR0U4 J1 1.5G ABO! I32375M@ SA00005UH40 SA00006ED50 AV8062701313100 SR0U4 J1 1.5G ABO! SAGE 3G AV8062701313000 SR0U3 J1 1.4G ABO! 3 4 Compal Electronics, Inc Compal Secret Data Security Classification 2011/06/24 Issued Date Deciphered Date 2012/07/12 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Option Component Size Document Number Custom V1JB1 M/B LA-A041P Schematic Date: Sheet Thursday, March 14, 2013 E 52 of 52 Rev 0.1 ... 1 Compal Electronics, Inc Compal Secret Data Security Classification 3.3K_0402_5% LPC Reserved SPI D Title PCH (1/8) SATA,HDA,SPI, LPC, XDP Size Document Number Custom Rev 0.1 V1JB1 M/B LA- A041P. .. 3.3 0.001 Display DAC Analog Power This power is supplied by the core well VccADPLLA 1.05 0.08 Display PLL A power C523 0.1U_0201_10V6K VccADPLLB 1.05 0.08 Display PLL B power place near AG16... INC V1JB1 M/B LA- A041P Schematic Date: Tuesday, March 26, 2013 Sheet 23 of 52 Rev 0.1 For Wireless LAN SAGE 3G 60mil +3VS +3VS_W LAN Mini Card Power Rating +3VS_W LAN U1 +3VS_W LAN J10 D JUMP_43X79