8 ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5% ALL CAPACITANCE VALUES ARE IN MICROFARADS ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ REV ECN DESCRIPTION OF REVISION CK APPD DATE SCHEM,WHITE_ARROW,MLB,K18 02/01/10 (.csa) D Page TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM C TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM B TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 39 40 41 42 43 45 46 48 49 Date Contents Sync Table of Contents System Block Diagram Power Block Diagram Revision History BOM Configuration Functional / ICT Test Power Aliases Signal Aliases CPU DMI/PEG/FDI/RSVD CPU Clock/Misc/JTAG CPU DDR3 Interfaces CPU Power (1 of 2) CPU Power (2 of 2) CPU Grounds CPU Non-GFX Decoupling (1 of 2) CPU Non-GFX Decoupling (2 of 2) PCH SATA/PCIE/CLK/LPC/SPI PCH DMI/FDI/Graphics PCH PCI/FlashCache/USB PCH MISC PCH Power PCH Grounds PCH Non-GFX Decoupling CPU/PCH GFX Decoupling eXtended Debug Port (XDP) Clock (CK505) Chipset Support DDR3 SO-DIMM Connector A DDR3 Byte/Bit Swaps DDR3 SO-DIMM Connector B CPU Memory S3 Support FSB/DDR3/FRAMEBUF Vref Margining X16/ALS/CAMERA CONNECTOR SecureDigital Card Reader USB HUB USB HUB Ethernet PHY (Caesar II/IV) Ethernet Connector FireWire LLC/PHY (FW643) FireWire Port Power FireWire Ports SATA Connectors External USB Connectors Front Flex Support SMC MASTER (.csa) Page TABLE_TABLEOFCONTENTS_HEAD MASTER 06/30/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/30/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF MASTER TABLE_TABLEOFCONTENTS_ITEM MASTER 05/28/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF MASTER TABLE_TABLEOFCONTENTS_ITEM MASTER MASTER TABLE_TABLEOFCONTENTS_ITEM MASTER 06/11/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 08/24/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 10/07/2009 TABLE_TABLEOFCONTENTS_ITEM K18_MLB 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/23/2009 TABLE_TABLEOFCONTENTS_ITEM K17_MLB 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF MASTER TABLE_TABLEOFCONTENTS_ITEM MASTER MASTER TABLE_TABLEOFCONTENTS_ITEM MASTER MASTER TABLE_TABLEOFCONTENTS_ITEM MASTER 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K18_COMMS 08/26/2009 TABLE_TABLEOFCONTENTS_ITEM T27_REF 10/07/2009 TABLE_TABLEOFCONTENTS_ITEM K18_MLB 10/06/2009 TABLE_TABLEOFCONTENTS_ITEM K23F 08/20/2009 TABLE_TABLEOFCONTENTS_ITEM T27_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 05/29/2009 TABLE_TABLEOFCONTENTS_ITEM K19_MLB 05/29/2009 TABLE_TABLEOFCONTENTS_ITEM K19_MLB 05/29/2009 TABLE_TABLEOFCONTENTS_ITEM K19_MLB 10/01/2009 TABLE_TABLEOFCONTENTS_ITEM T27_REF 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF 05/29/2009 TABLE_TABLEOFCONTENTS_ITEM K19_MLB 06/15/2009 TABLE_TABLEOFCONTENTS_ITEM K17_REF TABLE_TABLEOFCONTENTS_ITEM 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 50 51 52 53 54 55 56 57 58 59 60 61 62 63 65 66 67 68 69 70 72 73 74 75 76 77 78 79 80 81 82 84 85 86 87 88 89 90 93 94 95 96 97 98 99 Date Contents Sync SMC Support LPC+SPI Debug Connector K18 SMBus Connections Current & Voltage Sensing Current Sensing Thermal Sensors Fan Connectors WELLSPRING WELLSPRING Sudden Motion Sensor (SMS) DEBUG SENSORS AND ADC SPI ROM AUDIO: CODEC/REGULATOR AUDIO: LINE INPUT FILTER AUDIO: HEADPHONE FILTER AUDIO: SPEAKER AMP AUDIO: JACKS AUDIO: JACK TRANSLATORS DC-In & Battery Connectors PBus Supply & Battery Charger 5V / 3.3V Power Supply 1.5V DDR3 Supply CPU IMVP VCore Regulator GFX IMVP VCore Regulator CPUVTT (1.05V) Power Supply Misc Power Supplies Power FETs Power Control NV GT216 PCI-E NV GT216 CORE/FB POWER NV GT216 FRAME BUFFER I/F GDDR3 Frame Buffer A (Top) GDDR3 Frame Buffer B (Top) NV GT216 GPIO/MIO/MISC GT216 GPIOS & STRAPS NV GT216 VIDEO INTERFACES GPU (GT216) CORE SUPPLY LVDS Display Connector Muxed Graphics Support DisplayPort Connector 1V8 / 1V55 FB Power Supply Graphics MUX (GMUX) LCD BACKLIGHT DRIVER LCD Backlight Support Misc Power Supplies 06/29/2009 K18_SENSORS 06/23/2009 K17_MLB 06/18/2009 K18_SENSORS 06/29/2009 K18_SENSORS 07/02/2009 K18_SENSORS 06/18/2009 K18_SENSORS 05/29/2009 K19_MLB 05/29/2009 K19_MLB 05/29/2009 K19_MLB 05/29/2009 K19_MLB 07/07/2009 K18_SENSORS 06/15/2009 K17_REF 09/21/2009 K18_AUDIO 07/29/2009 K18_AUDIO 07/29/2009 K18_AUDIO 07/29/2009 K18_AUDIO 07/29/2009 K18_AUDIO 07/29/2009 K18_AUDIO 06/30/2009 K18_POWER 06/30/2009 K18_POWER 07/13/2009 K18_POWER 07/14/2009 K18_POWER 06/29/2009 K18_POWER 07/08/2009 K18_POWER 07/14/2009 K18_POWER 06/29/2009 K18_POWER 06/10/2009 K18_POWER 06/15/2009 K17_REF 06/15/2009 K17_REF 06/15/2009 K17_REF 06/15/2009 K17_REF 06/15/2009 K17_REF 06/15/2009 K17_REF 06/15/2009 K17_REF 06/15/2009 K17_REF 06/15/2009 K17_REF 07/14/2009 K18_POWER 05/29/2009 K19_MLB 06/15/2009 K17_REF 06/15/2009 K17_REF 06/26/2009 K18_POWER 06/15/2009 K17_REF 07/29/2009 K18_BKLT 05/29/2009 K19_MLB 06/10/2009 K18_POWER (.csa) Page TABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM 91 92 93 94 95 96 97 98 99 100 101 101 102 103 104 105 106 107 108 109 132 CPU Constraints Memory Constraints PCH Constraints PCH Constraints Ethernet Constraints FireWire Constraints SMC Constraints GPU (GT216) CONSTRAINTS Project Specific Constraints PCB Rule Definitions BluRay Decrypter Card Connector D Date Sync 06/15/2009 K17_REF 06/15/2009 K17_REF 06/15/2009 K17_REF 06/15/2009 K17_REF 06/15/2009 K17_REF 06/15/2009 K17_REF 06/15/2009 K17_REF 06/15/2009 K17_REF 06/15/2009 K17_REF 06/15/2009 K17_REF 06/15/2009 K17_REF TABLE_TABLEOFCONTENTS_ITEM C B TABLE_TABLEOFCONTENTS_ITEM ALIASES RESOLVED A 100 Contents A DRAWING TITLE SCHEM,WHITE_ARROW,MLB,K18 Schematic / PCB #’s PART NUMBER DRAWING NUMBER Apple Inc QTY DESCRIPTION REFERENCE DES CRITICAL 051-8504 SCHEM,WHITE_ARROW,MLB,K18 SCH CRITICAL 820-2850 PCBF,WHITE_ARROW,MLB,K18 PCB CRITICAL BOM OPTION R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED DRAWING TITLE=MLB ABBREV=DRAWING LAST_MODIFIED=Mon Feb 10:13:48 2010 SIZE D REVISION BRANCH PAGE OF 132 SHEET OF 101 U2600 INTEL CPU U8000 XDP CONN PRAPHICS 2.X GHZ NV GT216 ARRANDALE PG 25 PG PG 73 J2900 UDIMMs DDR3-1067/1333MHZ D DIMM D J6950 PG 28,30 DC/BATT POWER SUPPLY PG 63 GPIO PG 20 FDI DMI RTC PG 18 PG 18 PG 17 U4900 TEMP SENSOR CLOCK CK505 U2700 Misc CLK PG 44 PG 20 U6100 BUFFER P8 26 PG 17 J4500 SATA Conn HD SPI FAN CONN AND CONTROL PG 56 1.05V/3GHZ PG 51 INTEL SATA U4900 ADC B,0 BSB IBEX PEAK-MPCH SATA SMC LPC PG 17 1.05V/3GHZ C J5650,5660 PG 17 P8 40 J4501 POWER PGSENSE 44 SPI Boot ROM Fan Ser Prt J5100 PG 44 LPC Conn Port80,serial C PG 46 Conn ODD PG 17 U1800 P8 40 J9000 PWR DISPLAY PORT CONN CTRL DP OUT PG 84 RGB OUT U9600 GMUX XP2-5 LVDS OUT PG 85 USB PG 18 PG 19 TMDS OUT PCI PG 19 J9400 LVDS CONN B (UP TO 14 DEVICES) DVI OUT PCI-E 10 11 12 13 J3401 HDMI OUT J5713 Bluetooth PG 33 J3401 TRACKPAD/ KEYBOARD J3401 IR PG 33 PG 52 J4600,J4610,4720 CAMERA EXTERNAL USB Connectors PG 33 PG 41 B PG 19 SMB JTAG PG 71 SMB CONN PG 17 PG 17 HDA PCI-E PEG PG 47 DIMM’s (UP TO 16 LINES) PG 17 PG 17 PG 17 U6200 Audio Codec PG 57 U4100 A U3900 U6500 J3500 GB E-NET FW643 BCM5764M EXPRESSCARD CONN Line In Amp HEADPHONE Amp Speaker Amps PG 59 PG 60 PG 37 PG 35 U6610,6620,6630,6640,6650 Line Out Amp SYNC_MASTER=K17_REF SYNC_DATE=06/30/2009 PAGE TITLE System Block Diagram PG 34 DRAWING NUMBER J3400 J4310 Apple Inc J4000 R Mini PCI-E AirPort E-NET Conn E-NET Conn PG 39 PG 36 J6780,6781,6782,6700,6750 NOTICE OF PROPRIETARY PROPERTY: Audio Conns PG 28 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED PG 61 SIZE D REVISION BRANCH PAGE OF 132 SHEET OF 101 A K17 POWER SYSTEM ARCHITECTURE PPDCIN_G3H_OR_PBUS_R SMC PWRGD NCP303LSN U5000 (PAGE 45) R6905 SMC_RESET_L ENABLE SMC AVREF SUPPLY 3.425V G3HOT J6900 V F7040 D SMC_TPAD_RST_L U7000 VIN PPVBAT_G3H_CHGR_REG VIN VOUT PP5V_S3_GPUVCORE VDD F7041 8A FUSE ISL6259HRTZ SMC_DCIN_ISENSE PBUS SUPPLY/ BATTERY CHARGER ISL6263C U8900 PPVCORE_GPU PP5V_S0_CPUVTTS0 VIN U5410 PGOOD EN V A CPU VCORE VOUT VIN ISL9522 A SMC_CPU_FSB_ISENSE CPUVTTS0_PGOOD CPUVTTS0_EN (PAGE 69) GPUVCORE_PGOOD SMC_CPU_HI_ISENSE PPCPUVTT_S0 TPS51513 U7600 SMC_GPU_ISENSE R5388 PPVBAT_G3H_CHGR_R A VOUT 1.05V (PAGE 81) Q7055 PPVBATT_G3H_CONN A U5001 R7640 SMC_GPU_VSENSE PGOOD GPUVCORE_EN SMC_BATT_ISENSE (PAGE 64) J6950 V GPU VCORE A R7050 VOUT VR_ON SMC_CPU_VSENSE PPVCORE_S0_CPU IBEX PEAK MPM_PWRBTN_L PWRBTN# SMC_CPU_ISENSE U7400 SYS_RERST# CPUIMVP_VR_ON VR_ON CHGR_BGATE RSMRST# CPUIMVP_GOOD PGOOD ACPRESENT (PAGE 67) PM_PCH_PWRGD PLT_RERST_L PS_PWRGD C PLTRST# U1800 GMUX U9600 XP2-5 PB16B EG_RAIL1_EN P1V1GPU_EN PB17A EG_RAIL2_EN P3V3GPU_EN PB17B EG_RAIL3_EN GPUVCORE_EN PB18A EG_RAIL4_EN PP5V_S3_DDRREG SMC_DDR_ISENSE VIN P1V1GPU_EN EN1 PP1V1_S0GPU VIN DDRVTT_EN VOUT1 R5413 1.103V(L/H) P1V8FB_EN U4900 RC P60 (PAGE 44) DELAY SMC_PM_G2_EN EN2 1.8V(R/H) ISL6236 U9500 (PAGE 85) P3V3S5_EN A VOUT2 VLDOIN 1.5V S5 VOUT1 S3 0.75V VOUT2 PPVTT_S0_DDR_LDO CPU PP1V8_S0GPU TPS51116 DDRREG_PGOOD U7300 PGOOD (PAGE 66) SMC_GPU_1V8_ISENSE POK1 P1V1GPU_PGOOD POK2 P1V8FB_PGOOD PP1V5_S0 SLG5AP020 VOUT P1V5DDR_EN RESET* (PAGE 9~14) Q7850 PP1V2_GMUX_FET P5VS0_EN VIN EN1 5V EN2 3.3V VOUT1 P3V3S5_EN RC RC BKLT_PLT_RST_L && LCD_BKLT_EN DDRREG_EN DELAY U1800 P3V3S3_EN U9700 BKLT_EN VOUT PP3V3_S5 VIN P1V2ENET_EN ISL8009B EN (R/H) Q7870 U7760 VOUT U7980 PP1V2_ENET (PAGE 70) RSMRST_PWRGD P5VS3_PGOOD PPVOUT_S0_LCDBKLT P1V5_EXP_S0_EN EN P3V3GPU_EN VIN ISL8009B U7710 Q7922 PP3V3_S0_PWRCTL LTC1872 VIN U7790 VIN P1V8_S0_EN EN (PAGE 70) P3V3S0_EN SMC_ADAPTER_EN&&PM_SLP_S3_L RC DELAY P1V2GMUX_EN U7720 GFX_VR_ENVR_ON RES* PP1V8_S0 P1V8S0_PGOOD U4900 (PAGE 44) PP3V3_S0 A PP1V5_S0 U7971 ADJ1 PP3V3_FW_FET ISL88042IRTEZ RST* PP1V05_S0 PPVCORE_S0_GFX ADJ2 FW_PWR_EN (PAGE 72) TPS51981 TRST = 200mS U7500 SYNC_MASTER=K17_REF Power Block Diagram (PAGE 68) CPUVTTS0_EN SYNC_DATE=06/30/2009 PAGE TITLE DRAWING NUMBER P3V3S0_EN GFX_DPRSLPVR DPRSLPVR SMC_RESET_L PM_SLP_S3_L VCC Q4291 V P5VS0_EN PM_SLP_S4_L SLP_S3_L(P93) VOUT (PAGE 70) PGOOD R7540 GFXIMVP_ISENSE VIN VOUT P1V8S0_EN SLP_S5_L(P95) Q3810 1.05V AUX RC DELAY ISL8014 SMC_GFX_VSENSE R7978 PM_SLP_S3_L_R PM_PWRBTN_L P17(BTN_OUT) PM_SLP_S5_L SLP_S4_L(P94) S0PGOOD_PWROK PP3V3_S0_FET VOUT P5VS3_PGOOD PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN Q7830 SLP_S3#(P12) IMVP_VR_ON PM_SYSRST_L PP3V3_ENET P3V3S3_EN (PAGE 17~22) 99ms DLY IMVP_VR_ON(P16) SYSRST(PA2) PP3V3_S3 PFWBOOST PM_RSMRST_L RSMRST_OUT(P15) (PAGE 70) Q7810 Q4260 RSMRST_IN(P13) PWR_BUTTON(P90) OUT P1V8S0_PGOOD PM_SLP_S3_L (P64) SMC_ONOFF_L PP1V5_EXP_S0 PGOOD Apple Inc GFXIMVP_PGOOD NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED P1V5DDR_EN SIZE D REVISION R PBUSVSENS_EN B SMC_ADAPTER_EN PWRGD(P12) (PAGE 87) PM_SLP_S4_L SMC ALL_SYS_PWRGD PP3V3_S0_GPU P3V3S5_PGOOD VIN APP001 ENA SLP_S4#(H7) PP3V3_S5 VOUT2 TPS51980 U7201 (PAGE 65) PGOOD1 PGOOD2 P5VS3_EN DELAY P1V2GMUX_EN PP5V_S3 PM_ALL_GPU_PGOOD (L/H) PM_SLP_S5_L Q9806 SM_DRAMPWROK U1000 VCCCPUPWRGD Q7860 PP5V_S0_FET P5VS3_EN B RC DELAY PP1V5_S3 U7801 SLP_S5#(E4) RC DELAY (PAGE 17~22) V A PPDDR_S3_REG ON IBEX_PEAK_M A U2850 SMC_CPU_DDR_VSENSE R7350 DDRREG_EN SMC C PM_MEM_PWRGD P1V8_S0GPU_EN (PAGE 86) CPU_PWRGD PROCPWRGD DRAMPWROK U5440 PM_ALL_GPU_PGOOD PL32A D SMC_ONOFF_L A DCIN(16.5V) IN 2S4P VR5020 VOUT (PAGE 45) R7020 ADAPTER (6 TO 8.4V) VIN PPBUS_G3H F6905 6A FUSE AC Q5315 PP3V3_S5_AVREF_SMC PP3V42_G3H LT3470A U6990 (PAGE 63) SMC_PBUS_VSENSE BRANCH PAGE OF 132 SHEET OF 101 A PROTO: D D C C B B A SYNC_MASTER=MASTER SYNC_DATE=MASTER PAGE TITLE Revision History DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE OF 132 SHEET OF 101 A BOM NAME BOM OPTIONS PART NUMBER ALTERNATE FOR PART NUMBER 138S0603 BOM OPTION REF DES COMMENTS: 138S0602 ALL Murata alt to Samsung 157S0058 157S0055 ALL Delta alt to TDK Magnetics 152S0896 152S0518 ALL MAG LAYERS ALT TO CYNTEC 155S0457 155S0329 ALL MAG LAYERS ALT TO MURATA 333S0506 333S0535 ALL Hynix 900M alt to 1000M 516S0805 516S0806 ALL Molex alt to Foxconn 152S1102 152S1088 ALL Mag layer alt to Vishay TABLE_BOMGROUP_ITEM PCBA,2.0G,512SAM_VRAM,K18 TABLE_ALT_ITEM K18_COMMON,CPU_2_4GHZ,FB_256_SAMSUNG,K18_PVT,EEEE_DCJ7 TABLE_BOMGROUP_ITEM 639-0953 PCBA,2.0G,512HYN_VRAM,K18 K18_COMMON,CPU_2_4GHZ,FB_256_HYNIX,K18_PVT,EEEE_DCJ8 639-0954 PCBA,2.13G,512SAM_VRAM,K18 K18_COMMON,CPU_2_53GHZ,FB_512_SAMSUNG,K18_PVT,EEEE_DCJ9 TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM TABLE_ALT_ITEM TABLE_BOMGROUP_ITEM 639-0955 PCBA,2.13G,512HYN_VRAM,K18 TABLE_ALT_ITEM K18_COMMON,CPU_2_53GHZ,FB_512_HYNIX,K18_PVT,EEEE_DCJC TABLE_BOMGROUP_ITEM 639-0956 PCBA,2.4G,512SAM_VRAM,K18 TABLE_ALT_ITEM K18_COMMON,CPU_2_66GHZ,FB_512_SAMSUNG,K18_PVT,EEEE_DCJD TABLE_BOMGROUP_ITEM D 639-0957 PCBA,2.4G,512HYN_VRAM,K18 TABLE_ALT_ITEM K18_COMMON,CPU_2_66GHZ,FB_512_HYNIX,K18_PVT,EEEE_DCJF TABLE_BOMGROUP_ITEM 085-1404 TABLE_ALT_HEAD TABLE_BOMGROUP_HEAD 639-0952 Alternate Parts BOM Variants BOM NUMBER D TABLE_ALT_ITEM K18 DEVELOPMENT BOM TABLE_ALT_ITEM 353S2805 353S2603 ALL Fairchild wafer option 333S0542 333S0507 ALL Samsung I die alt to H 128S0264 128S0257 ALL Sanyo alt to Kemet 128S0303 128S0282 ALL Panasonic alt to Sanyo 337S3808 337S3839 ALL A02 alt to A03 GPU 128S0305 128S0294 ALL 6.3V alt to 11V Sanyo TABLE_ALT_ITEM TABLE_ALT_ITEM K18 BOM GROUPS TABLE_ALT_ITEM TABLE_BOMGROUP_HEAD BOM GROUP TABLE_ALT_ITEM BOM OPTIONS TABLE_BOMGROUP_ITEM K18_COMMON TABLE_ALT_ITEM ALTERNATE,COMMON,K18_COMMON1,K18_COMMON2,K18_PROGPARTS,USBHUB_2061,RDRV:8515A2,DCI TABLE_BOMGROUP_ITEM K18_COMMON1 BATT_3S,BCM5764M,GL137,CPUPOC_IMAX_40_50,CPUMEM_S0,SMC_EXCARD_NOT,SMC_DEBUG_YES,HUB1_2NONREM,HUB2_3NONREM K18_COMMON2 GMUXPLL_3V3,GPU_SS_INT,MIKEY,GPUVID_0P90V,DPMUX_EN_PLD,DP_CA_DET_EG_PLD,DP_ESD,VFRQ_SLPS3,SMC_OSC_YES,RAIL_MON K18_PVT BMON_PROD,VREFMRGN_NOT,XDP,XDP_NORMAL,XDP_CPU_BPM K18_PROGPARTS GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_HEAD BOM GROUP BOM OPTIONS FB_256_SAMSUNG VRAM4,VRAM_256_SAMSUNG,FB1V55 FB_256_HYNIX VRAM4,VRAM_256_HYNIX,FB1V55 FB_512_SAMSUNG VRAM4,VRAM_512_SAMSUNG,FB1V35 FB_512_HYNIX VRAM4,VRAM_512_HYNIX,FB1V35 TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM C C Bar Code Labels / EEE #’s B A PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE:DCJ7] CRITICAL EEEE_DCJ7 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE:DCJ8] CRITICAL EEEE_DCJ8 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE:DCJ9] CRITICAL EEEE_DCJ9 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE:DCJC] CRITICAL EEEE_DCJC 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE:DCJD] CRITICAL EEEE_DCJD 826-4393 LBL,P/N LABEL,PCB,28MM X MM [EEEE:DCJF] CRITICAL EEEE_DCJF DESCRIPTION REFERENCE DES CRITICAL BOM OPTION Module Parts PART NUMBER QTY 337S3848 ARD,SLBPE,PRQ,2.66G,35W,C2,3M,BGA U1000 CRITICAL CPU_2_66GHZ 337S3847 ARD,SLBPF,PRQ,2.53G,35W,C2,3M,BGA U1000 CRITICAL CPU_2_53GHZ 337S3846 ARD,SLBNA,PRQ,2.4G,35W,C2,4M,BGA U1000 CRITICAL CPU_2_4GHZ 337S3849 IC,PCH,IBEX PEAK-M,SLGZS,PRQ,B3,BGA U1800 CRITICAL 337S3839 IC,GPU,NV GT216 LP++,969BGA,40NM,A03 U8000 CRITICAL 343S0493 IC,ASIC,BCM5764M,ENET CONTROLLER,8x8,64 QFN U3900 CRITICAL 341S2731 IC,1MBIT,SPI FLASH,K17/K18 U3990 CRITICAL 338S0753 IC,FW643-E2,1394B PHY/OHCI LINK/PCI-E,12 U4100 CRITICAL 338S0563 IC,SMC,HS8/2117,9MMX9MM,TLP U4900 CRITICAL 341T0233 IC,SMC,K18 U4900 CRITICAL SMC_PROG 335S0610 IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP U6100 CRITICAL BOOTROM_BLANK BOOTROM_PROG 341S2562 IC,EFI ROM,DEVELOPMENT,K18 U6100 CRITICAL 341S2384 IR,ENCORE II, CY7C63833-LFXC U4800 CRITICAL BCM5764M SMC_BLANK 341S2616 IC,PSOC +W/USB,56PIN,MLF,K18 U5701 CRITICAL TPAD_PROG 336S0025 IC,XP2-5,HF,CPLD,BLANK U9600 CRITICAL GMUX_5K_BLANK 341S2566 IC,CPLD,LATTICE,132CSBGA,K18 U9600 CRITICAL GMUX_PROG 333S0507 CRITICAL VRAM_256_SAMSUNG 333S0483 U8400,U8450,U8500,U8550 CRITICAL VRAM_256_HYNIX 333S0533 IC,SGRAM,GDDR3,32MX32,1000MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_512_SAMSUNG 333S0535 IC,SDRAM,GDDR3,32MX32,1000MHZ,136 FBGA U8400,U8450,U8500,U8550 CRITICAL VRAM_512_HYNIX IC,SGRAM,GDDR3,16MX32,1000MHZ,136 FBGA U8400,U8450,U8500,U8550 B SYNC_MASTER=K17_REF SYNC_DATE=05/28/2009 PAGE TITLE IC,SDRAM,GDDR3,16MX32,900MHZ,136 FBGA BOM Configuration DRAWING NUMBER Apple Inc R Development BOM NOTICE OF PROPRIETARY PROPERTY: PART NUMBER QTY DESCRIPTION REFERENCE DES CRITICAL BOM OPTION 085-1404 K18 MLB DEVELOPMENT DEVEL CRITICAL DEVEL_BOM THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE OF 132 SHEET OF 101 A Functional Test Points USB PORTS I1038 TRUE J5650 (LEFT FAN CONN) FUNC_TEST 70 72 86 88 PP5V_S0 TRUE 23 42 47 52 54 68 69 TRUE TRUE FAN_LT_PWM FAN_LT_TACH I1039 TRUE TPs per Fan D TRUE I1103 I1102 43 I1104 43 99 I1105 43 99 I1107 I1106 52 I1108 I1042 TRUE I1043 TRUE I1044 TRUE TRUE 52 J5660 (RIGHT FAN CONN) TRUE TRUE TRUE I1040 TRUE PP5V_S3_RTUSB_A_F USB2_LT1_N USB2_LT1_P GND FAN_RT_PWM FAN_RT_TACH GND 52 PP5V_S3_RTUSB_B_F USB_LT2_N USB_LT2_P GND 43 I1109 43 99 I1110 43 99 I1111 I1112 52 I1113 TPs per Fan I1114 I1115 I1117 J6780 (MIC CONN) I1116 I1118 TRUE TRUE TRUE I557 I558 I559 BI_MIC_N BI_MIC_SHIELD BI_MIC_P 62 63 I1119 J3401 & J3402 (AIRPORT/BT/CAMERA CONN) I1120 17 33 94 I1122 I1051 TRUE PCIE_AP_D2R_P 17 33 94 I1121 I1050 TRUE PCIE_AP_D2R_N PCIE_AP_R2D_P TRUE 33 94 I1123 I1053 33 94 I1124 I1052 TRUE PCIE_AP_R2D_N I1125 I1054 TRUE PCIE_CLK100M_AP_CONN_P 33 99 33 PCIE_CLK100M_AP_CONN_N I1127 I1056 TRUE 99 AP_CLKREQ_Q_L 33 TRUE I1126 I1055 18 27 33 I1128 I1058 TRUE PCIE_WAKE_L 33 I1129 I1057 TRUE AP_RESET_CONN_L PP3V3_WLAN TRUE 33 I1130 I1059 I1061 TRUE PP5V_S3_ALSCAMERA_F 33 J6950 (BIL CABLE CONN) I1060 TRUE SMBUS_SMC_A_S3_SDA 33 45 48 54 97 I1063 TRUE SMBUS_SMC_A_S3_SCL 33 45 48 54 97 USB_CAMERA_CONN_P TRUE 33 93 I1062 I1150 TRUE PP5V_S3_IR_R I1064 TRUE USB_CAMERA_CONN_N 33 93 I1149 TRUE SMC_LID_R 33 99 I1066 TRUE CONN_USB2_BT_P I1151 TRUE IR_RX_OUT 33 99 I1065 TRUE CONN_USB2_BT_N I1152 TRUE SYS_LED_ANODE J3500 (SD CARD CONN) GND 62 63 62 63 J6781 & J6782 (SPEAKERS CONN) I989 I990 I992 I991 I994 I993 TRUE TRUE TRUE TRUE TRUE TRUE C SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N SPKRCONN_S_OUT_P SPKRCONN_S_OUT_N 61 62 99 61 62 99 61 62 99 61 62 99 61 62 99 61 62 99 I1452 I1451 I996 I997 I998 I1000 I1001 I1002 I1004 I1003 I1005 I1007 I1006 I1009 I1008 I1010 I1011 I1012 I1014 I1013 I1015 I1016 I1017 I1018 B I1019 I1020 I1022 I1021 PP3V3_SW_LCD 83 84 85 87 88 99 50 51 52 54 58 62 63 68 69 72 PP3V3_S0 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 PPVOUT_S0_LCDBKLT 73 80 83 TP needed LVDS_DDC_CLK 83 84 LVDS_DDC_DATA 83 84 LVDS_CONN_A_DATA_P 83 84 98 LVDS_CONN_A_DATA_N 83 84 98 LVDS_CONN_A_DATA_P 83 84 98 LVDS_CONN_A_DATA_N 83 84 98 LVDS_CONN_A_DATA_P 83 84 98 LVDS_CONN_A_DATA_N 83 84 98 LVDS_CONN_A_CLK_F_P 83 98 LVDS_CONN_A_CLK_F_N 83 98 LVDS_CONN_B_DATA_P 83 84 98 LVDS_CONN_B_DATA_N 83 84 98 LVDS_CONN_B_DATA_P 83 84 98 LVDS_CONN_B_DATA_N 83 84 98 LVDS_CONN_B_DATA_P 83 84 98 LVDS_CONN_B_DATA_N 83 84 98 LVDS_CONN_B_CLK_F_P 83 98 LVDS_CONN_B_CLK_F_N 83 98 LED_RETURN_1 83 88 LED_RETURN_2 83 88 LED_RETURN_3 83 88 LED_RETURN_4 83 88 LED_RETURN_5 83 88 LED_RETURN_6 83 88 GND TPs TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE I1453 I1454 I1455 PP5V_SW_ODD SMC_ODD_DETECT SATA_ODD_D2R_C_P SATA_ODD_D2R_C_N SATA_ODD_R2D_P SATA_ODD_R2D_N GND I1026 TRUE I1025 I1028 I1027 I1029 TRUE TRUE TRUE TRUE TRUE I1086 TRUE I1273 TRUE I1089 TRUE I1088 TRUE I1090 TRUE I1464 I1098 I1097 I1095 I1096 I1094 TPs I1099 42 56 I1100 42 45 I1101 42 93 42 93 I1031 TRUE I1033 TRUE I1035 TRUE I1034 TRUE 42 93 42 93 A TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE PP18V5_S3 42 42 93 42 93 42 93 SPIROM_USE_MLB SPI_ALT_CLK SPI_ALT_CS_L SPI_ALT_MISO SPI_ALT_MOSI SYS_LED_ANODE_R TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD 17 45 47 18 45 47 18 27 45 45 47 TP_CPU_RSVD_NCTF 45 47 18 45 46 47 18 45 46 47 18 45 48 54 97 45 48 54 97 64 TRUE J5815 (KBD BACKLIGHT CONN) KBDLED_ANODE 54 SMC_KDBLED_PRESENT_L 54 45 46 47 18 45 47 18 20 47 57 18 47 18 18 47 18 42 18 42 17 NC_CRT_IG_HSYNC NC_CRT_IG_VSYNC NC_CRT_IG_HSYNC TRUE MAKE_BASE=TRUE NC_CRT_IG_VSYNC TRUE MAKE_BASE=TRUE NC_LVDS_IG_CTRL_CLK NC_LVDS_IG_CTRL_DATA NC_PCH_LVDS_VBG NC_LVDS_IG_CTRL_CLK TRUE MAKE_BASE=TRUE TRUE NC_LVDS_IG_CTRL_DATA MAKE_BASE=TRUE NC_PCH_LVDS_VBG TRUE MAKE_BASE=TRUE 64 17 NC_HDA_SDIN1 NC_HDA_SDIN2 NC_HDA_SDIN3 J6995 (BAT LED CONN) PP3V42_G3H TRUE SMBUS_SMC_BSA_SDA TRUE SMBUS_SMC_BSA_SCL TRUE SMC_BIL_BUTTON_L I1142 GND I1141 I1143 42 44 TRUE GND 17 73 64 65 66 17 48 49 53 17 21 23 43 45 46 47 17 6 45 48 64 65 97 45 48 64 17 65 97 45 46 64 17 17 GND 17 TRUE TPs GND 17 17 17 19 19 TRUE PM_SLP_S3_L 18 31 45 73 85 TRUE PP0V75_S0_DDRVTT 28 30 31 67 54 TRUE PP18V5_S3 I603 TRUE PP1V05_S0 10 12 13 15 17 18 20 21 23 24 I604 25 26 40 70 73 86 PP1V05_S0GPU TRUE 74 76 79 81 86 I605 PP1V05_S5 TRUE 17 71 I607 TRUE PP1V0_FW_FWPHY 39 40 I606 37 71 72 TRUE PP1V2_ENET I610 TRUE PP1V2_S0 72 87 I612 TRUE PP1V5_S3 28 30 31 67 72 I611 PP1V5_S3RS0 TRUE 13 16 31 42 72 73 99 I613 PP1V8R1V55_S0GPU_ISNS 50 56 75 76 77 78 TRUE I600 PP1V8R1V55_S0GPU_ISNS_R 50 86 TRUE I625 TRUE PP1V8_GPUIFPX 72 81 I624 TRUE PP1V8_S0 12 16 21 23 24 58 71 72 87 I623 TRUE PP3V3_ENET 27 37 73 I620 TRUE PP3V3_FW_FWPHY 39 40 41 I621 83 84 85 87 88 99 50 51 52 54 58 62 63 68 69 72 TRUE PP3V3_S0 17 18 19 20 21 23 24 25 26 I618 27 28 30 34 37 40 42 46 47 48 73 80 PP3V3_S0GPU TRUE 72 74 79 80 81 82 84 I617 TRUE PP3V3_S3 17 20 31 32 33 34 35 36 48 50 53 54 I615 55 72 73 87 101 TRUE PP3V3_S5 17 18 19 20 21 23 27 31 35 57 I616 66 71 72 73 83 85 99 TRUE PP3V3_S5_AVREF_SMC 45 46 I614 PP3V42_G3H TRUE 17 21 23 43 45 46 47 48 49 I627 53 64 65 66 73 TRUE PP5V_S0 23 42 47 52 54 68 69 70 72 I626 86 88 TRUE PP5V_S3 31 33 42 43 44 46 54 56 58 61 66 67 72 I639 82 101 TRUE PP5V_S5 23 66 72 I638 PPBUS_G3H TRUE 40 49 65 66 67 69 70 82 86 89 I637 TRUE PPDCIN_G3H 64 65 I636 TRUE PPVCORE_GPU 49 75 82 I709 PPVCORE_S0_CPU 12 15 49 68 I714 TRUE PPVCORE_S0_GFX TRUE 13 24 49 69 I1156 40 41 I1160 TRUE PPVP_FW 32 67 I1161 TRUE PPVTTDDR_S3 I640 NC_HDA_SDIN1 NC_HDA_SDIN2 NC_HDA_SDIN3 NC_PCIE_PE7_D2RN NC_PCIE_PE7_D2RP NC_PCIE_PE7_R2D_CN NC_PCIE_PE7_R2D_CP NC_PCIE_PE8_D2RN NC_PCIE_PE8_D2RP NC_PCIE_PE8_R2D_CN NC_PCIE_PE8_R2D_CP 18 18 6 18 18 6 18 18 6 18 18 19 19 19 19 TP_PCI_AD TP_PCI_C_BE_L NC_PCI_GNT3_L NC_PCI_GNT2_L NC_PCI_GNT1_L NC_PCI_GNT0_L NC_PCI_PAR NC_PCI_RESET_L NC_PCI_PME_L NC_PCI_CLK33M_OUT3 NC_PCH_NV_RCOMP TP_NV_DQ TP_NV_DQS TP_NV_CE_L 19 19 19 17 17 17 17 20 20 20 20 53 17 17 17 17 17 17 17 17 17 17 NC_NV_ALE NC_NV_CLE NC_NV_RB_L TP_NV_WR_RE_L TP_NV_WE_CK_L NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5P NC_PCIE_CLK100M_PE6N NC_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE7N NC_PCIE_CLK100M_PE7P NC_PSOC_P1_3 NC_SATA_C_D2RN NC_SATA_C_D2RP NC_SATA_C_R2D_CN NC_SATA_C_R2D_CP NC_SATA_D_D2RN NC_SATA_D_D2RP NC_SATA_D_R2D_CN NC_SATA_D_R2D_CP NC_SATA_SSD2_D2RN NC_SATA_SSD2_D2RP NC_SATA_SSD2_R2D_CN NC_SATA_SSD2_R2D_CP 18 6 17 18 6 17 TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 18 18 NC_PCI_AD 19 NC_PCI_C_BE_L NC_PCI_GNT3_L 19 NC_PCI_GNT2_L 19 NC_PCI_GNT1_L 19 NC_PCI_GNT0_L 19 NC_PCI_PAR 19 NC_PCI_RESET_L 19 NC_PCI_PME_L 19 NC_PCI_CLK33M_OUT3 TRUE 18 MAKE_BASE=TRUE 19 TRUE 18 MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 74 TRUE 80 79 MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 80 TRUE MAKE_BASE=TRUE 80 79 TRUE 80 79 MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 19 TRUE MAKE_BASE=TRUE NC_PCH_NV_RCOMP TRUE 19 MAKE_BASE=TRUE NC_NV_DQ 19 TRUE MAKE_BASE=TRUE 93 18 NC_NV_DQS TRUE 19 MAKE_BASE=TRUE 93 18 NC_NV_CE_L TRUE 19 18 MAKE_BASE=TRUE NC_NV_ALE TRUE 19 MAKE_BASE=TRUE NC_NV_CLE TRUE 19 MAKE_BASE=TRUE NC_NV_RB_L TRUE 19 20 MAKE_BASE=TRUE NC_NV_WR_RE_L 19 20 TRUE MAKE_BASE=TRUE NC_NV_WE_CK_L 19 20 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE4N 1720 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE4P 1720 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE5N 1720 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE5P 1720 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE6N 2020 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE6P 2020 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE7N 2020 TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PE7P 2020 TRUE MAKE_BASE=TRUE 20 NC_PSOC_P1_3 TRUE 53 MAKE_BASE=TRUE 20 NC_SATA_C_D2RN 17 TRUE MAKE_BASE=TRUE 20 NC_SATA_C_D2RP 17 TRUE MAKE_BASE=TRUE 20 NC_SATA_C_R2D_CN 17 TRUE MAKE_BASE=TRUE 20 NC_SATA_C_R2D_CP 17 TRUE MAKE_BASE=TRUE 20 NC_SATA_D_D2RN 17 TRUE MAKE_BASE=TRUE 20 NC_SATA_D_D2RP 17 TRUE MAKE_BASE=TRUE 20 NC_SATA_D_R2D_CN 17 TRUE MAKE_BASE=TRUE 20 NC_SATA_D_R2D_CP 17 TRUE 20 MAKE_BASE=TRUE NC_SATA_SSD2_D2RN 17 TRUE 20 MAKE_BASE=TRUE NC_SATA_SSD2_D2RP 17 TRUE 20 MAKE_BASE=TRUE NC_SATA_SSD2_R2D_CN 17 TRUE 20 MAKE_BASE=TRUE NC_SATA_SSD2_R2D_CP 17 TRUE MAKE_BASE=TRUE 20 TP_SMC_P41 NC_SMC_P41 TRUE MAKE_BASE=TRUE NC_PCIE_PE6_D2RN NC_PCIE_PE6_D2RP NC_PCIE_PE6_R2D_CN NC_PCIE_PE6_R2D_CP NC_PCIE_PE7_D2RN NC_PCIE_PE7_D2RP NC_PCIE_PE7_R2D_CN NC_PCIE_PE7_R2D_CP NC_PCIE_PE8_D2RN NC_PCIE_PE8_D2RP NC_PCIE_PE8_R2D_CN NC_PCIE_PE8_R2D_CP I767 I766 I769 I768 I770 I772 I771 I774 NC_DP_IG_D_HPD NC_DP_IG_D_CTRL_CLK NC_DP_IG_D_CTRL_DATA TP_DP_IG_D_MLP TP_DP_IG_D_MLN NC_DP_IG_D_AUXP NC_DP_IG_D_AUXN NC_SDVO_TVCLKINN NC_SDVO_TVCLKINP TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE NC_SDVO_STALLN NC_SDVO_STALLP NC_SDVO_INTN NC_SDVO_INTP 6 6 6 6 6 6 6 6 6 I1442 18 18 18 18 NC_SDVO_TVCLKINN NC_SDVO_TVCLKINP 18 18 NC_SDVO_STALLN NC_SDVO_STALLP 18 18 NC_SDVO_INTN NC_SDVO_INTP 18 TRUE TRUE TRUE TRUE TRUE TRUE TRUE PCH_VSS_NCTF 20 94 PCH_VSS_NCTF 20 94 PCH_VSS_NCTF 20 94 PCH_VSS_NCTF PCH_VSS_NCTF 20 94 PCH_VSS_NCTF 20 94 PCH_VSS_NCTF 20 94 17 I1443 I1444 I1445 I1446 I1447 I1448 I1449 I1450 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE 6 20 20 20 20 20 20 20 20 20 B 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF 20 94 20 94 20 94 20 94 20 94 20 94 20 94 20 94 17 SYNC_MASTER=MASTER 17 SYNC_DATE=MASTER PAGE TITLE 17 Functional / ICT Test 17 DRAWING NUMBER 17 Apple Inc 17 17 17 6 17 17 17 NC_CLINK_CLK NC_CLINK_DATA NC_CLINK_RESET_L 17 17 17 6 17 17 NC_PCIE_CLK100M_PEBN NC_PCIE_CLK100M_PEBP NC_CLINK_CLK 17 TRUE MAKE_BASE=TRUE NC_CLINK_DATA 17 TRUE MAKE_BASE=TRUE NC_CLINK_RESET_L TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PEBN TRUE MAKE_BASE=TRUE NC_PCIE_CLK100M_PEBP TRUE MAKE_BASE=TRUE 17 R NOTICE OF PROPRIETARY PROPERTY: 17 17 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH 17 PAGE OF 132 SHEET OF 101 C 18 NC_PCH_SST TRUE MAKE_BASE=TRUE NC_PCH_NC1 TRUE MAKE_BASE=TRUE NC_PCH_NC2 TRUE MAKE_BASE=TRUE NC_PCH_NC3 TRUE MAKE_BASE=TRUE NC_PCH_NC4 TRUE MAKE_BASE=TRUE NC_PCH_NC5 TRUE MAKE_BASE=TRUE NC_PCH_TP19 TRUE MAKE_BASE=TRUE NC_PCH_TP18 TRUE MAKE_BASE=TRUE NC_PCH_TP17 TRUE MAKE_BASE=TRUE NC_PCH_TP16 TRUE MAKE_BASE=TRUE NC_PCH_TP15 TRUE MAKE_BASE=TRUE NC_PCH_TP14 TRUE MAKE_BASE=TRUE NC_PCH_TP13 TRUE MAKE_BASE=TRUE NC_PCH_TP12 TRUE MAKE_BASE=TRUE NC_PCH_TP11 TRUE MAKE_BASE=TRUE NC_PCH_TP10 TRUE MAKE_BASE=TRUE NC_PCH_TP9 TRUE MAKE_BASE=TRUE NC_PCH_TP8 TRUE MAKE_BASE=TRUE NC_PCH_TP7 TRUE MAKE_BASE=TRUE NC_PCH_TP6 TRUE MAKE_BASE=TRUE NC_PCH_TP5 TRUE MAKE_BASE=TRUE NC_PCH_TP4 TRUE MAKE_BASE=TRUE NC_PCH_TP3 TRUE MAKE_BASE=TRUE NC_PCH_TP2 TRUE MAKE_BASE=TRUE NC_PCH_TP1 TRUE MAKE_BASE=TRUE I1441 18 18 NC_SMC_BS_ALRT_L TRUE MAKE_BASE=TRUE 6 17 18 NC_PCH_SST NC_PCH_NC1 NC_PCH_NC2 NC_PCH_NC3 NC_PCH_NC4 NC_PCH_NC5 NC_PCH_TP19 NC_PCH_TP18 NC_PCH_TP17 NC_PCH_TP16 NC_PCH_TP15 NC_PCH_TP14 NC_PCH_TP13 NC_PCH_TP12 NC_PCH_TP11 NC_PCH_TP10 NC_PCH_TP9 NC_PCH_TP8 NC_PCH_TP7 NC_PCH_TP6 NC_PCH_TP5 NC_PCH_TP4 NC_PCH_TP3 NC_PCH_TP2 NC_PCH_TP1 6 17 18 NC_SMC_BS_ALRT_L I1440 18 NC_LVDS_EG_BKL_PWM TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_CLKN TRUE MAKE_BASE=TRUE NC_LVDS_IG_B_CLKP TRUE MAKE_BASE=TRUE NC_LVDS_IG_BKL_PWM TRUE MAKE_BASE=TRUE I1439 18 18 NC_LVDS_EG_BKL_PWM TP_LVDS_IG_B_CLKN TP_LVDS_IG_B_CLKP TP_LVDS_IG_BKL_PWM 6 17 18 18 NC_GPU_BUFRST_L 74 TRUE MAKE_BASE=TRUE NC_GPU_GSTATE TRUE MAKE_BASE=TRUE NC_GPU_GSTATE TRUE MAKE_BASE=TRUE NC_GPU_MIOA_D TRUE MAKE_BASE=TRUE NC_GPU_MIOA_DE TRUE MAKE_BASE=TRUE I1437 18 NC_GPU_BUFRST_L TP_GPU_GSTATE TP_GPU_GSTATE TP_GPU_MIOA_D TP_GPU_MIOA_DE I1436 D NC_FW643_AVREG 39 TRUE MAKE_BASE=TRUE NC_FW643_TDI TRUE 39 MAKE_BASE=TRUE NC_DP_IG_C_HPD TRUE MAKE_BASE=TRUE NC_DP_IG_C_CTRL_CLK TRUE MAKE_BASE=TRUE NC_DP_IG_C_CTRL_DATA TRUE MAKE_BASE=TRUE NC_DP_IG_C_MLP TRUE MAKE_BASE=TRUE NC_DP_IG_C_MLN TRUE MAKE_BASE=TRUE NC_DP_IG_C_AUXP TRUE MAKE_BASE=TRUE NC_DP_IG_C_AUXN TRUE MAKE_BASE=TRUE NC_DP_IG_D_HPD TRUE MAKE_BASE=TRUE NC_DP_IG_D_CTRL_CLK TRUE MAKE_BASE=TRUE NC_DP_IG_D_CTRL_DATA TRUE MAKE_BASE=TRUE NC_DP_IG_D_MLP TRUE MAKE_BASE=TRUE NC_DP_IG_D_MLN TRUE MAKE_BASE=TRUE NC_DP_IG_D_AUXP TRUE MAKE_BASE=TRUE NC_DP_IG_D_AUXN TRUE MAKE_BASE=TRUE NC_DP_IG_C_HPD NC_DP_IG_C_CTRL_CLK NC_DP_IG_C_CTRL_DATA TP_DP_IG_C_MLP TP_DP_IG_C_MLN NC_DP_IG_C_AUXP NC_DP_IG_C_AUXN I1438 NC_PCIE_PE5_D2RN NC_PCIE_PE5_D2RP NC_PCIE_PE5_R2D_CN NC_PCIE_PE5_R2D_CP I765 17 18 NC NO_TESTs NO_TEST NC_PCIE_PE6_D2RN NC_PCIE_PE6_D2RP NC_PCIE_PE6_R2D_CN NC_PCIE_PE6_R2D_CP 18 I764 18 NCNO_TEST NO_TESTs 46 45 17 FUNC_TEST TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE TRUE MAKE_BASE=TRUE 64 65 17 18 42 46 17 GND 18 18 17 19 NC_PCIE_PE5_D2RN NC_PCIE_PE5_D2RP NC_PCIE_PE5_R2D_CN NC_PCIE_PE5_R2D_CP 18 6 18 18 47 17 6 45 48 64 65 97 17 6 17 18 6 18 NC_CRT_IG_DDC_CLK TRUE MAKE_BASE=TRUE NC_CRT_IG_DDC_DATA TRUE MAKE_BASE=TRUE 47 64 45 48 64 65 97 18 NC_CRT_IG_DDC_CLK NC_CRT_IG_DDC_DATA 43 45 46 47 GND I1140 TRUE I1146 TRUE NC_CRT_IG_BLUE TRUE MAKE_BASE=TRUE NC_CRT_IG_GREEN TRUE MAKE_BASE=TRUE NC_CRT_IG_RED TRUE MAKE_BASE=TRUE 45 46 47 19 6 54 39 NC_CRT_IG_BLUE NC_CRT_IG_GREEN NC_CRT_IG_RED I763 NC_SMC_FAN_3_TACH 45 46 NC_SMC_FAN_3_CTL 45 46 NC_SMC_FAN_2_TACH 45 46 NC_SMC_FAN_2_CTL 45 46 NC_FW2_TPBP 39 41 NC_FW2_TPBN 39 41 NC_FW2_TPBIAS 39 41 NC_FW2_TPAP 39 41 NC_FW2_TPAN 39 41 NC_FW0_TPBP 39 41 96 NC_FW0_TPBN 39 41 96 NC_FW0_TPAP 39 41 96 NC_ESTARLDO_EN 45 46 NC_ALS_GAIN 45 46 NC_FW643_AVREG NC_FW643_TDI 39 NO_TEST 43 45 46 47 POWER RAILS TPs NC_TP_CPU_RSVD TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD TRUE MAKE_BASE=TRUE NC_TP_CPU_RSVD_NCTF TRUE MAKE_BASE=TRUE NC NO_TESTs 45 46 53 45 46 47 65 FUNC_TEST 34 37 42 93 I1145 TRUE SMC_TX_L I762 NC NO_TESTs NO_TEST TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE I761 18 45 47 34 34 37 17 TRUE SMC_TCK SMC_TDI SMC_TDO SMC_TMS SMC_TRST_L I1297 NO_TEST 19 17 TRUE LPC_PWRDWN_L LPC_SERIRQ PM_CLKRUN_L PM_SYSRST_L SMC_MD1 SMC_NMI SMC_ONOFF_L SMC_RESET_L SMC_RX_L 34 Z2_CS_L 53 54 Z2_DEBUG3 53 54 Z2_MISO 53 54 Z2_BOOST_EN 54 Z2_SCLK 53 54 Z2_CLKIN 53 54 Z2_KEY_ACT_L 53 54 Z2_RESET 53 54 PSOC_F_CS_L 53 54 PICKB_L 53 54 PSOC_MISO 53 54 PSOC_MOSI 53 54 PSOC_SCLK 53 54 SMBUS_SMC_A_S3_SCL 33 SMBUS_SMC_A_S3_SDA 33 J6950 (MAIN BATT CONN) I1134 TRUE PPVBAT_G3H_CONN I1136 TRUE SMBUS_SMC_BSA_SCL I1135 TRUE SMBUS_SMC_BSA_SDA I1137 TRUE NC_SMC_BS_ALRT_L GND TRUE TRUE I732 TRUE I731 TRUE I734 TRUE I733 TRUE I735 TRUE TRUE I737 TRUE I739 TRUE I738 TRUE I740 TRUE I741 TRUE I742 TRUE I743 TRUE I744 TRUE I751 TRUE I752 TRUE TRUE I760 I756 TRUE I1292 TRUE I1288 TRUE I730 CPU NO_TESTs 34 GND J6900 (DC POWER CONN) I1131 TRUE ADAPTER_SENSE I1132 TRUE PP18V5_DCIN_FUSE J4501 (SATA HDD CONN) PP5V_S0_HDD_FLT SATA_HDD_R2D_P SATA_HDD_R2D_N SATA_HDD_D2R_C_N SATA_HDD_D2R_C_P SD_D SD_CMD SD_CLK SD_CD_L SD_WP J5800 (IPD FLEX CONN) TPs I1032 TRUE ICT Test Points I602 I1093 J4500 (SATA ODD CONN) TRUE TRUE TRUE TRUE TRUE TRUE I1092 I1024 TRUE FUNC_TEST 88 I720 TRUE BKLT_EN I722 TRUE TP_ISSP_SCLK_P1_1 53 I724 TRUE TP_ISSP_SDATA_P1_0 53 87 88 I723 TRUE LCD_BKLT_PWM 20 47 I725 TRUE LPCPLUS_GPIO I726 TRUE LPCPLUS_RESET_L 27 47 87 94 LPC_AD 17 45 47 87 94 I727 TRUE LPC_CLK33M_LPCPLUS 27 47 94 I729 TRUE LPC_FRAME_L 17 45 47 87 94 I728 TRUE TRUE J9000 (LVDS CONN) I995 J5713 (KEY BOARD CONN) 73 87 101 35 36 48 50 TRUE PP3V3_S3 17 20 31 32 33 34 53 54 55 72 TRUE PP3V42_G3H 17 21 23 43 45 46 47 5348 49 53 64 TRUE WS_KBD1 65 66 73 53 TRUE WS_KBD2 TRUE WS_KBD3 53 53 TRUE WS_KBD4 TRUE WS_KBD5 53 53 TRUE WS_KBD6 TRUE WS_KBD7 53 TRUE WS_KBD8 53 TRUE WS_KBD9 53 53 TRUE WS_KBD10 53 TRUE WS_KBD11 WS_KBD12 TRUE 53 53 TRUE WS_KBD13 53 TRUE WS_KBD14 53 TRUE WS_KBD15_CAP 53 TRUE WS_KBD16_NUM TRUE WS_KBD17 53 TRUE WS_KBD18 53 WS_KBD19 TRUE 53 TRUE WS_KBD20 53 53 TRUE WS_KBD21 53 TRUE WS_KBD22 WS_KBD23 53 TRUE TRUE WS_KBD_ONOFF_L 53 TRUE WS_LEFT_SHIFT_KBD 53 TRUE WS_LEFT_OPTION_KBD 53 TRUE WS_CONTROL_KBD 53 A "G3Hot" (Always-Present) Rails 89 86 82 66 65 49 40 70 69 67 PPBUS_G3H PPBUS_G3H MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H PPBUS_G3H D 68 49 PPBUS_CPU_IMVP_ISNS PPDCIN_G3H PPDCIN_G3H PPDCIN_G3H 73 53 49 48 43 23 21 17 47 46 45 66 65 64 PP3V42_G3H PP3V42_G3H MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM 53 VOLTAGE=3.42V MAKE_BASE=TRUE PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H C PP3V3_S5 40 49 65 66 67 69 70 82 86 89 40 49 65 66 67 69 70 82 86 89 49 68 49 68 64 65 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 17 18 19 20 21 23 27 31 57 66 71 72 73 83 85 99 17 18 19 20 21 23 27 31 57 66 71 72 73 83 85 99 99 17 18 19 20 21 23 27 31 57 66 71 72 73 83 83 85 99 17 18 19 20 21 23 27 31 35 57 66 71 72 73 50 48 36 35 34 33 32 31 20 17 101 87 73 72 55 54 PP3V3_S3 PP5V_S5 17 21 23 43 45 46 47 48 49 53 64 65 66 73 17 21 23 43 45 46 47 48 49 53 64 65 66 73 17 21 23 43 45 46 47 48 49 53 64 65 66 73 17 21 23 43 45 46 47 48 49 53 64 65 66 73 17 21 23 43 45 46 47 48 49 53 64 65 66 73 17 21 23 43 45 46 47 48 49 53 64 65 66 73 17 21 23 43 45 46 47 48 49 53 64 65 66 73 17 21 23 43 45 46 47 48 49 53 64 65 66 73 17 21 23 43 45 46 47 48 49 53 64 65 66 73 17 21 23 43 45 46 47 48 49 53 64 65 66 73 PP5V_S5 PP5V_S5 PP5V_S5 72 67 66 61 58 42 33 31 56 54 46 44 43 101 82 PP5V_S3 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 23 66 72 23 66 72 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 PP5V_S3 88 86 72 47 42 23 70 69 68 54 52 PP5V_S0 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 31 33 72 82 101 31 33 72 82 101 31 33 72 82 101 31 33 72 82 101 42 43 44 46 54 56 58 61 66 67 42 43 44 46 54 56 58 61 66 67 42 43 44 46 54 56 58 61 66 67 42 43 44 46 54 56 58 61 66 67 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 31 33 42 43 44 46 54 56 58 61 66 67 72 82 101 PP5V_S0 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 23 42 47 52 54 68 69 70 72 86 88 23 42 47 52 54 68 69 70 72 86 88 23 42 47 52 54 68 69 70 72 86 88 23 42 47 52 54 68 69 70 72 86 88 23 42 47 52 54 68 69 70 72 86 88 23 42 47 52 54 68 69 70 72 86 88 23 42 47 52 54 68 69 70 72 86 88 23 42 47 52 54 68 69 70 72 86 88 23 42 47 52 54 68 69 70 72 86 88 23 42 47 52 54 68 69 70 72 86 88 23 42 47 52 54 68 69 70 72 86 88 23 42 47 52 54 68 69 70 72 86 88 23 42 47 52 54 68 69 70 72 86 88 23 42 47 52 54 68 69 70 72 86 88 A PP1V0_FW_FWPHY 28 30 31 67 72 84 82 81 80 79 74 72 6 28 30 31 67 72 PP3V3_S0GPU 20 87 20 50 31 32 101 53 31 32 67 32 17 20 31 32 55 72 73 87 101 33 34 35 36 48 50 53 54 54 55 72 73 87 101 33 34 33 34 35 36 48 50 53 54 PPVTTDDR_S3 PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU PP3V3_S0GPU 81 72 6 13 16 31 42 72 73 99 PP1V8_GPUIFPX PP3V3_S0 PP0V75_S0_DDRVTT PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 50 51 52 54 58 62 63 68 69 72 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 50 51 52 54 58 62 63 68 69 72 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 27 28 17 18 19 20 21 23 24 25 26 30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 87 72 72 73 80 83 84 85 87 88 99 50 51 52 54 58 62 63 68 69 72 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 27 28 17 18 19 20 21 23 24 25 26 8830 34 37 40 42 46 47 48 50 6351 52 54 58 62 63 68 69 72 4273 80 83 84 85 87 88 99 28 17 18 19 20 21 23 24 25 26 27 71 17 30 34 37 40 46 47 48 50 51 52 54 58 62 69 68 69 72 73 80 83 84 85 87 996 17 18 19 20 21 23 24 47 25 3026 27 28 30 34 37 40 42 46 1748 50 51 52 54 58 62 63 68 72 73 80 83 84 85 87 88 99 18 19 20 21 23 24 25 26 27 28 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99 PP1V2_S0 21 20 18 17 15 13 12 10 86 73 70 40 26 25 24 23 PP1V8R1V55_S0GPU_ISNS PPVTTDDR_S3 PP1V8R1V55_S0GPU_ISNS 32 67 86 50 PP0V75_S0_DDRVTT 86 81 79 76 74 28 30 31 67 28 30 31 67 PP1V8R1V55_S0GPU_ISNS_R MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE PP1V05_S0GPU 72 87 72 87 PP1V05_S5 17 71 82 75 49 6 50 56 75 76 77 78 50 56 75 76 77 78 50 56 75 76 77 78 50 56 75 76 77 78 C 50 86 PP1V8R1V55_S0GPU_ISNS_R 50 86 PP1V05_S0GPU 74 76 79 81 86 PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PP1V05_S0GPU PP1V2_S0 50 56 75 76 77 78 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 28 30 31 67 PPVCORE_GPU 74 76 79 81 86 74 76 79 81 86 74 76 79 81 86 74 76 79 81 86 74 76 79 81 86 74 76 79 81 86 74 76 79 81 86 74 76 79 81 86 74 76 79 81 86 PPVCORE_GPU 49 75 82 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V MAKE_BASE=TRUE PPVCORE_GPU 17 71 49 75 82 B PP1V05_S0 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 PP1V05_S0 50 51 52 54 58 62 63 68 69 72 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 27 28 197 17 18 19 20 21 23 24 25 26 1730 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99 18 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99 50 51 52 54 58 62 63 68 69 72 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 27 28 197 17 18 19 20 21 23 24 25 26 1730 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99 18 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99 50 51 52 54 58 62 63 68 69 72 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 27 28 197 17 18 19 20 21 23 24 25 26 1730 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99 18 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 50 51 52 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99 73 37 27 50 51 52 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 54 58 62 63 68 69 72 73 80 83 84 85 87 88 99 50 51 52 54 58 62 63 68 69 72 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 58 62 63 68 69 72 73 80 83 84 28 30 34 37 40 42 46 47 48 50 17 18 19 20 21 23 24 25 26 27 72 71 37 51 52 54 85 87 88 99 26 40 70 73 86 10 12 13 15 17 18 20 21 23 24 25 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 Chipset "VCore" Rails PPVCORE_S0_CPU PPVCORE_S0_CPU 12 15 49 68 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V MAKE_BASE=TRUE 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 PPVCORE_S0_CPU PPVCORE_S0_GFX 12 15 49 68 PPVCORE_S0_GFX 69 49 24 13 6 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 13 24 49 69 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 PPVCORE_S0_GFX 10 12 13 15 17 18 20 21 16 12 23 24 25 266 40 70 73 86 1010 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 26 40 12 13 15 17 18 20 21 23 24 25 706 73 86 1010 12 13 15 16 12 7 17 18 20 21 23 24 25 26 1240 70 73 86 13 40 70 73 86 15 17 18 20 21 23 24 25 26 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 PPVCORE_S0_CPU_VCAP0 PPVCORE_S0_CPU_VCAP0 13 24 49 69 12 16 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V MAKE_BASE=TRUE PPVCORE_S0_CPU_VCAP1 PPVCORE_S0_CPU_VCAP1 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V MAKE_BASE=TRUE PPVCORE_S0_CPU_VCAP2 PPVCORE_S0_CPU_VCAP2 24 13 7 10 12 13 15 17 18 20 21 23 24 25 26 40 70 73 86 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=1.25V MAKE_BASE=TRUE 12 16 13 24 ENET Rails PP3V3_ENET PP3V3_ENET 27 37 73 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE SYNC_MASTER=MASTER SYNC_DATE=MASTER PAGE TITLE PP3V3_ENET 27 37 73 PP1V2_ENET 37 71 72 Power Aliases DRAWING NUMBER PP1V2_ENET PP1V8R1V55_S0GPU_ISNS_R 28 30 31 67 PP1V05_S5 50 51 52 54 58 62 63 68 69 72 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 27 28 17 18 19 20 21 23 24 25 26 30 34 37 40 42 46 47 48 50 8051 52 54 58 62 63 68 69 72 5073 80 83 84 85 87 88 99 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 51 52 54 58 62 63 68 69 72 73 83 84 85 87 88 99 72 81 PP1V8R1V55_S0GPU_ISNS PP1V8R1V55_S0GPU_ISNS PP1V8R1V55_S0GPU_ISNS PP1V8R1V55_S0GPU_ISNS MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE 50 51 52 54 58 62 63 68 69 72 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 72 81 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE 13 16 31 42 72 73 99 PP1V2_S0 PP1V05_S0 ? mA 72 74 79 80 81 82 84 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.15 MM VOLTAGE=1.8V MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.09 MM VOLTAGE=1.2V MAKE_BASE=TRUE PP1V05_S5 72 74 79 80 81 82 84 PP1V8_GPUIFPX 13 16 31 42 72 73 99 78 77 76 75 56 50 6 13 16 31 42 72 73 99 PP0V75_S0_DDRVTT PP0V75_S0_DDRVTT PP0V75_S0_DDRVTT 73 80 83 84 85 87 88 99 50 51 52 54 58 62 63 68 69 72 27 28 30 34 37 40 42 46 47 48 17 18 19 20 21 23 24 25 26 72 74 79 80 81 82 84 72 74 79 80 81 82 84 PP1V8_GPUIFPX MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0.75V MAKE_BASE=TRUE 50 51 52 54 58 62 63 68 69 72 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 73 80 83 84 85 87 88 99 72 74 79 80 81 82 84 13 16 31 42 72 73 99 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0.75V MAKE_BASE=TRUE 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 72 74 79 80 81 82 84 MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.10MM VOLTAGE=3.3V MAKE_BASE=TRUE 28 30 31 67 72 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.2V MAKE_BASE=TRUE Apple Inc 37 71 72 37 71 72 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION R NOTICE OF PROPRIETARY PROPERTY: PP1V2_ENET PP1V2_ENET PP3V3_S0GPU 28 30 31 67 72 PP1V5_S3RS0 39 40 "GPU" Rails 28 30 31 67 72 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 17 73 17 48 39 40 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V MAKE_BASE=TRUE 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 55 72 35 36 D 39 40 41 PP1V0_FW_FWPHY PP1V0_FW_FWPHY 28 30 31 67 72 PP1V5_S3RS0 PP1V5_S3RS0 PP1V5_S3RS0 PP1V5_S3RS0 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 39 40 41 12 16 21 23 24 58 71 72 87 MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.5V MAKE_BASE=TRUE 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 39 40 41 PP3V3_FW_FWPHY PP3V3_FW_FWPHY 12 16 21 23 24 58 71 72 87 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE 23 66 72 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE B PP3V3_S0 12 16 21 23 24 58 71 72 87 PP1V5_S3 PP1V5_S3 PP1V5_S3 PP1V5_S3 PP1V5_S3 PP1V5_S3RS0 40 41 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE 12 16 21 23 24 58 71 72 87 PP1V5_S3 99 73 72 42 31 16 13 6 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 40 41 PP3V3_FW_FWPHY PP3V3_FW_FWPHY MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=1.5V MAKE_BASE=TRUE 23 66 72 69 68 63 62 58 54 52 51 50 48 25 24 23 21 20 19 18 17 47 46 42 40 37 34 30 28 27 26 99 88 87 85 84 83 80 73 72 12 16 21 23 24 58 71 72 87 41 40 39 6 12 16 21 23 24 58 71 72 87 17 20 31 32 33 34 35 36 48 50 53 54 55 72 73 87 101 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 PP3V3_S3 17 21 23 43 45 46 47 48 49 53 64 65 66 73 17 21 23 43 45 46 47 48 49 53 64 65 66 73 17 21 23 43 45 46 47 48 49 53 64 65 66 73 PPVP_FW PPVP_FW 12 16 21 23 24 58 71 72 87 40 39 6 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 40 41 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=12.8V MAKE_BASE=TRUE 35 85 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V MAKE_BASE=TRUE 17 21 23 43 45 46 47 48 49 53 64 65 66 73 PPVP_FW PPVP_FW 12 16 21 23 24 58 71 72 87 35 PP1V5_S3 67 31 30 28 PP5V_S5 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V MAKE_BASE=TRUE 35 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 PP3V3_S3 PP1V8_S0 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V MAKE_BASE=TRUE PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0 PP1V8_S0 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 64 65 17 21 23 43 45 46 47 48 49 53 64 65 66 73 "FW" (FireWire) Rails 41 40 PP1V8_S0 2A max supply 87 72 71 58 24 23 21 73 83 85 99 16 12 6 17 18 19 20 21 23 27 31 35 57 66 71 72 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 40 49 65 66 67 69 70 82 86 89 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 99 5V Rails 72 66 23 1.8V/1.5V/1.2V/1.05V Rails MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V MAKE_BASE=TRUE 40 49 65 66 67 69 70 82 86 89 PPBUS_CPU_IMVP_ISNS MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.25 MM VOLTAGE=18.5V MAKE_BASE=TRUE PP3V3_S5 40 49 65 66 67 69 70 82 86 89 40 49 65 66 67 69 70 82 86 89 PPBUS_CPU_IMVP_ISNS 65 64 99 85 83 20 19 18 17 73 72 71 66 57 35 31 27 23 21 40 49 65 66 67 69 70 82 86 89 40 49 65 66 67 69 70 82 86 89 40 49 65 66 67 69 70 82 86 89 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.8V MAKE_BASE=TRUE 3.3V Rails BRANCH PAGE OF 132 SHEET OF 101 A ZT0984 Thermal Module Holes ZT0981 STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH Fan Holes ZT0930 CPU signals 91 15 12 ZT0985 ZT0988 STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH 91 13 1 CPU_VID CPUIMVP_VID 68 GFXIMVP_VID 69 91 12 MAKE_BASE=TRUE GFX_VID TP_CPU_VTT_SELECT TP_CPU_VTT_SELECT 12 91 MAKE_BASE=TRUE MAKE_BASE=TRUE MEMVTT_EN 67 31 MEMVTT_EN 31 67 MAKE_BASE=TRUE ZT0980 STDOFF-4.5OD.98H-1.1-3.48-TH ZT0986 ZT0989 STDOFF-4.5OD.98H-1.1-3.48-TH STDOFF-4.5OD.98H-1.1-3.48-TH GPU signals 1 D 91 74 PEG_D2R_P 91 74 PEG_D2R_N ZT0991 STDOFF-4.5OD.98H-1.1-3.48-TH D =PEG_D2R_N MAKE_BASE=TRUE PEG_R2D_C_P 91 74 PEG_R2D_C_N Frame Holes ZT0915 =PEG_D2R_P MAKE_BASE=TRUE 91 74 =PEG_R2D_C_P MAKE_BASE=TRUE =PEG_R2D_C_N MAKE_BASE=TRUE ** PEG LANES REVERSED ARD STRAP REQ’D ** 3R2P5 GND GMUX ALIASES ZT0940 Left Speaker Holes 3R2P5 PM_ALL_GPU_PGOOD 87 86 82 73 ZT0934 STDOFF-4.0OD3.0H-TH ZT0950 TH 87 8 73 82 86 87 91 25 CPU_CFG TP_LVDS_MUX_SEL_EG ZT0935 ZT0960 STDOFF-4.0OD3.0H-TH 3R2P5 87 74 TP_LVDS_MUX_SEL_EG EG_RESET_L MAKE_BASE=TRUE LVDS_IG_BKL_ON 87 18 LVDS_IG_BKL_ON 3.0K 87 74 87 TP_LVDS_IG_B_CLKN 18 LCD_BKLT_EN LVDS_IG_PANEL_PWR LCD_BKLT_EN TP_LVDS_IG_B_CLKP 18 93 TP_LVDS_IG_B_CLKN 18 93 MAKE_BASE=TRUE TP_LVDS_IG_BKL_PWM TP_LVDS_IG_BKL_PWM 93 84 3R2P5 DP_IG_ML_P NC_GPU_XTALOUT NC_GPU_XTALOUT 93 18 NC_LVDS_IG_A_DATAP 93 18 NC_LVDS_IG_A_DATAN DP_IG_B_ML_P 18 DP_IG_B_ML_N 18 93 18 8 18 84 93 93 18 8 18 MAKE_BASE=TRUE 79 MAKE_BASE=TRUE NO_TEST=TRUE 18 87 87 89 MAKE_BASE=TRUE ZT0990 93 18 8 18 87 MAKE_BASE=TRUE 89 87 TP_LVDS_IG_B_CLKP 79 LVDS_IG_PANEL_PWR 87 18 93 18 MAKE_BASE=TRUE MAKE_BASE=TRUE GND EG_RESET_L 5% 1/16W MF-LF 402 MAKE_BASE=TRUE 1 GND SL-3.1X2.7-6CIR-NSP R0902 PM_ALL_GPU_PGOOD MAKE_BASE=TRUE GND NC_LVDS_IG_A_DATAP 18 93 NC_LVDS_IG_A_DATAN 18 93 NC_LVDS_IG_B_DATAP 18 93 NC_LVDS_IG_B_DATAN 18 93 MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE NO_TEST=TRUE MAKE_BASE=TRUE GND 93 84 87 74 PEX_CLKREQ_L PEX_CLKREQ_L MAKE_BASE=TRUE 87 17 PEG_CLKREQ_L PEG_CLKREQ_L 73 71 C PM_ENET_EN 93 84 18 DP_IG_AUX_CH_N NC_LVDS_IG_B_DATAP MAKE_BASE=TRUE DP_IG_AUX_CH_P DP_IG_AUX_CH_N 18 84 93 DP_IG_DDC_CLK 18 80 84 MAKE_BASE=TRUE PM_ENET_EN MAKE_BASE=TRUE 71 73 84 80 18 84 80 18 84 18 DP_IG_DDC_CLK MAKE_BASE=TRUE DP_IG_DDC_DATA SH0902 SM ZT0953 SH0900 2.0DIA-TALL-EMI-MLB-M97-M98 40 20 FW_PLUG_DET_L 40 39 FW643_WAKE_L 18 80 84 DP_IG_HPD 18 84 MAKE_BASE=TRUE DP_IG_HPD SH0903 2.0DIA-TALL-EMI-MLB-M97-M98 SM SH0916 2.0DIA-TALL-EMI-MLB-M97-M98 SM NC_USB_HUB2_OCS3 17 NC_SATA_EXTA_D2R_N 17 NC_SATA_EXTA_D2R_P 17 NC_SATA_EXTA_R2D_C_N 17 NC_SATA_EXTA_R2D_C_P 17 NC_PCIE_EXCARD_D2R_N 17 NC_PCIE_EXCARD_D2R_P 17 NC_PCIE_EXCARD_R2D_C_N 17 NC_PCIE_EXCARD_R2D_C_P 94 17 94 17 Short (IO Row) EMI pogo pins SH0911 1.4DIA-SHORT-EMI-MLB-M97-M98 SH0910 SM 1.4DIA-SHORT-EMI-MLB-M97-M98 SM MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE MAKE_BASE=TRUE 17 USB_SDCARD_P NC_SATA_EXTA_D2R_P 17 NC_SATA_EXTA_R2D_C_N 17 NC_SATA_EXTA_R2D_C_P 17 NC_PCIE_EXCARD_D2R_N 17 NC_PCIE_EXCARD_D2R_P 17 MAKE_BASE=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE NO_TEST=TRUE USB_SDCARD_N 93 36 34 R09031 34 36 93 NC_PCIE_EXCARD_R2D_C_N 17 NC_PCIE_EXCARD_R2D_C_P 17 TP_ISSP_SCLK_P1_1 TP_ISSP_SDATA_P1_0 R0904 10K 5% 1/16W MF-LF 402 USB_EXTC_N USB_EXTC_P 35 93 35 93 R0900 17 94 78 77 76 75 56 50 PP1V8R1V55_S0GPU_ISNS1 10 TP_ISSP_SCLK_P1_1 53 TP_ISSP_SDATA_P1_0 53 GPU_FB_A_VREF_DIV MAKE_BASE=TRUE 1% 1/16W MF-LF 402 17 94 NO_TEST=TRUE 53 5% 1/16W MF-LF 402 GPU_FB_A_VREF_DIV 32 77 32 77 R0901 MAKE_BASE=TRUE 10 1% 1/16W MF-LF 402 MAKE_BASE=TRUE GND GND GND GND USB_SDCARD_N C PP3V3_S3 NO_TEST=TRUE 53 8 34 36 93 MAKE_BASE=TRUE 10K NC_PCIE_CLK100M_EXCARD_P NC_PCIE_CLK100M_EXCARD_P SM SM NC_SATA_EXTA_D2R_N NC_PCIE_CLK100M_EXCARD_N NC_PCIE_CLK100M_EXCARD_N SH0913 1.4DIA-SHORT-EMI-MLB-M97-M98 45 MAKE_BASE=TRUE 1.4DIA-SHORT-EMI-MLB-M97-M98 SH0912 TP_SMC_EXCARD_PWR_EN 36 USB_SDCARD_P MAKE_BASE=TRUE 93 36 34 54 53 50 48 36 35 34 33 32 31 20 17 101 87 73 72 55 TP_SMC_EXCARD_PWR_EN 2.0DIA-TALL-EMI-MLB-M97-M98 SM 39 40 35 NC_USB_HUB2_OCS3 MAKE_BASE=TRUE 45 SH0904 20 40 FW643_WAKE_L MAKE_BASE=TRUE SM FW_PLUG_DET_L NC_USB_HUB1_OCS4 MAKE_BASE=TRUE 36 MAKE_BASE=TRUE 4.0OD1.85H-M1.6X0.35 NO_TEST=TRUE NC_USB_HUB1_OCS4 35 DP_IG_DDC_DATA MAKE_BASE=TRUE 2.0DIA-TALL-EMI-MLB-M97-M98 NO_TEST=TRUE NC_LVDS_IG_B_DATAN MAKE_BASE=TRUE 4.0OD1.85H-M1.6X0.35 Tall EMI pogo pins DP_IG_AUX_CH_P MAKE_BASE=TRUE 17 87 Keyboard / IPD Conn Protect ZT0952 DP_IG_ML_N MAKE_BASE=TRUE 74 87 93 84 18 MAKE_BASE=TRUE B 1 ZT0987 STDOFF-4.5OD.98H-1.1-3.48-TH GPU_FB_B_VREF_DIV MAKE_BASE=TRUE B 32 78 GPU_FB_B_VREF_DIV 32 78 GND SH0917 1.4DIA-SHORT-EMI-MLB-M97-M98 SH0901 SM 1.4DIA-SHORT-EMI-MLB-M97-M98 SM 1 Digital Ground SH0914 GND 1.4DIA-SHORT-EMI-MLB-M97-M98 MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.095 mm VOLTAGE=0V SM GND_CHASSIS_AUDIO_JACK 62 A SYNC_MASTER=K17_REF SYNC_DATE=06/11/2009 PAGE TITLE Signal Aliases DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE OF 132 SHEET OF 101 A OMIT OMIT U1000 U1000 IN 91 18 IN 91 18 IN 91 18 D 91 18 91 18 IN IN 91 18 IN 91 18 IN OUT 91 18 OUT 91 18 OUT 91 18 OUT OUT 91 18 OUT 91 18 OUT 91 18 OUT 91 18 OUT 91 18 OUT 91 18 OUT 91 18 OUT 91 18 OUT 91 18 91 18 OUT OUT 91 18 OUT 91 18 OUT 91 18 OUT 91 18 OUT 91 18 OUT 91 18 OUT 91 18 OUT 91 18 OUT DMI_RX0* DMI_RX1* DMI_RX2* DMI_RX3* DMI_S2N_P DMI_S2N_P DMI_S2N_P DMI_S2N_P F9 J6 K9 J2 DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3 DMI_N2S_N DMI_N2S_N DMI_N2S_N DMI_N2S_N DMI_N2S_P DMI_N2S_P DMI_N2S_P DMI_N2S_P H17 K15 J13 F10 G17 M15 G13 J11 FDI_DATA_N FDI_DATA_N FDI_DATA_N FDI_DATA_N FDI_DATA_N FDI_DATA_N FDI_DATA_N FDI_DATA_N L2 N7 M4 P1 N10 R7 U7 W8 FDI_DATA_P FDI_DATA_P FDI_DATA_P FDI_DATA_P FDI_DATA_P FDI_DATA_P FDI_DATA_P FDI_DATA_P K1 N5 N2 R2 N9 R8 U6 W10 DMI_TX0* DMI_TX1* DMI_TX2* DMI_TX3* DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3 FDI_TX0* FDI_TX1* FDI_TX2* FDI_TX3* FDI_TX4* FDI_TX5* FDI_TX6* FDI_TX7* FDI_TX0 FDI_TX1 FDI_TX2 FDI_TX3 FDI_TX4 FDI_TX5 FDI_TX6 FDI_TX7 91 18 IN 91 18 IN FDI_FSYNC FDI_FSYNC AC7 AC9 91 18 IN FDI_INT AB5 FDI_INT 91 18 IN FDI_LSYNC FDI_LSYNC AA1 AB2 FDI_LSYNC0 FDI_LSYNC1 91 18 IN B FDI_FSYNC0 FDI_FSYNC1 FLEXIBLE DISPLAY INTERFACE 91 18 OUT F7 J8 K8 J4 BGA (SYM OF 11) DMI 91 18 91 18 C IN DMI_S2N_N DMI_S2N_N DMI_S2N_N DMI_S2N_N BGA (SYM OF 11) PCI EXPRESS GRAPHICS 91 18 ARRANDALE ARRANDALE PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS B12 A13 D12 B11 PEG_RX0* PEG_RX1* PEG_RX2* PEG_RX3* PEG_RX4* PEG_RX5* PEG_RX6* PEG_RX7* PEG_RX8* PEG_RX9* PEG_RX10* PEG_RX11* PEG_RX12* PEG_RX13* PEG_RX14* PEG_RX15* G40 G38 H34 P34 G28 H25 H24 D29 B26 D26 B23 D22 A20 D19 A17 B14 PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15 F40 J38 G34 M34 J28 G25 K24 B28 A27 B25 A24 B21 B19 B18 B16 D15 91 CPU_PEG_COMP 91 CPU_PEG_RBIAS =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N =PEG_D2R_N PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_D2R_P PEG_TX0* PEG_TX1* PEG_TX2* PEG_TX3* PEG_TX4* PEG_TX5* PEG_TX6* PEG_TX7* PEG_TX8* PEG_TX9* PEG_TX10* PEG_TX11* PEG_TX12* PEG_TX13* PEG_TX14* PEG_TX15* N40 L38 M32 D40 A38 G32 B33 B35 L30 A31 B32 L28 N26 M24 G21 J20 =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N =PEG_R2D_C_N PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15 L40 N38 N32 B39 B37 H32 A34 D36 J30 B30 D33 N28 M25 N24 F21 L20 PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P PEG_R2D_C_P R10121 R1010 IN IN IN IN IN IN IN 91 25 IN IN 91 25 IN IN 91 25 IN IN 91 25 IN IN IN IN IN IN IN IN 750 1% 1/16W MF-LF 402 49.9 1% 1/16W MF-LF 402 Embedded DisplayPort (eDP) pins (Auburndale only): 91 25 IN 91 25 IN 91 25 IN 91 25 IN 91 25 IN 91 25 IN 91 25 IN 91 25 IN 91 25 IN 91 25 IN 91 25 IN 91 25 IN 91 25 IN 91 25 IN eDP_AUX# 74 91 IN 74 91 IN 74 91 IN 74 91 IN 74 91 IN 74 91 IN 74 91 IN 74 91 IN 74 91 IN 74 91 IN 74 91 IN 74 91 IN 74 91 IN 74 91 IN 74 91 IN 74 91 NOTE: HPD must be inverted and level-shifted for Auburndale (1.05V) 6 eDP_HPD# eDP_AUX 6 6 OUT OUT OUT OUT OUT 6 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT 74 91 OUT 74 91 OUT 74 91 OUT 74 91 OUT 74 91 OUT 74 91 OUT 74 91 OUT 74 91 OUT 74 91 OUT 74 91 OUT 74 91 OUT 74 91 OUT 74 91 OUT 74 91 OUT 74 91 OUT 74 91 6 6 CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG CPU_CFG AL4 AM2 AK1 AK2 AK4 AJ2 AT2 AG7 AF4 AG2 AH1 AC2 AC4 AE2 AD1 AF8 AF6 AB7 TP_CPU_RSVD_TP0 AU1 TP_CPU_RSVD TP_CPU_RSVD T4 T2 RSVD15 RSVD16 TP_CPU_RSVD TP_CPU_RSVD U1 V2 RSVD17 RSVD18 TP_CPU_RSVD TP_CPU_RSVD AV71 AW70 RSVD19 RSVD20 TP_CPU_RSVD TP_CPU_RSVD AY69 BB69 RSVD21 RSVD22 TP_CPU_RSVD TP_CPU_RSVD D8 B7 RSVD23 RSVD24 TP_CPU_RSVD TP_CPU_RSVD A10 B9 RSVD26 RSVD27 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) RSVD_TP0 NC_TP_CPU_RSVD_NCTF NC_TP_CPU_RSVD_NCTF C5 A6 RSVD_NCTF7 RSVD_NCTF8 NC_TP_CPU_RSVD_NCTF NC_TP_CPU_RSVD_NCTF E3 F1 RSVD_NCTF6 RSVD_NCTF5 eDP_TX# eDP_TX# eDP_TX# eDP_TX# CFG0: PCIe Configuration Select CFG3: PCIe Lane Reversal CFG4: Display Port Presence RESERVED RSVD32 W66 RSVD33 W64 NC_TP_CPU_RSVD NC_TP_CPU_RSVD RSVD34 AC69 RSVD35 AC71 NC_TP_CPU_RSVD NC_TP_CPU_RSVD RSVD36 AA71 RSVD37 AA69 NC_TP_CPU_RSVD NC_TP_CPU_RSVD RSVD38 R66 RSVD39 R64 NC_TP_CPU_RSVD NC_TP_CPU_RSVD RSVD_NCTF3 BT5 RSVD_NCTF4 BR5 NC_TP_CPU_RSVD NC_TP_CPU_RSVD RSVD_NCTF2 BV6 RSVD_NCTF1 BV8 NC_TP_CPU_RSVD NC_TP_CPU_RSVD RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD54 RSVD55 RSVD56 RSVD57 RSVD58 AV69 AK71 AN69 AP66 AH66 AK66 AR71 AM66 AK69 AU71 AT70 AR69 AU69 AT67 TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD TP_CPU_RSVD RSVD_TP2 AP2 RSVD_TP1 AN7 TP_CPU_RSVD TP_CPU_RSVD RSVD62 AV4 RSVD63 AU2 CPU_THERMD_P CPU_THERMD_N RSVD64 BE69 RSVD65 BE71 TP_CPU_RSVD TP_CPU_RSVD DC_TEST_BV71 DC_TEST_BV69 DC_TEST_BV68 DC_TEST_BV5 DC_TEST_BV3 DC_TEST_BV1 DC_TEST_BT71 DC_TEST_BT69 DC_TEST_BT3 DC_TEST_BT1 DC_TEST_BR71 DC_TEST_BR1 DC_TEST_E71 DC_TEST_E1 DC_TEST_C71 DC_TEST_C69 DC_TEST_C3 DC_TEST_A71 DC_TEST_A69 DC_TEST_A68 DC_TEST_A5 BV71 BV69 BV68 BV5 BV3 BV1 BT71 BT69 BT3 BT1 BR71 BR1 E71 E1 C71 C69 C3 A71 A69 A68 A5 6 D 6 6 6 6 6 6 6 6 6 6 6 6 C BI 51 99 BI 51 99 6 CPU_TEST_BV71_BV69 TP_CPU_TEST_BV68 TP_CPU_TEST_BV5 CPU_TEST_BV3_BT3 CPU_TEST_BV1_BT1 CPU_TEST_BT71_BT69 TP_CPU_TEST_BR71 TP_CPU_TEST_BR1 TP_CPU_TEST_E71 TP_CPU_TEST_E1 CPU_TEST_C71_A71 CPU_TEST_C69_A69 TP_CPU_TEST_C3 TP_CPU_TEST_A68 TP_CPU_TEST_A5 = Single PEG = Normal Operation = eDP Disabled B = Bifurcation Enabled = Lanes Reversed = Embedded Display Port Enabled WF: RSVD nets with arrows have offpage marks on CRB schematic WF: RSVD nets with red wires have 0-ohm resistors to GND in CRB schematic eDP_TX eDP_TX eDP_TX eDP_TX A SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 PAGE TITLE CPU DMI/PEG/FDI/RSVD DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE 10 OF 132 SHEET OF 101 A NO STUFF R11011 R1100 D 49.9 68 1% 1/16W MF-LF 402 5% 1/16W MF-LF 402 91 91 91 R11101 R11121 20 91 R1113 20 49.9 1% 1/16W MF-LF 402 5% 1/16W MF-LF 402 ARRANDALE BGA AD71 AC70 AD69 AE66 CPU_COMP3 CPU_COMP2 CPU_COMP1 CPU_COMP0 1% 1/16W MF-LF 402 91 20 91 68 46 91 46 20 91 25 91 18 BI M71 (SYM OF 11) COMP3 COMP2 COMP1 COMP0 PROC_DETECT CPU_CATERR_L N61 CATERR* CPU_PECI N19 PECI BI CPU_PROCHOT_L N67 PROCHOT* OUT PM_THRMTRIP_L N17 THERMTRIP* OUT BI FSB_CPURST_L N70 PM_SYNC M17 PM_SYNC PP1V05_S0 (IPD) 1K 91 31 18 91 25 20 IN Y67 CPU_PWRGD VCCPWRGOOD_0 (IPD) AM5 PM_MEM_PWRGD IN SM_DRAMPWROK (IPD) 91 70 IN H15 CPUVTTS0_PGOOD VTTPWRGOOD (IPD) 91 25 OUT Y70 XDP_CPUPWRGD TAPPWRGOOD R1125 27 IN PLT_RST_BUF_L 1.5K 1% 1/16W MF-LF 402 G3 PLT_RESET_LS1V1_L R11261 RSTIN* PWR MANAGEMENT R1120 VCCPWRGOOD_1 JTAG & MBP AM7 R1151 10K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 BCLK AK7 BCLK* AK8 FSB_CLK133M_CPU_P FSB_CLK133M_CPU_N IN 20 91 IN 20 91 BCLK_ITP K71 BCLK_ITP* J70 FSB_CLK133M_ITP_P FSB_CLK133M_ITP_N OUT 25 91 PEG_CLK L21 PEG_CLK* J21 DPLL_REF_SSCLK Y2 DPLL_REF_SSCLK* W4 OUT 25 91 PCIE_CLK100M_CPU_P PCIE_CLK100M_CPU_N IN 17 91 IN 17 91 GFX_CLK120M_DPLLSS_P GFX_CLK120M_DPLLSS_N IN 17 93 IN 17 93 CPU_MEM_RESET_L SM_RCOMP0 BV33 SM_RCOMP1 BP39 SM_RCOMP2 BV40 91 91 91 PM_EXT_TS0* AV66 PM_EXT_TS1* AV64 RESET_OBS* D 10K SM_DRAMRST* BJ12 21 20 18 17 15 13 12 10 86 73 70 40 26 25 24 23 5% 1/16W MF-LF 402 R11501 U1000 1K THERMAL R1111 R1103 (GND) 1% 1/16W MF-LF 402 5% 1/16W MF-LF 402 TP_CPU_SKTOCC_L 49.9 1% 1/16W MF-LF 402 68 OMIT MISC 91 R11021 CLOCKS C PP1V05_S0 DDR3 MISC 21 20 18 17 15 13 12 10 86 73 70 40 26 25 24 23 PM_EXT_TS_L PM_EXT_TS_L (IPU) PRDY* U71 PREQ* U69 XDP_PRDY_L XDP_PREQ_L (IPU) (IPU) (IPU) TCK T67 TMS N65 TRST* P69 XDP_TCK XDP_TMS XDP_TRST_L (IPU) TDI T69 TDO T71 JTAG_CPU_TDI JTAG_GMCH_TDO (IPU) TDI_M P71 TDO_M T70 W71 DBR* JTAG_GMCH_TDI JTAG_CPU_TDO XDP_DBRESET_L (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) (IPU) BPM0* BPM1* BPM2* BPM3* BPM4* BPM5* BPM6* BPM7* J69 J67 J62 K65 K62 J64 K69 M69 750 OUT 31 CPU_SM_RCOMP0 CPU_SM_RCOMP1 CPU_SM_RCOMP2 XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L XDP_BPM_L IN 46 91 IN 46 91 OUT 25 91 IN 25 91 IN 25 91 IN 25 91 IN 25 91 IN 25 OUT 25 IN 25 OUT 25 OUT 25 27 91 OUT 25 91 OUT 25 91 OUT 25 91 OUT 25 91 OUT 25 91 OUT 25 91 OUT 25 91 OUT 25 91 R11601 R11621 130 100 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 R1161 C 24.9 1% 1/16W MF-LF 402 R1170 1% 1/16W MF-LF 402 51 5% 1/16W MF-LF 402 B B A SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 PAGE TITLE CPU Clock/Misc/JTAG DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE 11 OF 132 SHEET 10 OF 101 A 87 85 84 68 63 62 48 47 46 28 27 26 19 18 17 24 23 21 40 37 34 54 52 51 80 73 72 99 83 58 42 25 20 30 50 69 88 PP3V3_S0 C9610 0.1UF C9621 C9622 0.1UF 20% 10V CERM 402 20% 10V CERM 402 C9623 0.1UF C9624 0.1UF 20% 10V CERM 402 20% 10V CERM 402 C9625 0.1UF 20% 10V CERM 402 C9626 0.1UF 20% 10V CERM 402 C9627 0.1UF 20% 10V CERM 402 C9628 0.1UF 20% 10V CERM 402 PP1V8_S0 C9629 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.09 mm VOLTAGE=3.3V 0.1UF 20% 10V CERM 402 5% 1/16W MF-LF 402 C9611 0.1UF C9612 0.1UF 0.1UF 20% 10V CERM 402 20% 10V CERM 402 C9613 C9614 0.1UF 20% 10V CERM 402 20% 10V CERM 402 C9615 0.1UF C9616 0.1UF 20% 10V CERM 402 20% 10V CERM 402 93 87 18 93 87 18 R9612 93 87 18 5% 1/16W MF-LF 402 L9621 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.09 mm VOLTAGE=3.3V C9617 1 93 87 18 93 87 18 0.1UF 20% 10V CERM 402 98 87 81 98 87 81 98 87 81 FERR-220-OHM PP3V3R1V8_S0_GMUX_LRC_VCCPLL PP1V2_S0 MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.09 mm VOLTAGE=3.3V C9600 4.7UF 20% 4V X5R 402 C9604 0.1UF C9605 0.1UF 20% 10V CERM 402 C9606 0.1UF 20% 10V CERM 402 20% 10V CERM 402 C9607 0.1UF 20% 10V CERM 402 C9608 0.1UF 20% 10V CERM 402 1 LVDS_EG_B_DATA_P LVDS_EG_B_DATA_P LVDS_EG_B_DATA_P 98 87 81 98 87 81 0402 LVDS_EG_A_CLK_P LVDS_EG_A_DATA_P LVDS_EG_A_DATA_P LVDS_EG_A_DATA_P 98 87 81 L9620 72 98 87 81 C9609 20% 10V CERM 402 0.1UF 20% 10V CERM 402 GMUX_CFG0 10K 88 87 OUT 87 84 OUT 87 84 OUT 84 OUT 1% 1/16W MF-LF 402 OUT OUT OUT 87 73 72 OUT 87 82 73 OUT 87 86 73 72 OUT 17 OUT 80 OUT 87 83 OUT CRITICAL J9600 BI 94 47 45 17 BI 94 47 45 17 BI 94 47 45 17 BI 17 50 51 52 54 58 62 63 68 69 72 47 45 94 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 94 47 27 73 80 83 84 85 87 88 99 BI 1909782 M-RT-SM GMUX_JTAG_CONN PP3V3_S0 JTAG_GMUX_TDO JTAG_GMUX_TDI JTAG_GMUX_TMS IN 27 IN 20 OUT 19 87 19 87 B JTAG_GMUX_TCK 93 87 18 IN 93 87 18 IN 20 25 87 R96471 10K 1% 1/16W MF-LF 402 IN IN IN 93 87 18 IN 93 87 18 IN 93 87 18 IN 93 87 18 IN 93 87 18 IN 93 87 18 IN 93 87 18 IN 93 87 18 93 87 18 IN IN OUT 88 87 IN 88 87 86 82 73 IN 74 IN (Tie/strap low if EGPU doesn’t provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU) K12 PT9B PB27B PB28A PB28B PP3V3_S0 PT14A PT14B PT15A PT15B PT16A PT16B PT17A PT17B PT18A PT18B PT19A PT19B PT20A PT20B PT28A PT28B PL2A PL2B PR2A PR2B PL6A PR6A PL6B PR6B PL7A PL7B PR7A PR7B PL8A PR8A PL8B PL9A PR8B PR9A PR9B PL9B PL10A PL10B PL11A PL11B PL12A PL12B PL14A PL14B PL15A PL15B PL25A PL25B PR10A PR10B PR11A PR11B PR12A PR12B PR14A PR14B PR24A PR24B A2 A3 A1 B3 C5 A5 B6 C7 A6 A7 C8 C9 A8 B9 A9 C10 B10 A10 A11 B12 B13 A13 LVDS_B_DATA_P LVDS_B_DATA_N LVDS_B_DATA_P LVDS_B_DATA_N LVDS_B_DATA_P LVDS_B_DATA_N EG_PWRSEQ_EN GMUX_DEBUG_RESET_L LVDS_A_CLK_P LVDS_A_CLK_N LVDS_B_CLK_P LVDS_B_CLK_N LVDS_A_DATA_P LVDS_A_DATA_N LVDS_A_DATA_P LVDS_A_DATA_N LVDS_A_DATA_P LVDS_A_DATA_N GND GND GND GND A14 B14 D12 D13 D14 E14 E12 F12 F14 G14 G12 G13 H13 H12 H14 J12 L14 M13 N14 N13 DP_CA_DET DP_HOTPLUG_DET LVDS_EG_A_DATA_P LVDS_EG_A_DATA_N LVDS_EG_A_DATA_P LVDS_EG_A_DATA_N LVDS_EG_A_DATA_P LVDS_EG_A_DATA_N LVDS_EG_B_DATA_P LVDS_EG_B_DATA_N LVDS_EG_B_DATA_P LVDS_EG_B_DATA_N LVDS_EG_B_DATA_P LVDS_EG_B_DATA_N LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N LVDS_IG_PANEL_PWR EG_LCD_PWR_EN LVDS_IG_BKL_ON EG_BKLT_EN 101 73 17 72 55 54 53 50 48 36 35 34 33 32 31 20 OUT 84 98 OUT 84 98 OUT 84 98 OUT 84 98 OUT 84 98 2 100 100 100 R9660 R9661 R9662 R9663 R9664 R9665 R9666 2 402 1/16W MF-LF 402 1/16W MF-LF 402 1/16W MF-LF 402 1/16W MF-LF 402 PLACE_NEAR=U9600.B2:5mm 1/16W MF-LF 402 LVDS_IG_A_CLK_N LVDS_IG_A_DATA_N LVDS_IG_A_DATA_N LVDS_IG_A_DATA_N LVDS_IG_B_DATA_N LVDS_IG_B_DATA_N LVDS_IG_B_DATA_N PLACE_NEAR=U9600.J12:5mm LVDS_EG_A_CLK_N 1% 1/16W MF-LF 402 PLACE_NEAR=U9600.D13:5mm LVDS_EG_A_DATA_N 1% 1/16W MF-LF 402 PLACE_NEAR=U9600.E14:5mm LVDS_EG_A_DATA_N 1% 1/16W MF-LF 402 PLACE_NEAR=U9600.F12:5mm LVDS_EG_A_DATA_N 1/16W MF-LF 402 LVDS_EG_B_DATA_N PLACE_NEAR=U9600.G13:5mm LVDS_EG_B_DATA_N 1% 1/16W MF-LF 402 PLACE_NEAR=U9600.H12:5mm LVDS_EG_B_DATA_N 402 PLACE_NEAR=U9600.G3:5mm 1% 1% MF-LF PLACE_NEAR=U9600.G2:5mm 1% 1% EG_PWRSEQ_EN R9684 1K OUT 87 84 87 84 87 84 84 98 IN 87 IN 87 PLACE_NEAR=U9600.G14:5mm 1% 1/16W MF-LF 402 1% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 18 87 93 18 87 93 18 87 93 18 87 93 18 87 93 D 18 87 93 81 87 98 81 87 98 81 87 98 81 87 98 81 87 98 81 87 98 81 87 98 PP3V3_S0 10K 1% 1/16W MF-LF 402 OUT 84 98 OUT 84 98 OUT 84 98 OUT 84 98 OUT 84 98 OUT 84 98 OUT 84 98 OUT 84 98 OUT 84 98 OUT 84 98 IN 80 84 85 IN 84 85 IN 81 87 98 IN 81 87 98 IN 81 87 98 IN 81 87 98 IN 81 87 98 IN 81 87 98 IN 81 87 98 IN 81 87 98 IN 81 87 98 IN 81 87 98 IN 81 87 98 IN 81 87 98 IN 81 87 98 IN 81 87 98 IN 18 IN 79 80 IN 18 IN 79 80 R9676 10K C LVDS_DDC_SEL_IG R9682 10K LVDS_DDC_SEL_EG R9683 10K 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 87 83 NO STUFF 87 74 EG_RESET_L R9691 100K 88 87 LCD_BKLT_PWM R9693 100K 87 86 73 EG_RAIL1_EN 87 73 72 EG_RAIL2_EN 87 82 73 EG_RAIL3_EN 87 86 73 72 EG_RAIL4_EN 5% 1/16W MF-LF 402 5% 1/16W MF-LF 402 B LCD_PWR_EN R9672 R9674 4.7K 4.7K 4.7K 5% 1/16W MF-LF 2402 5% 1/16W MF-LF 402 4.7K 5% 1/16W MF-LF 2402 R9671 R9678 5% 1/16W MF-LF 402 R9673 4.7K 5% 1/16W MF-LF 2402 GMUX_S3_PD_GND Q9607 R9681 DP_MUX_SEL_EG D NO STUFF SSM6N15FEAPE R9675 SOT563 100K 5% 1/16W MF-LF 2402 G 5% 1/16W MF-LF 2402 S GMUX_S3_PD_EN R9670 SYNC_MASTER=K17_REF 10K Q9607 1% 1/16W MF-LF 402 SYNC_DATE=06/15/2009 PAGE TITLE D Graphics MUX (GMUX) SSM6N15FEAPE SOT563 GMUX_VSYNC 87 18 87 93 (Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rail’s source is valid) PP3V3_S3 NO STUFF DRAWING NUMBER Apple Inc 88 G 73 45 27 25 2 MF-LF PLACE_NEAR=U9600.G1:5mm 1K 100 100 100 100 1% 1% 1/16W PLACE_NEAR=U9600.E3:5mm A4 P11 ULC_VCCPLL LRC_VCCPLL VCCIO7 VCCIO6 VCCIO5 VCCIO4 VCCIO3 VCCIO2 PT9A J1 69 68 63 62 58 54 52 51 50 48 25 24 23 21 20 19 18 17 47 46 42 40 37 34 30 28 27 26 99 88 87 85 84 83 80 73 72 VCCIO1 PT8A PT8B GND A B5 B7 A12 C14 F13 M12 M9 M3 N5 M1 C3 F2 C11 J2 J14 M8 PT7B PB14A PB14B PB15A (OD) PB15B PB16A PB16B PB17A PB17B PB18A PB18B (OD) PB19A PB19B PB20A PB20B BANK6 27 B1 B2 C2 D3 D1 E1 D2 E3 F1 G1 F3 G2 H2 G3 H1 H3 L1 L3 K3 L2 N1 P1 1/16W PLACE_NEAR=U9600.E1:5mm 1% Required Pulldowns PT7A CSBGA BANK7 NO STUFF 93 87 18 93 87 18 93 87 18 LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N GMUX_PL10A TP_GMUX_PL10B LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N TP_LVDS_MUX_SEL_EG GMUX_VSYNC GMUX_RESET_L GMUX_VSYNC PM_ALL_GPU_PGOOD PEX_CLKREQ_L 100 100 100 PLACE_NEAR=U9600.H3:5mm 1% R96791 PB7B PB27A R9680 SILK_PART=GMUX_RST XP25-5 PB26A PB26B GMUX_DEBUG_RESET_L U9600 BANK4 94 47 45 17 PB7A BANK5 87 84 87 74 87 86 73 CFG0 P2 N2 P4 N4 N3 M4 P5 M5 P6 M6 P7 M7 N7 N8 P9 N9 P10 M10 P12 P13 N12 P14 BANK0 10K 1% 1/16W MF-LF 402 K1 BANK1 R9646 LCD_BKLT_EN LCD_BKLT_PWM LVDS_DDC_SEL_EG LVDS_DDC_SEL_IG DP_MUX_EN DP_MUX_SEL_EG EG_RESET_L EG_RAIL1_EN EG_RAIL2_EN EG_RAIL3_EN EG_RAIL4_EN PEG_CLKREQ_L DP_CA_DET_EG LCD_PWR_EN LPC_AD LPC_AD LPC_AD LPC_AD LPC_FRAME_L LPCPLUS_RESET_L LPC_CLK33M_GMUX GMUX_INT BANK2 OUT BANK3 R96411 89 ULC_GNDPLL LRC_GNDPLL NO STUFF NO STUFF B4 M11 NO STUFF GNDIO7 C VCCJ OMIT CRITICAL GNDIO6 87 19 GNDIO5 87 20 VCCIO0 87 19 GNDIO3 GNDIO4 1% 1/16W MF-LF 402 VCCAUX TCK TDI TDO TMS TOE GNDIO2 1% 1/16W MF-LF 402 K14 L13 K13 L12 K2 GNDIO1 10K JTAG_GMUX_TCK JTAG_GMUX_TDI JTAG_GMUX_TDO JTAG_GMUX_TMS GMUX_TOE GNDIO0 10K 87 25 20 B8 C6 C12 C13 E13 M14 N10 N6 P3 M2 C1 E2 R9645 Required Pullups 87 VCC SIGNAL_MODEL=EMPTY PP3V3_S0 R96401 0.1UF B11 C4 J3 J13 N11 P8 87 54 28 21 46 72 100 100 100 100 C9630 87 99 88 69 68 63 62 58 42 40 37 34 30 20 19 18 17 27 26 25 24 23 52 51 50 48 47 85 84 83 80 73 R9650 R9651 R9652 R9653 R9654 R9655 R9656 0402 C9631 0.1UF 20% 10V CERM 402 LVDS_IG_B_DATA_P LVDS_IG_B_DATA_P LVDS_IG_B_DATA_P 93 87 18 FERR-220-OHM PP3V3R1V8_S0_GMUX_ULC_VCCPLL MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.09 mm VOLTAGE=1.8V LVDS_IG_A_CLK_P LVDS_IG_A_DATA_P LVDS_IG_A_DATA_P LVDS_IG_A_DATA_P 93 87 18 GMUXPLL_3V3 1 PP3V3R1V8_S0_GMUX MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V 5% 1/16W MF-LF 402 99 88 87 80 73 63 62 51 50 42 40 28 27 23 21 17 20 19 18 26 25 24 37 34 30 48 47 46 58 54 52 72 69 68 85 84 83 PP3V3_S0 PP1V8_S0_GMUX_R R9610 87 72 71 16 12 58 24 23 21 1 LVDS Receiver Termination R9611 PP1V8_S0 PP3V3_S0_GMUX_R GMUXPLL_1V8 72 71 58 24 23 21 16 12 87 0.1UF 20% 10V CERM 402 GMUX CPLD 5% 1/16W MF-LF 402 D R9600 IN S R NOTICE OF PROPRIETARY PROPERTY: ALL_SYS_PWRGD THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE 96 OF 132 SHEET 87 OF 101 A *L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER *PPVOUT_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE * LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT D D R9701 PP5V_S0 70 69 68 54 52 47 42 23 86 72 5% 1/16W MF-LF 402 MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V R9702 5% 1/16W MF-LF 402 CRITICAL 89 88 PPBUS_S0_LCDBKLT_PWR CRITICAL L9701 XW9700 SM D9701 SOD-123 22UH-2.5A PPVIN_BKL CRITICAL 1 C9712 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=8.4V C9713 IHLP2525CZ-SM 0.1UF 10UF NO STUFF 10% 25V X5R 402 10% 25V X5R 805 PPBUS_S0_LCDBKLT_PWR_SW MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=50V SWITCH_NODE=TRUE PPVOUT_S0_LCDBKLT CRITICAL CRITICAL RB160M-60G C9796 220PF R9703 10% 50V X7R-CERM 402 5% 1/16W MF-LF 402 C9797 10UF 10% 50V X5R 1210-1 56 83 MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=50V C9799 10UF 10% 50V X5R 1210-1 BKL_VLDO PPVIN_BKL_R PP3V3_S0 68 63 62 58 54 52 51 50 48 25 24 23 21 20 19 18 17 47 46 42 40 37 34 30 28 27 26 99 87 85 84 83 80 73 72 69 C MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM C9714 0.01UF C9710 1UF 10% 16V CERM 402 10% 25V X5R 603-1 C C9711 0.1UF 10% 16V X5R 402 NO STUFF C9741 1UF VOLTAGE=5V 10% 6.3V X5R 402 47.0K2 20% 6.3V X5R 603 BKL_FLTR_RC VDDIO 10K BKL_FSET 5% 1/16W MF-LF 402 BKL_FLTR BKL_ISET 5% PPBUS_S0_LCDBKLT_PWR 301K NO STUFF OUT2 13 BKL_ISEN2 OUT3 14 BKL_ISEN3 BKL_SDA 11 SDA OUT4 16 BKL_ISEN4 PWM OUT5 17 BKL_ISEN5 TP_BKL_FAULT FAULT OUT6 18 BKL_ISEN6 BKLT_EN EN VSYNC 19 C9723 0.1UF 10% 25V X5R 402 R9715 100K 1% 1/16W MF-LF 402 (EEPROM should set EN_I_RES=1) R97141 16.2K R9704 IN BKL_ISEN1 LCD_BKLT_PWM R9704 SHOULD BE 47K IF RC FILTER IS USED R97161 90.9K 1% 1/16W MF-LF 402 2 5% 1/16W MF-LF 402 I_LED=23.2Ma I_LED=369/Riset NO STUFF R9755 10K 5% 1/16W MF-LF 402 THRM PAD 1 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm R9754 BKL_SGND LED_RETURN_2 5% 1/16W MF-LF 402 10.2 LED_RETURN_3 0.1% 1/16W TF 402 83 OUT MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 83 OUT MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 83 OUT MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 83 OUT MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 83 OUT 83 B R9720 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 10.2 LED_RETURN_4 0.1% 1/16W TF 402 R9721 XW9710 SM 33PF 10.2 0.1% 1/16W TF 402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm C9704 OUT MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm R9719 Fpwm=9.62KhZ details in spec 5% 50V CERM 402 LED_RETURN_1 R9718 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm BKL_VSYNC_R 10.2 0.1% 1/16W TF 402 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm NO STUFF 1% 1/16W MF-LF 402 87 OUT1 R9717 1% 1/16W MF-LF 402 1 89 88 21 12 ISET 1/16W MF-LF 402 R9731 24 FB 10 SCLK LVDS_BKL_PWM_RC 5% SW BKL_SCL 1/16W MF-LF 402 CRITICAL 25 R9757 20 FILTER 15 GND_L SMBUS_PCH_DATA FSET GND_S B 48 47 42 32 30 28 26 25 17 94 63 R9753 SMBUS_PCH_CLK GD GND_SW 63 48 47 42 32 30 28 26 25 17 94 VIN LLP NC VLDO U9701 1% 1/16W MF-LF 402 R9741 23 R9740 22 10UF LP8545SQX C9740 NO STUFF NO STUFF 10.2 LED_RETURN_5 0.1% 1/16W TF 402 R9722 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm GMUX_VSYNC IN 10.2 LED_RETURN_6 MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm 0.1% 1/16W TF 402 87 A SYNC_MASTER=K18_BKLT SYNC_DATE=07/29/2009 PAGE TITLE LCD BACKLIGHT DRIVER DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE 97 OF 132 SHEET 88 OF 101 A CRITICAL Q9806 FDC638APZ_SBMS001 CRITICAL F9800 IN 0402-HF PPBUS_S0_LCDBKLT_FUSED MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.251 mm VOLTAGE=12.6V R9808 301K C9802 0.1UF 1% 1/16W MF-LF 402 MOSFET FDC638APZ CHANNEL P-TYPE RDS(ON) LOADING 10% 16V X5R 402 D 43 mOhm @4.5V 0.4 A (EDP) D PPBUS_G3H 2AMP-32V 82 70 69 67 66 65 49 40 86 PPBUS S0 LCDBkLT FET SSOT6-HF PBUS_S0_LCDBKLT_EN_DIV R9809 147K 1% 1/16W MF-LF 402 PBUS_S0_LCDBKLT_EN_L Q9807 D SSM6N15FEAPE SOT563 89 87 IN G LCD_BKLT_EN S PPBUS_S0_LCDBKLT_PWR OUT MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V BKLT_EN_L Q9807 88 D SSM6N15FEAPE SOT563 C 27 IN G BKLT_PLT_RST_L C S B B LCD_BKLT_EN 87 89 R9840 4.7K 5% 1/16W MF-LF 402 A SYNC_MASTER=K19_MLB SYNC_DATE=05/29/2009 PAGE TITLE LCD Backlight Support DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE 98 OF 132 SHEET 89 OF 101 A D D Blank Page, was 1.2V/1.8V in K19 C C B B A SYNC_MASTER=K18_POWER SYNC_DATE=06/10/2009 PAGE TITLE Misc Power Supplies DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE 99 OF 132 SHEET 90 OF 101 A CPU Signal Constraints CPU Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP CPU_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD CPU_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET NET_TYPE SPACING PHYSICAL TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM CPU_27P4S * =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE MIL MIL NOTE: mil gap is for VCCSense pair, which Intel says to route with mil spacing without specifying a target impedance TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =STANDARD ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM D CPU_AGTL * DMI_S2N DMI_S2N DMI_N2S DMI_N2S PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE PCIE PCIE PCIE DMI_S2N_P DMI_S2N_N DMI_N2S_P DMI_N2S_N FDI_DATA FDI_DATA PCIE_85D PCIE_85D CPU_50S CPU_50S PCIE PCIE CPU_AGTL CPU_AGTL FDI_DATA_P FDI_DATA_N FDI_FSYNC FDI_LSYNC CPU_50S CPU_AGTL FDI_INT CPU_PECI FSB_CPURST_L PM_SYNC PM_MEM_PWRGD CPU_50S CPU_50S CPU_50S CPU_50S PCIE CPU_AGTL CPU_AGTL CPU_AGTL CPU_PECI FSB_CPURST_L PM_SYNC PM_MEM_PWRGD CPU_VTT_S0_PGOOD XDP_XPU_PWRGOOD XDP_BDRESET_L CPU_50S CPU_50S CPU_50S CPU_AGTL CPU_ITP CPU_ITP CPUVTTS0_PGOOD XDP_CPUPWRGD XDP_DBRESET_L XDP_PRDY_L XDP_PREQ_l CPU_50S CPU_50S CPU_ITP CPU_ITP XDP_PRDY_L XDP_PREQ_L CPU_50S CPU_50S CPU_27P4S CPU_27P4S CPU_27P4S CPU_50S CPU_50S CPU_50S CPU_AGTL CPU_AGTL CPU_COMP CPU_COMP CPU_COMP CPU_ITP CPU_AGTL CPU_AGTL PM_EXT_TS_L PM_EXT_TS_L CPU_SM_RCOMP0 CPU_SM_RCOMP1 CPU_SM_RCOMP2 CPU_CFG CPU_CATERR_L TP_CPU_VTT_SELECT CPU_PROCHOT_L CPU_PWRGD CPU_50S CPU_50S CPU_AGTL CPU_AGTL CPU_PROCHOT_L CPU_PWRGD PM_THRMTRIP_L CPU_50S CPU_8MIL PM_THRMTRIP_L FSB_CLK_CPU FSB_CLK_CPU FSB_CLK_ITP FSB_CLK_ITP PCIE_CLK100M_CPU PCIE_CLK100M_CPU CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE FSB_CLK133M_CPU_P FSB_CLK133M_CPU_N FSB_CLK133M_ITP_P FSB_CLK133M_ITP_N PCIE_CLK100M_CPU_P PCIE_CLK100M_CPU_N PM_DPRSLPVR CPU_55S CPU_50S CPU_8MIL CPU_AGTL CPU_PSI_L PM_DPRSLPVR CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_PEG_COMP CPU_PEG_RBIAS CPU_COMP3 CPU_COMP2 CPU_COMP1 CPU_COMP0 (FSB_CPURST_L) CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_50S CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP CPU_ITP XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L XDP_CPURST_L CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_55S CPU_50S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_8MIL CPU_AGTL CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VCCSENSE CPU_VID CPUIMVP_IMON CPU_VCCSENSE_P CPU_VCCSENSE_N CPU_VTTSENSE_P CPU_VTTSENSE_N CPU_27P4S CPU_27P4S CPU_55S CPU_50S CPU_50S CPU_50S CPU_VCCSENSE CPU_VCCSENSE CPU_8MIL CPU_AGTL CPU_AGTL CPU_AGTL GFX_VSENSE_P GFX_VSENSE_N GFX_VID GFX_DPRSLPVR GFX_VR_EN GFXIMVP_IMON PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PEG_R2D_P PEG_R2D_N PEG_R2D_C_P PEG_R2D_C_N PEG_D2R_P PEG_D2R_N PEG_D2R_C_P PEG_D2R_C_N TABLE_SPACING_RULE_ITEM CPU_AGTL TOP,BOTTOM 18 18 18 18 18 18 18 D 18 TABLE_SPACING_RULE_ITEM CPU_8MIL * ? MIL 18 TABLE_SPACING_RULE_ITEM CPU_COMP * 20 MIL ? CPU_ITP * =2:1_SPACING ? CPU_VCCSENSE * 25 MIL ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM Most CPU signals with impedance requirements are 50-ohm single-ended Some signals require 27.4-ohm single-ended impedance SOURCE: Calpella SFF DG (DG-407364_v1.5), Section 2.8 PCI-Express 10 20 10 25 10 18 10 18 31 10 70 10 25 10 25 27 10 25 10 25 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCIE_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF TABLE_PHYSICAL_RULE_ITEM CPU_SM_RCOMP CPU_SM_RCOMP CPU_SM_RCOMP CPU_CFG CPU_CATERR_L TABLE_PHYSICAL_RULE_ITEM CLK_PCIE_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =3X_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4X_DIELECTRIC ? TABLE_SPACING_RULE_ITEM PCIE * TABLE_SPACING_RULE_ITEM PCIE TOP,BOTTOM 10 46 10 46 10 10 10 25 10 12 TABLE_SPACING_RULE_ITEM CLK_PCIE * 20 MIL ? SOURCE: Calpella SFF DG (DG-407364_v1.5), Section 2.1 and Table 4-184 C XDP_TDI XDP_TDO XDP_TMS XDP_TCK XDP_TRST_L XDP_BPM_L XDP_BPM_L B CPU_VCCSENSE CPU_VCCSENSE PM_DPRSLPVR PEG_R2D PEG_D2R A 10 46 68 10 20 25 10 20 46 C 10 20 10 20 10 25 10 25 10 17 10 17 12 15 68 12 15 68 9 10 10 10 10 25 25 10 25 10 25 10 25 10 25 10 25 25 12 15 12 50 68 B 12 68 12 68 12 70 12 70 13 69 13 69 13 13 69 13 69 13 69 74 74 74 74 74 74 74 74 SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 PAGE TITLE CPU Constraints DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE 100 OF 132 SHEET 91 OF 101 A Memory Bus Constraints Memory Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP MEM_37S * =37_OHM_SE =37_OHM_SE =37_OHM_SE =37_OHM_SE =STANDARD =STANDARD MEM_40S * =40_OHM_SE =40_OHM_SE =40_OHM_SE =40_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM MEM_A_CLK MEM_A_CLK MEM_72D MEM_72D MEM_CLK MEM_CLK MEM_A_CLK_P MEM_A_CLK_N MEM_A_CNTL MEM_A_CNTL MEM_A_CNTL MEM_37S MEM_37S MEM_37S MEM_CTRL MEM_CTRL MEM_CTRL MEM_A_CKE MEM_A_CS_L MEM_A_ODT MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_A_CMD MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_A_A MEM_A_BA MEM_A_RAS_L MEM_A_CAS_L MEM_A_WE_L MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ MEM_A_DQ_BYTE0 MEM_A_DQ_BYTE1 MEM_A_DQ_BYTE2 MEM_A_DQ_BYTE3 MEM_A_DQ_BYTE4 MEM_A_DQ_BYTE5 MEM_A_DQ_BYTE6 MEM_A_DQ_BYTE7 MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DM MEM_A_DQS0 MEM_A_DQS0 MEM_A_DQS1 MEM_A_DQS1 MEM_A_DQS2 MEM_A_DQS2 MEM_A_DQS3 MEM_A_DQS3 MEM_A_DQS4 MEM_A_DQS4 MEM_A_DQS5 MEM_A_DQS5 MEM_A_DQS6 MEM_A_DQS6 MEM_A_DQS7 MEM_A_DQS7 MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_A_DQS_P MEM_A_DQS_N MEM_B_CLK MEM_B_CLK MEM_72D MEM_72D MEM_CLK MEM_CLK MEM_B_CLK_P MEM_B_CLK_N MEM_B_CNTL MEM_B_CNTL MEM_B_CNTL MEM_37S MEM_37S MEM_37S MEM_CTRL MEM_CTRL MEM_CTRL MEM_B_CKE MEM_B_CS_L MEM_B_ODT MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_B_CMD MEM_40S MEM_40S MEM_40S MEM_40S MEM_40S MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_CMD MEM_B_A MEM_B_BA MEM_B_RAS_L MEM_B_CAS_L MEM_B_WE_L DQ/DM signals should be matched within 0.508mm of associated DQS pair DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement DQS to clock matching should be within [CLK-12.7mm] and [CLK+25.4mm] CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm CONTROL signals should be matched within [CLK-12.7mm] to [CLK+0.0mm] of CLK pairs A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric Maximum length of any signal from die pad to SODIMM pad is 139.7mm, from procesor ball to SODIMM pad is 114.3mm MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ MEM_B_DQ SOURCE: Calpella SFF Platform DG, Rev 1.5 (#407364), Section 2.2 MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE7 MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_50S MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_DATA MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DM MEM_B_DQS0 MEM_B_DQS0 MEM_B_DQS1 MEM_B_DQS1 MEM_B_DQS2 MEM_B_DQS2 MEM_B_DQS3 MEM_B_DQS3 MEM_B_DQS4 MEM_B_DQS4 MEM_B_DQS5 MEM_B_DQS5 MEM_B_DQS6 MEM_B_DQS6 MEM_B_DQS7 MEM_B_DQS7 MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_85D MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_DQS MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N MEM_B_DQS_P MEM_B_DQS_N TABLE_PHYSICAL_RULE_ITEM 11 28 11 28 TABLE_PHYSICAL_RULE_ITEM MEM_72D * =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF =72_OHM_DIFF MEM_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM 11 28 11 28 11 28 TABLE_PHYSICAL_RULE_ITEM D MEM_85D * SPACING_RULE_SET LAYER =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM MEM_CLK2MEM * ? =4:1_SPACING 11 28 11 28 D 11 28 11 28 11 28 TABLE_SPACING_RULE_ITEM MEM_CTRL2CTRL * =3:1_SPACING ? MEM_CTRL2MEM * =2.5:1_SPACING ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM MEM_CMD2CMD * =1.5:1_SPACING ? TABLE_SPACING_RULE_ITEM MEM_CMD2MEM * ? =3:1_SPACING TABLE_SPACING_RULE_ITEM MEM_DATA2DATA * =1.5:1_SPACING ? MEM_DATA2MEM * =3:1_SPACING ? TABLE_SPACING_RULE_ITEM 11 29 11 29 11 29 11 29 11 28 29 11 29 11 29 11 29 TABLE_SPACING_RULE_ITEM MEM_DQS2MEM * =3:1_SPACING ? MEM_2OTHER * 25 MILS ? TABLE_SPACING_RULE_ITEM Memory Bus Spacing Group Assignments TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CLK * MEM_CLK2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_CLK * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK MEM_CTRL * MEM_CLK2MEM MEM_CLK MEM_CMD * MEM_CLK2MEM MEM_CLK MEM_DATA * MEM_CLK2MEM MEM_CMD MEM_CTRL * MEM_CMD2MEM MEM_CMD MEM_CMD * MEM_CMD2CMD MEM_CMD MEM_DATA * MEM_CMD2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS * MEM_CLK2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET C TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD MEM_DQS * MEM_CMD2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CLK * MEM_CTRL2MEM MEM_CTRL MEM_CTRL * MEM_CTRL2CTRL TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CLK * MEM_DATA2MEM MEM_DATA MEM_CTRL * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_CMD * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_CMD * MEM_DATA2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DATA * MEM_CTRL2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DATA * MEM_DATA2DATA TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL MEM_DQS * MEM_CTRL2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_DQS MEM_CLK * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA MEM_DQS * MEM_DATA2MEM NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET MEM_CLK * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CTRL * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_CMD * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CMD * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS MEM_DATA * MEM_DQS2MEM MEM_DQS MEM_DQS * MEM_DQS2MEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DATA * * MEM_2OTHER MEM_DQS * * MEM_2OTHER TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM Need to support MEM_*-style wildcards! DDR3: B 11 29 11 29 11 29 11 29 11 29 11 29 11 28 29 11 28 29 11 29 11 29 11 29 11 29 C 11 29 11 29 11 29 11 29 11 29 11 29 11 29 11 29 11 29 11 29 11 30 11 30 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS 11 29 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK 11 28 29 A 11 30 11 30 11 30 11 30 11 30 11 30 11 30 11 30 11 29 11 29 11 29 11 29 B 11 29 30 11 29 11 29 11 29 11 29 30 11 29 11 29 11 29 11 29 11 29 11 29 11 29 11 29 30 11 29 30 11 29 11 29 11 29 11 29 11 29 11 29 11 29 11 29 11 29 11 29 11 29 11 29 11 29 SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 PAGE TITLE Memory Constraints 11 29 DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE 101 OF 132 SHEET 92 OF 101 A Digital Video Signal Constraints LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM DP_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF LVDS_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM DISPLAYPORT * =3x_DIELECTRIC ? LVDS * =3x_DIELECTRIC ? NET_TYPE PHYSICAL SPACING DP_ML DP_ML DP_AUX_CH DP_AUX_CH DP_85D DP_85D DP_85D DP_85D DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DP_IG_ML_P DP_IG_ML_N DP_IG_AUX_CH_P DP_IG_AUX_CH_N LVDS_IG_A_CLK LVDS_IG_A_CLK LVDS_IG_A_DATA LVDS_IG_A_DATA LVDS_IG_A_DATA3 LVDS_IG_A_DATA3 LVDS_IG_B_CLK LVDS_IG_B_CLK LVDS_IG_B_DATA LVDS_IG_B_DATA LVDS_IG_B_DATA3 LVDS_IG_B_DATA3 LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS_IG_A_CLK_P LVDS_IG_A_CLK_N LVDS_IG_A_DATA_P LVDS_IG_A_DATA_N NC_LVDS_IG_A_DATAP NC_LVDS_IG_A_DATAN TP_LVDS_IG_B_CLKP TP_LVDS_IG_B_CLKN LVDS_IG_B_DATA_P LVDS_IG_B_DATA_N NC_LVDS_IG_B_DATAP NC_LVDS_IG_B_DATAN SATA_HDD_R2D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA SATA_HDD_R2D_C_P 17 42 SATA_HDD_R2D_C_N 17 42 SATA_HDD_R2D_P 42 SATA_HDD_R2D_N 42 SATA_HDD_D2R_P 17 42 SATA_HDD_D2R_N 17 42 SATA_HDD_D2R_C_P 42 SATA_HDD_D2R_C_N 42 SATA_ODD_R2D_C_P 17 42 SATA_ODD_R2D_C_N 17 42 SATA_ODD_R2D_P 42 SATA_ODD_R2D_N 42 SATA_ODD_D2R_P 17 42 SATA_ODD_D2R_N 17 42 SATA_ODD_D2R_C_P 42 SATA_ODD_D2R_C_N 42 SATA_HDD_R2D_RDRV_IN_P 42 SATA_HDD_R2D_RDRV_IN_N 42 SATA_HDD_R2D_RDRV_OUT_P 42 SATA_HDD_R2D_RDRV_OUT_N 42 SATA_HDD_D2R_RDRV_IN_P 42 SATA_HDD_D2R_RDRV_IN_N 42 SATA_HDD_D2R_RDRV_OUT_P 42 SATA_HDD_D2R_RDRV_OUT_N 42 USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D USB_85D SATA_ICOMP USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB USB PCH_SATAICOMP USB_HUB1_UP_P USB_HUB1_UP_N USB_HUB2_UP_P USB_HUB2_UP_N USB_EXTA_P USB_EXTA_N USB_EXTB_P USB_EXTB_N USB_EXTC_P USB_EXTC_N USB_EXTD_P USB_EXTD_N USB_MINI_P USB_MINI_N USB_WM_P USB_WM_N USB_CAMERA_CONN_P USB_CAMERA_CONN_N USB_BT_P USB_BT_N USB_TPAD_P USB_TPAD_N USB_IR_P USB_IR_N USB_SDCARD_P USB_SDCARD_N USB_BRCRYPT_P USB_BRCRYPT_N 84 84 18 84 18 84 TABLE_SPACING_RULE_ITEM DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ? LVDS TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM D PCH Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET TABLE_SPACING_RULE_ITEM LVDS intra-pair matching should be mils Pairs should be within 100 mils of clock length DisplayPort/TMDS intra-pair matching should be ps Inter-pair matching should be within 150 ps DIsplayPort AUX CH intra-pair matching should be ps No relationship to other signals Max length of LVDS/DisplayPort/TMDS traces: 12 inches SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4 SATA Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SATA_90D * =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF SPACING_RULE_SET LAYER 18 87 18 87 18 87 D 18 87 18 18 18 18 18 87 18 87 18 18 TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =3x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM SATA * TABLE_SPACING_RULE_ITEM ? =4x_DIELECTRIC SATA TOP,BOTTOM SATA_HDD_D2R TABLE_SPACING_RULE_ITEM SATA_ICOMP * ? MIL SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1 USB 2.0 Interface Constraints SATA_ODD_R2D TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP PCH_USB_RBIAS * =STANDARD MIL MIL =STANDARD =STANDARD =STANDARD USB_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM SATA_ODD_D2R TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM C USB * =2x_DIELECTRIC SATA_HDD_R2D TABLE_SPACING_RULE_ITEM ? USB TOP,BOTTOM SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.8 SATA_HDD_D2R PCH_SATA_ICOMP USB_HUB1_UP USB_HUB2_UP USB_EXTA USB_EXTB USB_EXTC USB_EXTD USB_MINI USB_WM USB_CAMERA B USB_BT USB_TPAD USB_IR USB_SDCARD USB_BRCRYPT PCH_USB_RBIAS PCH_USB_RBIAS PCH_USB_RBIAS PCH_CLK100M_PCH PCH_CLK100M_SATA PCH_CLK100M_SATA GFX_CLK_DPLLSS GFX_CLK_DPLLSS CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CPU_50S CPU_50S CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE PCIE_CLK100M_PCH_P PCIE_CLK100M_PCH_N FSB_CLK133M_PCH_P FSB_CLK133M_PCH_N PCH_CLK96M_DOT_P PCH_CLK96M_DOT_N PCH_CLK100M_SATA_P PCH_CLK100M_SATA_N PCH_CLK14P3M_REFCLK PCH_CLK33M_PCIIN GFX_CLK120M_DPLLSS_P GFX_CLK120M_DPLLSS_N A C 17 19 35 19 35 19 36 19 36 36 43 36 43 35 43 35 43 35 35 33 33 B 33 36 33 36 36 53 36 53 35 44 35 44 34 36 34 36 19 101 19 101 19 17 26 17 26 17 26 17 26 17 26 17 26 17 26 17 26 17 26 17 27 10 17 10 17 SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 PAGE TITLE PCH Constraints DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE 102 OF 132 SHEET 93 OF 101 A LPC Bus Constraints LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM LPC_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD CLK_LPC_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD PCH Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT MIL ? TABLE_SPACING_RULE_ITEM LPC * LPC_AD LPC_FRAME_L LPC_RESET_L LPC_50S LPC_50S LPC_50S LPC LPC LPC LPC_AD LPC_FRAME_L LPCPLUS_RESET_L MCP_LPC_CLK0 CLK_LPC_50S CLK_LPC_50S CLK_LPC_50S CLK_LPC CLK_LPC CLK_LPC LPC_CLK33M_SMC_R LPC_CLK33M_SMC LPC_CLK33M_LPCPLUS SMBUS_PCH_CLK SMBUS_PCH_DATA SMBUS_PCH_0_CLK SMBUS_PCH_0_DATA SMBUS_PCH_1_CLK SMBUS_PCH_1_DATA SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB SMB SMB SMB SMB SMB SMBUS_PCH_CLK SMBUS_PCH_DATA SML_PCH_0_CLK SML_PCH_0_DATA SML_PCH_1_CLK SML_PCH_1_DATA HDA_BIT_CLK HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA_50S HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA HDA_BIT_CLK HDA_BIT_CLK_R HDA_SYNC HDA_SYNC_R HDA_RST_R_L HDA_RST_L HDA_SDIN0 AUD_SDI_R HDA_SDOUT HDA_SDOUT_R PM_SUS_CLK CLK_SLOW_55S CLK_SLOW PM_CLK32K_SUSCLK SPI_CLK SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI_55S SPI SPI SPI SPI SPI SPI SPI SPI_CLK_R SPI_CLK SPI_MOSI_R SPI_MOSI SPI_MISO SPI_CS0_R_L SPI_CS0_L PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE_ENET_R2D_P PCIE_ENET_R2D_N PCIE_ENET_R2D_C_P PCIE_ENET_R2D_C_N PCIE_ENET_D2R_P PCIE_ENET_D2R_N PCIE_ENET_D2R_C_P PCIE_ENET_D2R_C_N PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE PCIE PCIE PCIE PCIE PCIE PCIE_AP_R2D_P PCIE_AP_R2D_N PCIE_AP_R2D_C_P PCIE_AP_R2D_C_N PCIE_AP_D2R_P PCIE_AP_D2R_N PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE PCIE_FW_R2D_P PCIE_FW_R2D_N PCIE_FW_R2D_C_P PCIE_FW_R2D_C_N PCIE_FW_D2R_P PCIE_FW_D2R_N PCIE_FW_D2R_C_P PCIE_FW_D2R_C_N PCIE_85D PCIE_85D PCIE_85D PCIE_85D PCIE PCIE PCIE PCIE CONN_PCIE_AP_D2R_P CONN_PCIE_AP_D2R_N CONN_PCIE_AP_R2D_P CONN_PCIE_AP_R2D_N CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE_90D CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE CLK_PCIE PEG_CLK100M_P 17 PEG_CLK100M_N 17 PCIE_CLK100M_ENET_P 17 PCIE_CLK100M_ENET_N 17 PCIE_CLK100M_AP_P 17 PCIE_CLK100M_AP_N 17 PCIE_CLK100M_FW_P 17 PCIE_CLK100M_FW_N 17 NC_PCIE_CLK100M_EXCARD_P NC_PCIE_CLK100M_EXCARD_N CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_27P4S CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP CPU_COMP PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF TP_PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF PCH_VSS_NCTF TABLE_SPACING_RULE_ITEM CLK_LPC D * ? MIL SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15 SMBus Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM SMB_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT HDA_SYNC TABLE_SPACING_RULE_ITEM SMB * =2x_DIELECTRIC ? HDA_RST_L HD Audio Interface Constraints HDA_SDIN0 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP HDA_SDOUT TABLE_PHYSICAL_RULE_ITEM HDA_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD 17 45 47 87 17 45 47 87 27 47 87 19 27 27 45 27 47 D 17 25 26 28 30 32 42 47 48 63 88 17 25 26 28 30 32 42 47 48 63 88 17 48 17 48 17 48 17 48 17 58 17 17 58 17 17 17 58 17 58 58 17 58 17 18 46 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT =2x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM HDA * SPI_MOSI SOURCE: Calpella Platform Design Guide for Ibex Peak M (DG-398905-398905_v1.5), Section 3.15 SIO Signal Constraints SPI_MISO SPI_CS0 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 17 47 47 17 47 47 17 47 17 47 47 TABLE_PHYSICAL_RULE_ITEM C CLK_SLOW_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD PCIE_ENET_R2D TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM CLK_SLOW * ? MIL PCIE_ENET_D2R SPI Interface Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM SPI_55S * =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE =STANDARD =STANDARD PCIE_AP_R2D PCIE_AP_D2R TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 37 C 37 17 37 17 37 17 37 17 37 37 37 33 33 17 33 17 33 17 33 17 33 TABLE_SPACING_RULE_ITEM SPI * MIL ? PCIE_FW_R2D PCIE_FW_D2R PCIE_AP_D2R PCIE_AP_R2D B MCP_PE0_REFCLK PCIE_CLK100M_ENET MCP_PE1_REFCLK MCP_PE2_REFCLK MCP_PE3_REFCLK I235 I236 I237 I238 I239 I240 I241 I242 I243 I244 I245 I246 A I247 I248 I249 I250 39 39 17 39 17 39 17 39 17 39 39 39 B 74 74 37 37 33 33 39 39 17 17 20 20 20 20 20 94 20 94 20 20 20 20 20 20 20 20 SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 PAGE TITLE PCH Constraints 20 20 DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE 103 OF 132 SHEET 94 OF 101 A CAESAR II (Ethernet) Constraints Ethernet Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ENET_50S * =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT ENET_50S ENET_50S ENET_50S ENET_3X ENET_3X ENET_3X BCM5764_CLK25M_XTALI BCM5764_CLK25M_XTALO ENET_RESET_L ENET_100D ENET_100D ENET_MDI ENET_MDI ENET_MDI_P ENET_MDI_N 27 37 27 37 27 37 TABLE_SPACING_RULE_ITEM ENET_3X * =3:1_SPACING ? ENET_MDI SOURCE: Broadcom 5764-DS04-RDS Page 38 D 37 38 37 38 CAESAR II (Ethernet PHY) Constraints D TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP ENET_100D * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF SPACING_RULE_SET LAYER TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT 0.6 MM ? TABLE_SPACING_RULE_ITEM ENET_MDI * SOURCE: Broadcom 5764-DS04-RDS Page 38 C C B B A SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 PAGE TITLE Ethernet Constraints DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE 104 OF 132 SHEET 95 OF 101 A FireWire Interface Constraints FireWire Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP FW_110D * =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF =110_OHM_DIFF ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM FW_P0_TPA FW_P0_TPA FW_P0_TPB FW_P0_TPB FW_P1_TPA FW_P1_TPA FW_P1_TPB FW_P1_TPB TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_SPACING_RULE_ITEM FW_TP * =3:1_SPACING ? FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_110D FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP FW_TP NC_FW0_TPAP NC_FW0_TPAN NC_FW0_TPBP NC_FW0_TPBN FW_PORT1_TPA_P FW_PORT1_TPA_N FW_PORT1_TPB_P FW_PORT1_TPB_N 39 41 39 41 39 41 39 41 39 40 41 39 40 41 39 40 41 39 40 41 D D Port Not Used C C B B A SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 PAGE TITLE FireWire Constraints DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE 105 OF 132 SHEET 96 OF 101 A SMC SMBus Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 1TO1_DIFFPAIR * =STANDARD =STANDARD =STANDARD =STANDARD 0.1 MM 0.1 MM ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING TABLE_PHYSICAL_RULE_ITEM SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA D SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB_50S SMB SMB SMB SMB SMB SMB SMB SMB SMB SMB SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA 33 45 48 54 33 45 48 54 45 48 51 45 48 51 45 48 51 81 45 48 51 81 45 48 64 65 45 48 64 65 D 45 48 56 45 48 56 SMBus Charger Net Properties ELECTRICAL_CONSTRAINT_SET NET_TYPE PHYSICAL SPACING CHGR_CSI 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSI_P CHGR_CSI_N CHGR_CSO 1TO1_DIFFPAIR 1TO1_DIFFPAIR CHGR_CSO_P CHGR_CSO_N 65 65 65 65 C C B B A SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 PAGE TITLE SMC Constraints DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE 106 OF 132 SHEET 97 OF 101 A GDDR3 Frame Buffer Signal Constraints GDDR3 FB A/B Net Properties GDDR3 FB C/D Net Properties TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM GDDR3_40R55SE * =55_OHM_SE =40_OHM_SE 0.095 MM 12.7 MM =STANDARD =STANDARD GDDR3_40SE * =40_OHM_SE =40_OHM_SE 0.095 MM =40_OHM_SE =STANDARD =STANDARD ELECTRICAL_CONSTRAINT_SET =85_OHM_DIFF =85_OHM_DIFF 0.095 MM =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF ELECTRICAL_CONSTRAINT_SET SPACING GDDR3_CLK GDDR3_CLK GDDR3_CLK GDDR3_CLK FB_A_CLK_P FB_A_CLK_N FB_A_CLK_P FB_A_CLK_N FB_AB_CMD FB_AB_CMD FB_AB_CMD FB_AB_CMD FB_AB_CMD FB_AB_CMD FB_AB_CMD_PD FB_AB_CMD_PD FB_AB_CS0 FB_AB_CMD_PD GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD FB_A_MA FB_A_MA FB_A_BA FB_A_RAS_L FB_A_UCAS_L FB_A_WE_L FB_A_UCKE FB_A_LCKE FB_A_LCS0_L FB_A_DRAM_RST FB_A_CMD FB_B_CMD GDDR3_40SE GDDR3_40SE GDDR3_CMD GDDR3_CMD FB_A_LMA FB_A_UMA FB_A_WDQS0 FB_A_WDQS1 FB_A_WDQS2 FB_A_WDQS3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_RDQS0 FB_A_RDQS1 FB_A_RDQS2 FB_A_RDQS3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_DQ_BYTE0 FB_A_DQ_BYTE1 FB_A_DQ_BYTE2 FB_A_DQ_BYTE3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQM0 FB_A_DQM1 FB_A_DQM2 FB_A_DQM3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_B_WDQS0 FB_B_WDQS1 FB_B_WDQS2 FB_B_WDQS3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_A_WDQS FB_B_RDQS0 FB_B_RDQS1 FB_B_RDQS2 FB_B_RDQS3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_A_RDQS FB_B_DQ_BYTE0 FB_B_DQ_BYTE1 FB_B_DQ_BYTE2 FB_B_DQ_BYTE3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_A_DQ FB_A_DQ FB_A_DQ FB_A_DQ FB_B_DQM0 FB_B_DQM1 FB_B_DQM2 FB_B_DQM3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L FB_A_DQM_L TABLE_PHYSICAL_RULE_ITEM * PHYSICAL GDDR3_80D GDDR3_80D GDDR3_80D GDDR3_80D FB_A_CLK TABLE_PHYSICAL_RULE_ITEM GDDR3_80D NET_TYPE NET_TYPE FB_B_CLK GDDR3_CLK GDDR3_CLK GDDR3_CLK GDDR3_CLK FB_B_CLK_P FB_B_CLK_N FB_B_CLK_P FB_B_CLK_N FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD FB_CD_CMD_PD FB_CD_CMD_PD FB_CD_CS0 FB_CD_CMD_PD GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_40R55SE GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD GDDR3_CMD FB_B_MA FB_B_MA FB_B_BA FB_B_RAS_L FB_B_UCAS_L FB_B_WE_L FB_B_UCKE FB_B_LCKE FB_B_LCS0_L FB_B_DRAM_RST FB_C_CMD FB_D_CMD GDDR3_40SE GDDR3_40SE GDDR3_CMD GDDR3_CMD FB_B_LMA FB_B_UMA FB_C_WDQS0 FB_C_WDQS1 FB_C_WDQS2 FB_C_WDQS3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_C_RDQS0 FB_C_RDQS1 FB_C_RDQS2 FB_C_RDQS3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_C_DQ_BYTE0 FB_C_DQ_BYTE1 FB_C_DQ_BYTE2 FB_C_DQ_BYTE3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_C_DQM0 FB_C_DQM1 FB_C_DQM2 FB_C_DQM3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_D_WDQS0 FB_D_WDQS1 FB_D_WDQS2 FB_D_WDQS3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_B_WDQS FB_D_RDQS0 FB_D_RDQS1 FB_D_RDQS2 FB_D_RDQS3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DQS GDDR3_DQS GDDR3_DQS GDDR3_DQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_B_RDQS FB_D_DQ_BYTE0 FB_D_DQ_BYTE1 FB_D_DQ_BYTE2 FB_D_DQ_BYTE3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_B_DQ FB_B_DQ FB_B_DQ FB_B_DQ FB_D_DQM0 FB_D_DQM1 FB_D_DQM2 FB_D_DQM3 GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_40SE GDDR3_DATA GDDR3_DATA GDDR3_DATA GDDR3_DATA FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_B_DQM_L FB_AB_CMD FB_CD_CMD GDDR3_40R55SE GDDR3_40R55SE GDDR3_CMD GDDR3_CMD FB_A_LCAS_L FB_B_LCAS_L 76 77 FB_D_CLK 76 77 SPACING GDDR3_80D GDDR3_80D GDDR3_80D GDDR3_80D FB_C_CLK 76 77 PHYSICAL 76 77 76 78 76 78 76 78 76 78 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT GDDR3_CLK * =2.5:1_SPACING ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM D GDDR3_CMD * ? =2.5:1_SPACING TABLE_SPACING_RULE_ITEM GDDR3_DATA * ? =2.5:1_SPACING TABLE_SPACING_RULE_ITEM GDDR3_DQS * ? =2.5:1_SPACING Digital Video Signal Constraints I205 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET ALLOW ROUTE ON LAYER? LAYER MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 I204 76 77 76 78 76 78 76 78 D 76 78 76 78 76 78 76 78 76 78 76 78 76 78 DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM DP_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF LVDS_85D * =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF 76 77 76 77 76 78 76 78 TABLE_PHYSICAL_RULE_ITEM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT DISPLAYPORT * =3x_DIELECTRIC ? LVDS * =3x_DIELECTRIC ? TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT DISPLAYPORT TOP,BOTTOM =4x_DIELECTRIC ? LVDS TOP,BOTTOM =4x_DIELECTRIC ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM LVDS intra-pair matching should be 0.127 mm Pairs should be within 0.508mm of entire channel DisplayPort/TMDS intra-pair matching should be 0.127mm Inter-pair matching should be within 2.54cm DIsplayPort AUX CH intra-pair matching should be 0.127mm Max length 330.2mm Max length of LVDS/DisplayPort/TMDS traces: 13 inches SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04 Max Length 241.3mm C MUXGFX Net Properties 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 76 77 G96 Net Properties I210 NET_TYPE ELECTRICAL_CONSTRAINT_SET I148 I149 B I199 I198 LVDS_A_CLK LVDS_A_CLK LVDS_A_DATA LVDS_A_DATA NET_TYPE PHYSICAL SPACING LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS LVDS LVDS LVDS ELECTRICAL_CONSTRAINT_SET LVDS_A_CLK_P LVDS_A_CLK_N 84 87 (CK505_DOT96) 84 87 LVDS_A_DATA_P LVDS_A_DATA_N 84 87 84 87 I206 I207 I152 I153 LVDS_B_CLK LVDS_B_CLK LVDS_85D LVDS_85D LVDS LVDS LVDS_B_CLK_P LVDS_B_CLK_N 84 87 84 87 I208 I209 I201 I200 LVDS_B_DATA LVDS_B_DATA LVDS_85D LVDS_85D LVDS LVDS LVDS_B_DATA_P LVDS_B_DATA_N 84 87 I142 84 87 I144 LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D I183 I182 I184 I185 I190 I191 I192 I193 I194 I195 I196 I197 A I161 DP_ML I160 I155 DP_ML I157 I202 DP_ML I203 DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT LVDS_CONN_A_CLK_F_P 83 LVDS_CONN_A_CLK_F_N 83 LVDS_CONN_B_CLK_F_P 83 LVDS_CONN_B_CLK_F_N 83 LVDS_CONN_A_CLK_P 83 84 LVDS_CONN_A_CLK_N 83 84 LVDS_CONN_A_DATA_P 83 LVDS_CONN_A_DATA_N 83 LVDS_CONN_B_CLK_P 83 84 LVDS_CONN_B_CLK_N 83 84 LVDS_CONN_B_DATA_P 83 LVDS_CONN_B_DATA_N 83 DP_ML_C_P DP_ML_C_N DP_ML_P DP_ML_N DP_ML_CONN_P DP_ML_CONN_N I145 I143 CK505_CLK27MSS LVDS_EG_A_CLK LVDS_EG_A_CLK LVDS_EG_A_DATA LVDS_EG_A_DATA LVDS_EG_A_DATA3 LVDS_EG_A_DATA3 LVDS_EG_B_DATA LVDS_EG_B_DATA LVDS_EG_B_DATA3 LVDS_EG_B_DATA3 DP_ML DP_ML DP_AUX_CH DP_AUX_CH I139 I138 PHYSICAL CLK_SLOW_55S CLK_SLOW_55S LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D LVDS_85D DP_85D DP_85D DP_85D DP_85D DP_85D DP_85D I211 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 78 76 77 76 78 SPACING CLK_SLOW CLK_SLOW LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT DISPLAYPORT GPU_CLK27M GPU_CLK27M_SS LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N LVDS_EG_A_DATA_P LVDS_EG_A_DATA_N NC_LVDS_EG_A_DATA_P NC_LVDS_EG_A_DATA_N LVDS_EG_B_DATA_P LVDS_EG_B_DATA_N NC_LVDS_EG_B_DATA_P NC_LVDS_EG_B_DATA_N DP_EG_ML_P DP_EG_ML_N DP_EG_AUX_CH_P DP_EG_AUX_CH_N DP_EG_AUX_CH_C_P DP_EG_AUX_CH_C_N 27 79 80 79 80 81 87 B 81 87 81 87 81 87 80 81 80 81 81 87 81 87 80 81 80 81 81 84 81 84 81 84 81 84 84 84 84 84 84 84 85 SYNC_MASTER=K17_REF 85 SYNC_DATE=06/15/2009 PAGE TITLE 84 85 GPU (GT216) CONSTRAINTS 84 85 DRAWING NUMBER 85 85 Apple Inc I158 DP_AUX_CH DP_AUX_CH DP_85D DP_85D DISPLAYPORT DISPLAYPORT NOTICE OF PROPRIETARY PROPERTY: DP_AUX_CH_C_P DP_AUX_CH_C_N BRANCH 84 85 THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 84 85 SIZE D REVISION R I159 C 76 78 76 78 PAGE 107 OF 132 SHEET 98 OF 101 A TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP K18 Specific Net Properties K18 Specific Net Properties NET_TYPE NET_TYPE TABLE_PHYSICAL_RULE_ITEM SENSE_1TO1_55S * =55_OHM_SE =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR =1:1_DIFFPAIR ELECTRICAL_CONSTRAINT_SET TABLE_PHYSICAL_RULE_ITEM THERM_1TO1_55S * =55_OHM_SE =1:1_DIFFPAIR =55_OHM_SE =55_OHM_SE =1:1_DIFFPAIR PHYSICAL SPACING ELECTRICAL_CONSTRAINT_SET ENET_100D ENETCONN ENET_100D ENETCONN ENETCONN_P ENETCONN_N SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA_90D SATA SATA SATA SATA SATA SATA SATA SATA SATA_ODD_R2D_UF_P SATA_ODD_R2D_UF_N SATA_ODD_D2R_UF_P SATA_ODD_D2R_UF_N SATA_HDD_D2R_UF_P SATA_HDD_D2R_UF_N SATA_HDD_R2D_UF_P SATA_HDD_R2D_UF_N =1:1_DIFFPAIR PHYSICAL SPACING 38 38 TABLE_PHYSICAL_RULE_ITEM DIFFPAIR * =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR =1:1_DIFFPAIR TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET WEIGHT TABLE_SPACING_ASSIGNMENT_ITEM CPU_COMP TABLE_SPACING_RULE_ITEM D SENSE * =2:1_SPACING ? THERM * =2:1_SPACING ? GND * GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM CPU_VCCSENSE TABLE_SPACING_RULE_ITEM GND * GND_P2MM 42 42 42 CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR 1TO1_DIFFPAIR PCIE_CLK100M_AP_CONN_P PCIE_CLK100M_AP_CONN_N CHGR_CSI_R_P CHGR_CSI_R_N CHGR_CSO_R_P CHGR_CSO_R_N USB_85D USB USB_85D USB USB2_EXTA_MUXED_P USB2_EXTA_MUXED_N USB_85D USB USB_85D USB 51 79 80 USB_85D USB 51 79 80 USB_85D USB PCIE_CLK100M_AP 42 42 42 42 42 33 33 65 D 65 49 65 49 65 TABLE_SPACING_RULE_ITEM AUDIO * ? =2:1_SPACING SENSE_DIFFPAIR THERM_1TO1_55S THERM THERM_1TO1_55S THERM THERM_1TO1_55S THERM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT I287 TABLE_SPACING_ASSIGNMENT_HEAD TABLE_SPACING_RULE_ITEM ENETCONN * 25 MILS NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET ENET_MDI GND * GND_P2MM SENSE_DIFFPAIR I288 ? TABLE_SPACING_ASSIGNMENT_ITEM SENSE_DIFFPAIR THERM_1TO1_55S THERM THERM_1TO1_55S THERM THERM_1TO1_55S THERM THERM_1TO1_55S THERM THERM_1TO1_55S THERM TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT SENSE_DIFFPAIR TABLE_SPACING_RULE_ITEM GND * =STANDARD TABLE_SPACING_ASSIGNMENT_HEAD ? NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET CLK_PCIE GND * GND_P2MM CPUTHMSNS_D2_P CPUTHMSNS_D2_N CPU_THERMD_P CPU_THERMD_N GPUTHMSNS_D_P GPUTHMSNS_D_N GPU_TDIODE_P GPU_TDIODE_N (USB_EXTA) (USB_EXTA) (USB_EXTA) (USB_EXTA) 51 51 PCIE GND * GND_P2MM SATA GND * GND_P2MM SENSE_DIFFPAIR TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT 0.20 MM 1000 SENSE_1TO1_55S SENSE * SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM USB GND * SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE GND_P2MM TABLE_SPACING_RULE_ITEM PWR_P2MM * 0.20 MM 43 43 51 51 51 USB_85D USB USB_85D USB CONN_USB2_BT_P CONN_USB2_BT_N 33 33 USB_LT2_P USB_LT2_N 43 43 50 50 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_RULE_ITEM GND_P2MM CPUVTTISNS_R_N CPUVTTISNS_R_P USB2_LT1_P USB2_LT1_N 51 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM 43 43 SENSE_DIFFPAIR 1000 TABLE_SPACING_ASSIGNMENT_ITEM CLK_PCIE SB_POWER * PWR_P2MM SATA SB_POWER * PWR_P2MM CPUVTTS0_CS_N CPUVTTS0_CS_P DDRISNS_R_N DDRISNS_R_P 50 70 DP_85D DISPLAYPORT 50 70 DP_85D DISPLAYPORT DP_IG_AUX_CH_C_P DP_IG_AUX_CH_C_N 84 84 50 50 TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM USB TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK GND * GND_P2MM MEM_CMD GND * GND_P2MM SB_POWER * PWR_P2MM SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM C MEM_CTRL GND * GND_P2MM MEM_DATA GND * GND_P2MM SENSE_DIFFPAIR TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET TABLE_SPACING_ASSIGNMENT_ITEM MEM_DQS GND * SENSE_DIFFPAIR GND_P2MM TABLE_SPACING_ASSIGNMENT_ITEM LVDS GND * GND_P2MM SENSE_DIFFPAIR SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP SENSE_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM MEM_40S * OVERRIDE OVERRIDE 0.09 MM OVERRIDE OVERRIDE 100 MIL OVERRIDE OVERRIDE OVERRIDE I249 OVERRIDE SENSE_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM MEM_72D * OVERRIDE OVERRIDE PCIE_85D * OVERRIDE OVERRIDE I250 0.09 MM 100 MIL OVERRIDE OVERRIDE 0.09 MM 10 mm I251 OVERRIDE I253 OVERRIDE I252 OVERRIDE SENSE_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE SENSE_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM USB_85D TOP OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.1 MM 500 MIL OVERRIDE OVERRIDE I254 OVERRIDE I256 OVERRIDE SENSE_DIFFPAIR TABLE_PHYSICAL_RULE_ITEM CPU_27P4S BOTTOM OVERRIDE OVERRIDE OVERRIDE OVERRIDE 0.23 MM 100 MIL OVERRIDE OVERRIDE I255 OVERRIDE OVERRIDE I281 SENSE_DIFFPAIR I282 I283 SENSE_DIFFPAIR I284 I285 SENSE_DIFFPAIR I286 SENSE_DIFFPAIR SENSE_DIFFPAIR B I292 SENSE_DIFFPAIR I291 SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE SENSE_1TO1_55S SENSE GFXIMVP_CS_N GFXIMVP_CS_P GFXIMVP_CS_R_N GFXIMVP_CS_R_P GFX_ISNS_R_N GFX_ISNS_R_P GPUISENS_N GPUISENS_P ISNS_1V5_S3_N ISNS_1V5_S3_P ISNS_AIRPORT_N ISNS_AIRPORT_N ISNS_AIRPORT_P ISNS_AIRPORT_P ISNS_AIRPORT_R_N ISNS_AIRPORT_R_P ISNS_CPU_N ISNS_CPU_P ISNS_HDD_N ISNS_HDD_P ISNS_HDD_R_N ISNS_HDD_R_P ISNS_LCDBKLT_N ISNS_LCDBKLT_P ISNS_ODD_N ISNS_ODD_P ISNS_ODD_R_N ISNS_ODD_R_P ISNS_P1V8GPU_N ISNS_P1V8GPU_P ISNS_P1V8GPU_R_N ISNS_P1V8GPU_R_P 69 69 50 69 50 69 C 50 50 SPK_OUT 50 50 SPK_OUT 50 67 50 67 SPK_OUT 99 99 DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR DIFFPAIR AUDIO AUDIO AUDIO AUDIO AUDIO AUDIO SPKRCONN_L_OUT_P SPKRCONN_L_OUT_N SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N SPKRCONN_S_OUT_P SPKRCONN_S_OUT_N 61 62 61 62 61 62 61 62 61 62 61 62 99 99 56 56 49 49 USB_85D USB USB_85D USB USB_TPAD_R_P USB_TPAD_R_N 53 53 56 56 SB_POWER SB_POWER SB_POWER GND 56 PP3V3_S5 PP3V3_S0 PP1V5_S3RS0 17 18 19 20 21 23 27 31 35 57 66 71 72 73 83 85 50 51 52 17 18 19 20 21 23 24 25 26 27 28 30 34 37 40 42 46 47 48 54 58 62 13 16 31 42 72 7363 68 87 69 72 73 84 80 88 83 85 GND 56 50 50 B 50 50 Graphics ,SATA Constraint Relaxations Alternate diffpair width/gap through BGA fanout areas (95-ohm diff) TABLE_PHYSICAL_ASSIGNMENT_HEAD NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET LVDS_85D BGA LVDS_85D DP_85D BGA 100_DIFF_BGA SATA_90D BGA 100_DIFF_BGA CLK_PCIE_90D BGA 100_DIFF_BGA TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM TABLE_PHYSICAL_ASSIGNMENT_ITEM A Memory Constraint Relaxations SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 PAGE TITLE Allow 0.127 mm necks for >0.127 mm lines for ARD fanout Project Specific Constraints TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER MEM_72D BOTTOM ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH 0.127 MM 6.35 MM DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP DRAWING NUMBER TABLE_PHYSICAL_RULE_ITEM Apple Inc TABLE_PHYSICAL_RULE_ITEM TOP MEM_85D 0.1 MM R THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED 6.35 MM NOTICE OF PROPRIETARY PROPERTY: SIZE D REVISION BRANCH PAGE 108 OF 132 SHEET 99 OF 101 A K18 Board-Specific Spacing & Physical Constraints TABLE_BOARD_INFO BOARD LAYERS BOARD AREAS BOARD UNITS (MIL or MM) ALLEGRO VERSION TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM NO_TYPE,BGA MM 15.5.1 TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_HEAD SPACING_RULE_SET LAYER LINE-TO-LINE SPACING WEIGHT TABLE_PHYSICAL_RULE_ITEM DEFAULT * Y =50_OHM_SE =50_OHM_SE 10 MM MM MM DEFAULT * 0.1 MM * Y =DEFAULT =DEFAULT 10 MM =DEFAULT =DEFAULT NET_SPACING_TYPE2 AREA_TYPE SPACING_RULE_SET * * BGA BGA_P1MM TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_PHYSICAL_RULE_ITEM STANDARD TABLE_SPACING_ASSIGNMENT_HEAD NET_SPACING_TYPE1 TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM STANDARD * =DEFAULT ? BGA_P1MM * =DEFAULT ? TABLE_SPACING_ASSIGNMENT_ITEM MEM_CLK * BGA BGA_P2MM CLK_PCIE * BGA BGA_P2MM CLK_SLOW * BGA BGA_P2MM TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM TABLE_PHYSICAL_RULE_HEAD D PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 55_OHM_SE TOP,BOTTOM Y 0.090 MM 0.090 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM BGA_P2MM * =DEFAULT D TABLE_SPACING_ASSIGNMENT_ITEM ? TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 55_OHM_SE * Y 0.076 MM 0.076 MM =STANDARD =STANDARD TABLE_SPACING_RULE_HEAD SPACING_RULE_SET =STANDARD LINE-TO-LINE SPACING WEIGHT 1.5:1_SPACING LAYER * 0.15 MM ? 2:1_SPACING * 0.2 MM ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_HEAD LINE-TO-LINE SPACING WEIGHT 2X_DIELECTRIC SPACING_RULE_SET LAYER * 0.140 MM ? 3X_DIELECTRIC * 0.210 MM ? 4X_DIELECTRIC * 0.280 MM ? TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 50_OHM_SE TOP,BOTTOM Y 0.110 MM 0.095 MM 50_OHM_SE * Y 0.090 MM 0.090 MM TABLE_SPACING_RULE_ITEM 2.5:1_SPACING 0.25 MM * ? TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM =STANDARD =STANDARD =STANDARD TABLE_SPACING_RULE_ITEM 3:1_SPACING * 0.3 MM ? TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP 4:1_SPACING * 0.4 MM ? DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM 40_OHM_SE TOP,BOTTOM Y 0.165 MM 0.095 MM 40_OHM_SE * Y 0.135 MM 0.090 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 37_OHM_SE TOP,BOTTOM Y 0.185 MM 0.095 MM 37_OHM_SE * Y 0.155 MM 0.090 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 27P4_OHM_SE TOP,BOTTOM Y 0.310 MM 0.095 MM 27P4_OHM_SE * Y 0.250 MM 0.1 MM =STANDARD =STANDARD =STANDARD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM C C TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM 72_OHM_DIFF * N =STANDARD =STANDARD 72_OHM_DIFF ISL3,ISL4 Y 0.154 MM 0.154 MM 72_OHM_DIFF ISL9,ISL10 Y 0.154 MM 72_OHM_DIFF TOP,BOTTOM Y 0.175 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 85_OHM_DIFF * N =STANDARD =STANDARD 85_OHM_DIFF ISL3,ISL4 Y 0.110 MM 0.090 MM 85_OHM_DIFF ISL9,ISL10 Y 0.110 MM 85_OHM_DIFF TOP,BOTTOM Y PHYSICAL_RULE_SET LAYER 90_OHM_DIFF =STANDARD =STANDARD =STANDARD 0.200 MM 0.200 MM 0.154 MM 0.200 MM 0.200 MM 0.175 MM 0.200 MM 0.200 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =STANDARD =STANDARD =STANDARD 0.180 MM 0.180 MM 0.090 MM 0.180 MM 0.180 MM 0.125 MM 0.090 MM 0.190 MM 0.190 MM ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD 90_OHM_DIFF ISL3,ISL4 Y 0.102 MM 0.090 MM 0.220 MM 0.220 MM 90_OHM_DIFF ISL9,ISL10 Y 0.102 MM 0.090 MM 0.220 MM 0.220 MM 90_OHM_DIFF TOP,BOTTOM Y 0.115 MM 0.090 MM 0.230 MM 0.230 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP TABLE_PHYSICAL_RULE_ITEM 1:1_DIFFPAIR * Y =STANDARD =STANDARD 0.1 MM =STANDARD 0.1 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM B B TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_HEAD MAXIMUM NECK LENGTH TABLE_PHYSICAL_RULE_HEAD PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP 100_DIFF_BGA * =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF 100_DIFF_BGA ISL3,ISL4 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM 100_DIFF_BGA ISL9,ISL10 Y 0.075 MM 0.075 MM 0.125 MM 0.125 MM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF * N =STANDARD =STANDARD =STANDARD =STANDARD =STANDARD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF ISL3,ISL4 Y 0.080 MM 0.080 MM 0.200 MM 0.200 MM 100_OHM_DIFF ISL9,ISL10 Y 0.080 MM 0.080 MM 0.200 MM 0.200 MM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM 100_OHM_DIFF TOP,BOTTOM Y 0.089 MM 0.089 MM PHYSICAL_RULE_SET LAYER ALLOW ROUTE ON LAYER? MINIMUM LINE WIDTH MINIMUM NECK WIDTH 110_OHM_DIFF * N =STANDARD =STANDARD 110_OHM_DIFF ISL3,ISL4 Y 0.075 MM 110_OHM_DIFF ISL9,ISL10 Y 110_OHM_DIFF TOP,BOTTOM Y NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers 0.220 MM 0.220 MM MAXIMUM NECK LENGTH DIFFPAIR PRIMARY GAP DIFFPAIR NECK GAP =STANDARD =STANDARD =STANDARD 0.075 MM 0.330 MM 0.330 MM 0.075 MM 0.075 MM 0.330 MM 0.330 MM 0.075 MM 0.075 MM 0.330 MM 0.330 MM TABLE_PHYSICAL_RULE_HEAD TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM NOTE: 110_DIFF is 110-ohms differential impedance on outer layers and 105-ohms on inner layers TABLE_PHYSICAL_RULE_ITEM TABLE_PHYSICAL_RULE_ITEM A SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 PAGE TITLE PCB Rule Definitions DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE 109 OF 132 SHEET 100 OF 101 A D D 56 54 46 44 43 42 33 31 82 72 67 66 61 58 PP5V_S3 T57 T57 CD230 ZTD200 0.01uF STDOFF-3.6OD3.4H-SM 20% 16V CERM 402 T57 ZTD201 C C STDOFF-3.6OD3.4H-SM 36 35 34 33 32 31 20 17 87 73 72 55 54 53 50 48 PP3V3_S3 T57 T57 CRITICAL CD225 0.01uF JD201 20% 16V CERM 402 AXK720427G F-ST-SM 21 NC 93 19 93 19 BI BI USB_BRCRYPT_P USB_BRCRYPT_N 17 IN NC BRCRYPT_RESET 10 11 12 13 14 15 16 17 18 19 20 BRCRYPT_PWR_EN IN 17 NC NC NC NC 22 VBUS NC IO NC IO GND B B DD220 RCLAMP0502N SLP1210N6 CRITICAL T57 A SYNC_MASTER=K17_REF SYNC_DATE=06/15/2009 PAGE TITLE BluRay Decrypter Card Connector DRAWING NUMBER Apple Inc R NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC THE POSESSOR AGREES TO THE FOLLOWING: I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART IV ALL RIGHTS RESERVED SIZE D REVISION BRANCH PAGE 132 OF 132 SHEET 101 OF 101 A ... GMUXPLL_3V3,GPU_SS_INT,MIKEY,GPUVID_0P90V,DPMUX_EN_PLD,DP_CA_DET_EG_PLD,DP_ESD,VFRQ_SLPS3,SMC_OSC_YES,RAIL_MON K18_ PVT BMON_PROD,VREFMRGN_NOT,XDP,XDP_NORMAL,XDP_CPU_BPM K18_ PROGPARTS GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG TABLE_BOMGROUP_ITEM TABLE_BOMGROUP_ITEM... SYNC_MASTER =K18_ SENSORS MAKE_BASE=TRUE K18 SMBus Connections DRAWING NUMBER R5222 Apple Inc 5% NOTICE OF PROPRIETARY PROPERTY: THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE. .. TABLE_ALT_ITEM K18 BOM GROUPS TABLE_ALT_ITEM TABLE_BOMGROUP_HEAD BOM GROUP TABLE_ALT_ITEM BOM OPTIONS TABLE_BOMGROUP_ITEM K18_ COMMON TABLE_ALT_ITEM ALTERNATE,COMMON ,K18_ COMMON1 ,K18_ COMMON2 ,K18_ PROGPARTS,USBHUB_2061,RDRV:8515A2,DCI