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A B C D E 1 Compal confidential Liverpool 10AR/10ARG 2 KSWAE LA-4971P Schematics Document Mobile AMD S1G2 S1G3/ RS780MN & RS780MC & RX781 & RS880 / SB700 & SB710 3 2009-04-22 Rev 1.0 4 Compal Secret Data Security Classification 2008-09-25 Issued Date 2009-09-25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc Cover Sheet Size Document Number Custom Date: Rev 1.0 LA-4971P Wednesday, April 22, 2009 Sheet E of 45 A B C D l o r t n o C n a F r o s n e S l a m r e h T U P C G S D M A Compal Confidential E E A W T K / E A W S K : e m a N l e d o M M I T A P A L : e m a N e l i F uFCPGA-638 Package m r o f t a l P n i f f i r G z H G k n i L t r o p s n a r T r e p y H with VRAM page ADM1032ARMZ APL5607KI-TRG page page 4,5,6,7 X 1 X M M I D O S I I R D D n i p 0 n n o C M X M A G V I T A page 8,9 BANK 0, 1, 2, Z H ) M I I R D / Dl6 ( Se I UnI BnR hD ya r CD o l ma V e u MD1 Page 19 T R C RS780MN RS780MC n n o C D C L page 16 RX781 RS880 n n o C I M D H r e l o r t n o C C E C I M D H page 17 EC SMBUS page 18 R5F211A4SP page 18 PCIe 4x page 10,11,12,13,14 1.5V 2.5GHz(250MB/s) SB700 SB710 5V 480MHz USBPort page 32 USB 5x 3IN1 5V 1.5GHz(150MB/s) USBPort 5V 480MHz USBPort page 27 3IN1 USBPort page 29 page 29 SATA PCI BUS 3.3V 33 MHz SATA port page 25 D D O A T A S r e l l o r t n o C s u B d r a C page 27 D D H A T A S page 25 USB E 5 S T R A T A S e J R SATA USB port r e t n i r P r e g n i F 5V 480MHz page 27 N A L W PCIe port SATA port 5V 1.5GHz(150MB/s) SATA B / B S U r o t a r e n e G k c o l C OZ601 page 28 page 32 page 20,21,22,23,24 SATA port page 25 5V 1.5GHz(150MB/s) LPC BUS 3.3V 33 MHz B / r e w o P T K C C T R D B K E N E page 35 page 34 page 31 page 31 l o r t n o C e m u l o V TPA6017 page 31 N N O C P H C D / C D t i u c r i C r e w o P page 33 C I M t n I page 33 page 30 N N O C C I M page 33 R E I F I L P M A D B K t n I page 35 ALC272 1 J R d a P h c u o T page 35 page 33 M O R I P S r o s n e s G T K C e c a f r e t n I C D / C D page 36 3.3V 24.576MHz/48Mhz c e d o C A D H page 33 page 35 HD Audio C D M B / W S T K C f f O / n O r e w o P page 35 t r o P g u b e D page 37 page 31 page 31 N N O C K P S USBPort page 32 h t o o t e u l B I T A USB USB port 11 page 27 page 26 SLG8SP626VTR page 15 a r e m a C t n I n n o C B S U t h g i R I I s s e r p x E EI kC n i LP X A4 PCIe Port page 32 d r a C W E N N A L W d r a C i n i M e I C P M 0 / N A L L E L T R page 26 PCIe port USB Port 0,1 page 37,38,39,40 41,42,43,44 page 31 Compal Secret Data Security Classification 2008-09-25 Issued Date 2009-09-25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc Block Diagram Size Document Number Custom Date: Rev 1.0 LA-4971P Wednesday, April 22, 2009 Sheet E of 45 A B C D E Symbol Note : Voltage Rails Platform : Digital Ground O : ON X : OFF Item PUMA@ : Analog Ground CPU NB VGA SB Comment GM@ S1G2 RS780MC NA SB700 GM@ S1G2 RS780MN NA SB700 PM@+GPM@ S1G2 RS780MN MXM SB700 PM@+PM1@ S1G2 RX781 MXM SB700 +5VS +3VS power plane @ : just reserve , no build +2.5VS +1.5VS State +B +5VALW +1.8V +3VL +3VALW +0.9V +5VL +1.2VALW +0.9V +RTCVCC +3V_LAN L +1.1VS Item Platform DEBUG@ : reserve for debug +1.8VS Layout Notes TIGRIS@ UMA@: means for RS780M +VGA_CORE CPU NB VGA SB Comment GM@ S1G3 RS880MC NA SB710 GM@ S1G3 RS880M NA SB710 PM@+GPM@ S1G3 RS880M MXM SB710 PM@+PM1@ S1G3 RX881 MXM SB710 +1.2V_HT BTO (Build-To-Order) +CPU_CORE_NB +CPU_CORE_0 Function +CPU_CORE_1 Option Table Express card / PCMCIA BLUE TOOTH RJ11 SSD (E/A) (B) (R) (S) MDC@ SSD@ Description Explain SATA ODD 16" S0 O O O O BTO EXPCARD@ / PCMCIA@ S1 O O O O Function FingerPrinter CAMERA & MIC HDMI S3 O O O X Description (F) (X) (Y) BT@ WiFi G- sensor in card reader (H) 17" 16inch@ Half - size 17inch@ WLAN@ First WIMAX@ Second G@ + G_1st@ DC-IN LVDS wireset RTS5159 G@ + G_2nd@ CARD@ CHIPSET 2 S5 S4/AC O O X X S5 S4/ Battery only O X X X S5 S4/AC & Battery don't exist X X X X Explain BTO FP@ CAMERA MIC AMD(UMA) ATI VGA/B COMMON Cost down CAM@ MIC@ IHDMI@ HDMI@ H@ LVDSSET@ INVERTER BATT HDMI CEC CPU THERMAL SENSOR EC_SMB_CK1 EC_SMB_DA1 I2C / SMBUS ADDRESSING EC_SMB_CK2 EC_SMB_DA2 DEVICE HEX ADDRESS DDR SO-DIMM A0 10100000 I2C_DATA DDR SO-DIMM A4 10100100 DDC_CLK0 CLOCK GENERATOR (EXT.) D2 11010010 DDC_DATA0 I2C_CLK DDC_CLK1 DDC_DATA1 SCL0 HEX Address Smart Battery 16H 0001 011X b HDMI-CEC 34H 0011 010X b SCL1 V SODIMM I / II TIGRIS@ SDA1 CLK GEN WLAN LCD DDC ROM HDMI DDC ROM NEW CARD MXM Thermal Sensor V KB926 V V RS780M V RS780M V RS780M V SB700 SCL2 V V V SB700 SDA2 SCL3 EC KB926D2 KB926 SB700 SDA0 EC SM Bus1 address Device PUMA@ SMBUS Control Table SOURCE 16inch_45@ 17inch_45@ SB700 SDA3 EC SM Bus2 address Device HEX Address ADI1032-1 CPU 98H 1001 100X b ADI1032-2 VGA 9AH 1001 101X b Compal Secret Data Security Classification EC KB926D2 2008-09-25 Issued Date Ext VGA/B 2009-09-25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC CS/B A B C D Title Compal Electronics, Inc Notes List Size Document Number Custom Date: Rev 1.0 LA-4971P Wednesday, April 22, 2009 Sheet E of 45 A B C D E < C1, C2 and C7 must be replaced to 10-uF for Caspian compatibility > +1.2V_HT VLDT CAP Near CPU Socket 250 mil PUMA@ C1 4.7U_0805_10V4Z TIGRIS@ C1 10U_0805_10V6K PUMA@ C2 4.7U_0805_10V4Z TIGRIS@ C2 10U_0805_10V6K C3 0.22U_0603_16V4Z C4 0.22U_0603_16V4Z C5 180P_0402_50V8J C6 180P_0402_50V8J 1 10 H_CADIP[0 15] 10 H_CADIN[0 15] H_CADIP[0 15] H_CADOP[0 15] H_CADIN[0 15] H_CADON[0 15] +1.2V_HT VLDT=500mA H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15 < From NB > H_CADOP[0 15] 10 H_CADON[0 15] 10 JCPUA D1 D2 D3 D4 E3 E2 E1 F1 G3 G2 G1 H1 J1 K1 L3 L2 L1 M1 N3 N2 E5 F5 F3 F4 G5 H5 H3 H4 K3 K4 L5 M5 M3 M4 N5 P5 10 10 10 10 H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1 J3 J2 J5 K5 10 10 10 10 H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1 N1 P1 P3 P4 @ HT LINK VLDT_A0 VLDT_A1 VLDT_A2 VLDT_A3 L0_CADIN_H0 L0_CADIN_L0 L0_CADIN_H1 L0_CADIN_L1 L0_CADIN_H2 L0_CADIN_L2 L0_CADIN_H3 L0_CADIN_L3 L0_CADIN_H4 L0_CADIN_L4 L0_CADIN_H5 L0_CADIN_L5 L0_CADIN_H6 L0_CADIN_L6 L0_CADIN_H7 L0_CADIN_L7 L0_CADIN_H8 L0_CADIN_L8 L0_CADIN_H9 L0_CADIN_L9 L0_CADIN_H10 L0_CADIN_L10 L0_CADIN_H11 L0_CADIN_L11 L0_CADIN_H12 L0_CADIN_L12 L0_CADIN_H13 L0_CADIN_L13 L0_CADIN_H14 L0_CADIN_L14 L0_CADIN_H15 L0_CADIN_L15 VLDT_B0 VLDT_B1 VLDT_B2 VLDT_B3 L0_CADOUT_H0 L0_CADOUT_L0 L0_CADOUT_H1 L0_CADOUT_L1 L0_CADOUT_H2 L0_CADOUT_L2 L0_CADOUT_H3 L0_CADOUT_L3 L0_CADOUT_H4 L0_CADOUT_L4 L0_CADOUT_H5 L0_CADOUT_L5 L0_CADOUT_H6 L0_CADOUT_L6 L0_CADOUT_H7 L0_CADOUT_L7 L0_CADOUT_H8 L0_CADOUT_L8 L0_CADOUT_H9 L0_CADOUT_L9 L0_CADOUT_H10 L0_CADOUT_L10 L0_CADOUT_H11 L0_CADOUT_L11 L0_CADOUT_H12 L0_CADOUT_L12 L0_CADOUT_H13 L0_CADOUT_L13 L0_CADOUT_H14 L0_CADOUT_L14 L0_CADOUT_H15 L0_CADOUT_L15 L0_CLKIN_H0 L0_CLKIN_L0 L0_CLKIN_H1 L0_CLKIN_L1 L0_CLKOUT_H0 L0_CLKOUT_L0 L0_CLKOUT_H1 L0_CLKOUT_L1 L0_CTLIN_H0 L0_CTLIN_L0 L0_CTLIN_H1 L0_CTLIN_L1 L0_CTLOUT_H0 L0_CTLOUT_L0 L0_CTLOUT_H1 L0_CTLOUT_L1 +VLDT_B AE2 AE3 AE4 AE5 < VLDT_A & VLDT_B : HyperTransport I/O ring power > TIGRIS@ C7 10U_0805_10V6K H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15 AD1 AC1 AC2 AC3 AB1 AA1 AA2 AA3 W2 W3 V1 U1 U2 U3 T1 R1 AD4 AD3 AD5 AC5 AB4 AB3 AB5 AA5 Y5 W5 V4 V3 V5 U5 T4 T3 PUMA@ C7 4.7U_0805_10V4Z < To NB > Y1 W1 Y4 Y3 H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1 10 10 10 10 R2 R3 T5 R5 H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1 10 10 10 10 FOX_PZ63823-284S-41F_638P < FAN Control Circuit : Vout = 1.6 x Vset > +5VS 1A D1 < From EC > 34 EN_DFAN1 @ 1SS355_SOD323-2 10U_0805_10V4Z U6 EN VIN VOUT VSET D2 GND GND GND GND @ +3VS JFAN +FAN1 C9 @ BAS16_SOT23-3 1 1000P_0402_25V8J 2 10U_0805_10V4Z C192 R12 GND GND 10K_0402_5% @ ACES_85204-0300N_3P C183 +FAN1 FAN_SPEED1 34 APL5607KI-TRG_SO8 < To EC > C8 @ Compal Secret Data Security Classification 2008-09-25 Issued Date 0.01U_0402_25V7K 2009-09-25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc AMD CPU S1G2 HT I/F Size Document Number Custom Date: Rev 1.0 LA-4971P Wednesday, April 22, 2009 Sheet E of 45 A +1.8V B < DDR2 VREF is 0.5 ratio > C D E < PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH > DDR_A_CLK0 DDR_B_CLK0 < Processor DDR2 Memory Interface > C10 C14 R1 DDR_A_CLK#0 1K_0402_1% 1.5P_0402_50V9C C12 0.1U_0402_16V7K DDR_A_CLK1 C13 DDR_B_CLK1 1 C11 C15 1000P_0402_25V8J DDR_A_CLK#1 1.5P_0402_50V9C DDR_B_CLK#1 +0.9V 1.5P_0402_50V9C +0.9V JCPUB Place them close to CPU within 1" +1.8V R4 R3 39.2_0402_1% 39.2_0402_1% T2 < To SO_DIMMA > DDR_CS0_DIMMA# DDR_CS1_DIMMA# < To SO_DIMMA > DDR_CKE0_DIMMA DDR_CKE1_DIMMA < To SO_DIMMA > DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_A_MA[15 0] < To SO_DIMMA > < To SO_DIMMA > DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# AF10 AE10 H16 PAD DDR_A_ODT0 DDR_A_ODT1 < To SO_DIMMA > < To SO_DIMMA > MEM_P MEM_N D10 C10 B10 AD10 DDR_A_ODT0 DDR_A_ODT1 T19 V22 U21 V19 DDR_CS0_DIMMA# T20 DDR_CS1_DIMMA# U19 U20 V20 DDR_CKE0_DIMMA J22 DDR_CKE1_DIMMA J20 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 N19 N20 E16 F16 Y16 AA16 P19 P20 DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 N21 M20 N22 M19 M22 L20 M24 L21 L19 K22 R21 L22 K20 V24 K24 K19 DDR_A_BS#0 DDR_A_BS#1 DDR_A_BS#2 R20 R23 J21 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# R19 T22 T24 @ VTT1 VTT2 VTT3 VTT4 MEM:CMD/CTRL/CLK VTT5 VTT6 VTT7 VTT8 VTT9 MEMZP MEMZN VTT_SENSE RSVD_M1 MEMVREF MA0_ODT0 MA0_ODT1 MA1_ODT0 MA1_ODT1 RSVD_M2 MA0_CS_L0 MA0_CS_L1 MA1_CS_L0 MA1_CS_L1 MA_CKE0 MA_CKE1 MB0_ODT0 MB0_ODT1 MB1_ODT0 MB0_CS_L0 MB0_CS_L1 MB1_CS_L0 MB_CKE0 MB_CKE1 MA_CLK_H0 MA_CLK_L0 MA_CLK_H1 MA_CLK_L1 MA_CLK_H2 MA_CLK_L2 MA_CLK_H3 MA_CLK_L3 MB_CLK_H0 MB_CLK_L0 MB_CLK_H1 MB_CLK_L1 MB_CLK_H2 MB_CLK_L2 MB_CLK_H3 MB_CLK_L3 MA_ADD0 MA_ADD1 MA_ADD2 MA_ADD3 MA_ADD4 MA_ADD5 MA_ADD6 MA_ADD7 MA_ADD8 MA_ADD9 MA_ADD10 MA_ADD11 MA_ADD12 MA_ADD13 MA_ADD14 MA_ADD15 MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15 MA_BANK0 MA_BANK1 MA_BANK2 MB_BANK0 MB_BANK1 MB_BANK2 MA_RAS_L MA_CAS_L MA_WE_L MB_RAS_L MB_CAS_L MB_WE_L W10 AC10 AB10 AA10 A10 < VTT regulator voltage > Y10 VTT_SENSE W17 +MCH_REF B18 W26 W23 Y26 DDR_B_ODT0 DDR_B_ODT1 V26 W25 U22 DDR_CS0_DIMMB# DDR_CS1_DIMMB# J25 H26 DDR_CKE0_DIMMB DDR_CKE1_DIMMB P22 R22 A17 A18 AF18 AF17 R26 R25 DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1 P24 N24 P26 N23 N26 L23 N25 L24 M26 K26 T26 L26 L25 W24 J23 J24 DDR_B_MA0 DDR_B_MA1 DDR_B_MA2 DDR_B_MA3 DDR_B_MA4 DDR_B_MA5 DDR_B_MA6 DDR_B_MA7 DDR_B_MA8 DDR_B_MA9 DDR_B_MA10 DDR_B_MA11 DDR_B_MA12 DDR_B_MA13 DDR_B_MA14 DDR_B_MA15 R24 U26 J26 DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2 U25 U24 U23 DDR_B_RAS# DDR_B_CAS# DDR_B_WE# JCPUC DDR_B_D[63 0] < From/To SO_DIMMB > 1K_0402_1% DDR_B_CLK#0 +MCH_REF R2 1.5P_0402_50V9C PAD T1 PAD T3 DDR_B_ODT0 DDR_B_ODT1 < To SO_DIMMB > DDR_CS0_DIMMB# DDR_CS1_DIMMB# 8 < To SO_DIMMB > DDR_CKE0_DIMMB DDR_CKE1_DIMMB 8 < To SO_DIMMB > DDR_B_CLK0 DDR_B_CLK#0 DDR_B_CLK1 DDR_B_CLK#1 < To SO_DIMMB > DDR_B_DM[7 0] DDR_B_MA[15 0] < To SO_DIMMB > DDR_B_BS#0 DDR_B_BS#1 DDR_B_BS#2 < To SO_DIMMB > DDR_B_RAS# DDR_B_CAS# DDR_B_WE# < To SO_DIMMB > < To SO_DIMMB > 8 8 8 8 8 8 8 8 DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7 MEM:DATA DDR_B_D0 DDR_B_D1 DDR_B_D2 DDR_B_D3 DDR_B_D4 DDR_B_D5 DDR_B_D6 DDR_B_D7 DDR_B_D8 DDR_B_D9 DDR_B_D10 DDR_B_D11 DDR_B_D12 DDR_B_D13 DDR_B_D14 DDR_B_D15 DDR_B_D16 DDR_B_D17 DDR_B_D18 DDR_B_D19 DDR_B_D20 DDR_B_D21 DDR_B_D22 DDR_B_D23 DDR_B_D24 DDR_B_D25 DDR_B_D26 DDR_B_D27 DDR_B_D28 DDR_B_D29 DDR_B_D30 DDR_B_D31 DDR_B_D32 DDR_B_D33 DDR_B_D34 DDR_B_D35 DDR_B_D36 DDR_B_D37 DDR_B_D38 DDR_B_D39 DDR_B_D40 DDR_B_D41 DDR_B_D42 DDR_B_D43 DDR_B_D44 DDR_B_D45 DDR_B_D46 DDR_B_D47 DDR_B_D48 DDR_B_D49 DDR_B_D50 DDR_B_D51 DDR_B_D52 DDR_B_D53 DDR_B_D54 DDR_B_D55 DDR_B_D56 DDR_B_D57 DDR_B_D58 DDR_B_D59 DDR_B_D60 DDR_B_D61 DDR_B_D62 DDR_B_D63 C11 A11 A14 B14 G11 E11 D12 A13 A15 A16 A19 A20 C14 D14 C18 D18 D20 A21 D24 C25 B20 C20 B24 C24 E23 E24 G25 G26 C26 D26 G23 G24 AA24 AA23 AD24 AE24 AA26 AA25 AD26 AE25 AC22 AD22 AE20 AF20 AF24 AF23 AC20 AD20 AD18 AE18 AC14 AD14 AF19 AC18 AF16 AF15 AF13 AC12 AB11 Y11 AE14 AF14 AF11 AD11 DDR_B_DM0 DDR_B_DM1 DDR_B_DM2 DDR_B_DM3 DDR_B_DM4 DDR_B_DM5 DDR_B_DM6 DDR_B_DM7 A12 B16 A22 E25 AB26 AE22 AC16 AD12 DDR_B_DQS0 DDR_B_DQS#0 DDR_B_DQS1 DDR_B_DQS#1 DDR_B_DQS2 DDR_B_DQS#2 DDR_B_DQS3 DDR_B_DQS#3 DDR_B_DQS4 DDR_B_DQS#4 DDR_B_DQS5 DDR_B_DQS#5 DDR_B_DQS6 DDR_B_DQS#6 DDR_B_DQS7 DDR_B_DQS#7 C12 B12 D16 C16 A24 A23 F26 E26 AC25 AC26 AF21 AF22 AE16 AD16 AF12 AE12 < From/To SO_DIMMB > @ MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63 MA_DATA0 MA_DATA1 MA_DATA2 MA_DATA3 MA_DATA4 MA_DATA5 MA_DATA6 MA_DATA7 MA_DATA8 MA_DATA9 MA_DATA10 MA_DATA11 MA_DATA12 MA_DATA13 MA_DATA14 MA_DATA15 MA_DATA16 MA_DATA17 MA_DATA18 MA_DATA19 MA_DATA20 MA_DATA21 MA_DATA22 MA_DATA23 MA_DATA24 MA_DATA25 MA_DATA26 MA_DATA27 MA_DATA28 MA_DATA29 MA_DATA30 MA_DATA31 MA_DATA32 MA_DATA33 MA_DATA34 MA_DATA35 MA_DATA36 MA_DATA37 MA_DATA38 MA_DATA39 MA_DATA40 MA_DATA41 MA_DATA42 MA_DATA43 MA_DATA44 MA_DATA45 MA_DATA46 MA_DATA47 MA_DATA48 MA_DATA49 MA_DATA50 MA_DATA51 MA_DATA52 MA_DATA53 MA_DATA54 MA_DATA55 MA_DATA56 MA_DATA57 MA_DATA58 MA_DATA59 MA_DATA60 MA_DATA61 MA_DATA62 MA_DATA63 MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7 MA_DM0 MA_DM1 MA_DM2 MA_DM3 MA_DM4 MA_DM5 MA_DM6 MA_DM7 MB_DQS_H0 MB_DQS_L0 MB_DQS_H1 MB_DQS_L1 MB_DQS_H2 MB_DQS_L2 MB_DQS_H3 MB_DQS_L3 MB_DQS_H4 MB_DQS_L4 MB_DQS_H5 MB_DQS_L5 MB_DQS_H6 MB_DQS_L6 MB_DQS_H7 MB_DQS_L7 MA_DQS_H0 MA_DQS_L0 MA_DQS_H1 MA_DQS_L1 MA_DQS_H2 MA_DQS_L2 MA_DQS_H3 MA_DQS_L3 MA_DQS_H4 MA_DQS_L4 MA_DQS_H5 MA_DQS_L5 MA_DQS_H6 MA_DQS_L6 MA_DQS_H7 MA_DQS_L7 DDR_A_D[63 0] G12 F12 H14 G14 H11 H12 C13 E13 H15 E15 E17 H17 E14 F14 C17 G17 G18 C19 D22 E20 E18 F18 B22 C23 F20 F22 H24 J19 E21 E22 H20 H22 Y24 AB24 AB22 AA21 W22 W21 Y22 AA22 Y20 AA20 AA18 AB18 AB21 AD21 AD19 Y18 AD17 W16 W14 Y14 Y17 AB17 AB15 AD15 AB13 AD13 Y12 W11 AB14 AA14 AB12 AA12 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 E12 C15 E19 F24 AC24 Y19 AB16 Y13 DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 G13 H13 G16 G15 C22 C21 G22 G21 AD23 AC23 AB19 AB20 Y15 W15 W12 W13 DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7 < From/To SO_DIMMA > DDR_A_DM[7 0] < To SO_DIMMA > DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7 9 9 9 9 9 9 9 9 < From/To SO_DIMMA > FOX_PZ63823-284S-41F_638P FOX_PZ63823-284S-41F_638P 4 Compal Secret Data Security Classification 2008-09-25 Issued Date 2009-09-25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc AMD CPU S1G2 DDRII I/F Size Document Number Custom Date: Rev 1.0 LA-4971P Wednesday, April 22, 2009 Sheet E of 45 A B C D E JCPUD < Differential feedback for VDDNB > < Close to CPU > +CPU_CORE_0 1 R487 10_0402_5% R486 10_0402_5% CPU_VDD0_RUN_FB_L R484 10_0402_5% CPU_VDDNB_RUN_FB_H R485 10_0402_5% CPU_VDDNB_RUN_FB_L Un-Mount R489 For Caspian +CPU_CORE_1 PUMA@ R489 10_0402_5% PUMA@ R488 10_0402_5% +2.5VDDA F8 F9 CPU_CLKIN_SC_P CPU_CLKIN_SC_N A9 A8 LDT_RST# H_PWRGD LDT_STOP# CPU_LDT_REQ_R# B7 A7 F10 C6 Close to CPU +VDDNB CPU_VDD0_RUN_FB_H < Sideband-Temperature Sensor Interface Clock & Data> CPU_VDD1_RUN_FB_H CPU_VDD1_RUN_FB_L AF4 AF5 AE6 < Sideband-Temperature Sensor Interface interrupt > R13 R14 < Compensation Resistor to VSS > < Compensation Resistor to VLDT > +1.2V_HT CPU_HTREF0 CPU_HTREF1 R6 P6 43 CPU_VDD0_RUN_FB_H 43 CPU_VDD0_RUN_FB_L CPU_VDD0_RUN_FB_H CPU_VDD0_RUN_FB_L F6 E6 43 CPU_VDD1_RUN_FB_H 43 CPU_VDD1_RUN_FB_L CPU_VDD1_RUN_FB_H CPU_VDD1_RUN_FB_L Y6 AB6 44.2_0402_1% 44.2_0402_1% 1 Change R488 to 10K For Caspian < Debug ready > < 200-MHz PLL Reference Clock > C20 3900P_0402_50V7K < JTAG debug port > CPU_CLKIN_SC_P T9 T10 T11 T12 T19 G10 AA9 AC9 AD9 AF9 PAD PAD PAD PAD PAD 15 CLK_CPU_BCLK CPU_TEST23_TSTUPD AD7 R8 H10 G9 C21 3900P_0402_50V7K 15 CLK_CPU_BCLK# Address:100_1100 169_0402_1% CPU_TEST25_H_BYPASSCLK_H CPU_TEST25_L_BYPASSCLK_L CPU_CLKIN_SC_N CPU_TEST21_SCANEN CPU_TEST20_SCANCLK2 CPU_TEST24_SCANCLK1 Place close to CPU wihtin 1.5" < Filtered PLL Supply Voltage > +2.5VS +2.5VDDA VDDA=300mA L1 FBM_L11_201209_300L_0805 1 C17 C18 @ R25 0_0402_5% C2 AA6 +2.5VDDA A3 A5 B3 B5 C1 C19 + C16 2 100U_D2_6.3VM 4.7U_0805_10V4Z 3300P_0402_50V7K E9 E8 AB8 AF7 AE7 AE8 AC8 AF8 0.22U_0603_16V4Z @ < Serial VID Interface clock & data > +1.8VS Add R497 and R498 at PVT VDDA1 VDDA2 RESET_L PWROK LDTSTOP_L LDTREQ_L M11 W18 KEY1 KEY2 CLKIN_H CLKIN_L CPU_SVC 43 CPU_SVD 43 AF6 CPU_THERMTRIP#_R AC7 CPU_PROCHOT#_1.8 AA8 R42 300_0402_5% THERMTRIP_L PROCHOT_L MEMHOT_L SIC SID ALERT_L CPU_SVC CPU_SVD A6 A4 SVC SVD < Thermal Sensor Trip output > < HTC-active state indication or command > +1.8V THERMDC_CPU THERMDA_CPU W7 W8 THERMDC THERMDA < Serial VID Interface clock & data > HT_REF0 HT_REF1 < Thermal diode cathode & anode > +1.8V sense no support VDD0_FB_H VDD0_FB_L W9 Y9 VDDIO_FB_H VDDIO_FB_L VDD1_FB_H VDD1_FB_L VDDNB_FB_H VDDNB_FB_L DBRDY TMS TCK TRST_L TDI DBREQ_L TEST28_H TEST28_L TEST18 TEST19 TEST17 TEST16 TEST15 TEST14 TEST25_H TEST25_L TEST21 TEST20 TEST24 TEST22 TEST12 TEST27 CPU_DBREQ# 43 43 < Differential feedback for VDDIO > < VDDIO : DDR SDRAM I/O ring power supply> < Differential feedback for VDDNB > < Northbridge power supply > < Debug request > PAD T20 J7 H8 CPU_TEST28_H_PLLCHRZ_P CPU_TEST28_L_PLLCHRZ_N D7 E7 F7 C7 CPU_TEST17_BP3 CPU_TEST16_BP2 CPU_TEST10_ANALOGOUT PAD PAD T5 T6 PAD PAD T7 T8 route as differential as short as possible testpoint under package @ R32 300_0402_5% +1.2V_HT Add R32 at PVT CPU_TEST29_H_FBCLKOUT_P CPU_TEST29_L_FBCLKOUT_N C9 C8 TEST29_H TEST29_L T22 T21 CPU_VDDNB_RUN_FB_H CPU_VDDNB_RUN_FB_L C4 TEST8 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 E10 C3 K8 TEST7 TEST10 TEST9 TEST6 CPU_VDDNB_RUN_FB_H CPU_VDDNB_RUN_FB_L AE9 TDO TEST23 PAD PAD H6 G6 PAD PAD T13 T14 H18 H19 AA7 D5 C5 RSVD10 RSVD9 RSVD8 RSVD7 RSVD6 FOX_PZ63823-284S-41F_638P +1.8V 0718 AMD > 1K ohm R22 1K_0402_5% CPU_SVC TIGRIS@ R497 510_0402_5% CPU_TEST25_H_BYPASSCLK_H @ R498 510_0402_5% R23 1K_0402_5% CPU_SVD @ R499 510_0402_5% CPU_TEST25_L_BYPASSCLK_L TIGRIS@ R500 510_0402_5% +1.8VS +1.8V R15 R10 10K_0402_5% 20 LDT_RST# LDT_RST# E R5 300_0402_5% CPU_THERMTRIP#_R @ D16 CH751H-40PT_SOD323-2 < To SB700 ACPI block> ENTRIP2 EN0 38,40 < HDT Connector > 37,40 @ R11 0_0402_5% 1 1 2 2 11,20 LDT_STOP# 0.1U_0402_16V7K +1.8V @ 0.01U_0402_25V7K 1 @ 0.01U_0402_25V7K 2 TIGRIS@ R31 300_0402_5% TIGRIS@ R29 300_0402_5% U2 CPU_TEST20_SCANCLK2 C26 0.1U_0402_16V7K 1 THERMDA_CPU THERMDC_CPU C27 2200P_0402_50V7K CPU_TEST23_TSTUPD CPU_LDT_REQ_R# R26 300_0402_5% R28 300_0402_5% B SCLK D+ SDATA D- ALERT# THERM# GND EC_SMB_CK2 EC_SMB_DA2 EC_SMB_CK2 19,34,35 EC_SMB_DA2 19,34,35 ADM1032ARM-1 ZREEL_MSOP8 CPU_TEST21_SCANEN Compal Secret Data Security Classification Un-Mount R27 For Caspian < From EC > VDD CPU_TEST24_SCANCLK1 2008-09-25 Issued Date 2009-09-25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A SAMTEC_ASP-68200-07 < Thermal Sensor > +3VS Add R29 and R31 at PVT C24 CPU_LDT_REQ# LDT_RST# NOTE: HDT TERMINATION IS REQUIRED FOR REV Ax SILICON ONLY < noise filter cap > PUMA@ R27 0_0402_5% 10 12 14 16 18 20 22 24 26 C25 R30 300_0402_5% 11 13 15 17 19 21 23 R494 0_0402_5% 220_0402_5% 220_0402_5% 220_0402_5% 220_0402_5% LDT_STOP# +1.8VS 11,20 CPU_LDT_REQ# 300_0402_5% H_PWRGD C23 R40 R39 R38 R37 @ H_PROCHOT# 20 @ 2 300_0402_5% @ @ @ @ +1.8V T24 PAD < To SB700 CPU block> R41 +1.8V T23 PAD H_THERMTRIP# 21 R9 300_0402_5% CPU_PROCHOT#_1.8 JP3 < R41 Close to CPU > < R494 Close to CPU > CPU_DBREQ# R36 300_0402_5% 1 +1.8V 2 +1.8VS R21 < To power circuitry> @ D20 CH751H-40PT_SOD323-2 MMBT3904_NL_SOT23-3 0.01U_0402_25V7K +1.8VS 20,43 H_PWRGD @ D12 CH751H-40PT_SOD323-2 < To power circuitry> Q3 C C22 B 300_0402_5% 2 C D Title Compal Electronics, Inc AMD CPU S1G2 CTRL Size Document Number Custom Date: Rev 1.0 LA-4971P Wednesday, April 22, 2009 Sheet E of 45 A B C D E +CPU_CORE_0 JCPUE VDD decoupling : +CPU_CORE +CPU_CORE_0 +CPU_CORE_0 1 + 330U_X_2VM_R6M + C30 +CPU_CORE_0 C32 C33 C34 C35 C40 C41 C42 C28 330U_X_2VM_R6M Near CPU Socket 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M Under CPU Socket 0.22U_0603_16V4Z 0.01U_0402_25V7K 180P_0402_50V8J Under CPU Socket +CPU_CORE_1 +CPU_CORE_1 1 + 330U_X_2VM_R6M + C31 +CPU_CORE_1 C36 C37 C38 C39 C43 C44 C45 C29 330U_X_2VM_R6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M Under CPU Socket Near CPU Socket 0.22U_0603_16V4Z 0.01U_0402_25V7K 180P_0402_50V8J +VDDNB Under CPU Socket +1.8V VDDIO decoupling : DDR SDRAM I/O ring power C46 22U_0805_6.3V6M C47 22U_0805_6.3V6M C48 0.22U_0603_16V4Z C49 0.22U_0603_16V4Z C50 180P_0402_50V8J K16 M16 P16 T16 V16 H25 J17 K18 K21 K23 K25 L17 M18 M21 M23 M25 N17 +1.8V G4 H2 J9 J11 J13 J15 K6 K10 K12 K14 L4 L7 L9 L11 L13 L15 M2 M6 M8 M10 N7 N9 N11 C51 180P_0402_50V8J Under CPU Socket +1.8V @ 1 C55 C56 C57 VDD0_1 VDD0_2 VDD0_3 VDD0_4 VDD0_5 VDD0_6 VDD0_7 VDD0_8 VDD0_9 VDD0_10 VDD0_11 VDD0_12 VDD0_13 VDD0_14 VDD0_15 VDD0_16 VDD0_17 VDD0_18 VDD0_19 VDD0_20 VDD0_21 VDD0_22 VDD0_23 VDDNB_1 VDDNB_2 VDDNB_3 VDDNB_4 VDDNB_5 VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 +CPU_CORE_1 VDD1_1 VDD1_2 VDD1_3 VDD1_4 VDD1_5 VDD1_6 VDD1_7 VDD1_8 VDD1_9 VDD1_10 VDD1_11 VDD1_12 VDD1_13 VDD1_14 VDD1_15 VDD1_16 VDD1_17 VDD1_18 VDD1_19 VDD1_20 VDD1_21 VDD1_22 VDD1_23 VDD1_24 VDD1_25 VDD1_26 VDDIO27 VDDIO26 VDDIO25 VDDIO24 VDDIO23 VDDIO22 VDDIO21 VDDIO20 VDDIO19 VDDIO18 VDDIO17 VDDIO16 VDDIO15 VDDIO14 VDDIO13 P8 P10 R4 R7 R9 R11 T2 T6 T8 T10 T12 T14 U7 U9 U11 U13 U15 V6 V8 V10 V12 V14 W4 Y2 AC4 AD2 +1.8V Y25 V25 V23 V21 V18 U17 T25 T23 T21 T18 R17 P25 P23 P21 P18 FOX_PZ63823-284S-41F_638P Athlon 64 S1 Processor Socket C58 JCPUF 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z 0.22U_0603_16V4Z AA4 AA11 AA13 AA15 AA17 AA19 AB2 AB7 AB9 AB23 AB25 AC11 AC13 AC15 AC17 AC19 AC21 AD6 AD8 AD25 AE11 AE13 AE15 AE17 AE19 AE21 AE23 B4 B6 B8 B9 B11 B13 B15 B17 B19 B21 B23 B25 D6 D8 D9 D11 D13 D15 D17 D19 D21 D23 D25 E4 F2 F11 F13 F15 F17 F19 F21 F23 F25 H7 H9 H21 H23 J4 Between CPU Socket and DIMM +1.8V C60 0.01U_0402_25V7K C61 0.01U_0402_25V7K Between CPU Socket and DIMM +1.8V 180PF Qt'y follow the distance between CPU socket and DIMM0 C62 180P_0402_50V8J C63 180P_0402_50V8J C64 180P_0402_50V8J C65 180P_0402_50V8J Between CPU Socket and DIMM +1.8V Change to B2 size 1 C74 4.7U_0805_10V4Z C75 4.7U_0805_10V4Z C76 4.7U_0805_10V4Z C77 @ 4.7U_0805_10V4Z + C78 220U_B2_4VM_R45M Between CPU Socket and DIMM +0.9V VTT decoupling 1 C66 4.7U_0805_10V4Z C67 4.7U_0805_10V4Z C68 0.22U_0603_16V4Z C69 0.22U_0603_16V4Z C70 1000P_0402_25V8J C71 1000P_0402_25V8J C72 180P_0402_50V8J C73 180P_0402_50V8J Near CPU Socket Right side +0.9V Near Power Supply Change to B2 size +0.9V + C59 220U_B2_4VM_R45M C79 4.7U_0805_10V4Z C80 4.7U_0805_10V4Z C81 0.22U_0603_16V4Z C82 0.22U_0603_16V4Z C83 1000P_0402_25V8J 2 C84 1000P_0402_25V8J C85 180P_0402_50V8J C86 180P_0402_50V8J 2 Near CPU Socket Left side +VDDNB decoupling : Northbridge power +VDDNB @ C52 22U_0805_6.3V6M TIGRIS@ C54 C53 22U_0805_6.3V6M 2008-09-25 Issued Date FOX_PZ63823-284S-41F_638P Athlon 64 2009-09-25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 Compal Secret Data Security Classification 22U_0805_6.3V6M VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 D J6 J8 J10 J12 J14 J16 J18 K2 K7 K9 K11 K13 K15 K17 L6 L8 L10 L12 L14 L16 L18 M7 M9 AC6 M17 N4 N8 N10 N16 N18 P2 P7 P9 P11 P17 R8 R10 R16 R18 T7 T9 T11 T13 T15 T17 U4 U6 U8 U10 U12 U14 U16 U18 V2 V7 V9 V11 V13 V15 V17 W6 Y21 Y23 N6 Title S1 Processor Socket Compal Electronics, Inc AMD CPU S1G2 PWR & GND Size Document Number Custom Date: Rev 1.0 LA-4971P Wednesday, April 22, 2009 Sheet E of 45 A B C +1.8V < EMI require > C160 E +1.8V < EMI require > 0.1U_0402_16V7K D C155 0.1U_0402_16V7K +1.8V +0.9V JDDRH +V_DDR_MCH_REF 1 C104 1000P_0402_25V8J 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 DDR_B_D0 DDR_B_D1 DDR_B_DQS#0 DDR_B_DQS0 DDR_B_D2 DDR_B_D3 DDR_B_D8 DDR_B_D9 DDR_B_DQS#1 DDR_B_DQS1 DDR_B_D10 DDR_B_D11 RP8 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 DDR_B_RAS# DDR_B_D4 DDR_B_D5 C105 0.1U_0402_16V7K C106 0.1U_0402_16V7K C108 0.1U_0402_16V7K C107 0.1U_0402_16V7K C109 0.1U_0402_16V7K C110 0.1U_0402_16V7K C111 0.1U_0402_16V7K C112 0.1U_0402_16V7K C114 0.1U_0402_16V7K C113 0.1U_0402_16V7K C116 0.1U_0402_16V7K C115 0.1U_0402_16V7K C118 0.1U_0402_16V7K C117 0.1U_0402_16V7K DDR_B_DM0 47_0804_8P4R_5% DDR_B_D6 DDR_B_D7 RP9 DDR_B_MA14 DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 DDR_B_D12 DDR_B_D13 DDR_B_DM1 47_0804_8P4R_5% DDR_B_CLK0 DDR_B_CLK#0 RP10 DDR_CKE0_DIMMB DDR_B_BS#2 DDR_B_MA15 DDR_CKE1_DIMMB DDR_B_D14 DDR_B_D15 47_0804_8P4R_5% 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 DDR_B_D16 DDR_B_D17 DDR_B_DQS#2 DDR_B_DQS2 DDR_B_D18 DDR_B_D19 DDR_B_D24 DDR_B_D25 DDR_B_DM3 DDR_B_D26 DDR_B_D27 DDR_CKE0_DIMMB DDR_B_BS#2 DDR_CKE0_DIMMB DDR_B_BS#2 DDR_B_MA12 DDR_B_MA9 DDR_B_MA8 DDR_B_MA5 DDR_B_MA3 DDR_B_MA1 DDR_B_BS#0 DDR_B_WE# DDR_B_CAS# DDR_CS1_DIMMB# DDR_B_ODT1 DDR_B_MA10 DDR_B_BS#0 DDR_B_WE# DDR_B_CAS# DDR_CS1_DIMMB# DDR_B_ODT1 DDR_B_D32 DDR_B_D33 DDR_B_DQS#4 DDR_B_DQS4 DDR_B_D34 DDR_B_D35 DDR_B_D40 DDR_B_D41 DDR_B_DM5 DDR_B_D42 DDR_B_D43 DDR_B_D48 DDR_B_D49 DDR_B_DQS#6 DDR_B_DQS6 DDR_B_D50 DDR_B_D51 DDR_B_D56 DDR_B_D57 DDR_B_DM7 DDR_B_D58 DDR_B_D59 9,15,21,27 SMB_CK_DAT0 9,15,21,27 SMB_CK_CLK0 +3VS C119 VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 VSS 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 DDR_B_D20 DDR_B_D21 RP11 DDR_B_MA3 DDR_B_MA8 DDR_B_MA12 DDR_B_MA9 DDR_B_DM2 47_0804_8P4R_5% DDR_B_D22 DDR_B_D23 RP12 DDR_B_D28 DDR_B_D29 DDR_B_BS#0 DDR_B_MA10 DDR_B_MA1 DDR_B_MA5 DDR_B_DQS#3 DDR_B_DQS3 47_0804_8P4R_5% DDR_B_D30 DDR_B_D31 RP13 DDR_CKE1_DIMMB DDR_CKE1_DIMMB DDR_CS1_DIMMB# DDR_B_ODT1 DDR_B_CAS# DDR_B_WE# DDR_B_MA15 DDR_B_MA14 47_0804_8P4R_5% DDR_B_MA11 DDR_B_MA7 DDR_B_MA6 RP14 DDR_B_BS#1 DDR_CS0_DIMMB# DDR_B_MA13 DDR_B_ODT0 DDR_B_MA4 DDR_B_MA2 DDR_B_MA0 47_0804_8P4R_5% DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB# DDR_B_BS#1 DDR_B_RAS# DDR_CS0_DIMMB# DDR_B_ODT0 DDR_B_MA13 DDR_B_ODT0 DDR_B_D36 DDR_B_D37 DDR_B_DM4 DDR_B_D38 DDR_B_D39 DDR_B_D[0 63] DDR_B_D44 DDR_B_D45 DDR_B_DM[0 7] DDR_B_DQS[0 7] DDR_B_DQS#5 DDR_B_DQS5 DDR_B_MA[0 15] DDR_B_D46 DDR_B_D47 DDR_B_DQS#[0 7] DDR_B_D[0 63] DDR_B_DM[0 7] DDR_B_DQS[0 7] DDR_B_MA[0 15] DDR_B_DQS#[0 7] DDR_B_D52 DDR_B_D53 DDR_B_CLK1 DDR_B_CLK#1 DDR_B_DM6 DDR_B_D54 DDR_B_D55 DDR_B_D60 DDR_B_D61 DDR_B_DQS#7 DDR_B_DQS7 DDR_B_D62 DDR_B_D63 +3VS @ FOX_AS0A426-N8RN-7F_200P 0.1U_0402_16V7K DIMM0 STD H:9.2mm (Bot) Compal Secret Data Security Classification 2008-09-25 Issued Date 2009-09-25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc DDRII SO-DIMM Size Document Number Custom Date: Rev 1.0 LA-4971P Wednesday, April 22, 2009 Sheet E of 45 A B C D E +1.8V R43 1K_0402_1% +V_DDR_MCH_REF +V_DDR_MCH_REF R44 1K_0402_1% 0.1U_0402_16V7K C95 1000P_0402_25V8J DDR_A_D[0 63] DDR_A_DM[0 7] 1 C96 < EMI require > 0.1U_0402_16V7K +1.8V C193 JDDRL 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 DDR_A_D0 DDR_A_D1 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D2 DDR_A_D3 DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 203 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27 DDR_CKE0_DIMMA DDR_CKE0_DIMMA DDR_A_BS#2 DDR_A_BS#2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_MA10 DDR_A_BS#0 DDR_A_WE# DDR_A_BS#0 DDR_A_WE# DDR_A_CAS# DDR_CS1_DIMMA# DDR_A_CAS# DDR_CS1_DIMMA# DDR_A_ODT1 DDR_A_ODT1 DDR_A_D32 DDR_A_D33 DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7 DDR_A_D58 DDR_A_D59 8,15,21,27 SMB_CK_DAT0 8,15,21,27 SMB_CK_CLK0 +3VS +1.8V C103 VREF VSS DQ0 DQ1 VSS DQS0# DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1# DQS1 VSS DQ10 DQ11 VSS VSS DQ16 DQ17 VSS DQS2# DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DM3 NC VSS DQ26 DQ27 VSS CKE0 VDD NC BA2 VDD A12 A9 A8 VDD A5 A3 A1 VDD A10/AP BA0 WE# VDD CAS# NC/S1# VDD NC/ODT1 VSS DQ32 DQ33 VSS DQS4# DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DM5 VSS DQ42 DQ43 VSS DQ48 DQ49 VSS NC,TEST VSS DQS6# DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DM7 VSS DQ58 DQ59 VSS SDA SCL VDDSPD VSS C161 VSS DQ4 DQ5 VSS DM0 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1 VSS CK0 CK0# VSS DQ14 DQ15 VSS VSS DQ20 DQ21 VSS NC DM2 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DQS3# DQS3 VSS DQ30 DQ31 VSS NC/CKE1 VDD NC/A15 NC/A14 VDD A11 A7 A6 VDD A4 A2 A0 VDD BA1 RAS# S0# VDD ODT0 NC/A13 VDD NC VSS DQ36 DQ37 VSS DM4 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DQS5# DQS5 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS CK1 CK1# VSS DM6 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DQS7# DQS7 VSS DQ62 DQ63 VSS SAO SA1 VSS 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 204 A 5 DDR_A_DQS[0 7] DDR_A_MA[0 15] DDR_A_MA[0 15] DDR_A_DQS#[0 7] 5 DDR_A_DQS#[0 7] DDR_A_DM0 DDR_A_D6 DDR_A_D7 DDR_A_D12 DDR_A_D13 DDR_A_DM1 RP1 DDR_A_MA6 DDR_A_MA14 DDR_A_MA7 DDR_A_MA11 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 47_0804_8P4R_5% RP2 DDR_A_BS#1 DDR_A_MA2 DDR_A_MA0 DDR_A_MA4 47_0804_8P4R_5% RP3 DDR_A_MA5 DDR_A_MA8 DDR_A_MA9 DDR_A_MA12 47_0804_8P4R_5% RP4 DDR_A_BS#0 DDR_A_MA10 DDR_A_MA3 DDR_A_MA1 47_0804_8P4R_5% RP5 DDR_A_ODT1 DDR_CS1_DIMMA# DDR_A_CAS# DDR_A_WE# 47_0804_8P4R_5% RP6 DDR_A_MA13 DDR_A_ODT0 DDR_A_RAS# DDR_CS0_DIMMA# 47_0804_8P4R_5% RP7 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 DDR_CKE1_DIMMA DDR_A_MA15 DDR_A_MA14 DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# DDR_A_ODT0 DDR_A_MA13 DDR_A_BS#1 DDR_A_RAS# DDR_CS0_DIMMA# DDR_A_ODT0 DDR_CKE0_DIMMA DDR_A_BS#2 DDR_CKE1_DIMMA DDR_A_MA15 DDR_A_DM2 DDR_CKE1_DIMMA +1.8V +0.9V DDR_A_CLK0 DDR_A_CLK#0 DDR_A_D14 DDR_A_D15 C87 0.1U_0402_16V7K C88 0.1U_0402_16V7K C90 0.1U_0402_16V7K C89 0.1U_0402_16V7K C91 0.1U_0402_16V7K C92 0.1U_0402_16V7K C93 0.1U_0402_16V7K C94 0.1U_0402_16V7K C98 0.1U_0402_16V7K C97 0.1U_0402_16V7K C100 0.1U_0402_16V7K C99 0.1U_0402_16V7K C102 0.1U_0402_16V7K C101 0.1U_0402_16V7K 47_0804_8P4R_5% DDR_A_D36 DDR_A_D37 DDR_A_DM4 DDR_A_D38 DDR_A_D39 DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_CLK1 DDR_A_CLK#1 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 0.1U_0402_16V7K DIMM0 STD H:5.2mm (Bot) B DDR_A_D[0 63] DDR_A_DM[0 7] DDR_A_DQS[0 7] 0.1U_0402_16V7K DDR_A_D4 DDR_A_D5 @ FOX_AS0A426-M4R-TR_200P < EMI require > Compal Secret Data Security Classification 2008-09-25 Issued Date 2009-09-25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC C D Title Compal Electronics, Inc DDRII SO-DIMM Size Document Number Custom Date: Rev 1.0 LA-4971P Wednesday, April 22, 2009 Sheet E of 45 B C U3B PCIE_GTX_C_MRX_N[0 15] PCIE_GTX_C_MRX_P[0 15] 19 PCIE_GTX_C_MRX_N[0 15] 19 Polarity inversion Polarity inversion Polarity inversion Polarity inversion Polarity inversion Polarity inversion < From MXM VGA board > Polarity inversion Polarity inversion Polarity inversion Polarity inversion Polarity inversion Polarity inversion Polarity inversion Polarity inversion PCIE_GTX_C_MRX_N0 PCIE_GTX_C_MRX_P0 PCIE_GTX_C_MRX_P1 PCIE_GTX_C_MRX_N1 PCIE_GTX_C_MRX_N2 PCIE_GTX_C_MRX_P2 PCIE_GTX_C_MRX_N3 PCIE_GTX_C_MRX_P3 PCIE_GTX_C_MRX_N4 PCIE_GTX_C_MRX_P4 PCIE_GTX_C_MRX_N5 PCIE_GTX_C_MRX_P5 PCIE_GTX_C_MRX_P6 PCIE_GTX_C_MRX_N6 PCIE_GTX_C_MRX_N7 PCIE_GTX_C_MRX_P7 PCIE_GTX_C_MRX_N8 PCIE_GTX_C_MRX_P8 PCIE_GTX_C_MRX_N9 PCIE_GTX_C_MRX_P9 PCIE_GTX_C_MRX_N10 PCIE_GTX_C_MRX_P10 PCIE_GTX_C_MRX_N11 PCIE_GTX_C_MRX_P11 PCIE_GTX_C_MRX_N12 PCIE_GTX_C_MRX_P12 PCIE_GTX_C_MRX_N13 PCIE_GTX_C_MRX_P13 PCIE_GTX_C_MRX_N14 PCIE_GTX_C_MRX_P14 PCIE_GTX_C_MRX_N15 PCIE_GTX_C_MRX_P15 AE3 AD4 AE2 AD3 AD1 AD2 V5 W6 U5 U6 U8 U7 27 PCIE_PTX_C_IRX_P0 27 PCIE_PTX_C_IRX_N0 < To New Card > < To WLAN > 27 27 26 26 < To LAN > PCIE_PTX_C_IRX_P2 PCIE_PTX_C_IRX_N2 PCIE_PTX_C_IRX_P3 PCIE_PTX_C_IRX_N3 < From SB700 : x4 PCIE A-link > 20 20 20 20 20 20 20 20 D4 C4 A3 B3 C2 C1 E5 F5 G5 G6 H5 H6 J6 J5 J7 J8 L5 L6 M8 L8 P7 M7 P5 M5 R8 P8 R6 R5 P4 P3 T4 T3 AA8 Y8 AA7 Y7 AA5 AA6 W5 Y5 SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N GFX_RX0P GFX_RX0N GFX_RX1P GFX_RX1N GFX_RX2P GFX_RX2N GFX_RX3P GFX_RX3N GFX_RX4P GFX_RX4N GFX_RX5P GFX_RX5N GFX_RX6P GFX_RX6N GFX_RX7P GFX_RX7N GFX_RX8P GFX_RX8N GFX_RX9P GFX_RX9N GFX_RX10P GFX_RX10N GFX_RX11P GFX_RX11N GFX_RX12P GFX_RX12N GFX_RX13P GFX_RX13N GFX_RX14P GFX_RX14N GFX_RX15P GFX_RX15N GPP_RX0P GPP_RX0N GPP_RX1P GPP_RX1N GPP_RX2P GPP_RX2N GPP_RX3P GPP_RX3N GPP_RX4P GPP_RX4N GPP_RX5P GPP_RX5N SB_RX0P SB_RX0N SB_RX1P SB_RX1N SB_RX2P SB_RX2N SB_RX3P SB_RX3N GFX_TX0P GFX_TX0N GFX_TX1P GFX_TX1N GFX_TX2P GFX_TX2N GFX_TX3P GFX_TX3N GFX_TX4P GFX_TX4N GFX_TX5P GFX_TX5N GFX_TX6P GFX_TX6N GFX_TX7P GFX_TX7N GFX_TX8P GFX_TX8N GFX_TX9P GFX_TX9N GFX_TX10P GFX_TX10N GFX_TX11P GFX_TX11N GFX_TX12P GFX_TX12N GFX_TX13P GFX_TX13N GFX_TX14P GFX_TX14N GFX_TX15P GFX_TX15N PART OF PCIE I/F GPP PCIE I/F SB GPP_TX0P GPP_TX0N GPP_TX1P GPP_TX1N GPP_TX2P GPP_TX2N GPP_TX3P GPP_TX3N GPP_TX4P GPP_TX4N GPP_TX5P GPP_TX5N SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N PCE_CALRP(PCE_BCALRP) PCE_CALRN(PCE_BCALRN) RS780MCR3@ D E GM : RS780MN & RS780MC, PM : RX781 PCIE I/F GFX A PCIE_GTX_C_MRX_P[0 15] A5 B5 A4 B4 C3 B2 D1 D2 E2 E1 F4 F3 F1 F2 H4 H3 H1 H2 J2 J1 K4 K3 K1 K2 M4 M3 M1 M2 N2 N1 P1 P2 PCIE_MTX_GRX_P0 PCIE_MTX_GRX_N0 PCIE_MTX_GRX_P1 PCIE_MTX_GRX_N1 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_N3 PCIE_MTX_GRX_P4 PCIE_MTX_GRX_N4 PCIE_MTX_GRX_P5 PCIE_MTX_GRX_N5 PCIE_MTX_GRX_P6 PCIE_MTX_GRX_N6 PCIE_MTX_GRX_P7 PCIE_MTX_GRX_N7 PCIE_MTX_GRX_P8 PCIE_MTX_GRX_N8 PCIE_MTX_GRX_P9 PCIE_MTX_GRX_N9 PCIE_MTX_GRX_P10 PCIE_MTX_GRX_N10 PCIE_MTX_GRX_P11 PCIE_MTX_GRX_N11 PCIE_MTX_GRX_P12 PCIE_MTX_GRX_N12 PCIE_MTX_GRX_P13 PCIE_MTX_GRX_N13 PCIE_MTX_GRX_P14 PCIE_MTX_GRX_N14 PCIE_MTX_GRX_P15 PCIE_MTX_GRX_N15 AC1 AC2 AB4 AB3 AA2 AA1 Y1 Y2 Y4 Y3 V1 V2 PCIE_ITX_PRX_P0 PCIE_ITX_PRX_N0 PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ PM@ C120 C121 C122 C123 C124 C125 C126 C127 C128 C129 C130 C131 C132 C133 C134 C135 C136 C137 C138 C139 C140 C141 C142 C143 C144 C145 C146 C147 C148 C149 C150 C151 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K C152 C153 2 0.1U_0402_16V7K 0.1U_0402_16V7K PCIE_ITX_PRX_P2 WLAN@ C156 PCIE_ITX_PRX_N2 WLAN@ C157 PCIE_ITX_PRX_P3 C158 PCIE_ITX_PRX_N3 C159 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 2 2 2 2 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K 0.1U_0402_16V7K PCIE_MTX_C_GRX_N0 PCIE_MTX_C_GRX_P0 PCIE_MTX_C_GRX_N1 PCIE_MTX_C_GRX_P1 PCIE_MTX_C_GRX_P2 PCIE_MTX_C_GRX_N2 PCIE_MTX_C_GRX_N3 PCIE_MTX_C_GRX_P3 PCIE_MTX_C_GRX_P4 PCIE_MTX_C_GRX_N4 PCIE_MTX_C_GRX_P5 PCIE_MTX_C_GRX_N5 PCIE_MTX_C_GRX_P6 PCIE_MTX_C_GRX_N6 PCIE_MTX_C_GRX_P7 PCIE_MTX_C_GRX_N7 PCIE_MTX_C_GRX_P8 PCIE_MTX_C_GRX_N8 PCIE_MTX_C_GRX_P9 PCIE_MTX_C_GRX_N9 PCIE_MTX_C_GRX_P10 PCIE_MTX_C_GRX_N10 PCIE_MTX_C_GRX_P11 PCIE_MTX_C_GRX_N11 PCIE_MTX_C_GRX_N12 PCIE_MTX_C_GRX_P12 PCIE_MTX_C_GRX_P13 PCIE_MTX_C_GRX_N13 PCIE_MTX_C_GRX_N14 PCIE_MTX_C_GRX_P14 PCIE_MTX_C_GRX_P15 PCIE_MTX_C_GRX_N15 Polarity inversion PCIE_MTX_C_GRX_P[0 15] Polarity inversion PCIE_MTX_C_GRX_N[0 15] 4 H_CADOP0 H_CADON0 H_CADOP1 H_CADON1 H_CADOP2 H_CADON2 H_CADOP3 H_CADON3 H_CADOP4 H_CADON4 H_CADOP5 H_CADON5 H_CADOP6 H_CADON6 H_CADOP7 H_CADON7 < From S1G2 CPU : x16 HT> H_CADOP8 H_CADON8 H_CADOP9 H_CADON9 H_CADOP10 H_CADON10 H_CADOP11 H_CADON11 H_CADOP12 H_CADON12 H_CADOP13 H_CADON13 H_CADOP14 H_CADON14 H_CADOP15 H_CADON15 4 4 H_CLKOP0 H_CLKON0 H_CLKOP1 H_CLKON1 4 4 H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1 301_0402_1% 301_0402_1%1 0718 Place within 1" layout 1:2 Y25 Y24 V22 V23 V25 V24 U24 U25 T25 T24 P22 P23 P25 P24 N24 N25 AC24 AC25 AB25 AB24 AA24 AA25 Y22 Y23 W21 W20 V21 V20 U20 U21 U19 U18 T22 T23 AB23 AA22 H_CTLOP0 H_CTLON0 H_CTLOP1 H_CTLON1 R57 HT_RXCALP HT_RXCALN M22 M23 R21 R20 C23 A24 HT_RXCAD0P HT_RXCAD0N HT_RXCAD1P HT_RXCAD1N HT_RXCAD2P HT_RXCAD2N HT_RXCAD3P HT_RXCAD3N HT_RXCAD4P HT_RXCAD4N HT_RXCAD5P HT_RXCAD5N HT_RXCAD6P HT_RXCAD6N HT_RXCAD7P HT_RXCAD7N PART OF HT_RXCAD8P HT_RXCAD8N HT_RXCAD9P HT_RXCAD9N HT_RXCAD10P HT_RXCAD10N HT_RXCAD11P HT_RXCAD11N HT_RXCAD12P HT_RXCAD12N HT_RXCAD13P HT_RXCAD13N HT_RXCAD14P HT_RXCAD14N HT_RXCAD15P HT_RXCAD15N HT_RXCLK0P HT_RXCLK0N HT_RXCLK1P HT_RXCLK1N HT_RXCTL0P HT_RXCTL0N HT_RXCTL1P HT_RXCTL1N HT_RXCALP HT_RXCALN HT_TXCAD0P HT_TXCAD0N HT_TXCAD1P HT_TXCAD1N HT_TXCAD2P HT_TXCAD2N HT_TXCAD3P HT_TXCAD3N HT_TXCAD4P HT_TXCAD4N HT_TXCAD5P HT_TXCAD5N HT_TXCAD6P HT_TXCAD6N HT_TXCAD7P HT_TXCAD7N HT_TXCAD8P HT_TXCAD8N HT_TXCAD9P HT_TXCAD9N HT_TXCAD10P HT_TXCAD10N HT_TXCAD11P HT_TXCAD11N HT_TXCAD12P HT_TXCAD12N HT_TXCAD13P HT_TXCAD13N HT_TXCAD14P HT_TXCAD14N HT_TXCAD15P HT_TXCAD15N HT_TXCLK0P HT_TXCLK0N HT_TXCLK1P HT_TXCLK1N HT_TXCTL0P HT_TXCTL0N HT_TXCTL1P HT_TXCTL1N HT_TXCALP HT_TXCALN RS780MCR3@RS780M_FCBGA528 < To MXM VGA board > Polarity inversion Polarity inversion PCIE_ITX_C_PRX_P0 27 PCIE_ITX_C_PRX_N0 27 PCIE_ITX_C_PRX_P2 PCIE_ITX_C_PRX_N2 PCIE_ITX_C_PRX_P3 PCIE_ITX_C_PRX_N3 NEED CHECK R57 & R58 WITH AMD < To New Card > < To WLAN > < To LAN > AD7 AE7 AE6 AD6 AB6 AC6 AD5 AE5 SB_TX0P_C SB_TX0N_C SB_TX1P_C SB_TX1N_C SB_TX2P_C SB_TX2N_C SB_TX3P_C SB_TX3N_C AC8 AB8 PCIE_CALRP PCIE_CALRN C162 C163 C164 C165 C166 C168 C169 C167 R55 R56 1 1 1 1 1 SB_TX0P SB_TX0N SB_TX1P SB_TX1N SB_TX2P SB_TX2N SB_TX3P SB_TX3N 1.27K_0402_1% 2K_0402_1% 2 H_CADIP[0 15] H_CADIP0 H_CADIN0 H_CADIP1 H_CADIN1 H_CADIP2 H_CADIN2 H_CADIP3 H_CADIN3 H_CADIP4 H_CADIN4 H_CADIP5 H_CADIN5 H_CADIP6 H_CADIN6 H_CADIP7 H_CADIN7 D24 D25 E24 E25 F24 F25 F23 F22 H23 H22 J25 J24 K24 K25 K23 K22 H_CADIN[0 15] 20 20 20 20 20 20 20 20 < To SB700 : x4 PCEI A-link> < TX Impedance Calibration Connect to GND > < RX Impedance Calibration Connect to VDDPCIE > +1.1VS H24 H25 L21 L20 H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1 B24 B25 HT_TXCALP HT_TXCALN H_CADIN[0 15] DP0 GFX_TX0,TX1,TX2 and TX3 AUX0 and HPD0 DP1 GFX_TX4,TX5,TX6 and TX7 AUX1 and HPD1 < If integrated GFX is used, some PCIE pairs are used as HDMI signal pairs > H_CLKIP0 H_CLKIN0 H_CLKIP1 H_CLKIN1 M24 M25 P19 R18 RS780M Display Port Support (muxed on GFX) H_CADIP[0 15] < To S1G2 CPU : x16 HT> H_CADIP8 H_CADIN8 H_CADIP9 H_CADIN9 H_CADIP10 H_CADIN10 H_CADIP11 H_CADIN11 H_CADIP12 H_CADIN12 H_CADIP13 H_CADIN13 H_CADIP14 H_CADIN14 H_CADIP15 H_CADIN15 F21 G21 G20 H21 J20 J21 J18 K17 L19 J19 M19 L18 M21 P21 P18 M18 PCIE_MTX_GRX_P0 IHDMI@ R74 PCIE_MTX_GRX_N0 IHDMI@ R75 PCIE_MTX_GRX_P1 IHDMI@ R76 PCIE_MTX_GRX_N1 IHDMI@ R81 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% HDMI_TXD2+ HDMI_TXD2HDMI_TXD1+ HDMI_TXD1- 18,19 18,19 18,19 18,19 PCIE_MTX_GRX_P2 PCIE_MTX_GRX_N2 PCIE_MTX_GRX_P3 PCIE_MTX_GRX_N3 2 2 0_0402_5% 0_0402_5% 0_0402_5% 0_0402_5% HDMI_TXD0+ HDMI_TXD0HDMI_CLK0+ HDMI_CLK0- 18,19 18,19 18,19 18,19 IHDMI@ IHDMI@ IHDMI@ IHDMI@ R82 R83 R84 R85 H_CTLIP0 H_CTLIN0 H_CTLIP1 H_CTLIN1 R58 301_0402_1% < Transmitter Calibration Resistor to HT_TXCALN > Compal Secret Data 2008-09-25 2009-09-25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC C 4 4 Security Classification Issued Date B 27 27 26 26 0718 Place within 1" layout 1:2 / A 19 RS780M_FCBGA528 HYPER TRANSPORT CPU I/F H_CADOP[0 15] H_CADON[0 15] 19 PCIE_MTX_C_GRX_N[0 15] Polarity inversion U3A H_CADOP[0 15] H_CADON[0 15] PCIE_MTX_C_GRX_P[0 15] D Title Compal Electronics, Inc RS780M&RX781-HT/PCIE Size Document Number Custom Date: Rev 1.0 LA-4971P Wednesday, April 22, 2009 Sheet E 10 of 45 A B C < TPA6017 Medium Range Amplifier > D E < Ext Mic > +5VS RA20 4.7K_0402_5% 2 CA23 10U_0805_10V4Z CA24 0.1U_0402_16V4Z CA25 0.1U_0402_16V4Z 16 15 30 CA32 0.033U_0402_16V7K LINE_C_OUTL AMP_SPK_L 4.7U_0805_10V4Z ROUT- LIN- 18 SPKR+ 14 SPKR- SPKL+ SPKL- BYPASS @ Keep 10 mil width 10 AMP_BYPASS RA30 100K_0402_5% 100K_0402_5% DA3 PACDN042Y3R_SOT23-3 MIC@ CA26 1U_0402_6.3V4Z MIC2_L 1U_0402_6.3V4Z CA28 MIC@ MIC2_R MIC@ RA25 1K_0402_5% 1K_0402_5% RA26 MIC@ 10 15.6 45K 1 21.6 25K @ JMIC 1 NC1 2 NC2 INT_MIC CA27 220P_0402_50V7K @ J3 2 ACES_85204-0200N_2P 1 JUMP_43X39 close to Codec GND5 GND1 GND2 GND3 GND4 INT_MIC_R 17 close to JMIC RA29 30 12 SHUTDOWN CA33 0.47U_0603_10V7K TPA6017A2_TSSOP20 21 20 13 11 +MIC1_VREFO +MIC2_VREFO LVDSSET@ RA38 0_0402_5% 100K_0402_5% < Speaker Connector > DA4 PACDN042Y3R_SOT23-3 GAIN0 GAIN1 Av(db) Rin(ohm) 4.7K_0402_5% LIN+ RA24 NC 19 MIC@ DA2 CH751H-40PT_SOD323-2 1 30 MUTE# RA23 4.7K_0402_5% RIN- LOUT- 30 +MIC1_VREFO MIC1_L MIC1_R 1K_0402_5% RA22 LOUT+ CA22 2 GAIN0 ROUT+ CA31 0.033U_0402_16V7K MIC1_C_R 2 100K_0402_5% RIN+ GAIN1 17 30 DA1 CH751H-40PT_SOD323-2 RA21 1K_0402_5% RA28 CA30 0.033U_0402_16V7K LINE_C_OUTR AMP_SPK_R 1 4.7U_0805_10V4Z @ 30 RA27 VDD PVDD1 PVDD2 CA29 0.033U_0402_16V7K CA21 < Int Mic > +5VS UA3 MIC1_C_L 10 dB 30 90K 70K JSPK SPKL+ SPKLSPKR+ SPKR- LA3 LA4 LA5 LA6 SPK_L1 SPK_L2 SPK_R1 SPK_R2 FBMA-L11-160808-800LMT_0603 FBMA-L11-160808-800LMT_0603 FBMA-L11-160808-800LMT_0603 FBMA-L11-160808-800LMT_0603 @ 3 ACES_85204-0400N_4P < Volume Control > DA5 PACDN042Y3R_SOT23-3 +3VS < HeadPhone JACK > RA32 CA43 0.1U_0402_16V4Z 100K_0402_5% 1 +3VS A 0.01U_0402_25V7K 30 HP_R LA7 KC FBM-L11-160808-121LMT 0603 HP_R_L 30 HP_L LA8 KC FBM-L11-160808-121LMT 0603 HP_L_L 3 @ FOX_JA6333L-B3T0-7F 1 +3VS UA4 @ DA6 PACDN042Y3R_SOT23-3 Y 74LVC1G14GW_SOT353-5 UA5 RA36 10K_0402_5% CA37 SW_XRE094_3P P RA35 10K_0402_5% DIP B COM CA36 0.1U_0402_16V4Z JLINE < EMI require > NBA_PLUG CA35 0.1U_0402_16V4Z 10K_0402_5% NC RA34 10K_0402_5% G A RA33 2 DIP SW2 +3VS 30 CA38 0.01U_0402_25V7K CD1# D1 CP1 SD1# Q1 Q1# GND VCC CD2# D2 CP2 SD2# Q2 Q2# < Ext.MIC/LINE IN JACK > 14 13 12 11 10 09 08 CA44 74LCX74MTC_TSSOP14 CA39 0.1U_0402_16V4Z 0.1U_0402_16V4Z 30 JEXMIC < EMI require > MIC_SENSE MIC1_R LA9 KC FBM-L11-160808-121LMT 0603 MIC1_L_R MIC1_L LA10 KC FBM-L11-160808-121LMT 0603 MIC1_L_L ENCODER_DIR 34 ENCODER_PULSE 34 @ 1 @ DA7 PACDN042Y3R_SOT23-3 / 2008-09-25 2009-09-25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C CA40 100P_0402_50V8J @ D FOX_JA6333L-B3T0-7F CA41 100P_0402_50V8J Compal Secret Data Security Classification Issued Date @ Title Compal Electronics, Inc AMP/Audio Jack/HP/SPEAKER/VR Size Document Number Custom Date: Rev 1.0 LA-4971P Wednesday, April 22, 2009 Sheet E 31 of 45 A B C < USB Right-side Board, USB port 0,1 > +USB_VCCA BT@ 0_0402_5% USB_OC#0 21,34 G528_SO8 34 0.1U_0402_16V7K R441 47K_0402_5% BT@ BT_PWR# BT@ > t s e u q e r I M E r o f e v r e s e R < C196 +BT_VCC Inrush current = 0A 10 11 12 13 14 21 USB20_P0 4 USB20_N0_R USB20_P0_R USB20_N1_R USB20_P1_R WCM-2012-900T_0805 @ R108 0_0402_5% @ R109 0_0402_5% < Bluetooth Connector > JBT 12 11 21 21 34 BT@ BT_RST# R440 0_0402_5% BT_RESET# E-T_6905-E12N-00R_12P USB20_P6 USB20_N6 22 +BT_VCC BT_DET# (MAX=200mA) +3VS C483 C479 @ R437 1 C480 0_0402_5% R438 @ BT@ 0.1U_0402_16V4Z USB20_N1 21 USB20_P1 4 R439 @ 10 ACES_87213-1000G_10P BT@ 4.7U_0805_10V4Z 0.1U_0402_16V4Z 4.7K_0402_5% L51 21 4.7K_0402_5% BT@ GND2 GND1 10 USB20_P6 USB20_N6 BT@ @ 10 11 12 GND GND USB20_N0 JUSBB W=60mils L50 21 Q25 AO3413_SOT23 0.01U_0402_25V7K +USB_VCCA 0.1U_0402_16V4Z BT@ @ R107 0_0402_5% C482 BT@ 100K_0402_5% R422 C481 OUT OUT OUT FLG +3VS R432 GND IN IN EN# 4.7U_0805_10V4Z USB_EN# USB_EN# C438 G 34 +3VS W=60mils D 1.4A U25 E S +5VALW D < BlueTooth Interface, USB port6 > WCM-2012-900T_0805 @ R110 0_0402_5% < Int Camera, USB port > +5VS CAM@ R430 0_0603_5% +5VALW @ R428 0_0603_5% LVDSSET@ W=20mils +CAM_VDD R20 close to JCAM R20 0_0402_5% USB20_N9_R_CAM 17 < EMI require > CAM@ C744 0.1U_0402_16V4Z @ JCAM GND1 GND2 @ R103 CAM@ L60 1 USB20_N9_R USB20_P9_R 4 0_0402_5% 3 USB20_N9 21 USB20_P9 21 WCM-2012-900T_0805 ACES_88266-05001_5P @ R99 0_0402_5% R18 0_0402_5% LVDSSET@ USB20_P9_R_CAM 17 R18 close to JCAM < Finger Printer, USB port > FP@ +3VS R119 0_0603_5% +3VS_FP C468 0.1U_0402_16V4Z FP@ JFP 21 21 USB20_N7 USB20_P7 USB20_N7 USB20_P7 FP@ R118 0_0603_5% GND GND @ ACES_85201-04051 / Compal Secret Data Security Classification 2008-09-25 Issued Date 2009-09-25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc USB/BT/FingerPrint Size Document Number Custom Date: Rev 1.0 LA-4971P Sheet Wednesday, April 22, 2009 E 32 of 45 > * b M h s a l F I P S < A B C D E < MDC 1.5 Conn > +3VL U46 20mils 1 C786 C607 @ C608 10P_0402_50V8J @ 0.1U_0402_16V4Z 10P_0402_50V8J SPI_CS# 34 SPI_CS# 34 1 EC_SPICLK SPI_CLK 34 EC_SO_SPI_SI VCC VSS W HOLD S C D Q EC_SI_SPI_SO 34 JMDC MX25L8005M2C-15G 21 HDA_SDOUT_MDC R518 10_0402_5% C606 10P_0402_50V8J 21 HDA_SYNC_MDC 21 HDA_SDIN1 21 HDA_RST#_MDC MDC@ R495 33_0402_5% HDA_SDOUT_MDC HDA_SYNC_MDC HDA_SDIN1_MDC 11 GND1 RES0 IAC_SDATA_OUT RES1 GND2 3.3V IAC_SYNC GND3 IAC_SDATA_IN GND4 IAC_RESET# IAC_BITCLK 10 12 +3VALW +3VALW HDA_BITCLK_MDC 21 EC_SPICLK GND GND GND GND GND GND R496 20,34 LPC_AD3 20,34 LPC_AD1 PLT_RST# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 LPC_FRAME# 10P_0402_50V8J 10 +3VALW PLT_RST# 11,14,19,20,26,27,34 LPC_AD2 20,34 LPC_AD0 20,34 CLK_PCI_SIO2 MDC@ C778 1000P_0402_50V7K MDC@ C779 0.1U_0402_16V4Z 2 MDC@ C780 4.7U_0805_10V4Z 20,24 20,34 LPC_FRAME# C777 H1 R622 0_0402_5% @ SERIRQ 20,28,34 SERIRQ ACES_88018-124G_12P Connector for MDC Rev1.5 Please place the PAD under DDR DIMM +3VS 10_0402_5% 13 14 15 16 17 18 @ < LPC Debug Port > @ R634 @ DEBUG_PAD 22_0402_5% C639 22P_0402_50V8J < KEYBOARD CONN 16" > JKB1 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 < KEYBOARD CONN 17" > R502 JKB2 +3VS KSO16 300_0402_5% KSO17 KSO2 KSO1 KSO0 KSO4 KSO3 KSO5 KSO14 KSO6 KSO7 KSO13 KSO8 KSO9 KSO10 KSO11 KSO12 KSO15 KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1 C781 0.1U_0402_16V4Z C782 0.1U_0402_16V4Z < For EMI > R509 CAPS_LED# 34 < For EMI > +3VS 300_0402_5% NUM_LED# 34 @ ACES_88170-3400_34P C783 0.1U_0402_16V4Z 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 KSO16 KSO17 KSO2 KSO1 KSO0 KSO4 KSO3 KSO5 KSO14 KSO6 KSO7 KSO13 KSO8 KSO9 KSO10 KSO11 KSO12 KSO15 KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1 KSO2 KSO1 KSO0 KSO4 KSO3 KSO5 KSO14 KSO6 KSO7 KSO13 KSO8 KSO9 KSO10 KSO11 KSO12 KSO15 KSI7 KSI2 KSI3 KSI4 KSI0 KSI5 KSI6 KSI1 CAPS_LED# NUM_LED# C725 C717 C721 C609 C724 C728 C730 C715 C732 C733 C740 C737 C729 C738 C718 C736 C716 C741 C726 C723 C731 C739 C735 C734 C722 C714 KSO16 KSO17 C870 C871 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J 100P_0402_50V8J CAPS_LED# NUM_LED# @ ACES_88170-3400_34P 4 KSI[0 7] KSO[0 17] KSI[0 7] 34,35 / KSO[0 17] 34,35 Compal Secret Data Security Classification 2008-09-25 Issued Date 2009-09-25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc SPI/LPC/PS2/MDC/FM/CIR Size Document Number Custom Date: Rev 1.0 LA-4971P Wednesday, April 22, 2009 Sheet E 33 of 45 B C +3VL D +3VL_EC L25 0_0603_5% VCC VCC VCC VCC VCC VCC U33 67 22 33 96 111 125 21 GATEA20 21 KB_RST# 20,28,33 SERIRQ 20,33 LPC_FRAME# 20,33 LPC_AD3 20,33 LPC_AD2 20,33 LPC_AD1 20,33 LPC_AD0 Reserve for EMI request @ R530 33_0402_5% 20,24 CLK_PCI_EC 11,14,19,20,26,27,33 47K_0402_5% PLT_RST# 21 EC_SCI# 35 WL_BT_LED# 33,35 KSI[0 7] KSO[0 17] KSO[0 17] 2 2.2K_0402_5% R326 2.2K_0402_5% EC_SMB_DA1 R70 2.2K_0402_5% EC_SMB_CK1 R77 2.2K_0402_5% CEC_INT# R563 100K_0402_5% TP_CLK R534 4.7K_0402_5% TP_DATA R535 SYSON R539 +3VS 18,38 EC_SMB_CK1 18,38 EC_SMB_DA1 6,19,35 EC_SMB_CK2 6,19,35 EC_SMB_DA2 +3VL 21 21 21 35 PM_SLP_S3# PM_SLP_S5# EC_SMI# LID_SW# 10K_0402_5% R536 10K_0402_5% R538 100K_0402_5% +3VALW 100K_0402_5% +3VL E51_TXD E51_RXD ON/OFFBTN# PWR_SUSP_LED# NUM_LED# C813 15P_0402_50V8J CRY1 Y7 KSO2 R947 R948 NC NC @ OSC +3VL_EC GM@ UMA_ENBKL 11 +3VL_EC PM@ R683 0_0402_5% VGA_ENBKL 19 0_0603_5% D33 CH751H-40PT_SOD323-2 2 C805 0.1U_0402_16V4Z 63 64 65 66 75 76 BATT_TEMPA INVT_PWM 17 EC_BEEP 30 ACOFF ACOFF 39 BATT_TEMPA 38 39 68 70 71 72 EN_DFAN1 IREF CHGVADJ 83 84 85 86 87 88 ENCODER_DIR ENCODER_PULSE TP_CLK TP_DATA 97 98 99 109 100 101 102 103 104 105 106 107 108 110 112 114 115 116 117 118 L81 BT_RST# WOL_EN# USB_OC#2 USB_CHG_EN# 25 USB_EN# 32 ENCODER_DIR 31 ENCODER_PULSE 31 TP_CLK 35 TP_DATA 35 BT_RST# 32 WOL_EN# 36 USB_OC#2 21,25 VGATE 43 EC_SI_SPI_SO 33 EC_SO_SPI_SI 33 SPI_CLK 33 SPI_CS# 33 CEC_INT# FSTCHG BATT_FULL_LED# BATT_LOW_LED# PWR_ON_LED# SYSON VR_ON ACIN_D EC_RSMRST# EC_SWI# SB_PWRGD BKOFF# WL_OFF# VR_ON C807 1000P_0402_50V7K 43 R541 10K_0402_5% EC_RSMRST# 21 EC_LID_OUT# 21 EC_ON 35,36 SB_PWRGD 21,43 BKOFF# 17 WL_OFF# 27 HDPINT 35 HDPACT 35 ENBKL HDPLOC HDPLOC 35 EC_THERM# 22 SUSP# 19,27,30,36,39,41 PBTN_OUT# 21 SUSP# PBTN_OUT# LAN_WAKE# 124 C814 2 CEC_INT# 18 FSTCHG 39 BATT_FULL_LED# 35 CAPS_LED# 33 BATT_LOW_LED# 35 PWR_ON_LED# 35 SYSON 27,36,42 4.7U_0805_10V4Z 0_0603_5% 39 DAC_BRIG 17 EN_DFAN1 IREF 39 CHGVADJ 39 119 120 126 128 73 74 89 90 91 92 93 95 121 127 ADP_I C154 0.22U_0603_16V4Z KB926QFD3_LQFP128_14X14 C806 0.1U_0402_16V4Z R145 100K_0402_5% ADP_V C812 100P_0402_50V8J ECAGND LAN_WAKE# @ R24 0_0402_5% LAN_WAKE_R# EC_SWI# @ R33 0_0402_5% EC_SWI_R# LAN_WAKE_R# R34 0_0402_5% EC_SWI_R# LAN_WAKE# R35 0_0402_5% LAN_WAKE_R# 26 EC_SWI_R# 21,27 USB_OC#0 21,32 C808 0.1U_0402_16V4Z C809 1000P_0402_50V7K +3VL ACIN / 22,35,37 C326 100P_0402_50V8J A PM_SLP_S4#/GPXID1 ENBKL/GPXID2 GPXID3 GPXID4 GPXID5 GPXID6 GPXID7 GPI C816 0.1U_0402_16V4Z Compal Secret Data Security Classification 2008-09-25 Issued Date EC_RSMRST#/GPXO03 EC_LID_OUT#/GPXO04 EC_ON/GPXO05 EC_SWI#/GPXO06 ICH_PWROK/GPXO06 BKOFF#/GPXO08 WL_OFF#/GPXO09 GPXO10 GPXO11 V18R R684 0_0402_5% R560 150K_0402_5% GPO XCLK1 XCLK0 CRY2 L80 SPIDI/RD# SPIDO/WR# SPICLK/GPIO58 SPICS# CIR_RX/GPIO40 CIR_RLC_TX/GPIO41 FSTCHG/SELIO#/GPIO50 BATT_CHGI_LED#/GPIO52 CAPS_LED#/GPIO53 BATT_LOW_LED#/GPIO54 SUSP_LED#/GPIO55 SYSON/GPIO56 VR_ON/XCLK32K/GPIO57 AC_IN/GPIO59 SM Bus 47K_0402_5% ACIN_D SPI Flash ROM PM_SLP_S3#/GPIO04 PM_SLP_S5#/GPIO07 EC_SMI#/GPIO08 LID_SW#/GPIO0A SUSP#/GPIO0B PBTN_OUT#/GPIO0C GPIO EC_PME#/GPIO0D EC_THERM#/GPIO11 FAN_SPEED1/FANFB1/GPIO14 FANFB2/GPIO15 EC_TX/GPIO16 EC_RX/GPIO17 ON_OFF/GPIO18 PWR_LED#/GPIO19 NUMLED#/GPIO1A +EC_AVCC SDICS#/GPXOA00 SDICLK/GPXOA01 SDIDO/GPXOA02 SDIDI/GPXID0 INVT_PWM SPI Device Interface GPIO R545 20M_0402_5% 32.768KHZ_12.5PF_9H03200413 C815 15P_0402_50V8J 47K_0402_5% 122 123 SCL1/GPIO44 SDA1/GPIO45 SCL2/GPIO46 SDA2/GPIO47 PSCLK1/GPIO4A PSDAT1/GPIO4B PSCLK2/GPIO4C PSDAT2/GPIO4D TP_CLK/PSCLK3/GPIO4E TP_DATA/PSDAT3/GPIO4F PS2 Interface OSC Add for KB926D2 issue Please refer to KB926D-AN1-100 for detail ENBKL DAC_BRIG/DA0/GPIO3C EN_DFAN1/DA1/GPIO3D IREF/DA2/GPIO3E DA3/GPIO3F DA Output KSI0/GPIO30 KSI1/GPIO31 KSI2/GPIO32 KSI3/GPIO33 KSI4/GPIO34 KSI5/GPIO35 KSI6/GPIO36 KSI7/GPIO37 KSO0/GPIO20 KSO1/GPIO21 KSO2/GPIO22 KSO3/GPIO23 KSO4/GPIO24 KSO5/GPIO25 Int K/B KSO6/GPIO26 Matrix KSO7/GPIO27 KSO8/GPIO28 KSO9/GPIO29 KSO10/GPIO2A KSO11/GPIO2B KSO12/GPIO2C KSO13/GPIO2D KSO14/GPIO2E KSO15/GPIO2F KSO16/GPIO48 KSO17/GPIO49 KSO1 14 15 16 17 18 19 25 28 29 30 31 32 34 36 FAN_SPEED1 FAN_SPEED1 36 VLDT_EN 27 E51_TXD 27 E51_RXD 35 ON/OFFBTN# 35 PWR_SUSP_LED# 33 NUM_LED# LID_SW# PM_SLP_S3# PM_SLP_S5# EC_SMI# LID_SW# BT_PWR# 32 BT_PWR# 4.7K_0402_5% SUSP# R513 77 78 79 80 +5VS ON/OFFBTN# EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DA2 AD Input R330 EC_SMB_CK2 55 56 57 58 59 60 61 62 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 81 82 BATT_TEMP/AD0/GPIO38 BATT_OVP/AD1/GPIO39 ADP_I/AD2/GPIO3A AD3/GPIO3B AD4/GPIO42 SELIO2#/AD5/GPIO43 MISC PCICLK PCIRST#/GPIO05 ECRST# SCI#/GPIO0E CLKRUN#/GPIO1D 0.1U_0402_16V4Z 33,35 KSI[0 7] EC_SMB_DA2 KSI0 KSI1 KSI2 KSI3 KSI4 KSI5 KSI6 KSI7 KSO0 KSO1 KSO2 KSO3 KSO4 KSO5 KSO6 KSO7 KSO8 KSO9 KSO10 KSO11 KSO12 KSO13 KSO14 KSO15 KSO16 KSO17 PWM Output 21 23 26 27 AGND 12 13 37 20 38 INVT_PWM/PWM1/GPIO0F BEEP#/PWM2/GPIO10 FANPWM1/GPIO12 ACOFF/FANPWM2/GPIO13 69 CLK_PCI_EC PLT_RST# ECRST# EC_SCI# WL_BT_LED# GA20/GPIO00 KBRST#/GPIO01 SERIRQ# LFRAME# LAD3 LAD2 LAD1 LAD0 LPC & ECAGND C811 10 GND GND GND GND GND +3VL R533 GATEA20 KB_RST# SERIRQ LPC_LFRAME# LPC_AD3 LPC_AD2 LPC_AD1 LPC_AD0 11 24 35 94 113 @ C810 15P_0402_50V8J1 E +EC_AVCC AVCC A 2009-09-25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC B C D Title Compal Electronics, Inc ENE KB926C Size Document Number Custom Date: Rev 1.0 LA-4971P Wednesday, April 22, 2009 Sheet E 34 of 45 A B < Power Button for Debug > C D < G - Sensor > < Screw Hole > debug phase using H15 H16 H17 H18 H19 H20 G@ ON/OFFBTN# 34 H_3P0 @ H_3P0 @ H_3P0 @ H23 H24 H25 1U_0402_6.3V4Z G@ UG3 H_3P0 @ H_3P0 @ H_3P0 @ 1 1 H_3P0 @ SHDN# 1U_0402_6.3V4Z OUT GND +5VS 1 IN H26 H_3P0 @ CG13 G@ SMT1-05-A_4P H_3P0 @ +3VS_HDP DG1 CH751H-40PT_SOD323-2 1 H22 +3VS_HDP CG12 H21 0_0603_5% G@ H_3P0 @ H_3P0 @ H_3P0 @ ON/OFFBTN# SW5 @ 1 TOP side E @ R689 +3VS +5VS CG14 0.22U_0402_10V4Z @ BYP G9191-330T1U_SOT23-5 H33 H_3P2 @ H36 H32 H_3P2 @ H37 H_3P7 @ H31 H_3P1N @ H35 SELF_TEST H_3P7 @ H39 H40 H41 H42 +3VS_HDP H47 H_3P0 @ CG649 0.1U_0402_16V4Z VOUTX G_2nd@ CG642 0.1U_0402_16V4Z VOUTY G_2nd@ CG641 0.1U_0402_16V4Z G_2nd@ UG4 XOUT VOUTZ 0G-DET @ 10 13 SELF_TEST SLEEP# G-SELECT ST +3VS_HDP 11 12 14 NC NC NC NC NC ZOUT FD4 +3VS_HDP VDD YOUT @ G D FD3 G_2nd@ VSS MMA7360LR2_LGA14 S R515 120_0402_5% MDC: H30, H31 @ @ VGA: H38, H39 CPU: H32, H33, H34, H35 Mini Card : H36, H37 Others: H15, H16, H17, H18, H19, H20, H21, H22, H23, H24, H25, H26, H27, H28, H29, H40, H47 22,34,37 ACIN D54 FD2 FD1 < DC-IN LED > 1 13 GND1 GND2 H_3P0 @ H_3P0N @ H_3P1X4P1N @ 1 1 H_3P7 @ PCB Fedical Mark PAD +3VALW 0.033U_0402_16V7K 0.033U_0402_16V7K 0.033U_0402_16V7K 1 TSH35TR_LGA16 10K_0402_5% G_1st@ CG1 G_1st@ CG2 G_1st@ CG3 10 11 14 15 16 NC1 NC2 NC3 NC4 NC5 Rev VOUTX VOUTY VOUTZ Voutx Vouty Voutz ST PD FS H_3P7 @ 2N7002_SOT23-3 S G_1st@ UG1 Vdd1 12 Vdd2 +3VS_HDP H38 H_3P7 @ H_3P7 @ H_3P7 @ H_3P7 @ Q19 R514 H34 H30 37 D G EC_ON 1 51_ON# 34,36 H_3P0 @ H_3P0 @ H29 H28 1 H27 HT-110UYG-CT_YEL/GRN < LID Switch > C645 17inch@ 0.1U_0402_16V4Z VOUT 17inch@ C647 10P_0402_50V8J LID_SW# SELF_TEST 34 2 G@ RG3 4.7K_0402_5% G@ RG4 4.7K_0402_5% Remove WiMAX LED control circuit C646 GND +3VS_HDP 16inch@ U36 APX9132ATI-TRL_SOT23-3 VDD +3VALW 16inch@ 0.1U_0402_16V4Z VOUT G@ RG5 4.7K_0402_5% 16inch@ C648 10P_0402_50V8J G@ CG7 0.1U_0402_16V4Z 34 2 G@ CG8 0.1U_0402_16V4Z HDPINT HDPINT G@ RG6 4.7K_0402_5% G@ RG7 1K_0402_5% 10 < HDD LED > P3_5/SSCK/SCL/CMP1_2 P1_6/CLK0/SSI01 P3_7/CNTR0#/SSO/TXD1 P1_5/RXD0/CNTR01/INT11# RESET# P1_4/TXD0 11 G@ 12 RG9 47K_0402_5% VDD 6,19,34 EC_SMB_CK2 34 13 HDPLOC 34 2 G@ UG2 17inch@ U34 APX9132ATI-TRL_SOT23-3 GND +3VALW Vf=2.0V (typ), 2.4 V (max), If = 30mA (max) HDPACT XOUT/P4_7 P1_3/KI3#/AN11/TZOUT VSS/AVSS P1_2/KI2#/AN10/CMP0_2 XIN/P4_6 P4_2/VREF VCC/AVCC P1_1/KI1#/AN9/CMP0_1 14 G@ VOUTZ 15 RG10 47K_0402_5% 2N7002_SOT23-3 Q20 16 +3VS_HDP VOUTX G@ 17 MODE P1_0/KI0#/AN8/CMP0_0 P4_5/INT0#/RXD1 P3_3/TCIN/INT3#/SSI00/CMP1_0 P1_7/CNTR00/INT10# P3_4/SCS#/SDA/CMP1_1 CG6 0.1U_0402_16V4Z VOUTY 18 19 20 EC_SMB_DA2 6,19,34 R5F211B4D31SP-PLSP0020JB-A SATA_LED# 22 R546 10K_0402_5% +3VS +3VS R548 120_0402_5% D46 HT-110UYG-CT_YEL/GRN < Touch/B Connector > < EMI reserve > Q18A 2N7002DW-T/R7_SOT363-6 +5VALW Q18B 2N7002DW-T/R7_SOT363-6 < WL&BT LED > C199 0.22U_0603_16V4Z C200 0.22U_0603_16V4Z C201 0.22U_0603_16V4Z C202 0.22U_0603_16V4Z C203 0.22U_0603_16V4Z 1.C199 : U19 2.C200 : PU5 3.Top side of PU12 for noise bounce 4.C202 : U25 5.C203 : PU9 1.U25 2.Botton side of JWLAN for keep noise return path 3.Top side of PU12 for noise bounce 4.Top side of PU5 for noise bounce 5.U19 WLAN@ D50 +3VS WLAN@ R550 120_0402_5% WL_BT_LED# 34 HT-110UD_1204_AMBER < BATT CHARGE/FULL LED > D70 < POWER-ON & SUSPEND LED > +3VALW R773 120_0402_5% < Ultra Bright Amber > +3VALW R770 120_0402_5% BATT_LOW_LED# 34 < Ultra Bright Amber > PWR_ON_LED# PWR_SUSP_LED# < Ultra Bright Yellow Green > 34 HT-210UD/UYG_AMB/GRN Vf=1.9V(typ),2.4V(max) for amber Vf=2.0V(typ),2.4V(max) for green If=30mA(max) < Ultra Bright Yellow Green > B 34 34 TP_CLK TP_DATA @ < SW/B Connector > JPOWER 1 2 3 4 5 6 7 8 9 10 10 11 GND 12 GND C686 220P_0402_50V7K EC_REVBTN# @ C699 220P_0402_50V7K EC_FRDBTN# @ C702 220P_0402_50V7K EC_PLAYBTN# @ C705 220P_0402_50V7K EC_MUTEBTN# @ C708 220P_0402_50V7K JPWR1 ON/OFFBTN# KSO0 EC_PLAYBTN# EC_REVBTN# EC_FRDBTN# EC_MUTEBTN# KSO0 KSI1 KSI3 KSI5 KSI2 2009-09-25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC C @ ACES_85201-0405N_4P @ ACES_85201-1005N_10P 2008-09-25 Issued Date ON/OFFBTN# JTOUCH 10 GND GND 33,34 33,34 33,34 33,34 33,34 D 10 11 12 ON/OFFBTN# KSO0 EC_PLAYBTN# EC_REVBTN# EC_FRDBTN# EC_MUTEBTN# @ ACES_88514-104N Compal Secret Data Security Classification 34 HT-210UD/UYG_AMB/GRN A BATT_FULL_LED# 34 D68 < For EMI > +5VS Title Compal Electronics, Inc LED/LID/PB/FB/SCREW HOLE Size Document Number Custom Date: Rev 1.0 LA-4971P Wednesday, April 22, 2009 Sheet E 35 of 45 A B < +5VALW TO +5VS > C < close to PQ20, must EMI confirm > D E < +1.8V TO +1.8VS > +5VALW +1.8V +5VALW C864 S S S G 1 C833 C835 Q4 IRF8736TRPBF_SO8 C204 0.1U_0402_16V7K RUNON SI4800BDY_SO8 1U_0402_6.3V4Z 4.7U_0805_10V4Z +3VS 4.7U_0805_10V4Z Inrush current = 0A C842 C848 1U_0402_6.3V4Z C841 10U_0805_10V4Z 4.7U_0805_10V4Z 1.8VS_ENABLE 1 R138 750K_0402_1% +VSB R809 10M_0402_5% D C849 SUSP G Q13 2N7002_SOT23-3 0.01U_0402_25V7K S 2 < close to PQ20, must EMI confirm > < +3VALW TO +3VS > 1 D D D D Inrush current = 0A Q35 +1.8VS +5VS +3VS +3VS Q14 C840 4.7U_0805_10V4Z D D D D S S S G Inrush current = 0A SI4800BDY_SO8 C839 1U_0402_6.3V4Z 2 C197 < +1.2VALW TO +1.2V_HT > 0.1U_0402_16V7K C838 +1.2VALW 4.7U_0805_10V4Z RUNON R152 750K_0402_1% +VSB 10M_0402_5% S 0.01U_0402_25V7K G Q17 2N7002_SOT23-3 C847 @ SUSP 1 + C862 4.7U_0805_10V4Z 1K_0402_5% R808 10M_0402_5% 2 < +3VALW TO +3V_LAN > +3VALW 1U_0402_6.3V4Z C876 470U_D2E_2.5VM_R9M R367 4.7U_0805_10V4Z +3VALW C846 R233 330K_0402_5% +VSB R556 @ D C834 Inrush current = 0A 1 +1.2V_HT Q11 IRF8736TRPBF_SO8 +3V_LAN +3VALW C837 0.01U_0402_25V7K Q12A 2N7002DW-T/R7_SOT363-6 Vgs=-4.5V, Id=3A VLDT_EN# Rds R17 SUSP SUSP Q142A 2N7002DW-7-F_SOT363-6 SUSP# VLDT_EN# 42 EC_ON# Q142B 2N7002DW-7-F_SOT363-6 27,34,42 SYSON 1 SYSON# SYSON# 1U_0402_6.3V4Z 34 VLDT_EN 19,27,30,34,39,41 VLDT_EN Q143A 2N7002DW-7-F_SOT363-6 42 C680 Q143B 2N7002DW-7-F_SOT363-6 EC_ON 34,35 1 Inrush current = 0A 4.7U_0805_10V4Z R598 100K_0402_5% R597 100K_0402_5% 100K_0402_5% C679 R596 +5VL 1 @ +5VL 1 R595 100K_0402_5% Q38 AO3413_SOT23 0.01U_0402_25V7K C182 +5VL PJ29 JUMP_43X79 +5VL @ 1 R19 47K_0402_5% G WOL_EN# WOL_EN# D 34 C194 0.1U_0402_16V7K S 100K_0402_5% +1.5VS +1.1VS R293 R294 470_0805_5% 470_0805_5% 470_0805_5% 2N7002_SOT23-3 EC_ON# S @ SUSP Q42 2N7002_SOT23-3 D S SYSON# Q47 G 2N7002_SOT23-3 D S Q49 G 2N7002_SOT23-3 SUSP 1 1 D G D S SUSP Q50 G Q41 D S D G SYSON# 1 2N7002DW-T/R7_SOT363-6 R292 470_0805_5% VLDT_EN# R288 2N7002_SOT23-3 R368 470_0805_5% Q48 S G D Q12B 2N7002_SOT23-3 1 SUSP Q46 S 3 1 D G +0.9V @ 470_0805_5% 470_0805_5% R280 470_0805_5% R279 470_0805_5% R239 R284 SUSP +3VS +1.2VALW +1.8V 2 +1.2V_HT +1.8VS +5VS < Discharge circuit > S Q52 G 2N7002_SOT23-3 2N7002_SOT23-3 4 Compal Secret Data Security Classification 2008-09-25 Issued Date 2009-09-25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C D Title Compal Electronics, Inc DC/DC Circuits Size Document Number Custom Date: Rev 1.0 LA-4971P Wednesday, April 22, 2009 Sheet E 36 of 45 A B C D VS VIN SMB3025500YA_2P 1 PR2 5.6K_0402_5% + 39 LM393DG_SO8 PD1 GLZ4.3B_LL34-2 PR7 10K_0402_1% PR8 10K_0402_1% RTCVREF Vin Detector 3.3V VIN 2 PC6 1U_0402_16V7K PR6 20K_0402_1% 22,34,35 PACIN PACIN G - 1 PC5 0.068U_0402_10V6K ACIN PU1A O @ SINGA_2DW-0005-B03 PR4 10K_0402_1% P PR5 22K_0402_1% 2 PC4 100P_0402_50V8J PC3 1000P_0402_50V7K - PC2 100P_0402_50V8J - PC1 1000P_0402_50V7K N1 PR3 84.5K_0402_1% 2 + 10A_125V_451010MRL 1 + DC_IN_S2 1 DC_IN_S1 PJP1 PR1 1M_0402_1% VIN PL1 PF1 DC301001M80 High 18.384 17.901 17.430 Low 17.728 17.257 16.976 PR9 68_1206_5% PQ1 TP0610K-T1-E3_SOT23-3 PR11 200_0603_5% N1 VS CHGRTCP PR10 68_1206_5% RLS4148_LL34-2 2 BATT+ 1 PD2 RLS4148_LL34-2 PD3 PR12 1K_1206_5% PD4 VIN PR15 22K_0402_1% PR14 1K_1206_5% N3 RLS4148_LL34-2 B+ PR16 1K_1206_5% RTC Battery - PR18 200_0603_5% PR17 499K_0402_1% RTCVREF @ PR25 66.5K_0402_1% PC13 1000P_0402_50V7K PR23 10K_0402_1% - PR24 499K_0402_1% PR26 191K_0402_1% PC11 1000P_0402_50V7K PC12 1000P_0402_50V7K + O LM393DG_SO8 PU1B ACON 39 SP093MX0000 EN0 1U_0805_25V4Z 6,40 PD5 RB715F_SOT323-3 @ MAXEL_ML1220T10 PC10 P N2 PR20 2.2M_0402_5% G PR19 100K_0402_1% VL +RTCBATT IN GND +RTCBATT OUT PC9 10U_0805_10V4Z + PBJ1 2 3.3V G920AT24U_SOT89-3 PU2 PR22 560_0603_5% +CHGRTC PR21 560_0603_5% 2 RTCVREF 51_ON# 35 PC7 0.22U_1206_25V7K PC8 0.1U_0603_25V7K 2 PR13 100K_0402_1% 2 3 PR27 47K_0402_1% D PJ2 2 1 +3VALW +1.8VP @ JUMP_43X118 OCP(min) = 8.87A +5VALW +NB_COREP +NB_CORE ( 7A, 280mils , Via NO.=14 ) OCP(min) = 7.9A OCP(min) = 8.45A +VSB +1.2VALWP 1 @ JUMP_43X118 +1.2VALW 2 +VDDNBP 1 +VDDNB @ JUMP_43X79 (3A, 120mils, Via NO.= 6) 1 +5VALWP PQ3 DTC115EUA_SC70-3 +5VL Precharge detector 15.97V/14.84V FOR ADAPTOR +2.5VS (0.5A,20mils ,Via NO.= 1) OCP(min) = 8.51A +1.5VSP 2 +1.5VS Issued Date Compal Electronics, Inc Compal Secret Data Security Classification @ JUMP_43X79 A 2 @ JUMP_43X39 +2.5VSP (5A,200mils ,Via NO.=10) +0.9V (2A,80mils ,Via NO.= 4) +3VL (100mA,40mils ,Via NO.= 2) PJ12 @ JUMP_43X79 PJ7 PJ11 2 VL PJ9 @ JUMP_43X39 PJ10 @ JUMP_43X39 (5A,200mils ,Via NO.= 10) 2 PACIN G PQ2 SSM3K7002FU_SC70-3 PJ4 @ JUMP_43X118 (120mA,40mils ,Via NO.= 1) +0.9VP (100mA,40mils ,Via NO.= 2) PJ6 PJ8 +VSBP OCP(min) = 7.7A +3VLP @ JUMP_43X39 (8A,320mils ,Via NO.= 16) @ JUMP_43X118 +1.8V @ JUMP_43X118 (5A,200mils ,Via NO.= 10) PJ5 +5VALWP S PJ23 PJ1 +3VALWP @ JUMP_43X118 PJ3 2 2008/9/25 Deciphered Date 2009/9/25 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC (2A,80mils ,Via NO.=4) B C Title DCIN & DETECTOR Size Document Number Rev 0.1 LA-4971P Date: Sheet Wednesday, April 22, 2009 D 37 of 46 A B C D PH1 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 56 degree C VMB Liverpool PF2 15A_65V_451015MRL PJP2 VL PL2 SMB3025500YA_2P PR31 47K_0402_1% 40 P - PD6 O ENTRIP2 6,40 RLS4148_LL34-2 VL D S PQ5 SSM3K7002FU_SC70-3 G PR38 100K_0402_1% 1 PC18 1000P_0402_50V7K PR36 13.7K_0402_1% PQ4 SSM3K7002FU_SC70-3 LM393DG_SO8 PR40 100K_0402_1% +3VLP PR37 6.49K_0402_1% S PU3A + PC17 0.22U_0805_16V7K BATT_S1 G 2 2 PJP3 BATT_P3 BATT_P4 BATT_P5 EC_SMDA EC_SMCA TM_REF1 PR35 100_0402_1% Sunderland PR33 13.7K_0402_1% D G PC16 0.1U_0603_25V7K PR30 47K_0402_1% PH1 100K_0603_1%_TH11-4H104FT PC15 0.01U_0402_25V7K PC14 1000P_0402_50V7K +3VLP PR29 47K_0402_1% PR32 1K_0402_1% 1 2 3 4 5 10 GND 11 GND 12 GND 13 GND OCTEK_BTJ-09HA1G_9P @ ENTRIP1 1 PR28 1K_0402_1% 1 BATT_P3 BATT_P4 BATT_P5 EC_SMDA EC_SMCA PR34 100_0402_1% PR39 1K_0402_1% 2 VL VL BATT+ 2 10 GND 11 GND 12 GND 13 GND OCTEK_BTJ-09HA1G_9P @ BATT_S1 1 BATT_TEMPA 34 EC_SMB_DA1 18,34 EC_SMB_CK1 18,34 PH2 near main Battery CONN : BAT thermal protection at 92 degree C Recovery at 56 degree C VL P + - PU3B PD7 O G TM_REF1 PR46 15.4K_0402_1% 2 PC21 0.22U_0805_16V7K RLS4148_LL34-2 LM393DG_SO8 D PR48 0_0402_5% S PQ7 SSM3K7002FU_SC70-3 G 1 @ PC22 1U_0402_16V7K POK PR42 47K_0402_1% PR44 13.7K_0402_1% PR47 100K_0402_1% 40,41 PR41 47K_0402_1% PH2 100K_0603_1%_TH11-4H104FT 1 @ PC19 0.22U_1206_25V7K 2 PR43 100K_0402_1% PR45 22K_0402_1% VL +VSBP @ PC20 0.1U_0603_25V7K B+ VL PQ6 TP0610K-T1-E3_SOT23-3 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2008/9/25 Deciphered Date 2009/9/25 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title BATTERY CONN / OTP Size Document Number Rev 0.1 LA-4971P Date: Wednesday, April 22, 2009 Sheet D 38 of 46 B 2 B+ CHG_B+ PL17 HCB4532KF-800T90_1812 PR49 0.015_2512_1% CSIN PQ11 2 CSIN VCOMP CSIP ICM PHASE 1 1SS355_SOD323-2 20 19 10 VREF UGATE CHLIM BOOT ACLIM VDDP PR69 2.2_0603_5% BST_CHG 16 11 PR73 20K_0402_1% 12 VADJ LGATE GND PGND PQ20 AO4466_SO8 DL_CHG 14 13 26251VDD 2CHG PR66 0.02_2512_1% PR170 4.7_1206_5% PC39 0.1U_0603_25V7K BST_CHGA 1 PACIN G PQ17 SSM3K7002FU_SC70-3 PL3 10U_LF919AS-100M-P3_4.5A_20% PD12 RB751V-40TE17_SOD323-2 6251VDDP 15 S DH_CHG 17 PQ18 AO4466_SO8 PR64 2.2_0603_5% LX_CHG 18 D PC31 0.1U_0603_25V7K CSOP 21 CSON PR70 53.6K_0402_1% 6251VREF 6251aclim 2 BATT+ PC129 680P_0603_50V7K 1 PR60 20_0603_5% PC32 0.047U_0603_16V7K PR61 20_0603_5% PR62 PC35 20_0603_5% 0.1U_0603_25V7K PR72 4.7_0603_5% PC43 4.7U_0805_6.3V6K ICOMP 22 PR71 100K_0402_1% CSOP VIN PD11 ADP_I PC42 0.01U_0402_25V7K ACOFF CELLS PR55 200K_0402_1% 23 CSON PQ14 DTC115EUA_SC70-3 PR68 34 154K_0402_1% 1 IREF ACOFF PC41 10U_1206_25V6M PR65 47K_0402_1% PC38 1U_0402_16V7K 34 PD8 1SS355_SOD323-2 PC40 10U_1206_25V6M 6251VREF ACOFF VIN 6.81K_0402_1% EN @ PC30 0.1U_0603_25V7K ACSET ACPRN DCIN 24 6800P_0402_25V7K 2 PC37 @ 100P_0402_50V8J PR52 10K_0402_1% SUSP# 19,27,30,34,36,41 3 DCIN PR63 0.01U_0402_25V7K 6251_EN VDD S PC36 PU4 1 PQ19 SSM3K7002FU_SC70-3 34 1 D PR67 22K_0402_5% PQ21 DTC115EUA_SC70-3 PR51 47K_0402_1% 2 FSTCHG 2 PC34 1 ACON @ PQ45 AO4407A_SO8 RB715F_SOT323-3 PC33 @ 680P_0402_50V7K 2 G PR59 100K_0402_1% PC29 1U_0402_16V7K PR58 150K_0402_1% S 1 FSTCHG CSON 37 PQ13 DTC115EUA_SC70-3 6251VDD PR57 10K_0402_1% PC28 2.2U_0603_6.3V6K 1 34 PQ16 SSM3K7002FU_SC70-3 PACIN DCIN PR56 100K_0402_1% 2 PD10 1SS355_SOD323-2 D PACIN PR203 10_0603_5% 90W 4407A*1 120W 4407A*2 PD9 PQ15 DTC115EUA_SC70-3 G 1 P3 PR54 100K_0402_1% 37 TP0610K-T1-E3_SOT23-3 1 PC26 5600P_0402_25V7K PC27 0.1U_0603_25V7K PR53 47K_0402_1% PR50 200K_0402_1% PQ12 DTA144EUA_SC70-3 CSIP 1 PQ10 AO4407A_SO8 P3 4 VIN PQ9 AO4407A_SO8 D PC23 10U_1206_25V6M P2 PQ8 AO4407A_SO8 C PC24 10U_1206_25V6M A ISL6251AHAZ-T_QSOP24 34 CHGVADJ PR74 287K_0402_1% 3 PR49=0.02, PR70=75k, PR73=20k Iada=0~3.947A(75W) CP=3.63A PR49=0.02, PR70=24k, PR73=20k Iada=0~4.737A(90W) CP=4.36A PR49=0.015, PR70=53.6k, PR73=20k Iada=0~6.316A(120W) CP=5.81A PR49=0.015, PR70=8.25k, PR73=26.7k PR75 499K_0402_1% VIN CP=3.15A Iada=0~3.421A(65W) CP= 92%*Iada PR171 309K_0402_1% PR202 10K_0402_1% PR172 47K_0402_1% IREF=1.016*Icharge Vcell IREF=0.254V~3.048V 4V VCHLIM need over 95mV 4.2V 1.882V 4.35V 3.2935V CELLS CELL number PC130 1U_0402_16V7K CHGVADJ=(Vcell-4)/0.10627 CC=0.25A~3A ADP_V 34 2 @ PD14 GLZ4.3B_LL34-2 1 Iinput=(1/PR49)((0.05*Vaclm)/2.39+0.05) where Vaclm=1.09986V, Iinput=3.65A Vaclm=0.7717V, Iinput=4.41A Vaclm=0.4204V, Iinput=5.88A CP mode Vaclim=2.39*(Rb//152K/(Rt//152K+Rb//152K)) VDD GND CHGVADJ 0V Float - Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2008/9/25 Deciphered Date 2009/9/25 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Title CHARGER Size Document Number Custom Date: Rev 0.1 LA-4971P Wednesday, April 22, 2009 D Sheet 39 of 46 AO4712 Rds(on) = 15/18 2VREF_51125 5VALWP Imax = 5A Ipeak = 7A Iocp = 8.59A PC44 0.22U_0603_10V7K 3.3VALWP Imax = 5A Ipeak = 7A Iocp = 8.59A D D OCP = 7.94A PC47 4.7U_1206_25V6K 1 LX_5V f = 245kHz TPS51125RGER_QFN24_4X4 + PQ25 AO4712_SO8 @ PC57 680P_0603_50V7K PC55 220U_6.3VM_R15 LG_5V @ PR85 4.7_1206_5% 19 +5VALWP 20 PL6 4.7U_LF919AS-4R7M-P3_5.2A_20% VCLK VREG5 ESR=15m VL 1 PR88 @ 0_0402_5% S 2VREF_51125 VL 21 22 PR86 499K_0402_1% PQ27 SSM3K7002FU_SC70-3 3 S 18 17 VIN 16 14 GND DRVL1 D G LL1 PC53 PR83 0.1U_0402_16V7K BST_5V 2 0_0603_1% UG_5V 23 DRVH1 PC59 0.1U_0603_25V7K 1 G VFB1 DRVH2 B++ D PQ26 SSM3K7002FU_SC70-3 ENTRIP1 VBST1 13 EN0 6,38 VBST2 ENTRIP2 VREF PGOOD EN0 38 TONSEL VO1 VREG3 DRVL2 38,41 24 B PC58 4.7U_0805_10V6K ENTRIP1 C POK LL2 12 PQ22 AO4466_SO8 6,37 B+ B 11 ESR=15m 10 LX_3V LG_3V 2 UG_3V f = 305kHz PR87 100K_0402_1% @ PC56 680P_0603_50V7K + PR81 150K_0402_1% VO2 BST_3V 15 1 PC54 220U_6.3VM_R15 PQ24 AO4712_SO8 @ PR84 4.7_1206_5% ENTRIP1 ENTRIP2 PC52 0.1U_0402_16V7K PR82 21 0_0603_1% +3VALWP P PAD VFB2 25 ENTRIP2 PL5 4.7U_LF919AS-4R7M-P3_5.2A_20% 1 PU5 SKIPSEL C PR80 150K_0402_1% B++ PC51 4.7U_0805_10V6K PC49 4.7U_1206_25V6K PC50 4.7U_1206_25V6K +3VLP PQ23 AO4466_SO8 PR79 20K_0402_1% PC45 2200P_0402_50V7K PR78 20K_0402_1% B++ PL18 HCB4532KF-800T90_1812 B+ PC48 2200P_0402_50V7K PR77 30K_0402_1% PC46 4.7U_1206_25V6K PR76 13K_0402_1% 1 VS D PR89 100K_0402_1% S PQ28 SSM3K7002FU_SC70-3 G PR90 100K_0402_1% PR91 49.9K_0402_1% A A Compal Electronics, Inc Compal Secret Data Security Classification 2008/9/25 Issued Date Deciphered Date 2009/9/25 Title 3VALWP/5VALWP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Size Document Number Custom Date: Rev 0.1 LA-4971P Wednesday, April 22, 2009 Sheet 40 of 46 PL19 HCB4532KF-800T90_1812 PR94 0_0603_1% V5DRV 10 PR97 15.4K_0402_1% DL_NB +5VALW PQ30 AO4712_SO8 11 TPS51117RGYR_QFN14_3.5x3.5 @ PC68 47P_0402_50V8J DRVL PGND PGOOD GND PC65 1U_0603_10V6K LX_NB 12 PC67 4.7U_0805_10V6K PR98 9.53K_0402_1% + 2 C C +NB_COREP PC64 220U_6.3VM_R15 VFB 13 TRIP DRVH LL V5FILT PR95 4.7_1206_5% 14 15 VOUT TON 0.1U_0603_25V7K BST_NB DH_NB +1.1V PL7 1.8UH_SIL104R-1R8PF_9.5A_30% PC63 VBST PR96 422_0603_1% +5VALW TP PU6 EN_PSV PC62 1U_0402_16V7K PC66 680P_0603_50V7K PR93 33K_0402_1% SUSP# D 19,27,30,34,36,39 B+ PC61 4.7U_1206_25V6K PQ29 AO4466_SO8 PR92 255K_0402_1% PC60 4.7U_1206_25V6K NB_B+ D PR99 20.5K_0402_1% PL20 HCB4532KF-800T90_1812 PR100 255K_0402_1% VFB V5DRV 11 10 PR105 15.4K_0402_1% DRVL DL_1.2V +5VALW PC173 100U_25V_M 1 PQ32 AO4712_SO8 PR103 4.7_1206_5% PGND GND @ PC77 47P_0402_50V8J 2 PC74 1U_0603_10V6K PGOOD 2 TRIP 0.1U_0603_25V7K LX_1.2V 12 TPS51117RGYR_QFN14_3.5x3.5 PC76 4.7U_0805_10V6K + PR106 12.1K_0402_1% 2 V5FILT DH_1.2V 13 LL DRVH +1.2VALWP PC73 220U_6.3VM_R15 14 VBST 15 VOUT TON PC75 680P_0603_50V7K 3 PL8 2.2UH_PCMC063T-2R2MN_8A_20% PC72 BST_1.2V PR104 422_0603_1% PU7 +5VALW B @PC71 @PC71 1U_0402_16V7K TP 0_0402_5% + 2 EN_PSV B 1 POK B+ PR102 0_0603_1% PR101 38,40 PC70 4.7U_0805_25V6-K PQ31 AO4466_SO8 PC69 4.7U_0805_25V6-K 1.2V_B+ PR107 20.5K_0402_1% A A Compal Secret Data Security Classification 2008/9/25 Issued Date 2009/9/25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc NB_COREP/1.2VALWP Size Document Number Rev 0.1 LA-4971P Date: Wednesday, April 22, 2009 Sheet 41 of 46 PL21 HCB4532KF-800T90_1812 V5DRV 10 PR113 15.4K_0402_1% DRVL DL_1.8VP PQ34 AO4712_SO8 PGND TPS51117RGYR_QFN14_3.5x3.5 @ PC85 47P_0402_50V8J 2 PC83 1U_0603_10V6K PGOOD GND +5VALW PC86 4.7U_0805_10V6K +1.8VP PC82 220U_6.3VM_R15 11 TRIP VFB LX_1.8VP V5FILT 12 PR111 4.7_1206_5% 14 15 VBST LL DRVH VOUT 0.1U_0603_25V7K TON DH_1.8VP +5VALW PL9 1.8UH_SIL104R-1R8PF_9.5A_30% PC81 BST_1.8VP 13 PR112 422_0603_1% TP PU8 EN_PSV @ PC80 1U_0402_16V7K D PR110 0_0603_1% 27,34,36 SYSON PR109 0_0402_5% PC84 680P_0603_50V7K D B+ PC79 4.7U_1206_25V6K PQ33 AO4466_SO8 PR108 255K_0402_1% PC78 4.7U_1206_25V6K 51117_B+ + PR114 28.7K_0402_1% C C PR115 20.5K_0402_1% +1.8V 1 PJ17 @ JUMP_43X79 PJ18 @ JUMP_43X79 PR116 1.2K_0402_1% NC TP B PC88 1U_0603_6.3V6M PC89 4.7U_0805_6.3V6K VIN VCNTL GND NC +3VALW VOUT PU10 PR117 1K_0402_1% VREF NC VOUT NC APL5331KAC-TRL_SO8 NC +5VALW VREF NC VCNTL GND VIN 2 PU9 PC87 4.7U_0805_6.3V6K 2 1 +3VS TP PC90 1U_0603_6.3V6M B PC91 1U_0402_16V7K S PQ36 SSM3K7002FU_SC70-3 2 IN PC94 10U_0805_6.3V6M OUT +2.5VSP GND 2 PC97 1U_0603_10V6K PC98 4.7U_0805_6.3V6K A Compal Secret Data Security Classification 2008/9/25 Issued Date 2009/9/25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 1 G @ PC96 1U_0402_16V7K SYSON# +0.9VP 2 2 36 PC93 10U_0805_6.3V6M PR119 1K_0402_1% 1 1 PC92 PQ35 1U_0402_16V7K SSM3K7002FU_SC70-3 D PU11 APL5508-25DC-TRL_SOT89-3 @ JUMP_43X39 A PR121 0_0402_5% 1 S G PJ19 +3VS +1.5VSP @ PC95 1U_0402_16V7K SUSP SUSP 36 PR118 D 1K_0402_1% APL5331KAC-TRL_SO8 PR120 0_0402_5% Title Compal Electronics, Inc 1.8VP/0.9VP/1.5VSP2.5VSP Size Document Number Rev 0.1 LA-4971P Date: Wednesday, April 22, 2009 Sheet 42 of 46 E PC109 0.1U_0603_25V7K UGATE1 25 BOOT1 COMP0 PC122 180P_0402_50V8J PC127 PC136 0.1U_0402_25V6 PC135 0.1U_0402_25V4K PC134 0.1U_0402_25V4K PC133 0.1U_0402_25V4K PC132 0.1U_0402_25V4K PC170 4.7U_0805_25V6-K 1 COMP1 PC125 180P_0402_50V8J 2 PC172 4.7U_0805_25V6-K UGATE1 1 @ JUMP_43X118 +CPU_CORE_0 +CPU_CORE_1 PJ21 2 1 @ JUMP_43X118 PL13 0.36UH_PCMC104T-R36MN1R17_30A_20% PR155 4.7_1206_5% PR156 3.65K_0402_1% PC119 680P_0603_50V7K 1 +CPU_CORE_1 1 PC118 0.22U_0603_10V7K PC120 0.1U_0603_16V7K LGATE1 PR166 1 PR159 47K_0402_1% PC126 1000P_0402_50V7K PR167 6.81K_0402_1% PC128 1 54.9K_0402_1% 1200P_0402_50V7K PR168 @ 36.5K_0402_1% PR169 @ 36.5K_0402_1% Compal Secret Data Security Classification 2008/9/25 Issued Date 2009/9/25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A PC169 4.7U_0805_25V6-K PC111 4.7U_0805_25V6-K 1 2 5 49 PQ42 TPCA8023-H_SO8 VW1 PR165 1K_0402_5% 54.9K_0402_1% 1200P_0402_50V7K PJ20 PC123 1000P_0402_50V7K PR164 6.81K_0402_1% 2 PR163 1 PR147 47K_0402_1% PR157 0_0402_5% VSEN1 DIFF_1 2 PHASE1 PR161 PC124 255_0402_1% 4700P_0402_25V7K FB_1 2 PC114 ISP1 VW0 PR143 3.65K_0402_1% CPU_B+ DIFF_0 +CPU_CORE_0 0.1U_0603_16V7K LGATE0 PR152 0_0603_1% BOOT1 2 ISN0 26 PC115 1U_0603_10V6K ISN1 PHASE1 PC113 680P_0603_50V7K ISP0 27 28 PQ41 TPCA8028-H_SOP-ADVANCE8-5 LGATE1 29 30 PR141 4.7_1206_5% CPU_VDD1_RUN_FB_H LGATE0 31 +1.8V +5VS 0_0402_5% PHASE0 32 @ PQ40 TPCA8028-H_SOP-ADVANCE8-5 UGATE0 33 PC112 0.22U_0603_10V7K TP ISN1 ISP1 24 23 ISP1 34 ISN1 VW1 COMP1 22 FB1 21 14 BOOT1 BOOT0 PC171 4.7U_0805_25V6-K UGATE1 35 PL12 0.36UH_PCMC104T-R36MN1R17_30A_20% PC117 4.7U_0805_25V6-K COMP0 BOOT_NB PC116 4.7U_0805_25V6-K PHASE1 VW0 PR138 0_0603_1% BOOT0 PQ43 TPCA8028-H_SOP-ADVANCE8-5 PR151 PR162 1K_0402_5% PC101 220U_25V_M PQ39 TPCA8023-H_SO8 PC110 4.7U_0805_25V6-K 37 PGND1 FB0 36 1RTN1 CPU_VDD1_RUN_FB_L 38 LGATE1 VDIFF0 13 CPU_VDD0_RUN_FB_L PR160 PC121 255_0402_1% 4700P_0402_25V7K FB_0 2 PC100 220U_25V_M CPU_VDDNB_RUN_FB_L @ PR173 10K_0402_1% CPU_VDD0_RUN_FB_H UGATE_NB 39 OCSET ISP0 ISN0 PR149 0_0402_5% VSEN0 0_0402_5% PR150 RTN0 PHASE_NB 40 42 43 44 41 PGND_NB OCSET_NB RTN_NB VSEN_NB 45 FB_NB FSET_NB LGATE_NB PVCC ISL6265HRTZ-T_QFN48_6X6 ISP0 12 RBIAS 20 11 LGATE0 VDIFF1 10 ENABLE VSEN1 PGND0 19 SVC 18 PHASE0 RTN1 PR146 4.02K_0402_1% UGATE0 SVD RTN0 PR144 0_0402_5% PWROK VSEN0 17 34 VR_ON BOOT_NB BOOT0 16 PC107 220U_D2_4VM PHASE0 PGOOD ISN0 PR142 0_0402_5% OFS/VFIXEN 15 ISL6265_PWROK COMP_NB VCC 46 47 48 VIN CPU_SVD CPU_SVC PR145 113K_0402_1% + CPU_B+ PU12 6 2 1 2 21,34 SB_PWRGD PC108 680P_0603_50V7K LGATE_NB UGATE0 @ PR139 0_0402_5% PR140 0_0402_5% UGATE_NB PR133 0_0402_5% EMC +VDDNBP PHASE_NB PR132 @ 105K_0402_1% PR137 @ 105K_0402_1% 6,20 H_PWRGD PR125 4.7_1206_5% PR135 @ 10K_0402_1% PR134 105K_0402_1% VGATE PQ38 AO4712_SO8 34 B+ PHASE_NB PR131 0_0402_5% PR130 9.09K_0402_1% + PL11 4.7U_LF919AS-4R7M-P3_5.2A_20% 2 PC106 0.22U_0603_10V7K CPU_VDDNB_RUN_FB_H +3VS +5VS PR128 2_0603_5% 2 CPU_B+ PR129 0_0402_5% 2 + PR124 2.2_0603_1% BOOT_NB 1 PQ37 AO4466_SO8 PHASE_NB PR126 22K_0402_1% LGATE_NB PC103 10U_1206_25V6M UGATE_NB PC104 1000P_0402_50V7K PC105 0.1U_0603_16V7K +5VS 1 2 PC102 1000P_0402_50V7K 1 PR122 44.2K_0402_1% PR123 2_0603_5% PC99 33P_0402_50V8K PL10 HCB4532KF-800T90_1812 PC138 0.1U_0402_25V6 D CPU_B+ PC137 0.1U_0402_25V6 C PC131 0.1U_0402_25V4K B PQ44 @ TPCA8028-H_SOP-ADVANCE8-5 A B C D Title Compal Electronics, Inc +CPU_CORE Size Document Number Custom Date: Rev 0.1 LA-4971P Wednesday, April 22, 2009 Sheet E 43 of 46 A B C D E Version Change List ( P I R List ) for Circuit Item Page# Title Request Owner Date Issue Description Rev Solution Description 2009/02/23 > change R70, R77 from 4.7K to 2.2K 2009/02/23 > change R178 from 4.7K to 47K 2009/02/26 > change SPI ROM from SST to MXIC 2009/02/26 > change D36 from ROHM to PANJI 2009/02/27 > change the footprint of T9, T10, T11, T12, T19, T20 from TPC12 to TPC24 2009/02/27 > change 5V power of LCD connector 2009/03/02 > unmount R556 2009/03/04 > change RA16 from 5% to 1% 2009/03/10 > change R146 from 100k ohm to 10k ohm 10 2009/03/10 > change Y2 from SJ114P3M730 to SJ114P3MG00 11 2009/03/11 > change C686, C699, C702, C705, C706, C708, CA27 from SE074221K00SE to SE074221K80 for Green part 12 2009/03/11 > change LAN_WAKE# & EC_SWI# 13 2009/03/11 > unmount USB sleep & charge, add R97 & R98 14 2009/03/11 > unmount HDMI CEC controller and related components 15 2009/03/11 > connect USB_OC#0 to LAN_WAKE# through ohm 16 2009/03/12 > change H42 from NPH to PH 17 2009/03/12 > add PR203 10Ohm 18 2009/03/24 > change F2 footprint to F_MINISMDC110F-2 19 2009/03/24 > Add R370 & R381 20 2009/03/24 > change R557’s BOM structure from H@ to @ 21 2009/03/24 > change R440 from ohm to 100k ohm 22 2009/03/31 > Replace PJ13, PJ30, PJ14, PJ15, PJ16 by PL17, PL18, PL19, PL20, PL21 23 2009/04/02 > Add R969 on E51_TXD 24 2009/04/02 > Modify +HDMI_5V_OUT Circuit Remove Q159, R160, Q26, R557, C876 and add D19 25 2009/04/02 > Change R440 from 100k to for Askey BT Reset 26 2009/04/02 > Change C480's BOM Stuucture from BT@ to @ 27 2009/04/06 > Change SW5's BOM Stuucture to @ for MP 28 2009/04/06 > Add C876 for Power noise issue 29 2009/04/06 > Add D20 for Power issue 30 2009/04/17 > Change D12's BOM Stuucture to @ 31 2009/04/22 > Change C876 & C234 from 330u to 470u (SGA00001U00) for Power noise issue 3 4 Compal Secret Data Security Classification 2008/9/25 Issued Date 2009/9/25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C 12 52 D VGA_CORE 1/2 Compal Title Compal Electronics, Inc List History Size Document Number Custom Date: Rev 1.0 LA-4971P Wednesday, April 22, 2009 Sheet 44 of 45 E for EMI requset Add PR7 HW4 Product Improvement Record (P.I.R.) D < Liverpool & Sunderland > < R1 for customer BOM STRUCTURE > < R3 for mass production BOM STRUCTURE > U3 RS780MN < Tigris > < R1 for customer BOM STRUCTURE > U3 < R3 for mass production BOM STRUCTURE > U3 RS780MN RS780MNR1@ RS780MN R1 D RS880MN RS780MNR3@ RS780MN R3 RS880MNR1@ U3 RS880MN RS880MN R1 U3 RS780MC RS880MC RS780MCR1@ RS780MC R1 RS880MCR1@ U3 RX781 U3 RS880MC RS880MC R1 U3 RX781 RX881 RX881 C C RX781R1@ RX781 R1 RX781R3@ RX781 R3 RX881R1@ U15 RX881 R1 U15 SB700 SB710 SB700R1@ SB700R1 SB710 SB710R1@ SB710 R1 < DC Jack > Use MEMO : change UG1 R5F211B4D31SP (SA000037Y60) to R5F211B4D34SP (SA00003A600) PJP1 DC-IN 16inch_45@ PJP1 PJP1 B B DC-IN 17inch_45@ PJP1 < PCB > ZZZ PCB PCB 075 LA-4971P LS-4971P/4972P/4973P REV1.0 M/B A A 2008-09-25 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2009-09-25 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title PIR Size Date: Document Number Rev 1.0 Wednesday, April 22, 2009 Sheet 45 of 45 ... 2 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J... 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J 10 0P _04 02_50V8J... 99 10 1 10 3 10 5 10 7 10 9 11 1 11 3 11 5 11 7 11 9 12 1 12 3 12 5 12 7 12 9 13 1 13 3 13 5 13 7 13 9 14 1 14 3 14 5 14 7 14 9 15 1 15 3 15 5 15 7 15 9 16 1 16 3 16 5 16 7 16 9 17 1 17 3 17 5 17 7 17 9 18 1 18 3 18 5 18 7 18 9 19 1 19 3 19 5