A B C D E 1 Compal Confidential 2 KALH0 /KAL90+ /KALG0 M/B Schematics Document Intel Penryn Processor with Cantiga + DDRIII + ICH9M 2009-3-4 3 REV:1.0 4 2008/11/24 Issued Date 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Compal Electronics, Inc Compal Secret Data Security Classification D Title Size Document Number Custom Date: Cover Page KALH0/KALG0/KAL90+ Monday, April 27, 2009 E Sheet Rev 1.0 of 53 A B Compal Confidential C Intel Penryn Processor Fan Control Model Name : KALH0/KALG0/KAL90+ D page 40 uPGA-478 Package (Socket P) page HDMI Conn LCD Conn page 24,30 page 22 page 23 LVDS TMDS Memory BUS(DDRIII) 204pin DDRIII-SO-DIMM X2 Dual Channel DMI USB conn x3 C-Link page 17,18,19,20,21 PCI-Express Intel ICH9-M LAN(GbE) MINI Card x2 WLAN, Robson2 Bluetooth Conn CMOS Camera Finger Print page 34 page 35 page 22 AES1610 3.3V 48MHz USB page 32 page 34 page 25,26,27,28 GMCH HDA page 35 port RJ45 ESATA Conn page 35 page 33 HD Audio BGA-676 New Card Socket LS-4494P USB port 0, 2, 3.3V 24.576MHz/48Mhz S-ATA ATHEROS AR8121 page 13,14 page 7,8,9,10,11,12,13 page 31 BANK 0, 1, 2, 1.5V DDRIII 800/1066 16X VGA page 16 uFCBGA-1329 PCI-Express Card Reader JMB385 ICS9LPRS387 H_D#(0 63) Intel Cantiga LVDS Clock Generator EMC 1402 4,5,6 667/800/1066MHz CRT Conn Thermal Sensor page FSB H_A#(3 35) E port port CDROM Conn page 29 SATA HDD Conn page 29 MDC 1.5 Conn page 38 page 08 HDA Codec VGA HDA ALC888S-VC page 39 page 18 Audio AMP LPC BUS page 40 3 Phone Jack x3 ENE KB926 page 40 page 36 RTC CKT page 38 KALG0 page 38 DC/DC Interface CKT page 44 Power Circuit DC/DC page 44,45,46,47,48 ,49,50,51 Int.KBD Touch Pad Media/B Conn Power On/Off CKT KAL90+ LS-4493P LS-4498P FUN Conn KALH0 page 37 LS-4495P EC I/O Buffer USB/B Conn USB port LS-4492P LS-4495P page 37 USB/B Conn USB port BIOS page 37 LS-4921P page 37 FUN Conn LS-5042P E_KEY/B Conn LED/B Conn LS-4495P FINGERPRINT/Comm page 38 LS-5041P USB/B Conn LS-4494P CIR Media/B Conn USB port POWER SW 2008/11/24 Issued Date 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Compal Electronics, Inc Compal Secret Data Security Classification Page 43 D Title Size B Date: Document Number Block Diagrams KALH0/KALG0/KAL90+ Monday, April 27, 2009 E Sheet Rev 1.0 of 53 A B C STATE Voltage Rails E SLP_S1# SLP_S3# SLP_S4# SLP_S5# Full ON +VALW +V +VS HIGH HIGH HIGH HIGH ON ON ON Clock ON Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF B+ AC or battery power rail for power circuit N/A N/A N/A +CPU_CORE Core voltage for CPU ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF +0.75VS 0.75V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF +1.05VS 1.05V switched power rail ON OFF OFF +1.25VS 1.25V switched power rail ON OFF OFF +1.5V 1.5V power rail for HDA/DDR3 ON ON OFF +1.5VS 1.5V switched power rail ON OFF OFF +1.8V 1.8V GM LVDS MODULE ON ON OFF Vcc Ra/Rc/Re +1.8VS 1.8V switched power rail ON OFF OFF Board ID +1.1VS 1.1V switched power rail ON OFF OFF +3VALW 3.3V always on power rail ON ON ON* +3V 3.3V power rail for SB ON ON X +3V_LAN 3.3V power rail for LAN ON ON X +3VS 3.3V switched power rail ON OFF OFF +5VALW 5V always on power rail ON ON ON* +5VS 5V switched power rail ON OFF OFF +VSB VSB always on power rail ON ON ON* +RTCVCC RTC power ON ON ON +VGA_CORE Core voltage for GPU ON OFF OFF IDSEL# EC SM Bus1 address Device Address Smart Battery 0001 011X b MEDIA CONSOLE 1010 000X b REQ#/GNT# V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V BOARD ID Table Board ID Interrupts EC SM Bus2 address Device 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC External PCI Devices Device BTO Option Table PCB Revision 0.1 0.2 0.3 1.0 1A BTO Item KAL90 UMA PM@ ALC888VC ALC888VB AR8121 AR8112 ALC268 GL40 GM45 KAL90-G0 KAL90-H0 KALG0 KALH0 ALC268 Address ADI ADT7421 1001 100X b NB9M THERMAL SENSOR ICH9M SM Bus address Device Address Clock Generator (ICS9LPRS387, SLG8SP556V) 1101 001Xb DDR DIMM0 1001 000Xb DDR DIMM2 1001 010Xb BOM Configuration Table Project KAL90-UMA KAL90-Dis KALH0-GM45 KALH0-GL40 KALH0-PM45 KAL90+ -UMA KAL90+ -Dis Board ID / SKU ID Table for AD channel Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF D SIGNAL BOM Configuration XXXXXXXXXX:KAL90@/GM@/888VC@/8121@/GM45@ XXXXXXXXXX:KAL90@/PM@/888VC@/8121@ XXXXXXXXXX:KALH0@/GM@/888VC@/8121@/GM45@ XXXXXXXXXX:KALH0@/GM@/888VC@/8121@/GL40@ XXXXXXXXXX:KALH0@/PM@/888VC@/8121@ BOM Structure KAL90@ GM@ PM@ 888VC@ 888VB@ 8121@ 8112@ 268@ GL40@ GM45@ KAL90_G0@ KAL90_H0@ KALG0@ KALH0@ 268@ KAL90_90+@ KAL90_H0_G0@ KAL90+_G0 KALH0_G0 KAL90_G0_90+@ KAL90_H0_90+@ KAL90+_PCB@ KALG0_PCB@ GM@/888VC@/8121@/GM45@/KAL90+_G0@/KAL90_90+@/KAL90_G0_90+@/KAL90_H0_90+@/KAL90+_PCB@ PM@/888VC@/8121@/KAL90+_G0@/KAL90_90+@/KAL90_G0_90+@/KAL90_H0_90+@/KAL90+_PCB@/PM45@ KALG0 -UMA(GL40) KALG0 -Dis KALG0@/GM@/888VC@/8121@/GL40@/KAL90+_G0@/KALH0_G0@/KAL90_G0_90+@/KALG0_DDR2 PCB RV0 @/KALG0+@ KALG0@/PM@/888VC@/8121@/PM45@/KAL90+_G0@/KALH0_G0@/KAL90_G0_90+@/KALG0_DDR2 PCB RV0 @/KALG0+@ KALG0 -UMA(GM45) KALG0@/GM@/888VC@/8121@/GM45@/KAL90+_G0@/KALH0_G0@/KAL90_G0_90+@/KALG0_DDR2 PCB RV0 @/KALG0+@ KALG0 -DIS(GM45) KALG0@/PM@/888VC@/8121@/GM45@/KAL90+_G0@/KALH0_G0@/KAL90_G0_90+@/KALG0_DDR2 PCB RV0 @/KALG0+@ 4 KALG0 LAN to AR-8131 - 8121@ Change to 8131@ 2008/11/24 Issued Date 2009/12/31 Deciphered Date THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC A B C Compal Electronics, Inc Compal Secret Data Security Classification D Title Size B Date: Document Number Notes List KALH0/KALG0/KAL90+ Monday, April 27, 2009 E Sheet Rev 1.0 of 53 H_A#[3 35] H_A#[3 35] H_REQ#[0 4] H_REQ#[0 4] H_RS#[0 2] H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 K3 H2 K2 J3 L1 H_ADSTB#0 H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# A6 A5 C4 H_STPCLK# H_INTR H_NMI H_SMI# D5 C6 B4 A3 C DEFER# DRDY# DBSY# BR0# LOCK# HIT# HITM# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# A20M# FERR# IGNNE# IERR# INIT# RESET# RS[0]# RS[1]# RS[2]# TRDY# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] H1 E2 G5 H_ADS# H_BNR# H_BPRI# H5 F21 E1 H_DEFER# H_DRDY# H_DBSY# F1 H_BR0# H_INIT# D H_IERR# D20 B3 H4 H_LOCK# H_RESET# H_RS#0 H_RS#1 H_RS#2 C1 F3 F4 G3 G2 H_RESET# H_TRDY# G6 E4 H_HIT# H_HITM# AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TMS XDP_TRST# XDP_DBRESET# C XDP_DBRESET# +1.05VS THERMAL PROCHOT# THERMDA THERMDC THERMTRIP# STPCLK# LINT0 LINT1 SMI# M4 N5 T2 V3 B2 D2 D22 D3 F6 B ADS# BNR# BPRI# ICH Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# ADDR GROUP_1 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 JCPU1A CONTROL J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 ADDR GROUP_0 D H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 XDP/ITP SIGNALS H_RS#[0 2] H CLK BCLK[0] BCLK[1] H_PROCHOT# H_THERMDA H_THERMDC D21 A24 B25 C7 XDP_TDI R2 54.9_0402_1% XDP_TMS R3 54.9_0402_1% XDP_BPM#5 R5 54.9_0402_1% H_PROCHOT# R13 56_0402_5% H_IERR# R18 56_0402_5% XDP_TRST# R7 54.9_0402_1% XDP_TCK R8 54.9_0402_1% left NC if no ITP H_THERMTRIP# A22 A21 @ 39Ohm CLK_CPU_BCLK CLK_CPU_BCLK# Layout Note: H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil RESERVED B Penryn CONN@ +3VS BSEL1 BSEL0 BCLK 0 266 1 1 R17 @ 56_0402_5% 200 166 2200P_0402_50V7K H_THERMDC B E C H_PROCHOT# A C3 0 U1 H_THERMDA +1.05VS BSEL2 C2 0.1U_0402_16V4Z OCP# VDD SMDATA DN ALERT# THERM# SMCLK DP EC_SMB_CK2 GND EC_SMB_DA2 R1133 10K_0402_5% +3VS EMC1402-1-ACZL-TR_MSOP8 A Q1 MMBT3904_SOT23-3 @ Compal Secret Data Security Classification 2008/11/24 Issued Date Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size B Date: Compal Electronics, Inc Document Number Penryn (1/3) KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet Rev 1.0 of 53 H_D#[0 63] H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 +1.05VS R27 1K_0402_1% R29 2K_0402_1% R21 R22 H_DSTBN#1 H_DSTBP#1 H_DINV#1 2 C1477 @ @ @ GTL_REF0 TEST1 1K_0402_5% TEST2 1K_0402_5% TEST3 @ PAD T1 0.1U_0402_16V4Z TEST4 TEST5 @ PAD T2 1 Width=4 mil , Spacing: 15mil (55Ohm) Trace Close CPU < 0.5' CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 AD26 C23 D25 C24 AF26 AF1 A26 C3 B22 B23 C21 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 BSEL[0] BSEL[1] BSEL[2] Penryn DATA GRP C H_DSTBN#0 H_DSTBP#0 H_DINV#0 MISC D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# DATA GRP D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# DATA GRP E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 DATA GRP H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 D JCPU1B COMP[0] COMP[1] COMP[2] COMP[3] DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 R26 U26 AA1 Y1 E5 B5 D24 D6 D7 AE6 H_D#[0 63] +CPU_CORE H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_DSTBN#3 H_DSTBP#3 H_DINV#3 COMP0 COMP1 COMP2 COMP3 R26 R25 R24 R23 1 1 H_PWRGOOD H_CPUSLP# 2 2 27.4_0402_1% 54.9_0402_1% 27.4_0402_1% 54.9_0402_1% H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGOOD H_CPUSLP# PSI# CONN@ TRACE CLOSELY CPU < 0.5' COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms) COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms) B A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 JCPU1C VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] Penryn AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] +CPU_CORE D C G21 V6 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] +1.05VS 20mils B26 C26 VCCA[01] VCCA[02] AD6 AF5 AE5 AF4 AE3 AF3 AE2 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] VCCSENSE VSSSENSE AF7 VCCSENSE AE7 VSSSENSE CONN@ CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 R28 C7 C8 0.01U_0402_16V7K 2 10U_0805_10V4Z 100_0402_1% B +CPU_CORE VCCSENSE VSSSENSE R30 +1.5VS 1 100_0402_1% A A Compal Secret Data Security Classification 2008/11/24 Issued Date Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Size B Date: Compal Electronics, Inc Document Number Penryn (2/3) KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet Rev 1.0 of 53 +CPU_CORE D + C55 900P_PFAF250E128MNTTE_2.5VM +CPU_CORE C426 C427 C428 C429 10U_0805_6.3V6M 10U_0805_6.3V6M C425 10U_0805_6.3V6M 10U_0805_6.3V6M C416 10U_0805_6.3V6M 10U_0805_6.3V6M C C430 +CPU-CORE Decoupling SPCAP,Polymer MLCC 0805 X5R C,uF ESR, mohm ESL,nH 4X330uF 6m ohm/4 1.8nH/6 32X22uF 3m ohm/32 0.6nH/32 32X10uF 3m ohm/32 0.6nH/32 A + C1478 C45 C46 C47 C48 C49 C50 A Compal Secret Data Security Classification 2008/11/24 Issued Date Deciphered Date 2009/12/31 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 0.1U_0402_16V4Z 0.1U_0402_16V4Z CONN@ 0.1U_0402_16V4Z +1.05VS C431 B 0.1U_0402_16V4Z Penryn 0.1U_0402_16V4Z B P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19 AF21 A25 AF25 VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] VSS[163] 0.1U_0402_16V4Z C VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] 10U_0805_6.3V6M D JCPU1D 330U_D2E_2.5VM_R15 A4 A8 A11 A14 A16 A19 A23 AF2 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 10U_0805_6.3V6M Title Size B Date: Compal Electronics, Inc Document Number Penryn (3/3) KALH0/KALG0/KAL90+ Monday, April 27, 2009 Sheet Rev 1.0 of 53 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 +1.05VS 2 R47 221_0402_1% R55 100_0402_1% width=10mil C59 0.1U_0402_16V4Z C H_RCOMP width=10mil R54 24.9_0402_1% B H_SWING H_RCOMP C5 E3 H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 H_A#_32 H_A#_33 H_A#_34 H_A#_35 R46 1K_0402_1% 1 width:spacing=10mil:20mil (